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LodeRunner: sound works (not sure if it's fully correct)

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This commit is contained in:
Gyorgy Szombathelyi 2020-03-01 21:07:48 +01:00
parent 1d98e4b642
commit 723e8ebbcd
6 changed files with 207 additions and 54 deletions
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140
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/LodeRunner_MiST.sdc Normal file
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@ -0,0 +1,140 @@
## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set game_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set aud_clk "pll|altpll_component|auto_generated|pll1|clk[3]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
set_clock_groups -asynchronous -group [get_clocks $sdram_clk] -group [get_clocks $aud_clk]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks $game_clk] -to [get_clocks $sdram_clk] -setup 2
set_multicycle_path -from [get_clocks $game_clk] -to [get_clocks $sdram_clk] -hold 1
set_multicycle_path -to {VGA_*[*]} -setup 3
set_multicycle_path -to {VGA_*[*]} -hold 2
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

20
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv
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@ -98,8 +98,10 @@ user_io(
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire [13:0] snd_addr;
wire [16:0] snd_addr;
wire [13:0] snd_rom_addr;
wire [15:0] snd_do;
wire snd_vma;
wire [14:0] sp_addr;
wire [31:0] sp_do;
@ -111,7 +113,7 @@ wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sd ),
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
@ -141,7 +143,7 @@ sdram sdram(
.cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]} ),
.cpu1_q ( rom_do ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h4000 + snd_addr[13:1]) ),
.cpu2_addr ( ioctl_downl ? 16'hffff : snd_addr[16:1] ),
.cpu2_q ( snd_do ),
// port2 for sprite graphics
@ -158,8 +160,9 @@ sdram sdram(
);
// ROM download controller
always @(posedge clk_sd) begin
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
reg snd_vma_r, snd_vma_r2;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
@ -168,6 +171,10 @@ always @(posedge clk_sd) begin
port2_req <= ~port2_req;
end
end
// clock domain crossing here (clk_snd -> clk_sys)
snd_vma_r <= snd_vma; snd_vma_r2 <= snd_vma_r;
if (snd_vma_r2) snd_addr <= snd_rom_addr + 16'h8000;
end
// reset signal generation
@ -221,8 +228,9 @@ target_top target_top(
.VGA_B(b),
.cpu_rom_addr(rom_addr),
.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr(snd_addr),
.snd_rom_do(snd_addr[0] ? snd_do[15:8] : snd_do[7:0])
.snd_rom_addr(snd_rom_addr),
.snd_rom_do(snd_rom_addr[0] ? snd_do[15:8] : snd_do[7:0]),
.snd_vma(snd_vma)
);
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(

32
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd
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@ -1,4 +1,5 @@
---------------------------------------------------------------------------------
-- Irem M62 sound board, based on
-- Moon patrol sound board by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
@ -31,8 +32,9 @@ port(
select_sound : in std_logic_vector(7 downto 0);
audio_out : out std_logic_vector(11 downto 0);
snd_rom_addr : out std_logic_vector(13 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0);
snd_rom_addr : out std_logic_vector(13 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0);
snd_vma : out std_logic;
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
@ -76,6 +78,7 @@ architecture struct of Sound_Board is
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_vma : std_logic;
signal irqraz_cs : std_logic;
signal irqraz_we : std_logic;
@ -161,9 +164,9 @@ dbg_cpu_addr <= cpu_addr;
-- cs
wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF
ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F
adpcm_cs <= '1' when cpu_addr(14 downto 11) = "0001" else '0'; -- 0800-0FFF / 8800-8FFF
irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF / 9000-9FFF
rom_cs <= '1' when cpu_addr(14 downto 12) = "111" else '0'; -- 7000-7FFF / F000-FFFF
adpcm_cs <= '1' when cpu_addr(14) = '0' and cpu_addr(11) = '1' and cpu_addr(1 downto 0) /= "00" else '0'; -- 0801-0802
irqraz_cs <= '1' when cpu_addr(14) = '0' and cpu_addr(11) = '1' and cpu_addr(1 downto 0) = "00" else '0'; -- 0800
rom_cs <= '1' when cpu_addr(14) = '1' else '0'; -- 4000-7FFF / C000-FFFF
-- write enables
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
@ -178,7 +181,7 @@ cpu_di <=
port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
rom_do when rom_cs = '1' else X"55";
snd_rom_do when rom_cs = '1' else X"55";
process (clock_E)
begin
@ -334,7 +337,7 @@ port map(
clk => clock_E, -- E clock input (falling edge)
rst => reset, -- reset input (active high)
rw => cpu_rw, -- read not write output
vma => open, -- valid memory address (active high)
vma => cpu_vma, -- valid memory address (active high)
address => cpu_addr, -- address bus output
data_in => cpu_di, -- data bus input
data_out => cpu_do, -- data bus output
@ -346,14 +349,15 @@ port map(
test_cc => open
);
rom_cpu : entity work.snd_prg
port map(
clk => clock_E, -- E clock input (falling edge)
addr => cpu_addr(13 downto 0),
data => rom_do
);
--rom_cpu : entity work.snd_prg
--port map(
-- clk => clock_E, -- E clock input (falling edge)
-- addr => cpu_addr(13 downto 0),
-- data => rom_do
--);
-- snd_rom_addr <= cpu_addr(13 downto 0);
snd_vma <= rom_cs and cpu_vma;
snd_rom_addr <= cpu_addr(13 downto 0);
-- cpu wram

6
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/pace.vhd
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@ -26,15 +26,15 @@ entity PACE is
-- video
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t;
sound_data_o : out std_logic_vector(7 downto 0);
sound_data_o : out std_logic_vector(7 downto 0);
-- custom i/o
-- project_i : in from_PROJECT_IO_t;
-- project_o : out to_PROJECT_IO_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0)
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0)
);
end entity PACE;

31
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform.vhd
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@ -45,15 +45,15 @@ entity platform is
-- various graphics information
graphics_i : in from_GRAPHICS_t;
graphics_o : out to_GRAPHICS_t;
sound_data_o : out std_logic_vector(7 downto 0);
sound_data_o : out std_logic_vector(7 downto 0);
-- custom i/o
-- project_i : in from_PROJECT_IO_t;
-- project_o : out to_PROJECT_IO_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0)
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0)
);
end platform;
@ -164,25 +164,24 @@ begin
-- RAM $E000-$EFFF
wram_cs <= '1' when STD_MATCH(cpu_a, X"E"&"------------") else '0';
-- OUTPUT $DXX0
snd_cs <= '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else '0';
-- OUTPUT $XX00
snd_cs <= '1' when cpu_a(7 downto 0) = X"00" else '0';
-- INPUTS (I/O) $00-$04
in_cs <= '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else
'1' when STD_MATCH(cpu_a(7 downto 0), X"04") else
'0';
process (clk_sys, rst_sys) begin
if rst_sys = '1' then
sound_data_o <= X"00";
elsif rising_edge(clk_sys) then
if cpu_clk_en = '1' and cpu_mem_wr = '1' and snd_cs = '1' then
sound_data_o <= cpu_d_o;
end if;
end if;
end process;
process (clk_sys, rst_sys) begin
if rst_sys = '1' then
sound_data_o <= X"FF";
elsif rising_edge(clk_sys) then
if cpu_clk_en = '1' and cpu_io_wr = '1' and snd_cs = '1' then
sound_data_o <= cpu_d_o;
end if;
end if;
end process;
-- memory read mux
cpu_d_i <= in_d_o when (cpu_io_rd = '1' and in_cs = '1') else
cpu_rom_do when rom_cs = '1' else

32
Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/target_top.vhd
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@ -41,7 +41,8 @@ entity target_top is port(
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
snd_rom_addr : out std_logic_vector(13 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0)
snd_rom_do : in std_logic_vector(7 downto 0);
snd_vma : out std_logic
);
end target_top;
@ -86,17 +87,18 @@ end generate GEN_RESETS;
VGA_HS <= video_o.hsync;
VGA_VS <= video_o.vsync;
--Sound_Board : entity work.Sound_Board
-- port map(
-- clock_E => clk_aud,
-- areset => clkrst_i.rst(1),
-- select_sound => sound_data,
-- audio_out => audio_out,
-- snd_rom_addr => snd_rom_addr,
-- snd_rom_do => snd_rom_do,
-- dbg_cpu_addr => open
-- );
Sound_Board : entity work.Sound_Board
port map(
clock_E => clk_aud,
areset => clkrst_i.rst(1),
select_sound => sound_data,
audio_out => audio_out,
snd_rom_addr => snd_rom_addr,
snd_rom_do => snd_rom_do,
snd_vma => snd_vma,
dbg_cpu_addr => open
);
pace_inst : entity work.pace
port map(
clkrst_i => clkrst_i,
@ -106,10 +108,10 @@ pace_inst : entity work.pace
video_i => video_i,
video_o => video_o,
sound_data_o => sound_data,
platform_i => platform_i,
platform_o => platform_o,
platform_i => platform_i,
platform_o => platform_o,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do
cpu_rom_do => cpu_rom_do
);
inputs_i.jamma_n.coin(1) <= not usr_coin1;