github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-03-10 12:28:26 +00:00
Code Issues Releases Wiki Activity

Release Supervision

Browse Source
This commit is contained in:
Marcel
2022-06-20 18:52:46 +02:00
parent 6fe7618dcf
commit 78e466fe6f
29 changed files with 2080 additions and 4529 deletions
Download Patch File Download Diff File Expand all files Collapse all files

99
Console_MiST/Gamate_MiST/Gamate_MiST.qsf
View File

@@ -18,14 +18,14 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 15:15:28 January 23, 2021
# Date created = 18:49:14 June 20, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Gaplus_assignment_defaults.qdf
# Gamate_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -43,6 +43,17 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Gamate_MiST.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gamate_top.sv
set_global_assignment -name VHDL_FILE rtl/bram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/lcd.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv
set_global_assignment -name VHDL_FILE rtl/rom/gamate_bios_bit.vhd
set_global_assignment -name VHDL_FILE rtl/rom/gamate_bios_umc.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/T65/T65.qip"
# Pin & Location Assignments
# ==========================
@@ -169,69 +180,57 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -------------------------
# start ENTITY(Gaplus_MiST)
# start ENTITY(Gamate_MiST)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Gaplus_MiST)
# end ENTITY(Gamate_MiST)
# -----------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Gamate_MiST.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gamate_top.sv
set_global_assignment -name VHDL_FILE rtl/bram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/lcd.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv
set_global_assignment -name VHDL_FILE rtl/rom/gamate_bios_bit.vhd
set_global_assignment -name VHDL_FILE rtl/rom/gamate_bios_umc.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/T65/T65.qip"
set_global_assignment -name VHDL_FILE rtl/rom/Cube_Up.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

135
Console_MiST/Gamate_MiST/Gamate_MiST.sdc Normal file
View File

@@ -0,0 +1,135 @@
## Generated SDC file "Gamate_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

9
Console_MiST/Gamate_MiST/Readme.md
View File

@@ -1,4 +1,11 @@
# Gamate Handheld System for MiSTer
# Gamate Handheld System for MiST
Usage
Start = ESC
Select = TAB
A = Control
B = LALT
## General description
This is an FPGA implementation of the Gamate handheld system by Jamie Blanks. This was a Gameboy clone from the early 2000's from the Bit Corp, later to be part of UMC. There's not much to say about it.

19
Console_MiST/Supervision_MiST/ReadMe.txt
View File

@@ -1,19 +0,0 @@
Watara Supervision for MiSTer by Pierre Cornier
wip
VGA Only
Working for Now
Brain Power
Galactic Crusader
Galaxy Fighter
Happy Pairs
John Advenzure
Kabi Island
Penguin Hideout
Super Kong

18
Console_MiST/Supervision_MiST/Readme.md Normal file
View File

@@ -0,0 +1,18 @@
# Watara Supervision for MiST
Based upon initial work by Pierco, rewritten by Jamie Blanks.
Usage
Start = ESC
Select = TAB
A = Control
B = LALT
An implementation of the unfortunate GameBoy clone, the Watara SuperVision. No boot ROMs are required and there is no additional setup.
This core is compatible with gameboy palettes which can be found with the GameBoy core.
The full game library is supported, including the rare "Journey to the West".
## Special Thanks
A special thank you to Osman Celimli for his very thorough reverse engineering notes and personal help in getting this core accurate.

BIN
Console_MiST/Supervision_MiST/Snapshot/Supervision_MiST.rbf
View File

Binary file not shown.

7
Console_MiST/Supervision_MiST/Supervision_MiST.qpf
View File

@@ -18,13 +18,14 @@
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 14:59:16 November 16, 2017
# Date created = 00:21:03 December 03, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "14:59:16 November 16, 2017"
DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "Supervision_MiST"
PROJECT_REVISION = "Supervision_MiST"

41
Console_MiST/Supervision_MiST/Supervision_MiST.qsf
View File

@@ -18,7 +18,7 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 21:20:48 December 16, 2020
# Date created = 18:42:19 June 20, 2022
#
# -------------------------------------------------------------------------- #
#
@@ -39,13 +39,20 @@
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Supervision_MiST.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sv_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/lcd.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/audio.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dma.sv
set_global_assignment -name VHDL_FILE rtl/bram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/65C02/r65c02.qip"
# Pin & Location Assignments
# ==========================
@@ -124,21 +131,17 @@ set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY Supervision_MiST
# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
@@ -158,6 +161,11 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
@@ -224,17 +232,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# end ENTITY(Supervision_MiST)
# ----------------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Supervision_MiST.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Supervision_Top.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/audio.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dma.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram88.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
set_global_assignment -name VERILOG_FILE rtl/65c02/cpu_65c02.v
set_global_assignment -name VERILOG_FILE rtl/65c02/cpu.v
set_global_assignment -name VERILOG_FILE rtl/65c02/ALU.v
set_global_assignment -name VERILOG_FILE rtl/pll1.v
set_global_assignment -name VERILOG_FILE rtl/pll2.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

135
Console_MiST/Supervision_MiST/Supervision_MiST.sdc Normal file
View File

@@ -0,0 +1,135 @@
## Generated SDC file "Supervision_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

35
Console_MiST/Supervision_MiST/clean.bat
View File

@@ -2,40 +2,15 @@
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
del /s build_id.v
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del *.cdf
del /s new_rtl_netlist
del /s old_rtl_netlist
del sys\vip.qip
del sys\sysmem.qip
del sys\sdram.sv
del sys\ddram.sv
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

108
Console_MiST/Supervision_MiST/rtl/65c02/ALU.v
View File

@@ -1,108 +0,0 @@
/*
* ALU.
*
* AI and BI are 8 bit inputs. Result in OUT.
* CI is Carry In.
* CO is Carry Out.
*
* op[3:0] is defined as follows:
*
* 0011 AI + BI
* 0111 AI - BI
* 1011 AI + AI
* 1100 AI | BI
* 1101 AI & BI
* 1110 AI ^ BI
* 1111 AI
*
*/
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = { temp_h, temp_l[3:0] };
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if( RDY ) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule

67
Console_MiST/Supervision_MiST/rtl/65c02/README
View File

@@ -1,67 +0,0 @@
========================================================
A Verilog HDL version of the old MOS 6502 and 65C02 CPUs
========================================================
Original 6502 core by Arlet Ottens
65C02 extensions by David Banks and Ed Spittles
==========
6502 Core
==========
Arlet's original 6502 core (cpu.v) is unchanged.
Note: the 6502/65C02 cores assumes a synchronous memory. This means
that valid data (DI) is expected on the cycle *after* valid
address. This allows direct connection to (Xilinx) block RAMs. When
using asynchronous memory, I suggest registering the address/control
lines for glitchless output signals.
Have fun.
==========
65C02 Core
==========
A second core (cpu_65c02.v) has been added, based on Arlet's 6502
core, with additional 65C02 instructions and addressing modes:
- PHX, PHY, PLX, PLY
- BRA
- INC A, DEC A
- (zp) addressing mode
- STZ
- BIT zpx, absx, imm
- TSB/TRB
- JMP (,X)
- NOPs (optional)
- 65C02 BCD N/Z flags (optional, disabled)
The Rockwell/WDC specific instructions (RMB/SMB/BBR/BBS/WAI/STP) are
not currently implemented
The 65C02 core passes the Dormann 6502 test suite, and also passes the
Dormann 65C02 test suite if the optional support for NOPs and 65C02
BCD flags is enabled.
It has been tested as a BBC Micro "Matchbox" 65C02 Co Processor, in a
XC6SLX9-2 FPGA, running at 80MHz using 64KB of internel block RAM. It
just meets timing at 80MHz in this environment. It successfully runs
BBC Basic IV and Tube Elite.
============
Known Issues
============
The Matchbox Co Processor needed one wait state (via RDY) to be added
to each ROM access (only needed early in the boot process, as
eventually everything runs from RAM). The DIHOLD logic did not work
correctly with a single wait state, and so has been commented out.
I now believe the correct fix is actually just:
always @(posedge clk )
if( RDY )
DIHOLD <= DI;
assign DIMUX = ~RDY ? DIHOLD : DI;

1225
Console_MiST/Supervision_MiST/rtl/65c02/cpu.v
View File

File diff suppressed because it is too large Load Diff

1395
Console_MiST/Supervision_MiST/rtl/65c02/cpu_65c02.v
View File

File diff suppressed because it is too large Load Diff

295
Console_MiST/Supervision_MiST/rtl/Supervision_MiST.sv
View File

@@ -14,7 +14,6 @@ module Supervision_MiST(
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
@@ -26,60 +25,64 @@ module Supervision_MiST(
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"SVISION;bin;",
// "O34,Scanlines,Off,25%,50%,75%;",
// "O5,Blending,Off,On;",
"O6,Joyswap,Off,On;",
"O8,Screen Color,Green,White;",
"Supervision;;",
"F1,binsv,Load Cartridge;",
// "F2,sgbgbp,Load Palette;",
"O7,Custom Palette,Off,On;",
"O4,Flickerblend,On,Off;",
"O23,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
// "O6,Framerate,60hz,Original;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = ~ioctl_downl;
assign SDRAM_CLK = ~clk_sys;
assign SDRAM_CKE = 1;
wire clk_sys, clk_ram, pll_locked;
wire clk_sys, clk_vid, clk_cpu, pll_locked;
pll1 pll1(
pll pll
(
.inclk0(CLOCK_27),
.c0(clk_sys),//50
.c1(clk_cpu),// 4
.areset(0),
.c0(clk_ram),//64.000000 MHz Reduced 56Mhz(better Rom loading)
.c1(clk_sys), //16.000000 MHz
.locked(pll_locked)
);
pll2 pll2(
.inclk0(CLOCK_27),
.c0(clk_vid)// 25.175
);
);
wire [63:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire ypbpr;
wire scandoublerD;
wire [3:0] audio_ch1, audio_ch2;
wire hs, vs, hb, vb;
wire blankn = ~(hb | vb);
wire [7:0] r, g, b;
wire key_strobe;
wire key_pressed;
wire [15:0] joystick_0;
wire [15:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire [31:0] joystick_0, joystick_1;
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire ioctl_wait;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [8:0] r,g,b;
wire [15:0] audio_l, audio_r;
data_io data_io(
.clk_sys ( clk_sys ),
.clk_sys ( clk_ram ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
@@ -90,90 +93,8 @@ data_io data_io(
.ioctl_dout ( ioctl_dout )
);
reg port1_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_sys ),
// port1 used for main CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]}),
.cpu1_q ( rom_do )
);
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sys) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
Supervision_Top Supervision_Top(
.clk_sys(clk_sys),
.clk_vid(clk_vid),
.clk_cpu(clk_cpu),
.reset(reset),
.hsync(hs),
.vsync(vs),
.hblank(hb),
.vblank(vb),
.white(status[8]),
.red(r),
.green(g),
.blue(b),
.joystick({m_fireA, m_fireB, m_fireC, m_fireD, m_up, m_down, m_left, m_right}),
.audio_ch1(audio_ch1),
.audio_ch2(audio_ch2),
.cpu_rom_addr(rom_addr),
.cpu_rom_data(rom_addr[0] ? rom_do[15:8] : rom_do[7:0])
);
mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(9)) mist_video(
.clk_sys(clk_vid),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r[7:2] : 0),
.G(blankn ? g[7:2] : 0),
.B(blankn ? b[7:2] : 0),
.HSync(~hs),
.VSync(~vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.ce_divider(1'b0),
.blend(status[5]),
.scandoubler_disable(1'b1),//scandoublerD),
.scanlines(status[4:3]),
.ypbpr(ypbpr)
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
user_io #(.STRLEN($size(CONF_STR)>>3))user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
@@ -184,6 +105,7 @@ user_io(
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
@@ -191,26 +113,45 @@ user_io(
.joystick_1 (joystick_1 ),
.status (status )
);
mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(11)) mist_video(
.clk_sys(clk_sys),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r[7:2] : 0),
.G(blankn ? g[7:2] : 0),
.B(blankn ? b[7:2] : 0),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.ce_divider(1'b0),
.scandoubler_disable(scandoublerD),
.scanlines(status[3:2]),
.ypbpr(ypbpr)
);
dac #(
.C_bits(4))
dac_l(
dac #(16) dac_l(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio_ch1),
.dac_i(audio_l),
.dac_o(AUDIO_L)
);
dac #(
.C_bits(4))
dac_r(
dac #(16) dac_r(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio_ch2),
.dac_i(audio_r),
.dac_o(AUDIO_R)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
@@ -219,10 +160,114 @@ arcade_inputs inputs (
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joyswap ( status[6] ),
.oneplayer ( 1'b1 ),
.joystick_1 ( joystick_1 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} )
);
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
wire reset = status[0] | buttons[1] | rom_download;
sv_top core(
.clk_sys (clk_sys),
.reset (reset),
.joystick ({m_coin1,m_tilt, m_fireB, m_fireA, m_up, m_down, m_left, m_right}),
.rom_dout (rom_dout),
// .compat60 (~status[6]),
.large_rom (|rom_mask[18:17]),
.hsync (hs),
.vsync (vs),
.hblank (hb),
.vblank (vb),
.audio_r (audio_r),
.audio_l (audio_l),
.pixel (pixel),
.pix_ce (ce_pix),
.addr_bus (rom_addr),
.rom_read (rom_cs)
);
sdram cart_rom
(
.SDRAM_DQ (SDRAM_DQ),
.SDRAM_A (SDRAM_A),
.SDRAM_DQML (SDRAM_DQML),
.SDRAM_DQMH (SDRAM_DQMH),
.SDRAM_BA (SDRAM_BA),
.SDRAM_nCS (SDRAM_nCS),
.SDRAM_nWE (SDRAM_nWE),
.SDRAM_nRAS (SDRAM_nRAS),
.SDRAM_nCAS (SDRAM_nCAS),
.SDRAM_CLK (SDRAM_CLK),
.SDRAM_CKE (SDRAM_CKE),
.init (!pll_locked),
.clk (clk_ram),
.ch0_addr (rom_download ? ioctl_addr : (rom_addr & rom_mask)),
.ch0_rd (rom_cs && ~rom_download),
.ch0_wr (rom_download & ioctl_wr),
.ch0_din (ioctl_dout),
.ch0_dout (rom_dout),
.ch0_busy (cart_busy)
);
wire rom_download = (~|ioctl_index[5:0] || ioctl_index[5:0] == 1) && ioctl_downl;
wire ce_pix;
wire [7:0] rom_dout;
wire [18:0] rom_addr;
wire [1:0] last_pixel, pixel, prev_pixel;
wire rom_cs;
reg [14:0] vbuffer_addr;
wire cart_busy;
reg [18:0] rom_mask = 19'h7FFFF;
assign ioctl_wait = cart_busy & rom_download;
logic [127:0] user_palette = 128'hF7BEF7_E78686_7733E7_2C2C96_2020_2020;
wire [127:0] default_palette = 128'h87BA6B_6BA378_386B82_384052_0000_0000;
logic [2:0][7:0] palette[4];
assign palette[0] = status[7] ? user_palette[127:104] : default_palette[127:104];
assign palette[1] = status[7] ? user_palette[103:80] : default_palette[103:80];
assign palette[2] = status[7] ? user_palette[79:56] : default_palette[79:56];
assign palette[3] = status[7] ? user_palette[55:32] : default_palette[55:32];
always @(posedge clk_sys) begin
if (ce_pix) begin
r <= ~status[4] ? (({1'b0, palette[pixel][2]} + palette[prev_pixel][2]) >> 1'd1) : palette[pixel][2];
g <= ~status[4] ? (({1'b0, palette[pixel][1]} + palette[prev_pixel][1]) >> 1'd1) : palette[pixel][1];
b <= ~status[4] ? (({1'b0, palette[pixel][0]} + palette[prev_pixel][0]) >> 1'd1) : palette[pixel][0];
last_pixel <= pixel;
if (~vb && ~hb)
vbuffer_addr <= vbuffer_addr + 1'd1;
if (vs)
vbuffer_addr <= 0;
end
end
dpram #(.data_width(2), .addr_width(15)) vbuffer (
.clock (clk_sys),
.address_a (vbuffer_addr - 1'd1),
.data_a (last_pixel),
.wren_a (~vb && ~hb && ce_pix),
.address_b (vbuffer_addr),
.q_b (prev_pixel)
);
always @(posedge clk_sys) begin
if (rom_download && ioctl_wr)
rom_mask <= ioctl_addr[18:0];
// if (palette_download)
// user_palette[{~ioctl_addr[3:0], 3'b000}+:8] <= ioctl_dout;
end
endmodule

333
Console_MiST/Supervision_MiST/rtl/Supervision_Top.sv
View File

@@ -1,333 +0,0 @@
module Supervision_Top(
input clk_sys,//50
input clk_vid,// 25.175
input clk_cpu,//4
input reset,
output hsync,
output vsync,
output hblank,
output vblank,
input white,
output [7:0] red,
output [7:0] green,
output [7:0] blue,
output [3:0] audio_ch1,
output [3:0] audio_ch2,
input [7:0] joystick,
output [15:0]cpu_rom_addr,
input [7:0] cpu_rom_data
);
reg [15:0] nmi_clk;
wire nmi = nmi_clk == 0;
always @(posedge clk_cpu)
nmi_clk <= nmi_clk + 16'b1;
reg [7:0] sys_ctl;
reg [7:0] irq_timer; // 2023
reg [7:0] irq_status; // 2027 ??????DT 1=expired/finished
reg irq_tim;
reg irq_dma;
wire [15:0] cpu_addr;
wire [7:0] cpu_dout;
wire [7:0] wram_dout;
wire [7:0] vram_dout;
wire [7:0] rom_dout;
wire [7:0] sys_dout;
reg [7:0] dma_src_lo;
reg [7:0] dma_src_hi;
reg [7:0] dma_dst_lo;
reg [7:0] dma_dst_hi;
reg [7:0] dma_length;
reg [7:0] dma_ctrl;
wire [7:0] dma_dout;
wire [13:0] dma_addr;
wire dma_busy;
wire dma_sel;
wire dma_write;
reg [7:0] lcd_xscroll;
reg [7:0] lcd_yscroll;
reg [7:0] lcd_xsize;
reg [7:0] lcd_ysize;
wire [7:0] lcd_din;
wire lcd_pulse;
wire cpu_rdy = ~dma_busy;
wire dma_rdy = ~lcd_pulse;
wire cpu_we;
wire [15:0] lcd_addr;
reg [7:0] ch1_freq_hi, ch1_freq_low, ch1_length, ch1_vduty;
reg [7:0] ch2_freq_hi, ch2_freq_low, ch2_length, ch2_vduty;
reg [7:0] audio_dma_addr_low, audio_dma_addr_high;
reg [7:0] audio_dma_ctrl, audio_dma_length, audio_dma_trigger;
reg [7:0] noise_ctrl, noise_freq_vol, noise_length;
////////////////////// IRQ //////////////////////////
reg [13:0] timer_div;
// irq_tim
always @(posedge clk_sys)
if (sys_ctl[1]) begin // irq enable flag
if (irq_timer == 0 && ~irq_status[0]) irq_tim <= 1;
else if (sys_cs && cpu_we && AB[2:0] == 3'h3 && cpu_dout == 0) irq_tim <= 1;
else irq_tim <= 0;
end
// irq status
always @(posedge clk_sys)
if (sys_cs && ~cpu_we && AB[2:0] == 3'h4) // write to irq timer ack
irq_status[0] <= 1'b0;
else if (irq_tim) // change status on irq
irq_status[0] <= 1'b1;
// timer prescaler
always @(posedge clk_cpu)
if (timer_div > 0)
timer_div <= timer_div - 14'b1;
else if (sys_ctl[4])
timer_div <= 14'h3fff;
else
timer_div <= 14'hff;
// irq_timer
always @(posedge clk_cpu)
if (sys_cs && cpu_we && AB[2:0] == 3'h3)
irq_timer <= cpu_dout;
else if (timer_div == 0 && irq_timer > 0)
irq_timer <= irq_timer - 8'b1;
/////////////////////////// MEMORY MAP /////////////////////
// 0000 - 1FFF - WRAM
// 2000 - 202F - CTRL
// 2030 - 3FFF - CTRL - mirrors ??
// 4000 - 5FFF - VRAM ??
// 6000 - 7FFF - VRAM - mirrors ??
// 8000 - BFFF - banks
// C000 - FFFF - last 16k of cartridge
wire wram_cs = AB ==? 16'b000x_xxxx_xxxx_xxxx;
wire lcd_cs = AB ==? 16'b0010_0000_0000_0xxx; // match 2000-2007 LCD control registers
wire dma_cs = AB ==? 16'b0010_0000_0000_1xxx; // match 2008-200F DMA control registers
wire snd_cs = AB ==? 16'b0010_0000_0001_xxxx; // match 2010-201F sound registers
wire sys_cs = AB ==? 16'b0010_0000_0010_0xxx; // match 2020-2027 sys registers
wire noi_cs = AB ==? 16'b0010_0000_0010_1xxx; // match 2028-202F sound registers (noise)
wire vram_cs = AB ==? 16'b01xx_xxxx_xxxx_xxxx;
wire rom_cs = AB ==? 16'b1xxx_xxxx_xxxx_xxxx;
wire rom_hi = AB ==? 16'b11xx_xxxx_xxxx_xxxx;
wire [15:0] AB = dma_busy ? { 2'b0, dma_addr } : cpu_addr;
reg [7:0] DI;
wire [7:0] DO = dma_busy ? dma_dout : cpu_dout;
wire wram_we = wram_cs ? dma_busy ? ~dma_write : ~cpu_we : 1'b1;
wire vram_we = vram_cs ? dma_busy ? ~dma_write : ~cpu_we : 1'b1;
wire [15:0] rom_addr = rom_hi ? AB : { sys_ctl[6:5], AB[13:0] };
always @(posedge clk_cpu)
DI <= sys_cs ? sys_dout :
wram_cs ? wram_dout :
vram_cs ? vram_dout :
rom_cs ? rom_dout : 8'hff;
// write to lcd registers
always @(posedge clk_sys)
if (lcd_cs && cpu_we) begin
case (AB[1:0])
2'h0: lcd_xsize <= cpu_dout;
2'h1: lcd_ysize <= cpu_dout;
2'h2: lcd_xscroll <= cpu_dout;
2'h3: lcd_yscroll <= cpu_dout;
endcase
end
// write to audio registers
always @(posedge clk_sys)
if (snd_cs && cpu_we) begin
case (AB[3:0])
4'h0: ch1_freq_low <= cpu_dout;
4'h1: ch1_freq_hi <= cpu_dout;
4'h2: ch1_vduty <= cpu_dout;
4'h3: ch1_length <= cpu_dout;
4'h4: ch2_freq_low <= cpu_dout;
4'h5: ch2_freq_hi <= cpu_dout;
4'h6: ch2_vduty <= cpu_dout;
4'h7: ch2_length <= cpu_dout;
4'h8: audio_dma_addr_low <= cpu_dout;
4'h9: audio_dma_addr_high <= cpu_dout;
4'ha: audio_dma_length <= cpu_dout;
4'hb: audio_dma_ctrl <= cpu_dout;
4'hc: audio_dma_trigger <= cpu_dout;
endcase
end
// write to noise registers
always @(posedge clk_sys)
if (noi_cs && cpu_we) begin
case (AB[2:0])
3'h0: noise_freq_vol <= cpu_dout;
3'h1: noise_length <= cpu_dout;
3'h2: noise_ctrl <= cpu_dout;
endcase
end
// write to dma registers
//CAUTION: This DMA can only be used to move data from WRAM/cartridge ROM to VRAM!
//Attempting to move data to a non-VRAM address will cause serious problems to occur.
//See my findings at the bottom of the document in the DMA timing section.
always @(posedge clk_sys)
if (dma_cs && cpu_we)
case (AB[2:0])
3'h0: dma_src_lo <= cpu_dout;//DMA Source low
3'h1: dma_src_hi <= cpu_dout;//DMA Source high
3'h2: dma_dst_lo <= cpu_dout;//DMA Destination low
3'h3: dma_dst_hi <= cpu_dout;//DMA Destination high
3'h4: dma_length <= cpu_dout;//DMA Length
3'h5: dma_ctrl <= cpu_dout;//DMA Control
default:
dma_ctrl <= 8'd0;
endcase
// write to sys registers
always @(posedge clk_sys)
if (sys_cs && cpu_we)
case (AB[2:0])
// 3'h3: irq_timer = cpu_dout;
3'h6: sys_ctl <= cpu_dout;
endcase
// read sys registers
always @(posedge clk_sys)
if (sys_cs && ~cpu_we)
case (AB[2:0])
3'h0: sys_dout <= {
~joystick[7],
~joystick[6],
~joystick[5],
~joystick[4],
~joystick[3],
~joystick[2],
~joystick[1],
~joystick[0]
};
3'h3: sys_dout <= irq_timer;
3'h6: sys_dout <= sys_ctl;
endcase
////////////////////////////////////////////////
//rom cart(
// .clk(clk_sys),
// .addr(rom_addr),
// .dout(rom_dout),
// .cs(~rom_cs),
// .rom_init(ioctl_download),
// .rom_init_clk(clk_sys),
// .rom_init_address(ioctl_addr),
// .rom_init_data(ioctl_dout)
//);
assign cpu_rom_addr = rom_addr;
assign rom_dout = cpu_rom_data;
ram88 wram(
.clk(clk_sys),
.addr(AB[12:0]),
.din(DO), // <= cpu or dma
.dout(wram_dout),
.we(wram_we),
.cs(~wram_cs)
);
// dual port ram
ram88 vram(
.clk(clk_sys),
.addr(AB[12:0]),
.din(DO), // <= cpu or dma
.dout(vram_dout),
.addrb(lcd_addr),
.doutb(lcd_din),
.we(vram_we),
.cs(~vram_cs)
);
dma dma(
.clk(clk_sys),
.rdy(dma_rdy),
.irq_dma(irq_dma),
.ctrl(dma_ctrl),
.src_addr({ dma_src_hi, dma_src_lo }),
.dst_addr({ dma_dst_hi, dma_dst_lo }),
.addr(dma_addr), // => to AB
.din(DI),
.dout(dma_dout),
.length(dma_length),
.busy(dma_busy),
.sel(dma_sel),
.write(dma_write)
);
audio audio(
.clk(clk_sys),
.CH1_freq({ ch1_freq_hi[2:0], ch1_freq_low }),
.CH1_vduty(ch1_vduty),
.CH1_length(ch1_length),
.CH2_freq({ ch2_freq_hi[2:0], ch2_freq_low }),
.CH2_vduty(ch2_vduty),
.CH2_length(ch2_length),
.DMA_addr({ audio_dma_addr_high, audio_dma_addr_low }),
.DMA_length(audio_dma_length),
.DMA_ctrl(audio_dma_ctrl),
.DMA_trigger(audio_dma_trigger),
.noise_freq_vol(noise_freq_vol),
.noise_length(noise_length),
.noise_ctrl(noise_ctrl),
.CH1(audio_ch1),
.CH2(audio_ch2)
);
video video(
.clk(clk_vid),
.ce(sys_ctl[3]),
.white(white),
.lcd_xsize(lcd_xsize),
.lcd_ysize(lcd_ysize),
.lcd_xscroll(lcd_xscroll),
.lcd_yscroll(lcd_yscroll),
.lcd_pulse(lcd_pulse),
.addr(lcd_addr),
.data(lcd_din),
.hsync(hsync),
.vsync(vsync),
.hblank(hblank),
.vblank(vblank),
.red(red),
.green(green),
.blue(blue)
);
cpu_65c02 cpu(
.clk(clk_cpu),
.reset(reset),
.AB(cpu_addr),
.DI(DI),
.DO(cpu_dout),
.WE(cpu_we),
.IRQ(irq_tim | irq_dma),
.NMI(nmi),
.RDY(cpu_rdy)
);
endmodule

304
Console_MiST/Supervision_MiST/rtl/audio.sv
View File

@@ -1,102 +1,236 @@
module audio (
input clk, // clk_sys
input clk, // clk_sys
input ce,
input reset,
input snd_cs,
input cpu_rwn,
input [5:0] AB,
input [7:0] dbus_in,
input [15:0] prescaler,
input adma_irq_en,
input [9:0] CH1_freq,
input [7:0] CH1_vduty,
input [7:0] CH1_length,
output reg [15:0] adma_addr,
output reg adma_irq_n,
output reg adma_read,
output [2:0] adma_bank,
input [9:0] CH2_freq,
input [7:0] CH2_vduty,
input [7:0] CH2_length,
input [7:0] DMA_addr,
input [7:0] DMA_length,
input [7:0] DMA_ctrl,
input [7:0] DMA_trigger,
input [7:0] noise_freq_vol,
input [7:0] noise_length,
input [7:0] noise_ctrl,
output [3:0] CH1,
output [3:0] CH2
output [3:0] CH1,
output [3:0] CH2
);
typedef enum bit[5:0] {
CH1_FREQ_LOW = 6'h10,
CH1_FREQ_HIGH = 6'h11,
CH1_VDUTY = 6'h12,
CH1_FRAME_LEN = 6'h13,
CH2_FREQ_LOW = 6'h14,
CH2_FREQ_HIGH = 6'h15,
CH2_VDUTY = 6'h16,
CH2_FRAME_LEN = 6'h17,
ADMA_ADDR_LO = 6'h18,
ADMA_ADDR_HI = 6'h19,
ADMA_LENGTH = 6'h1A,
ADMA_CONFIG = 6'h1B,
ADMA_REQ = 6'h1C,
ADMA_ACK = 6'h25,
NOISE_VDIV = 6'h28,
NOISE_LENGTH = 6'h29,
NOISE_CONFIG = 6'h2A
} apu_reg_t;
reg [23:0] clk_cnt;
reg pulse;
reg clk_audio;
reg [15:0] prescaler;
reg prescaler_overflow;
// 50000/125=400/2=200 2^24/200=83886
always @(posedge clk)
{ pulse, clk_cnt } <= clk_cnt + 24'd83886;
always @(posedge pulse)
clk_audio <= ~clk_audio;
always @(posedge clk)
{ prescaler_overflow, prescaler } <= prescaler + 16'd1;
reg [16:0] CH1_sum, CH2_sum;
reg [16:0] CH1_dc, CH2_dc; // duty cycle
reg ch1_mute, ch2_mute, noise_mute;
reg [14:0] lfsr;
reg [10:0] ch1_freq, ch2_freq;
reg [3:0] adma_phase;
reg [7:0] adma_config, adma_length, adma_sample;
reg adma_sample_pending, adma_active;
reg CH1_sw, CH2_sw; // square wave
reg [7:0] CH1_dlength, CH2_dlength, CH1_timer, CH2_timer;
reg [7:0] noise_vdiv, noise_timer, noise_config, ch1_vdiv, ch2_vdiv;
reg [7:0] CH1_dlength, CH2_dlength, ch1_timer, ch2_timer;
reg [16:0] CH1_sum, CH2_sum, noise_sum, adma_sum;
wire [3:0] CH1_out = CH1_sw ? CH1_vduty[3:0] : 4'd0;
wire [3:0] CH2_out = CH2_sw ? CH2_vduty[3:0] : 4'd0;
wire CH1_en = CH1_timer || CH1_vduty[6] ? 1'b1 : 1'b0;
wire CH2_en = CH2_timer || CH2_vduty[6] ? 1'b1 : 1'b0;
assign CH1 = CH1_en ? CH1_out : 4'd0;
assign CH2 = CH2_en ? CH2_out : 4'd0;
wire [3:0] CH1_dc, CH2_dc; // duty cycle
wire [3:0] adma_out = adma_sample_pending ? adma_sample[7:4] : adma_sample[3:0];
wire [16:0] noise_div = (17'd8 << noise_vdiv[7:4]) - 1'd1;
wire lfsr_next = noise_config[0] ? (lfsr[14] ^ lfsr[13]) : (lfsr[6] ^ lfsr[5]);
always @(posedge clk) begin
if (prescaler_overflow && CH1_timer > 8'd0) CH1_timer <= CH1_timer - 8'd1;
if (prescaler_overflow && CH2_timer > 8'd0) CH2_timer <= CH2_length - 8'd1;
if (CH1_dlength != CH1_length) begin
CH1_dlength <= CH1_length;
CH1_timer <= CH1_length;
end
if (CH2_dlength != CH2_length) begin
CH2_dlength <= CH2_length;
CH2_timer <= CH2_length;
end
wire [3:0] CH1_out = CH1_sw ? ch1_vdiv[3:0] : 4'd0;
wire [3:0] CH2_out = CH2_sw ? ch2_vdiv[3:0] : 4'd0;
wire [3:0] noise_out = lfsr_next ? noise_vdiv[3:0] : 4'd0;
wire CH1_en = ~ch1_mute || ch1_vdiv[6] ? 1'b1 : 1'b0;
wire CH2_en = ~ch2_mute || ch2_vdiv[6] ? 1'b1 : 1'b0;
wire noise_en = ~noise_mute || noise_config[1] ? noise_config[4] : 1'b0;
// Clamp to 4 bits (real system had a 4 bit dac and did this)
wire [5:0] ch1_unclamped = (CH1_en ? CH1_out : 6'd0) + (adma_active && adma_config[2] ? adma_out : 6'd0) + (noise_en && noise_config[2] ? noise_out : 6'd0);
wire [5:0] ch2_unclamped = (CH2_en ? CH2_out : 6'd0) + (adma_active && adma_config[3] ? adma_out : 6'd0) + (noise_en && noise_config[3] ? noise_out : 6'd0);
assign CH1 = |ch1_unclamped[5:4] ? 4'hF : ch1_unclamped[3:0];
assign CH2 = |ch2_unclamped[5:4] ? 4'hF : ch2_unclamped[3:0];
assign adma_bank = adma_config[6:4];
always_comb begin
case (ch1_vdiv[5:4])
2'b00: CH1_dc = 4'd1; // 12.5%
2'b01: CH1_dc = 4'd3; // 25%
2'b10: CH1_dc = 4'd7; // 50%
2'b11: CH1_dc = 4'd11; // 75%
endcase
case (ch2_vdiv[5:4])
2'b00: CH2_dc = 4'd1; // 12.5%
2'b01: CH2_dc = 4'd3; // 25%
2'b10: CH2_dc = 4'd7; // 50%
2'b11: CH2_dc = 4'd11; // 75%
endcase
end
always @*
case (CH1_vduty[5:4])
2'b00: CH1_dc = 17'd15240; // 12.5%
2'b01: CH1_dc = 17'd31750; // 25%
2'b10: CH1_dc = 17'd63500; // 50%
2'b11: CH1_dc = 17'd95250; // 75%
endcase
always_ff @(posedge clk) begin : audio_clock
always @*
case (CH2_vduty[5:4])
2'b00: CH2_dc = 17'd15240; // 12.5%
2'b01: CH2_dc = 17'd31750; // 25%
2'b10: CH2_dc = 17'd63500; // 50%
2'b11: CH2_dc = 17'd95250; // 75%
endcase
reg sys_div;
reg ch1_clk;
reg ch2_clk;
reg [3:0] ch1_phase;
reg [3:0] ch2_phase;
reg old_ps15;
always @(posedge clk_audio) begin
CH1_sum <= CH1_sum + { 7'd0, CH1_freq };
if (CH1_sum >= CH1_dc) begin
CH1_sum <= 17'd0;
CH1_sw = ~CH1_sw;
end
if (ce) begin // CPU CLK
sys_div <= ~sys_div;
old_ps15 <= prescaler[15];
if (old_ps15 && ~prescaler[15]) begin
if (|ch1_timer)
ch1_timer <= ch1_timer - 8'd1;
if (~|ch1_timer[7:1])
ch1_mute <= 1;
if (|ch2_timer > 8'd0)
ch2_timer <= ch2_timer - 8'd1;
if (~|ch2_timer[7:1])
ch2_mute <= 1;
if (|noise_timer > 8'd0)
noise_timer <= noise_timer - 8'd1;
if (~|noise_timer[7:1])
noise_mute <= 1;
end
noise_sum <= noise_sum + 1'd1;
if (noise_sum >= noise_div) begin
lfsr <= {lfsr[13:0], lfsr_next};
noise_sum <= 0;
end
if (sys_div) begin
CH1_sum <= CH1_sum + 1'd1;
CH2_sum <= CH2_sum + 1'd1;
if (CH1_sum == ch1_freq) begin
CH1_sum <= 0;
ch1_phase <= ch1_phase + 1'd1;
if (ch1_phase == CH1_dc)
CH1_sw <= 0;
else if (ch1_phase == 15)
CH1_sw <= 1;
end
if (CH2_sum == ch2_freq) begin
CH2_sum <= 0;
ch2_phase <= ch2_phase + 1'd1;
if (ch2_phase == CH2_dc)
CH2_sw <= 0;
else if (ch2_phase == 15)
CH2_sw <= 1;
end
end
if (adma_read) begin
adma_read <= 0;
adma_sample <= dbus_in;
end
if (adma_active) begin
adma_sum <= adma_sum + 1'd1;
if (adma_sum >= ((17'd256 << adma_config[1:0]) - 1'd1)) begin
adma_sum <= 0;
if (adma_sample_pending) begin
adma_sample_pending <= 0;
end else begin
adma_addr <= adma_addr + 1'd1;
adma_sample_pending <= 1;
adma_read <= 1;
adma_phase <= adma_phase - 1'd1;
if (~|adma_phase) begin
adma_length <= adma_length - 1'd1;
if (adma_length == 1) begin
adma_read <= 0;
adma_irq_n <= 0;
adma_active <= 0;
end
end
end
end
end
if (snd_cs) begin
if (~cpu_rwn) begin
case (AB)
CH1_FREQ_LOW: begin ch1_freq[7:0] <= dbus_in; CH1_sum <= 0; end
CH1_FREQ_HIGH: begin ch1_freq[10:8] <= dbus_in[2:0]; CH1_sum <= 0; end
CH1_VDUTY: begin ch1_vdiv <= dbus_in; if (dbus_in[6] && ch1_timer > 0) CH1_sum <= 0; end
CH1_FRAME_LEN: begin ch1_timer <= dbus_in; if (dbus_in != 0) ch1_mute <= 0; end
CH2_FREQ_LOW: begin ch2_freq[7:0] <= dbus_in; CH2_sum <= 0; end
CH2_FREQ_HIGH: begin ch2_freq[10:8] <= dbus_in[2:0]; CH2_sum <= 0; end
CH2_VDUTY: begin ch2_vdiv <= dbus_in; if (dbus_in[6] && ch2_timer > 0) CH2_sum <= 0; end
CH2_FRAME_LEN: begin ch2_timer <= dbus_in; if (dbus_in != 0) ch2_mute <= 0; end
ADMA_ADDR_LO: begin adma_addr[7:0] <= dbus_in; end
ADMA_ADDR_HI: begin adma_addr[15:8] <= dbus_in; end
ADMA_LENGTH: begin adma_length <= dbus_in;
if (adma_active) begin
if (dbus_in == 0) begin
adma_length <= 0;
adma_active <= 0;
adma_irq_n <= 0;
end
end
end
ADMA_CONFIG: begin adma_config <= dbus_in; end
ADMA_REQ: begin adma_active <= dbus_in[7]; adma_phase <= 4'd15; adma_sample <= 0; adma_read <= 1; adma_sample_pending <= 1; end
ADMA_ACK: begin adma_irq_n <= 1; end
NOISE_VDIV, 6'h2c: begin noise_vdiv <= dbus_in; end
NOISE_LENGTH, 6'h2d: begin noise_timer <= dbus_in; if (dbus_in != 0) noise_mute <= 0; end
NOISE_CONFIG, 6'h2E: begin noise_config <= dbus_in; lfsr <= 15'h7FFF; noise_sum <= 0; end
endcase
end else begin
if (AB == ADMA_ACK)
adma_irq_n <= 1;
end
end
end
if (reset) begin
adma_sample_pending <= 0;
adma_sample <= 0;
adma_read <= 0;
ch1_mute <= 0;
ch2_mute <= 0;
noise_mute <= 0;
adma_active <= 0;
adma_irq_n <= 1;
noise_config <= 0;
noise_timer <= 0;
noise_vdiv <= 0;
ch1_vdiv <= 0;
ch2_vdiv <= 0;
ch1_freq <= 0;
ch2_freq <= 0;
ch1_timer <= 0;
ch2_timer <= 0;
end
end
always @(posedge clk_audio) begin
CH2_sum <= CH2_sum + { 7'd0, CH2_freq };
if (CH2_sum >= CH2_dc) begin
CH2_sum <= 17'd0;
CH2_sw = ~CH2_sw;
end
end
endmodule
endmodule

236
Console_MiST/Supervision_MiST/rtl/bram.vhd Normal file
View File

@@ -0,0 +1,236 @@
--------------------------------------------------------------
-- Single port Block RAM
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width : integer := 8;
data_width : integer := 8;
mem_init_file : string := " ";
mem_name : string := "MEM" -- for InSystem Memory content editor.
);
PORT
(
clock : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable : in STD_LOGIC := '1';
wren : in STD_LOGIC := '0';
q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs : in std_logic := '1'
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
spram_sz : work.spram_sz
generic map(addr_width, data_width, 2**addr_width, mem_init_file, mem_name)
port map(clock,address,data,enable,wren,q,cs);
END SYN;
--------------------------------------------------------------
-- Single port Block RAM with specific size
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram_sz IS
generic (
addr_width : integer := 8;
data_width : integer := 8;
numwords : integer := 2**8;
mem_init_file : string := " ";
mem_name : string := "MEM" -- for InSystem Memory content editor.
);
PORT
(
clock : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable : in STD_LOGIC := '1';
wren : in STD_LOGIC := '0';
q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs : in std_logic := '1'
);
END ENTITY;
ARCHITECTURE SYN OF spram_sz IS
signal q0 : std_logic_vector((data_width - 1) downto 0);
BEGIN
q<= q0 when cs = '1' else (others => '1');
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME="&mem_name,
lpm_type => "altsyncram",
numwords_a => numwords,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
init_file => mem_init_file,
widthad_a => addr_width,
width_a => data_width,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren and cs,
q_a => q0
);
END SYN;
--------------------------------------------------------------
-- Dual port Block RAM same parameters on both ports
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
addr_width : integer := 8;
data_width : integer := 8;
mem_init_file : string := " "
);
PORT
(
clock : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data_a : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable_a : in STD_LOGIC := '1';
wren_a : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs_a : in std_logic := '1';
address_b : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0) := (others => '0');
data_b : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable_b : in STD_LOGIC := '1';
wren_b : in STD_LOGIC := '0';
q_b : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs_b : in std_logic := '1'
);
end entity;
ARCHITECTURE SYN OF dpram IS
BEGIN
ram : work.dpram_dif generic map(addr_width,data_width,addr_width,data_width,mem_init_file)
port map(clock,address_a,data_a,enable_a,wren_a,q_a,cs_a,address_b,data_b,enable_b,wren_b,q_b,cs_b);
END SYN;
--------------------------------------------------------------
-- Dual port Block RAM different parameters on ports
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram_dif is
generic (
addr_width_a : integer := 8;
data_width_a : integer := 8;
addr_width_b : integer := 8;
data_width_b : integer := 8;
mem_init_file : string := " "
);
PORT
(
clock : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (addr_width_a-1 DOWNTO 0);
data_a : in STD_LOGIC_VECTOR (data_width_a-1 DOWNTO 0) := (others => '0');
enable_a : in STD_LOGIC := '1';
wren_a : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (data_width_a-1 DOWNTO 0);
cs_a : in std_logic := '1';
address_b : in STD_LOGIC_VECTOR (addr_width_b-1 DOWNTO 0) := (others => '0');
data_b : in STD_LOGIC_VECTOR (data_width_b-1 DOWNTO 0) := (others => '0');
enable_b : in STD_LOGIC := '1';
wren_b : in STD_LOGIC := '0';
q_b : out STD_LOGIC_VECTOR (data_width_b-1 DOWNTO 0);
cs_b : in std_logic := '1'
);
end entity;
ARCHITECTURE SYN OF dpram_dif IS
signal q0 : std_logic_vector((data_width_a - 1) downto 0);
signal q1 : std_logic_vector((data_width_b - 1) downto 0);
BEGIN
q_a<= q0 when cs_a = '1' else (others => '1');
q_b<= q1 when cs_b = '1' else (others => '1');
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_a,
numwords_b => 2**addr_width_b,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
init_file => mem_init_file,
widthad_a => addr_width_a,
widthad_b => addr_width_b,
width_a => data_width_a,
width_b => data_width_b,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock,
clock1 => clock,
clocken0 => enable_a,
clocken1 => enable_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a and cs_a,
wren_b => wren_b and cs_b,
q_a => q0,
q_b => q1
);
END SYN;

128
Console_MiST/Supervision_MiST/rtl/dma.sv
View File

@@ -1,77 +1,63 @@
module dma(
input clk, // 4 x CPU speed ?
input rdy,
output irq_dma,
input [7:0] ctrl,
input [15:0] src_addr,
input [15:0] dst_addr,
output reg [15:0] addr,
input [7:0] din,
output reg [7:0] dout,
input [7:0] length,
output busy,
output sel, // 1: src -> dst, 2: src <- dst
output write
module dma
(
input clk,
input ce,
input reset,
input [5:0] AB,
input cpu_rwn,
input dma_cs,
input lcd_en,
input [7:0] data_in,
output reg [15:0] cbus_addr,
output reg [12:0] vbus_addr,
output reg dma_dir,
output dma_en
);
reg [11:0] queue;
reg [12:0] addr_a, addr_b;
reg started;
assign irq_dma = 1'b1;
reg dma_started;
reg [7:0] dma_length;
reg [3:0] dma_phase;
reg [2:0] lcd_div;
assign sel = dst_addr[14];
assign busy = state != DONE;
assign write = state == WRITE;
reg [1:0] state;
assign dma_en = dma_started;
wire lcd_ce = lcd_div == 5 && lcd_en;
parameter
DONE = 2'b00,
START = 2'b01,
READ = 2'b10,
WRITE = 2'b11;
always_ff @(posedge clk) begin
if (ce) begin
lcd_div <= lcd_div + 1'd1;
if (lcd_div == 5)
lcd_div <= 0;
always @(posedge clk)
started <= ctrl[7] ? 1'b1 : 1'b0;
if (dma_started && ~lcd_ce) begin
cbus_addr <= cbus_addr + 1'd1;
vbus_addr <= vbus_addr + 1'd1;
dma_phase <= dma_phase - 1'd1;
if (~|dma_phase) begin
dma_length <= dma_length - 1'd1;
if (dma_length == 1) begin
dma_started <= 0;
end
end
end
always @(posedge clk)
if (rdy)
case (state)
DONE: if (~started & ctrl[7]) state <= START;
START: state <= READ;
READ: state <= WRITE;
WRITE: state <= queue == 0 ? DONE : READ;
endcase
always @(posedge clk)
if (rdy)
case (state)
START: queue <= { length, 4'd0 };
WRITE: queue <= queue - 12'b1;
endcase
always @(posedge clk)
if (rdy)
case (state)
READ: addr <= addr_a;
WRITE: addr <= addr_b;
endcase
always @(posedge clk)
if (rdy && state == WRITE) dout <= din;
always @(posedge clk)
if (rdy)
case (state)
START: begin
addr_a <= sel ? src_addr[12:0] : dst_addr[12:0];
addr_b <= sel ? dst_addr[12:0] : src_addr[12:0];
end
WRITE: begin
addr_a <= addr_a + 13'b1;
addr_b <= addr_b + 13'b1;
end
endcase
endmodule
if (~cpu_rwn && dma_cs) begin
case(AB)
6'h08: cbus_addr[7:0] <= data_in;
6'h09: cbus_addr[15:8] <= data_in;
6'h0A: vbus_addr[7:0] <= data_in;
6'h0B: {dma_dir, vbus_addr[12:8]} <= {data_in[6], data_in[4:0]};
6'h0C: dma_length <= data_in;
6'h0D: if (data_in[7]) begin dma_started <= 1; dma_phase <= 4'd15; end
endcase
end
end
if (reset) begin
dma_started <= 0;
dma_length <= 0;
vbus_addr <= 0;
cbus_addr <= 0;
lcd_div <= 0;
dma_dir <= 0;
end
end
endmodule

123
Console_MiST/Supervision_MiST/rtl/lcd.sv Normal file
View File

@@ -0,0 +1,123 @@
module lcd
(
input clk,
input ce,
input reset,
input lcd_cs,
input cpu_rwn,
input compat60,
input [5:0] AB,
input [7:0] dbus_in,
input [7:0] vram_data,
input lcd_off,
output ce_pix,
output reg [1:0]pixel,
output [13:0] vram_addr,
output hsync,
output vsync,
output reg hblank,
output reg vblank
);
localparam H_WIDTH = 9'd300;
localparam H_WIDTH_COMPAT = 9'd254;
localparam V_HEIGHT = 9'd262;
localparam PHYS_WIDTH = 9'd160;
localparam PHYS_HEIGHT = 9'd160;
wire [8:0] h_w = compat60 ? H_WIDTH_COMPAT : H_WIDTH;
reg [7:0] lcd_xsize, lcd_ysize, lcd_xscroll, lcd_yscroll;
reg lcd_off_latch;
reg wrapped;
reg [9:0] wrap_offset;
reg [8:0] hblank_start, hblank_end, vblank_start, vblank_end, vpos, hpos;
reg [31:0] dot_count, frame_len;
wire [9:0] vpos_off = (vpos - vblank_end) + lcd_yscroll;
wire [9:0] hpos_off = (hpos - hblank_end) + lcd_xscroll;
wire [9:0] vpos_wrap = vpos_off > 169 && lcd_xscroll < 8'h1C ? vpos_off - 10'd170 : vpos_off;
wire [7:0] hpos_div_4 = hpos_off[9:2];
wire [13:0] vram_addr_t = (vpos_wrap * 8'h30) + hpos_div_4;
// The lcd does a weird trunction of any extra bits past the end of it's buffer to make the 192x170
// dimensions work, while the memory is 8kb. This is intentionally truncated to 12 bits.
assign vram_addr = vram_addr_t > 14'h1FE0 ? (vram_addr_t + 8'h40) : vram_addr_t[12:0];
initial begin
hblank_end = 8'd70;
vblank_end = 8'd51;
vpos = 0;
hpos = 0;
lcd_xsize = 8'd160;
lcd_ysize = 8'd160;
frame_len = 20'd78719;
end
assign ce_pix = ce;
reg [7:0] vb;
wire hblank_im = hpos <= hblank_end || hpos > hblank_end + PHYS_WIDTH;
wire vblank_im = vpos < vblank_end || vpos >= vblank_end + PHYS_HEIGHT;
assign vsync = vpos < 2 || vpos > V_HEIGHT - 1'd1; // Catch the uneven line in vsync to see if it helps
assign hsync = hpos < 16 || hpos > (h_w - 8'd16);
always_ff @(posedge clk) begin
reg old_compat;
if (ce) begin
old_compat <= compat60;
hblank <= hblank_im;
vblank <= vblank_im;
pixel <= lcd_off_latch ? 2'b00 : vram_data[{hpos_off[1:0], 1'b1}-:2];
if (lcd_off)
lcd_off_latch <= 1;
dot_count <= dot_count + 1'd1;
hpos <= hpos + 1'd1;
if (hpos == (h_w - 1'd1)) begin
hpos <= 0;
vpos <= vpos + 1'd1;
end
// Synchronize with real frame, we'll see how it goes.
if ((compat60 ?
(hpos == (h_w - 1'd1) && vpos == (V_HEIGHT - 1'd1)) :
(dot_count >= frame_len)
) || (old_compat != compat60)) begin
hpos <= 0;
vpos <= 0;
dot_count <= 0;
hblank_end <= (h_w - PHYS_WIDTH) >> 1'd1;
vblank_end <= (V_HEIGHT - PHYS_HEIGHT) >> 1'd1;
lcd_off_latch <= lcd_off;
frame_len <= ((lcd_xsize[7:2] + 1'd1) * lcd_ysize * 12) - 1'd1;
end
if (lcd_cs && ~cpu_rwn) begin
case(AB)
6'h00, 6'h04: lcd_xsize <= dbus_in;
6'h01, 6'h05: lcd_ysize <= dbus_in;
6'h02, 6'h06: lcd_xscroll <= dbus_in;
6'h03, 6'h07: lcd_yscroll <= dbus_in;
endcase
end
end
if (reset) begin
lcd_xscroll <= 0;
lcd_yscroll <= 0;
hblank_end <= (h_w - lcd_xsize) >> 1'd1;
vblank_end <= (V_HEIGHT - lcd_ysize) >> 1'd1;
lcd_off_latch <= 1;
// Do not reset these registers intentionally
// lcd_xsize <= 8'd160;
// lcd_ysize <= 8'd160;
end
end
endmodule

4
Console_MiST/Supervision_MiST/rtl/pll2.qip → Console_MiST/Supervision_MiST/rtl/pll.qip
View File

@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll2.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2.ppf"]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

397
Console_MiST/Supervision_MiST/rtl/pll.vhd Normal file
View File

@@ -0,0 +1,397 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 56,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 16,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "56.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "56"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "56.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "56"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

348
Console_MiST/Supervision_MiST/rtl/pll1.v
View File

@@ -1,348 +0,0 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll1.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll1 (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 20,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 27,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 4,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "60.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "4.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "60.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "4.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

320
Console_MiST/Supervision_MiST/rtl/pll2.v
View File

@@ -1,320 +0,0 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll2.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll2 (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 44,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 41,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "44"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.159090"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "44"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

23
Console_MiST/Supervision_MiST/rtl/ram88.sv
View File

@@ -1,23 +0,0 @@
module ram88 (
input clk,
input [12:0] addr,
input [12:0] addrb,
input [7:0] din,
input we,
input cs,
output reg [7:0] dout,
output reg [7:0] doutb
);
reg [7:0] memory[8191:0] /*verilator public_flat_rd*/;
always @(posedge clk) begin
if (~cs) begin
if (~we) memory[addr] <= din;
dout <= memory[addr];
end
doutb <= memory[addrb];
end
endmodule

22
Console_MiST/Supervision_MiST/rtl/rom.v
View File

@@ -1,22 +0,0 @@
module rom (
input clk,
input [15:0] addr,
output reg [7:0] dout,
input cs,
input rom_init,
input rom_init_clk,
input [15:0] rom_init_address,
input [7:0] rom_init_data
);
reg [7:0] memory[65535:0];
always @(posedge clk)
if (~cs) dout <= memory[addr];
always @(posedge rom_init_clk)
if (rom_init)
memory[rom_init_address] <= rom_init_data;
endmodule

427
Console_MiST/Supervision_MiST/rtl/sdram.sv
View File

@@ -1,12 +1,10 @@
//
// sdram.v
// This version issues refresh only when 8bit channel reads the same 16bit word 2 times
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
// sdram controller implementation
// Copyright (c) 2018 Sorgelig
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
@@ -21,222 +19,269 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
module sdram
(
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
output reg SDRAM_DQML, // byte mask
output reg SDRAM_DQMH, // byte mask
output reg [1:0] SDRAM_BA, // two banks
output reg SDRAM_nCS, // a single chip select
output reg SDRAM_nWE, // write enable
output reg SDRAM_nRAS, // row address select
output reg SDRAM_nCAS, // columns address select
output SDRAM_CLK,
output SDRAM_CKE,
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input init, // init signal after FPGA config to initialize RAM
input clk, // sdram is accessed at up to 128MHz
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output [15:0] port1_q,
input [24:0] ch0_addr,
input ch0_rd,
input ch0_wr,
input [7:0] ch0_din,
output reg [7:0] ch0_dout,
output reg ch0_busy,
input [17:1] cpu1_addr,
output reg [15:0] cpu1_q
input [24:0] ch1_addr,
input ch1_rd,
input ch1_wr,
input [7:0] ch1_din,
output reg [7:0] ch1_dout,
output reg ch1_busy,
input [24:0] ch2_addr,
input ch2_rd,
input ch2_wr,
input [7:0] ch2_din,
output reg [7:0] ch2_dout,
output reg ch2_busy
);
parameter MHZ = 80; // 80 MHz default clock, adjust to calculate the refresh rate correctly
assign SDRAM_nCS = 0;
assign SDRAM_CKE = 1;
assign {SDRAM_DQMH,SDRAM_DQML} = SDRAM_A[12:11];
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam RASCAS_DELAY = 3'd1; // tRCD=20ns -> 2 cycles@85MHz
localparam BURST_LENGTH = 3'd0; // 0=1, 1=2, 2=4, 3=8, 7=full page
localparam ACCESS_TYPE = 1'd0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'd0; // only 0 (standard operation) allowed
localparam NO_WRITE_BURST = 1'd1; // 0=write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 16'd78*MHZ/10;
localparam STATE_IDLE = 3'd0; // state to check the requests
localparam STATE_START = STATE_IDLE+1'd1; // state in which a new command is started
localparam STATE_NEXT = STATE_START+1'd1; // state in which a new command is started
localparam STATE_CONT = STATE_START+RASCAS_DELAY;
localparam STATE_READY = STATE_CONT+CAS_LATENCY+2'd2;
localparam STATE_LAST = STATE_READY; // last state in cycle
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
reg [2:0] state;
reg [22:0] a;
reg [1:0] bank;
reg [15:0] data;
reg we;
reg ram_req=0;
/*
SDRAM state machine
1 word burst, CL2
cmd issued registered
0 RAS0 data ready
1
2 CAS0
3
4
5 DATA0
*/
wire [2:0] rd,wr;
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 2
localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 2'd2; // 6
localparam STATE_LAST = 3'd5;
reg [2:0] t;
assign rd = {ch2_rd, ch1_rd, ch0_rd};
assign wr = {ch2_wr, ch1_wr, ch0_wr};
// access manager
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
reg old_ref;
reg [2:0] old_rd,old_wr;//,rd,wr;
reg [24:1] last_a[3] = '{'1,'1,'1};
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
old_rd <= old_rd & rd;
old_wr <= old_wr & wr;
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch;
reg [24:1] addr_latch_next;
reg [17:1] addr_last;
reg [15:0] din_latch;
reg oe_latch;
reg we_latch;
reg [1:0] ds;
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_REQ = 2'd2;
reg [2:0] next_port;
reg [2:0] port;
reg port1_state;
// PORT1
always @(*) begin
if (port1_req ^ port1_state) begin
next_port = PORT_REQ;
addr_latch_next = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last) begin
next_port = PORT_CPU1;
addr_latch_next = { 7'd0, cpu1_addr };
end else begin
next_port = PORT_NONE;
addr_latch_next = addr_latch;
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
if(state == STATE_IDLE && mode == MODE_NORMAL) begin
ram_req <= 0;
we <= 0;
ch0_busy <= 0;
ch1_busy <= 0;
ch2_busy <= 0;
if((~old_rd[0] & rd[0]) | (~old_wr[0] & wr[0])) begin
old_rd[0] <= rd[0];
old_wr[0] <= wr[0];
we <= wr[0];
{bank,a} <= ch0_addr;
data <= {ch0_din,ch0_din};
ram_req <= wr[0] || (last_a[0] != ch0_addr[24:1]);
last_a[0] <= wr[0] ? '1 : ch0_addr[24:1];
ch0_busy <= 1;
state <= STATE_START;
end
end else begin
// RAS phase
if(t == STATE_RAS0) begin
addr_latch <= addr_latch_next;
port <= next_port;
{ oe_latch, we_latch } <= 2'b00;
else if((~old_rd[1] & rd[1]) | (~old_wr[1] & wr[1])) begin
old_rd[1] <= rd[1];
old_wr[1] <= wr[1];
we <= wr[1];
{bank,a} <= ch1_addr;
data <= {ch1_din,ch1_din};
ram_req <= wr[1] || (last_a[1] != ch1_addr[24:1]);
last_a[1] <= wr[1] ? '1 : ch1_addr[24:1];
ch1_busy <= 1;
state <= STATE_START;
end
else if((~old_rd[2] & rd[2]) | (~old_wr[2] & wr[2])) begin
old_rd[2] <= rd[2];
old_wr[2] <= wr[2];
we <= wr[2];
{bank,a} <= ch2_addr;
data <= {ch2_din,ch2_din};
ram_req <= wr[2] || (last_a[2] != ch2_addr[24:1]);
last_a[2] <= wr[2] ? '1 : ch2_addr[24:1];
ch2_busy <= 1;
state <= STATE_START;
end
end
if (next_port != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[22:10];
SDRAM_BA <= addr_latch_next[24:23];
if (next_port == PORT_REQ) begin
{ oe_latch, we_latch } <= { ~port1_we, port1_we };
ds <= port1_ds;
din_latch <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch, we_latch } <= 2'b10;
ds <= 2'b11;
addr_last <= cpu1_addr;
if (state == STATE_READY) begin
ch0_busy <= 0;
ch1_busy <= 0;
ch2_busy <= 0;
end
if(mode != MODE_NORMAL || state != STATE_IDLE || reset) begin
state <= state + 1'd1;
if(state == STATE_LAST) state <= STATE_IDLE;
end
end
localparam MODE_NORMAL = 2'b00;
localparam MODE_RESET = 2'b01;
localparam MODE_LDM = 2'b10;
localparam MODE_PRE = 2'b11;
// initialization
reg [1:0] mode;
reg [4:0] reset=5'h1f;
always @(posedge clk) begin
reg init_old=0;
init_old <= init;
if(init_old & ~init) reset <= 5'h1f;
else if(state == STATE_LAST) begin
if(reset != 0) begin
reset <= reset - 5'd1;
if(reset == 14) mode <= MODE_PRE;
else if(reset == 3) mode <= MODE_LDM;
else mode <= MODE_RESET;
end
else mode <= MODE_NORMAL;
end
end
localparam CMD_NOP = 3'b111;
localparam CMD_ACTIVE = 3'b011;
localparam CMD_READ = 3'b101;
localparam CMD_WRITE = 3'b100;
localparam CMD_BURST_TERMINATE = 3'b110;
localparam CMD_PRECHARGE = 3'b010;
localparam CMD_AUTO_REFRESH = 3'b001;
localparam CMD_LOAD_MODE = 3'b000;
wire [1:0] dqm = {we & ~a[0], we & a[0]};
// SDRAM state machines
always @(posedge clk) begin
reg [15:0] last_data[3];
reg [15:0] data_reg;
if(state == STATE_START) SDRAM_BA <= (mode == MODE_NORMAL) ? bank : 2'b00;
SDRAM_DQ <= 'Z;
casex({ram_req,we,mode,state})
{2'b1X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_ACTIVE;
{2'b11, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ} <= {CMD_WRITE, data};
{2'b10, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_READ;
{2'b0X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_AUTO_REFRESH;
// init
{2'bXX, MODE_LDM, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_LOAD_MODE;
{2'bXX, MODE_PRE, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_PRECHARGE;
default: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_NOP;
endcase
casex({ram_req,mode,state})
{1'b1, MODE_NORMAL, STATE_START}: SDRAM_A <= a[13:1];
{1'b1, MODE_NORMAL, STATE_CONT }: SDRAM_A <= {dqm, 2'b10, a[22:14]};
// init
{1'bX, MODE_LDM, STATE_START}: SDRAM_A <= MODE;
{1'bX, MODE_PRE, STATE_START}: SDRAM_A <= 13'b0010000000000;
default: SDRAM_A <= 13'b0000000000000;
endcase
data_reg <= SDRAM_DQ;
if(state == STATE_READY) begin
if(ch0_busy) begin
if(ram_req) begin
if(we) ch0_dout <= data[7:0];
else begin
ch0_dout <= a[0] ? data_reg[15:8] : data_reg[7:0];
last_data[0] <= data_reg;
end
end else begin
sd_cmd <= CMD_AUTO_REFRESH;
end
else ch0_dout <= a[0] ? last_data[0][15:8] : last_data[0][7:0];
end
// CAS phase
if(t == STATE_CAS0 && (we_latch || oe_latch)) begin
sd_cmd <= we_latch?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds;
if (we_latch) begin
SDRAM_DQ <= din_latch;
port1_ack <= port1_req;
if(ch1_busy) begin
if(ram_req) begin
if(we) ch1_dout <= data[7:0];
else begin
ch1_dout <= a[0] ? data_reg[15:8] : data_reg[7:0];
last_data[1] <= data_reg;
end
end
SDRAM_A <= { 4'b0010, addr_latch[9:1] }; // auto precharge
SDRAM_BA <= addr_latch[24:23];
else ch1_dout <= a[0] ? last_data[1][15:8] : last_data[1][7:0];
end
// Data returned
if(t == STATE_READ0 && oe_latch) begin
case(port)
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
default: ;
endcase;
if(ch2_busy) begin
if(ram_req) begin
if(we) ch2_dout <= data[7:0];
else begin
ch2_dout <= a[0] ? data_reg[15:8] : data_reg[7:0];
last_data[2] <= data_reg;
end
end
else ch2_dout <= a[0] ? last_data[2][15:8] : last_data[2][7:0];
end
end
end
altddio_out
#(
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone V"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1)
)
sdramclk_ddr
(
.datain_h(1'b0),
.datain_l(1'b1),
.outclock(clk),
.dataout(SDRAM_CLK),
.aclr(1'b0),
.aset(1'b0),
.oe(1'b1),
.outclocken(1'b1),
.sclr(1'b0),
.sset(1'b0)
);
endmodule

268
Console_MiST/Supervision_MiST/rtl/sv_top.sv Normal file
View File

@@ -0,0 +1,268 @@
module sv_top
(
input clk_sys,
input reset,
input [7:0] joystick,
input [7:0] rom_dout,
input [3:0] user_in,
input large_rom,
input compat60,
output hsync,
output hblank,
output vsync,
output vblank,
output [15:0] audio_r,
output [15:0] audio_l,
output [1:0] pixel,
output pix_ce,
output [18:0] addr_bus,
output rom_read,
output reg [7:0] link_ddr,
output reg [7:0] link_data
);
reg [1:0] sys_div = 0;
reg irq_pending = 0;
reg [7:0] open_bus = 8'hFF;
reg [15:0] nmi_clk;
reg irq_timer;
reg old_nmi_clk_15;
reg nmi_latch = 0;
// System Registers
reg [7:0] irq_timer_len;
reg [7:0] sys_ctl;
wire irq_adma_n;
wire [7:0] cpu_dout, wram_dout, vram_dout, sys_dout;
wire dma_en;
wire dma_dir;
wire adma_read;
wire [7:0] lcd_din;
wire [13:0] lcd_addr, vram_addr;
wire [15:0] adma_addr, dma_addr, cpu_addr;
wire [2:0] adma_bank;
wire [5:0] audio_right, audio_left;
wire cpu_rwn;
// Clock divider
wire phi1 = sys_div == 2'b00;
wire phi2 = sys_div == 2'b10;
// Chip Selects
wire wram_cs = AB[15:13] == 3'b000; // Work ram from 0000 to 1FFF
wire sys_cs = AB[15:6] == 10'b0010_0000_00; // System Registers from 2000 to 3FFF (open bus above 202F)
wire vram_cs = AB[15:13] == 3'b010; // Vram from 4000 to 5FFF
//wire ob_cs = AB[15:13] == 3'b011; // Open bus from 6000 to 7FFF
wire rom_cs = AB[15]; // Cart ROM at 8000 to FFFF banked from 8000-BFFF, fixed for the rest
// Bank Selection
wire [2:0] b = AB[14] ? 3'b111 : adma_read ? adma_bank : sys_ctl[7:5];
wire [18:0] magnum_addr = {(b[2] ? 4'b1111 : link_data[3:0]), b[0], AB[13:0]};
// IRQ/NMI Masking
wire nmi = old_nmi_clk_15 & ~nmi_clk[15];
wire timer_tap = (sys_ctl[4] ? nmi_clk[13] : nmi_clk[7]);
wire irq_timer_masked = irq_timer & sys_ctl[1];
wire irq_adma_masked = ~irq_adma_n & sys_ctl[2];
wire nmi_masked = (nmi | nmi_latch) & sys_ctl[0]; // the CPU misses nmi's when paused in this implementation so we have to latch it
// (A)DMA bus multiplexing
wire [15:0] AB = adma_read ? adma_addr : (dma_en ? dma_addr : cpu_addr);
wire cpu_rdy = ~dma_en && ~adma_read;
wire [7:0] DO = dma_en ? (dma_dir ? DII : vram_dout) : cpu_dout;
wire cpu_we = adma_read ? 1'b0 : dma_en ? ~dma_dir : ~cpu_rwn;
// Read Data Bus
wire [7:0] DII =
sys_cs ? sys_dout :
wram_cs ? wram_dout :
vram_cs ? vram_dout :
rom_cs ? rom_dout :
open_bus;
// Top Level assignments
assign addr_bus = large_rom ? magnum_addr : {2'b11, b, AB[13:0]};
assign rom_read = rom_cs & ~phi1;
assign audio_l = { audio_left, 10'd0 };
assign audio_r = { audio_right, 10'd0 };
// System Register reads
always_comb begin
sys_dout = open_bus;
if (~cpu_we) begin
case (AB[5:0])
6'h20: sys_dout = ~joystick;
6'h21: sys_dout = {open_bus[7:4], (user_in[3:0] & link_ddr[3:0]) | (link_data[3:0] & ~link_ddr[3:0])};
6'h23: sys_dout = irq_timer_len;
6'h26: sys_dout = sys_ctl;
6'h27: sys_dout = {open_bus[7:2], ~irq_adma_n, irq_timer};
default: sys_dout = open_bus;
endcase
end
end
always_ff @(posedge clk_sys) begin
reg old_tap;
sys_div <= sys_div + 1'd1;
if (phi1) begin
if (~cpu_rdy)
nmi_latch <= nmi_masked | nmi_latch;
else
nmi_latch <= 0;
end
if (phi2) begin
old_tap <= timer_tap;
old_nmi_clk_15 <= nmi_clk[15];
nmi_clk <= nmi_clk + 16'b1;
if (~old_tap && timer_tap) begin
if (irq_timer_len > 0) begin
irq_timer_len <= irq_timer_len - 8'b1;
if (irq_timer_len == 1)
irq_pending <= 1;
end
end
if (irq_pending && ~timer_tap) begin
irq_pending <= 0;
irq_timer <= 1;
end
open_bus <= ~cpu_we ? DII : DO;
// System Register writes
if (sys_cs) begin
if (AB[5:0] == 6'h24) begin // read or write to ack timer IRQ
irq_timer <= 0;
end
if (cpu_we) begin
case (AB[5:0])
6'h21: link_data <= cpu_dout;
6'h22: link_ddr <= cpu_dout;
6'h23: begin
irq_timer_len <= cpu_dout;
if (cpu_dout == 0) begin
if (~timer_tap) begin
irq_timer <= 1;
end else begin
irq_pending <= 1;
end
end
end
6'h26: sys_ctl <= cpu_dout;
endcase
end
end
end
if (reset) begin
irq_timer <= 0;
irq_pending <= 0;
irq_timer_len <= 0;
nmi_clk <= 0;
sys_ctl <= 0;
link_ddr <= 0;
nmi_latch <= 0;
link_data <= 0;
end
end
spram #(.addr_width(13)) wram
(
.clock(clk_sys),
.address(AB[12:0]),
.data(DO),
.wren(cpu_we && wram_cs && phi2),
.q(wram_dout)
);
dpram #(.addr_width(14)) vram
(
.clock(clk_sys),
.address_a(dma_en ? vram_addr : AB[13:0]),
.data_a(DO),
.q_a(vram_dout),
.wren_a((dma_en ? dma_dir : (vram_cs && cpu_we)) && phi2),
.address_b(lcd_addr),
.q_b(lcd_din)
);
dma dma
(
.clk (clk_sys),
.ce (phi1),
.reset (reset),
.AB (AB[5:0]),
.cpu_rwn (~cpu_we),
.dma_cs (sys_cs),
.lcd_en (sys_ctl[3]),
.data_in (cpu_dout),
.vbus_addr (vram_addr),
.cbus_addr (dma_addr),
.dma_en (dma_en),
.dma_dir (dma_dir)
);
audio audio
(
.clk (clk_sys),
.ce (phi1),
.reset (reset),
.cpu_rwn (~cpu_we),
.snd_cs (sys_cs),
.AB (AB[5:0]),
.dbus_in (adma_read ? DII : cpu_dout),
.adma_irq_n (irq_adma_n),
.prescaler (nmi_clk),
.adma_read (adma_read),
.adma_bank (adma_bank),
.adma_addr (adma_addr),
.CH1 (audio_right),
.CH2 (audio_left)
);
lcd lcd
(
.clk (clk_sys),
.ce (phi2),
.compat60 (compat60),
.reset (reset),
.lcd_cs (sys_cs),
.cpu_rwn (~cpu_we),
.AB (AB[5:0]),
.dbus_in (cpu_dout),
.ce_pix (pix_ce),
.pixel (pixel),
.lcd_off (~sys_ctl[3] || (cpu_we && sys_cs && AB[5:0] == 16'h26)),
.vram_data (lcd_din),
.vram_addr (lcd_addr),
.hsync (hsync),
.vsync (vsync),
.hblank (hblank),
.vblank (vblank)
);
r65c02_tc cpu3
(
.clk_clk_i (clk_sys),
.d_i (cpu_rwn ? DII : DO),
.ce (phi1 && cpu_rdy),
.irq_n_i (~(irq_timer_masked | irq_adma_masked)),
.nmi_n_i (~nmi_masked),
.rdy_i (1), // This system seems to halt the clock for dma rather than use traditional rdy
.rst_rst_n_i (~reset),
.so_n_i (1),
.a_o (cpu_addr),
.d_o (cpu_dout),
.rd_o (),
.sync_o (),
.wr_n_o (cpu_rwn),
.wr_o ()
);
endmodule

88
Console_MiST/Supervision_MiST/rtl/video.sv
View File

@@ -1,88 +0,0 @@
module video(
input clk,//vga
input clk7p16,//rgb
output ce_pxl,
input white,
// from lcd ctrl registers
input ce,
input [7:0] lcd_xsize,
input [7:0] lcd_ysize,
input [7:0] lcd_xscroll,
input [7:0] lcd_yscroll,
output lcd_pulse,
// to/from vram
output [12:0] addr,
input [7:0] data,
// to vga interface
output hsync,
output vsync,
output hblank,
output vblank,
output reg [7:0] red,
output reg [7:0] green,
output reg [7:0] blue
);
reg [9:0] hcount;
reg [9:0] vcount;
assign lcd_pulse = ce_pxl;
// VGA industry standard 640x480@60 800 525 31.5 - - 25.2 16 96 48 10 2 33 MHi modelines table
// visible area | front porch <sync pulse> back porch
// 640 | 32 < 48 > 112
assign hsync = ~((hcount >= 672) && (hcount < 720));
assign vsync = ~((vcount >= 481) && (vcount < 484));
assign hblank = hcount > 639;
assign vblank = vcount > 479;
// convert vga coordinates to lcd coordinates (with borders)
wire [8:0] vgax = hcount < 640 ? hcount[9:1] : 9'd0; // 0 - 319
wire [8:0] vgay = vcount < 480 ? vcount[9:1] : 9'd0; // 0 - 239
wire [7:0] lcdx = vgax >= 80 && vgax < 240 ? vgax - 8'd80 : 8'd0; // 0-79(80)|80-239(160)|240-319(80)
wire [7:0] lcdy = vgay >= 40 && vgay < 200 ? vgay - 8'd40 : 8'd0; // 0-39(40)|40-199(160)|200-239(40)
// calcul vram address (TODO include xsize, ysize, xscroll[1:0] in calculation)
//assign addr = lcd_yscroll * 8'h30 + lcd_xscroll[7:2] + lcdy * 8'h30 + lcdx[7:2];
assign addr = lcdy * 8'h30 + lcdx[7:2];
assign ce_pxl = hcount[0] == 1;
// assign colors
wire [2:0] index = { lcdx[1:0], 1'b0 };
always @(posedge clk)
if (ce && lcdx != 0 && lcdy != 0) begin
if (ce_pxl) begin
case ({white,data[index+:2]})
3'b000: { red, green, blue } <= 24'h87BA6B;//lightest colour
3'b001: { red, green, blue } <= 24'h6BA378;//1/3rd darkness
3'b010: { red, green, blue } <= 24'h386B82;//2/3rd darkness
3'b011: { red, green, blue } <= 24'h384052;//dark as possible
3'b100: { red, green, blue } <= 24'hFFFFFF;//white
3'b101: { red, green, blue } <= 24'hC0C0C0;//light gray
3'b110: { red, green, blue } <= 24'h808080;//gray
3'b111: { red, green, blue } <= 24'h000000;//black
endcase
end
end
else
{ red, green, blue } <= 24'h0;
always @(posedge clk) begin
hcount <= hcount + 10'd1;
if (hcount == 10'd799) hcount <= 0;
end
always @(posedge clk)
if (hcount == 10'd799)
vcount <= vcount + 10'd1;
else if (vcount == 10'd509)
vcount <= 0;
endmodule