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Merge pull request #148 from gyurco/master

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SNK 68000 + remove duplicated jtopl + Galivan fix + Laguna Racer
This commit is contained in:
Marcel
2022-10-16 10:51:37 +02:00
committed by GitHub
parent 0a666b63d0 0f0d3f5ac7
commit 99a3370486
101 changed files with 11053 additions and 3470 deletions
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30
Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/Lagunar.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 21:27:39 November 20, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "21:27:39 November 20, 2017"
# Revisions
PROJECT_REVISION = "Lagunar"

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Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/Lagunar.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 20:51:02 August 09, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Lagunar_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY Lagunar_mist
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# ----------------------------
# start ENTITY(DLagunar_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(DLagunar_mist)
# --------------------------
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Lagunar_mist.sv
set_global_assignment -name VHDL_FILE rtl/spy_hunter_control.vhd
set_global_assignment -name VHDL_FILE rtl/invaders.vhd
set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Lagunar_memory.sv
set_global_assignment -name VHDL_FILE rtl/Lagunar_Overlay.vhd
set_global_assignment -name VHDL_FILE rtl/sound/sprint1_sound.vhd
set_global_assignment -name VHDL_FILE rtl/sound/screech.vhd
set_global_assignment -name VHDL_FILE rtl/sound/EngineSound.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {VGA_*}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

0
Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/Lagunar_description.txt Normal file
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Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/README.txt Normal file
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---------------------------------------------------------------------------------
--
-- Arcade: 280zzzap port to MiST by Gehstock
-- 05 June 2019
--
---------------------------------------------------------------------------------
--
-- Midway 8080 Hardware
-- Audio based on work by Paul Walsh.
-- Audio and scan converter by MikeJ.
---------------------------------------------------------------------------------
--
--
-- Keyboard inputs :
--
-- F1 : Start
-- SPACE : Fire
-- RIGHT/LEFT : Movement
--
-- Joystick support.
--
--
---------------------------------------------------------------------------------
ToDo: Color Prom
Controls + DIP

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Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

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Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/rtl/Lagunar_Overlay.vhd Normal file
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--Datsun 280 ZZZAP Color Overlay Gehstock 2019
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Lagunar_Overlay is
port(
Video : in std_logic;
Overlay : in std_logic;
CLK : in std_logic;
Rst_n_s : in std_logic;
HSync : in std_logic;
VSync : in std_logic;
O_VIDEO_R : out std_logic;
O_VIDEO_G : out std_logic;
O_VIDEO_B : out std_logic;
O_HSYNC : out std_logic;
O_VSYNC : out std_logic
);
end Lagunar_Overlay;
architecture rtl of Lagunar_Overlay is
signal HCnt : std_logic_vector(11 downto 0);
signal VCnt : std_logic_vector(11 downto 0);
signal HSync_t1 : std_logic;
signal Overlay_B1 : boolean;
signal Overlay_B1_VCnt : boolean;
signal VideoRGB : std_logic_vector(2 downto 0);
signal col_data : std_logic_vector(3 downto 0);
signal col_addr : std_logic_vector(9 downto 0);
begin
process (Rst_n_s, Clk)
variable cnt : unsigned(3 downto 0);
begin
if Rst_n_s = '0' then
cnt := "0000";
elsif Clk'event and Clk = '1' then
if cnt = 9 then
cnt := "0000";
else
cnt := cnt + 1;
end if;
end if;
end process;
p_overlay : process(Rst_n_s, Clk)
variable HStart : boolean;
begin
if Rst_n_s = '0' then
HCnt <= (others => '0');
VCnt <= (others => '0');
HSync_t1 <= '0';
Overlay_B1_VCnt <= false;
Overlay_B1 <= false;
elsif Clk'event and Clk = '1' then
HSync_t1 <= HSync;
HStart := (HSync_t1 = '0') and (HSync = '1');
if HStart then
HCnt <= (others => '0');
else
HCnt <= HCnt + "1";
end if;
if (VSync = '0') then
VCnt <= (others => '0');
elsif HStart then
VCnt <= VCnt + "1";
end if;
Overlay_B1 <= false;
end if;
end process;
p_video_out_comb : process(Video, Overlay_B1)
begin
if (Video = '0') then
VideoRGB <= "000";
else
if Overlay_B1 then
VideoRGB <= "001";
else
VideoRGB <= "111";
end if;
end if;
end process;
O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_HSYNC <= HSync;
O_VSYNC <= VSync;
end;

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module Lagunar_memory(
input Clock,
input RW_n,
input [15:0]Addr,
input [15:0]Ram_Addr,
output [7:0]Ram_out,
input [7:0]Ram_in,
output [7:0]Rom_out
);
wire [7:0]rom_data_0;
wire [7:0]rom_data_1;
wire [7:0]rom_data_2;
wire [7:0]rom_data_3;
sprom #(
.init_file("./roms/lagunar_h.hex"),
.widthad_a(11),
.width_a(8))
u_rom_h (
.clock(Clock),
.Address(Addr[10:0]),
.q(rom_data_0)
);
sprom #(
.init_file("./roms/lagunar_g.hex"),
.widthad_a(11),
.width_a(8))
u_rom_g (
.clock(Clock),
.Address(Addr[10:0]),
.q(rom_data_1)
);
sprom #(
.init_file("./roms/lagunar_f.hex"),
.widthad_a(11),
.width_a(8))
u_rom_f (
.clock(Clock),
.Address(Addr[10:0]),
.q(rom_data_2)
);
sprom #(
.init_file("./roms/lagunar_e.hex"),
.widthad_a(11),
.width_a(8))
u_rom_e (
.clock(Clock),
.Address(Addr[10:0]),
.q(rom_data_3)
);
always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3) begin
Rom_out = 8'b00000000;
case (Addr[15:11])
6'b00000 : Rom_out = rom_data_0; //0
6'b00001 : Rom_out = rom_data_1; //0800
6'b00010 : Rom_out = rom_data_2; //1000
6'b00011 : Rom_out = rom_data_3; //1800
default : Rom_out = 8'b00000000;
endcase
end
spram #(
.addr_width_g(13),
.data_width_g(8))
u_ram0(
.address(Ram_Addr[12:0]),
.clken(1'b1),
.clock(Clock),
.data(Ram_in),
.wren(~RW_n),
.q(Ram_out)
);
endmodule

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Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/rtl/Lagunar_mist.sv Normal file
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module Lagunar_mist(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"LAGUNAR;;",
"O34,Scanlines,Off,25%,50%,75%;",
"O2,Rotate Controls,Off,On;",
"P1,Switches;",
"P1O89,Coinage,1C_1C,1C_2C,2C_1C,2C_3C;",
"P1OAB,Game Time,45+22s,60+30s,75+37s,90+45s;",
"P1OCD,Extended Time At,350,400,450,500;",
"P1OEF,Mode,Normal,RAM/ROM Test,Input Test,No Extended Time;",
"T0,Reset;",
"V,v0.00.",`BUILD_DATE
};
wire [1:0] scanlines = status[4:3];
wire rotate = status[2];
wire overlay = 0;
wire [7:0] dip = status[15:8];
assign LED = 1;
wire clk_core, clk_vid, clk_aud;
wire pll_locked;
pll pll
(
.inclk0(CLOCK_27),
.areset(),
.c0(clk_core),
.c1(clk_vid),
.c2(clk_aud)
);
wire reset = status[0] | buttons[1];
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0,joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_core ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire signed [7:0] steering;
wire signed [7:0] steering_adj = -(steering + 8'h10); // range adjust and negate: 30-b0 -> 40-c0
wire [7:0] pedal;
spy_hunter_control controls (
.clock_40(clk_core),
.reset(reset),
.vsync(vs),
.gas_plus(m_up),
.gas_minus(m_down),
.steering_plus(m_right),
.steering_minus(m_left),
.steering(steering),
.gas(pedal)
);
wire gear;
input_toggle gear_sw(
.clk(clk_core),
.reset(reset),
.btn(m_fireA),
.state(gear)
);
wire hsync,vsync;
wire hs, vs;
wire r,g,b;
wire [15:0]RAB;
wire [15:0]AD;
wire [7:0]RDB;
wire [7:0]RWD;
wire [7:0]IB;
wire [5:0]SoundCtrl3;
wire [5:0]SoundCtrl5;
wire Rst_n_s;
wire RWE_n;
wire Video;
wire HSync;
wire VSync;
wire [7:0] audio;
invaderst invaderst(
.Rst_n(~reset),
.Clk(clk_core),
.ENA(),
.Coin(m_coin1 | m_coin2),
.Sel1Player(m_one_player),
.Sel2Player(m_two_players),
.Fire(gear),
.Pedal(pedal[7:4]),
.Steering(steering_adj),
.DIP(dip),
.RDB(RDB),
.IB(IB),
.RWD(RWD),
.RAB(RAB),
.AD(AD),
.SoundCtrl3(SoundCtrl3),
.SoundCtrl5(SoundCtrl5),
.Rst_n_s(Rst_n_s),
.RWE_n(RWE_n),
.Video(Video),
.HSync(HSync),
.VSync(VSync)
);
Lagunar_memory Lagunar_memory (
.Clock(clk_core),
.RW_n(RWE_n),
.Addr(AD),
.Ram_Addr(RAB),
.Ram_out(RDB),
.Ram_in(RWD),
.Rom_out(IB)
);
Lagunar_Overlay Lagunar_Overlay (
.Video(Video),
.Overlay(~overlay),
.CLK(clk_core),
.Rst_n_s(Rst_n_s),
.HSync(HSync),
.VSync(VSync),
.O_VIDEO_R(r),
.O_VIDEO_G(g),
.O_VIDEO_B(b),
.O_HSYNC(hs),
.O_VSYNC(vs)
);
mist_video #(.COLOR_DEPTH(1)) mist_video(
.clk_sys(clk_vid),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(r),
.G(g),
.B(b),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.scandoubler_disable(scandoublerD),
.scanlines(scanlines),
.ce_divider(0),
.rotate({1'b1, rotate}),
.ypbpr(ypbpr),
.no_csync(no_csync)
);
/*
--* Port 3:
--* bit 0= sound freq
--* bit 1= sound freq
--* bit 2= sound freq
--* bit 3= sound freq
--* bit 4= HI SHIFT MODIFIER
--* bit 5= LO SHIFT MODIFIER
--* bit 6= NC
--* bit 7= NC
--*
--* Port 5:
--* bit 0= BOOM sound
--* bit 1= ENGINE sound
--* bit 2= Screeching Sound
--* bit 3= after car blows up, before it appears again
--* bit 4= NC
--* bit 5= coin counter
--* bit 6= NC
--* bit 7= NC
*/
audio audio_inst (
.Clk_5(clk_aud),
.Motor1_n(SoundCtrl5[1]),
.Skid1(SoundCtrl5[2]),
.Crash_n(~SoundCtrl5[0]),
.NoiseReset_n(1'b1),
.motorspeed(SoundCtrl3[3:0]),
.Audio1(audio)
);
assign AUDIO_R = AUDIO_L;
dac dac (
.clk_i(clk_aud),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_core ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( 2'b11 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

227
Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/rtl/invaders.vhd Normal file
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-- Space Invaders core logic
-- 9.984MHz clock
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.fpgaarcade.com
--
-- Limitations :
--
-- File history :
--
-- 0241 : First release
--
-- 0242 : Cleaned up reset logic
--
-- 0300 : MikeJ tidyup for audio release
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity invaderst is
port(
Rst_n : in std_logic;
Clk : in std_logic;
ENA : out std_logic;
Coin : in std_logic;
Sel1Player : in std_logic;
Sel2Player : in std_logic;
Fire : in std_logic;
Pedal : in std_logic_vector(3 downto 0);
Steering : in std_logic_vector(7 downto 0);
DIP : in std_logic_vector(8 downto 1);
RDB : in std_logic_vector(7 downto 0);
IB : in std_logic_vector(7 downto 0);
RWD : out std_logic_vector(7 downto 0);
RAB : out std_logic_vector(12 downto 0);
AD : out std_logic_vector(15 downto 0);
SoundCtrl3 : out std_logic_vector(5 downto 0);
SoundCtrl5 : out std_logic_vector(5 downto 0);
Rst_n_s : out std_logic;
RWE_n : out std_logic;
Video : out std_logic;
HSync : out std_logic;
VSync : out std_logic
);
end invaderst;
architecture rtl of invaderst is
signal GDB0 : std_logic_vector(7 downto 0);
signal GDB1 : std_logic_vector(7 downto 0);
signal GDB2 : std_logic_vector(7 downto 0);
signal S : std_logic_vector(7 downto 0);
signal GDB : std_logic_vector(7 downto 0);
signal DB : std_logic_vector(7 downto 0);
signal Sounds : std_logic_vector(7 downto 0);
signal AD_i : std_logic_vector(15 downto 0);
signal PortWr : std_logic_vector(6 downto 2);
signal EA : std_logic_vector(2 downto 0);
signal D5 : std_logic_vector(15 downto 0);
signal WD_Cnt : unsigned(7 downto 0);
signal Sample : std_logic;
signal Rst_n_s_i : std_logic;
begin
Rst_n_s <= Rst_n_s_i;
RWD <= DB;
AD <= AD_i;
process (Rst_n, Clk)
variable Rst_n_r : std_logic;
begin
if Rst_n = '0' then
Rst_n_r := '0';
Rst_n_s_i <= '0';
elsif Clk'event and Clk = '1' then
Rst_n_s_i <= Rst_n_r;
if WD_Cnt = 255 then
Rst_n_s_i <= '0';
end if;
Rst_n_r := '1';
end if;
end process;
process (Rst_n_s_i, Clk)
variable Old_S0 : std_logic;
begin
if Rst_n_s_i = '0' then
WD_Cnt <= (others => '0');
Old_S0 := '1';
elsif Clk'event and Clk = '1' then
if Sounds(0) = '1' and Old_S0 = '0' then
WD_Cnt <= WD_Cnt + 1;
end if;
if PortWr(6) = '1' then
WD_Cnt <= (others => '0');
end if;
Old_S0 := Sounds(0);
end if;
end process;
u_mw8080: entity work.mw8080
port map(
Rst_n => Rst_n,--Rst_n_s_i,
Clk => Clk,
ENA => ENA,
RWE_n => RWE_n,
RDB => RDB,
IB => IB,
RAB => RAB,
Sounds => Sounds,
Ready => open,
GDB => GDB,
DB => DB,
AD => AD_i,
Status => open,
Systb => open,
Int => open,
Hold_n => '1',
IntE => open,
DBin_n => open,
Vait => open,
HldA => open,
Sample => Sample,
Wr => open,
Video => Video,
HSync => HSync,
VSync => VSync);
with AD_i(9 downto 8) select
GDB <= GDB0 when "00",
GDB1 when "01",
GDB2 when "10",
S when others;
--IN0
GDB0(3 downto 0) <= Pedal;
GDB0(4) <= not Fire; -- fire
GDB0(5) <= '1'; -- UNUSED
GDB0(6) <= not Coin; -- coin
GDB0(7) <= not Sel1Player; -- start
--IN1
GDB1 <= Steering;
--IN2
GDB2 <= DIP;
PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
process (Rst_n_s_i, Clk)
variable OldSample : std_logic;
begin
if Rst_n_s_i = '0' then
D5 <= (others => '0');
EA <= (others => '0');
SoundCtrl3 <= (others => '0');
SoundCtrl5 <= (others => '0');
OldSample := '0';
elsif Clk'event and Clk = '1' then
if PortWr(4) = '1' then
EA <= DB(2 downto 0);
end if;
if PortWr(2) = '1' then
SoundCtrl3 <= DB(5 downto 0);
end if;
if PortWr(3) = '1' and OldSample = '0' then
D5(15 downto 8) <= DB;
D5(7 downto 0) <= D5(15 downto 8);
end if;
if PortWr(5) = '1' then
SoundCtrl5 <= DB(5 downto 0);
end if;
OldSample := Sample;
end if;
end process;
with EA select
S <= D5(15 downto 8) when "000",
D5(14 downto 7) when "001",
D5(13 downto 6) when "010",
D5(12 downto 5) when "011",
D5(11 downto 4) when "100",
D5(10 downto 3) when "101",
D5( 9 downto 2) when "110",
D5( 8 downto 1) when others;
end;

335
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-- Midway 8080 main board
-- 9.984MHz Clock
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.fpgaarcade.com
--
-- Limitations :
--
-- File history :
--
-- 0241 : First release
--
-- 0242 : Removed the ROM
--
-- 0300 : MikeJ tidyup for audio release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mw8080 is
port(
Rst_n : in std_logic;
Clk : in std_logic;
ENA : out std_logic;
RWE_n : out std_logic;
RDB : in std_logic_vector(7 downto 0);
RAB : out std_logic_vector(12 downto 0);
Sounds : out std_logic_vector(7 downto 0);
Ready : out std_logic;
GDB : in std_logic_vector(7 downto 0);
IB : in std_logic_vector(7 downto 0);
DB : out std_logic_vector(7 downto 0);
AD : out std_logic_vector(15 downto 0);
Status : out std_logic_vector(7 downto 0);
Systb : out std_logic;
Int : out std_logic;
Hold_n : in std_logic;
IntE : out std_logic;
DBin_n : out std_logic;
Vait : out std_logic;
HldA : out std_logic;
Sample : out std_logic;
Wr : out std_logic;
Video : out std_logic;
HSync : out std_logic;
VSync : out std_logic);
end mw8080;
architecture struct of mw8080 is
component T8080se
generic(
Mode : integer := 2;
T2Write : integer := 0);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0));
end component;
signal Ready_i : std_logic;
signal Hold : std_logic;
signal IntTrig : std_logic;
signal IntTrigOld : std_logic;
signal Int_i : std_logic;
signal IntE_i : std_logic;
signal DBin : std_logic;
signal Sync : std_logic;
signal Wr_n, Rd_n : std_logic;
signal ClkEnCnt : unsigned(2 downto 0);
signal Status_i : std_logic_vector(7 downto 0);
signal A : std_logic_vector(15 downto 0);
signal ISel : std_logic_vector(1 downto 0);
signal DI : std_logic_vector(7 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal RR : std_logic_vector(9 downto 0);
signal VidEn : std_logic;
signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320
signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2
signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262
signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2
signal Shift : std_logic_vector(7 downto 0);
begin
ENA <= ClkEnCnt(2);
Status <= Status_i;
Ready <= Ready_i;
DB <= DO;
Systb <= Sync;
Int <= Int_i;
Hold <= not Hold_n;
IntE <= IntE_i;
DBin_n <= not DBin;
Sample <= not Wr_n and Status_i(4);
Wr <= not Wr_n;
AD <= A;
Sounds(0) <= CntE7(3);
Sounds(1) <= CntE7(2);
Sounds(2) <= CntE7(1);
Sounds(3) <= CntE7(0);
Sounds(4) <= CntE6(3);
Sounds(5) <= CntE6(2);
Sounds(6) <= CntE6(1);
Sounds(7) <= CntE6(0);
IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
ISel(1) <= Status_i(0) nor Status_i(6);
with ISel select
DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
GDB when "01",
IB when "10",
RR(7 downto 0) when others;
RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
RAB <= A(12 downto 0) when CntD5(2) = '1' else
std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
u_8080: T8080se
generic map (
Mode => 2,
T2Write => 1)
port map (
RESET_n => Rst_n,
CLK => Clk,
CLKEN => ClkEnCnt(2),
READY => Ready_i,
HOLD => Hold,
INT => Int_i,
INTE => IntE_i,
DBIN => DBin,
SYNC => Sync,
VAIT => Vait,
HLDA => HLDA,
WR_n => Wr_n,
A => A,
DI => DI,
DO => DO);
-- Clock enables
process (Rst_n, Clk)
begin
if Rst_n = '0' then
ClkEnCnt <= "000";
VidEn <= '0';
elsif Clk'event and Clk = '1' then
VidEn <= not VidEn;
if ClkEnCnt = 4 then
ClkEnCnt <= "000";
else
ClkEnCnt <= ClkEnCnt + 1;
end if;
end if;
end process;
-- Glue
process (Rst_n, Clk)
variable OldASEL : std_logic;
begin
if Rst_n = '0' then
Status_i <= (others => '0');
IntTrigOld <= '0';
Int_i <= '0';
OldASEL := '0';
Ready_i <= '0';
RR <= (others => '0');
elsif Clk'event and Clk = '1' then
-- E3
-- Interrupt
IntTrigOld <= IntTrig;
if Status_i(0) = '1' then
Int_i <= '0';
elsif IntTrigOld = '0' and IntTrig = '1' then
Int_i <= IntE_i;
end if;
-- D7
-- Status register
if Sync = '1' then
Status_i <= DO;
end if;
-- A3, C3, E3
-- RAM register/ready logic
if Sync = '1' and A(13) = '1' then
Ready_i <= '0';
elsif Ready_i = '1' then
Ready_i <= '1';
else
Ready_i <= RR(9);
end if;
if Sync = '1' and A(13) = '1' then
RR <= (others => '0');
elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge
(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
RR(7 downto 0) <= RDB;
RR(8) <= '1';
RR(9) <= RR(8);
end if;
OldASEL := CntD5(2);
end if;
end process;
-- Video counters
process (Rst_n, Clk)
begin
if Rst_n = '0' then
CntD5 <= (others => '0');
CntE5 <= (others => '0');
CntE6 <= (others => '0');
CntE7 <= (others => '0');
elsif Clk'event and Clk = '1' then
if VidEn = '1' then
CntD5 <= CntD5 + 1;
if CntD5 = 15 then
CntE5 <= CntE5 + 1;
if CntE5(3 downto 0) = 15 then
if CntE5(4) = '0' then
CntE5 <= "11100";
CntE6 <= CntE6 + 1;
if CntE6 = 15 then
CntE7 <= CntE7 + 1;
if CntE7(3 downto 0) = 15 then
if CntE7(4) = '0' then
CntE6 <= "1010";
CntE7 <= "11101";
else
CntE7 <= "00010";
end if;
end if;
end if;
end if;
else
end if;
end if;
end if;
end if;
end process;
-- Video shift register
process (Rst_n, Clk)
begin
if Rst_n = '0' then
Shift <= (others => '0');
Video <= '0';
elsif Clk'event and Clk = '1' then
if VidEn = '1' then
if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
Shift(7 downto 0) <= RDB(7 downto 0);
else
Shift(6 downto 0) <= Shift(7 downto 1);
Shift(7) <= '0';
end if;
Video <= Shift(0);
end if;
end if;
end process;
-- Sync
process (Rst_n, Clk)
begin
if Rst_n = '0' then
HSync <= '1';
VSync <= '1';
elsif Clk'event and Clk = '1' then
if VidEn = '1' then
if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
HSync <= '0';
else
HSync <= '1';
end if;
if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
VSync <= '0';
else
VSync <= '1';
end if;
end if;
end if;
end process;
end;

4
Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

414
Arcade_MiST/Midway-Taito 8080 Hardware/LagunaRacer_MiST/rtl/pll.vhd Normal file
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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
c2 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1125,
clk0_duty_cycle => 50,
clk0_multiply_by => 416,
clk0_phase_shift => "0",
clk1_divide_by => 1125,
clk1_duty_cycle => 50,
clk1_multiply_by => 832,
clk1_phase_shift => "0",
clk2_divide_by => 1125,
clk2_duty_cycle => 50,
clk2_multiply_by => 208,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "4.992000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "4.99200000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1125"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "208"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

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:20040000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC
:20042000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDC
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159
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-- Motor sound generator for Kee Games Sprint 1
-- Identical circuits are used in a number of other related games
-- (c) 2017 James Sweet
--
-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
-- a four bit binary value. The output of this oscillator drives a counter configured to produce an
-- irregular thumping simulating the sound of an engine.
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity EngineSound is
generic(
constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency
);
port(
Clk_5 : in std_logic;
Ena_3k : in std_logic;
EngineData : in std_logic_vector(3 downto 0);
Motor : out std_logic_vector(5 downto 0)
);
end EngineSound;
architecture rtl of EngineSound is
signal RPM_val : integer range 1 to 350;
signal Ramp_term_unfilt : integer range 1 to 80000;
signal Ramp_Count : integer range 0 to 80000;
signal Ramp_term : integer range 1 to 80000;
signal Freq_mod : integer range 0 to 400;
signal Motor_Clk : std_logic;
signal Counter_A : std_logic;
signal Counter_B : unsigned(2 downto 0);
signal Counter_A_clk : std_logic;
signal Motor_prefilter : unsigned(1 downto 0);
signal Motor_filter_t1 : unsigned(3 downto 0);
signal Motor_filter_t2 : unsigned(3 downto 0);
signal Motor_filter_t3 : unsigned(3 downto 0);
signal Motor_filtered : unsigned(5 downto 0);
begin
-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
-- The output of this DAC has a capacitor to smooth out the frequency variation.
-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve
Speed_select: process(Clk_5)
begin
if rising_edge(Clk_5) then
case EngineData is
when "0000" => RPM_val <= 280;
when "0001" => RPM_val <= 245;
when "0010" => RPM_val <= 230;
when "0011" => RPM_val <= 205;
when "0100" => RPM_val <= 190;
when "0101" => RPM_val <= 175;
when "0110" => RPM_val <= 160;
when "0111" => RPM_val <= 145;
when "1000" => RPM_val <= 130;
when "1001" => RPM_val <= 115;
when "1010" => RPM_val <= 100;
when "1011" => RPM_val <= 85;
when "1100" => RPM_val <= 70;
when "1101" => RPM_val <= 55;
when "1110" => RPM_val <= 40;
when "1111" => RPM_val <= 25;
end case;
end if;
end process;
-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
-- not truly accurate but should be close enough.
RC_filt: process(Clk_5, ena_3k, ramp_term_unfilt)
begin
if rising_edge(Clk_5) then
if ena_3k = '1' then
if ramp_term_unfilt > ramp_term then
ramp_term <= ramp_term + 5;
elsif ramp_term_unfilt = ramp_term then
ramp_term <= ramp_term;
else
ramp_term <= ramp_term - 3;
end if;
end if;
end if;
end process;
-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
-- to simulate the function of the frequency adjustment pot in the original hardware.
ramp_term_unfilt <= ((200 - freq_tune) * RPM_val);
-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
Ramp_osc: process(Clk_5)
begin
if rising_edge(Clk_5) then
motor_clk <= '1';
ramp_count <= ramp_count + 1;
if ramp_count > ramp_term then
ramp_count <= 0;
motor_clk <= '0';
end if;
end if;
end process;
-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train
-- 7492 has two sections, one div-by-2 and one div-by-6.
Engine_counter: process(motor_clk, Counter_A_clk, Counter_B)
begin
if rising_edge(motor_clk) then
Counter_B <= Counter_B + '1';
end if;
Counter_A_clk <= Counter_B(0) xor Counter_B(2);
if rising_edge(counter_A_clk) then
Counter_A <= (not Counter_A);
end if;
end process;
motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A);
-- Very simple low pass filter, borrowed from MikeJ's Asteroids code
Engine_filter: process(Clk_5)
begin
if rising_edge(Clk_5) then
if (ena_3k = '1') then
motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter);
motor_filter_t2 <= motor_filter_t1;
motor_filter_t3 <= motor_filter_t2;
end if;
motor_filtered <= ("00" & motor_filter_t1) +
('0' & motor_filter_t2 & '0') +
("00" & motor_filter_t3);
end if;
end process;
motor <= std_logic_vector(motor_filtered);
end rtl;

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-- Tire screech sound generator for Kee Games Sprint 1
-- Identical circuit is used in a number of related Kee/Atari games
-- (c) 2017 James Sweet
--
-- Original circuit used a 7414 Schmitt trigger oscillator operating at approximately
-- 1.2kHz producing a sawtooth with the frequency modulated slightly by the pseudo-random
-- noise generator. This is an extension of work initially done in Verilog by Jonas Elofsson.
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity tire_screech is
generic(
constant Inc1 : integer := 24; -- These constants can be adjusted to tune the frequency and modulation
constant Inc2 : integer := 34;
constant Dec1 : integer := 23;
constant Dec2 : integer := 12
);
port(
Clk : in std_logic; -- 750kHz from the horizontal line counter chain works well here
Noise : in std_logic; -- Output from LFSR pseudo-random noise generator
Screech_out : out std_logic -- Screech output - single bit
);
end tire_screech;
architecture rtl of tire_screech is
signal Screech_count : integer range 1000 to 11000;
signal Screech_state : std_logic;
begin
Screech: process(Clk, Screech_state)
begin
if rising_edge(Clk) then
if screech_state = '1' then -- screech_state is 1, counter is rising
if noise = '1' then -- Noise signal from LFSR, when high increases the slope of the rising ramp
screech_count <= screech_count + inc2;
else -- When Noise is low, decreas the slope of the ramp
screech_count <= screech_count + inc1;
end if;
if screech_count > 10000 then -- Reverse the ramp direction when boundary value of 10,000 is reached
screech_state <= '0';
end if;
elsif screech_state = '0' then -- screech_state is now low, decrement the counter (ramp down)
if noise = '1' then
screech_count <= screech_count - dec2; -- Slope is influenced by the Noise signal
else
screech_count <= screech_count - dec1;
end if;
if screech_count < 1000 then -- Reverse the ramp direction again when the lower boundary of 1,000 is crossed
screech_state <= '1';
end if;
end if;
end if;
screech_out <= screech_state;
end process;
end rtl;

215
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-- Audio for Sprint 1
-- modified for 280zzap
-- First attempt at modeling the analog sound circuits used in Sprint 1, may be room for improvement as
-- I do not have a real board to compare.
-- (c) 2017 James Sweet
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity audio is
port(
Clk_5 : in std_logic;
Motor1_n : in std_logic;
Skid1 : in std_logic;
Crash_n : in std_logic;
NoiseReset_n : in std_logic;
motorspeed : in std_logic_vector(3 downto 0);
Audio1 : out std_logic_vector(7 downto 0)
);
end audio;
architecture rtl of audio is
signal H4 : std_logic;
signal V2 : std_logic;
signal Noise : std_logic;
signal Noise_Shift : std_logic_vector(15 downto 0);
signal Shift_in : std_logic;
signal Screech_count : integer range 1000 to 11000;
signal Screech_state : std_logic;
signal Screech_snd1 : std_logic;
signal Screech1 : std_logic_vector(3 downto 0);
signal Crash : std_logic_vector(3 downto 0);
signal Bang : std_logic_vector(3 downto 0);
signal Mtr1_Freq : std_logic_vector(3 downto 0);
signal Motor1_speed : std_logic_vector(3 downto 0);
signal Motor1_snd_o : std_logic_vector(5 downto 0);
signal Motor1_snd : std_logic_vector(5 downto 0);
signal P1_audio : std_logic_vector(6 downto 0);
signal ena_count : std_logic_vector(11 downto 0);
signal ena_3k : std_logic;
signal bang_prefilter : std_logic_vector(3 downto 0);
signal bang_filter_t1 : std_logic_vector(3 downto 0);
signal bang_filter_t2 : std_logic_vector(3 downto 0);
signal bang_filter_t3 : std_logic_vector(3 downto 0);
signal bang_filtered : std_logic_vector(5 downto 0);
signal h_counter : std_logic_vector(9 downto 0) := (others => '0');
signal HCount : std_logic_vector(8 downto 0);
begin
hcount <= h_counter(9 downto 1);
H_count: process(Clk_5)
begin
if rising_edge(Clk_5) then
if h_counter = "1111111111" then
h_counter <= "0100000000";
else
h_counter <= h_counter + 1;
end if;
end if;
end process;
-- HCount
-- (0) 1H 3 MHz
-- (1) 2H 1.5MHz
-- (2) 4H 750 kHz
-- (3) 8H 375 kHz
-- (4) 16H 187 kHz
-- (5) 32H 93 kHz
-- (6) 64H 46 kHz
-- (7) 128H 23 kHz
-- (8) 256H 12 kHz
-- HCount
-- (0) 1H 2.5 MHz
-- (1) 2H 1.25MHz
-- (2) 4H 625 kHz
-- (3) 8H 312 kHz
-- (4) 16H 156 kHz
-- (5) 32H 78 kHz
-- (6) 64H 39 kHz
-- (7) 128H 19 kHz
-- (8) 256H 9 kHz
--H4 <= HCount(2);
--V2 <= HCount(3); -- not correct
H4 <= HCount(2); -- 750kHz??
V2 <= HCount(5); -- not correct
-- Generate the 3kHz clock enable used by the filter
Enable: process(Clk_5)
begin
if rising_edge(Clk_5) then
ena_count <= ena_count + "1";
ena_3k <= '0';
--if (ena_count(11 downto 0) = "000000000000") then
if (ena_count(11 downto 0) = "110101010101") then
ena_3k <= '1';
ena_count<="000000000000";
end if;
end if;
end process;
-- LFSR that generates pseudo-random noise
Noise_gen: process(NoiseReset_n, V2)
begin
if (noisereset_n = '0') then
noise_shift <= (others => '0');
noise <= '0';
elsif rising_edge(V2) then
shift_in <= not(noise_shift(6) xor noise_shift(8));
noise_shift <= shift_in & noise_shift(15 downto 1);
noise <= noise_shift(0);
end if;
end process;
-- Tire screech sound
Screech_gen1: entity work.tire_screech
generic map( -- These values can be tweaked to tune the screech sound
Inc1 => 24, -- Ramp increase rate when noise = 0
Inc2 => 33, -- Ramp increase rate when noise = 1
Dec1 => 29, -- Ramp decrease rate when noise = 0
Dec2 => 16 -- Ramp decrease rate when noise = 1
)
port map(
Clk => H4,
Noise => noise,
Screech_out => screech_snd1
);
-- Convert screech from 1 bit to 4 bits wide and enable via skid1 signal
Screech_ctrl: process(screech_snd1, Skid1)
begin
if (Skid1 and screech_snd1) = '1' then
screech1 <= "1111";
else
screech1 <= "0000";
end if;
end process;
--Crash_sound: process(crash_n, motorspeed, noise)
--begin
-- if crash_n = '0' then
-- crash <= not motorspeed(3 downto 0);
-- end if;
-- if noise = '1' then
-- bang_prefilter <= crash;
-- else
-- bang_prefilter <= "0000";
-- end if;
--end process;
---- Very simple low pass filter, borrowed from MikeJ's Asteroids code
Crash_filter: process(Clk_5)
begin
if rising_edge(Clk_5) then
if (ena_3k = '1') then
bang_filter_t1 <= bang_prefilter;
bang_filter_t2 <= bang_filter_t1;
bang_filter_t3 <= bang_filter_t2;
end if;
bang_filtered <= ("00" & bang_filter_t1) +
('0' & bang_filter_t2 & '0') +
("00" & bang_filter_t3);
end if;
end process;
Motor1: entity work.EngineSound
generic map(
Freq_tune => 40 -- Tuning pot for engine sound frequency
)
port map(
Clk_5 => clk_5,
Ena_3k => ena_3k,
EngineData => motorspeed,
Motor => Motor1_Snd_o
);
Motor1_Snd <= Motor1_Snd_o when Motor1_n = '0' else (others => '0');
-- Audio mixer, also mutes sound in attract mode
--Audio1 <= '0' & ('0' & motor1_snd) + ('0' & screech1 & '0') + ('0' & bang_filtered);
--Audio1 <= '0' & ('0' & motor1_snd) + ("00" & screech1) ;
Audio1 <= ('0' & motor1_snd & '0') + ('0' & screech1 & '0');
end rtl;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
width_a => data_width_g,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => q
);
END SYN;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity spy_hunter_control is
port(
clock_40 : in std_logic;
reset : in std_logic;
vsync : in std_logic;
gas_plus : in std_logic;
gas_minus : in std_logic;
steering_plus : in std_logic;
steering_minus: in std_logic;
steering : out std_logic_vector(7 downto 0);
gas : out std_logic_vector(7 downto 0)
);
end spy_hunter_control;
architecture struct of spy_hunter_control is
signal steering_r : std_logic_vector(7 downto 0);
--signal steering_plus : std_logic;
signal steering_plus_r : std_logic;
--signal steering_minus : std_logic;
signal steering_minus_r : std_logic;
signal steering_timer : std_logic_vector(5 downto 0);
signal gas_r : std_logic_vector(7 downto 0);
--signal gas_plus : std_logic;
signal gas_plus_r : std_logic;
--signal gas_minus : std_logic;
signal gas_minus_r : std_logic;
signal gas_timer : std_logic_vector(5 downto 0);
signal vsync_r : std_logic;
begin-- absolute position decoder simulation
--
-- steering :
-- thresholds median
-- F5 < left 8 < 34 30
-- 35 < left 7 < 3C 38
-- 3D < left 6 < 44 40
-- 45 < left 5 < 4C 48
-- 4D < left 4 < 54 50
-- 45 < left 3 < 5C 58
-- 5D < left 2 < 64 60
-- 65 < left 1 < 6C 68
-- 6D < centrered < 74 70
-- 75 < right 1 < 7C 78
-- 7D < right 2 < 84 80
-- 85 < right 3 < 8C 88
-- 8D < right 4 < 94 90
-- 95 < right 5 < 9C 98
-- 9D < right 6 < A4 A0
-- A5 < right 7 < AC A8
-- AD < right 8 < F4 BO
-- gas :
-- threshold median
-- 00 < gas pedal 00 < 3B (39) 3E-5
-- 3C < gas pedal 01 < 40 3E
-- 41 < gas pedal 02 < 45 43
-- 46 < gas pedal 03 < 4A 48
-- 4B < gas pedal 04 < 4F 4D
-- 50 < gas pedal 05 < 54 52
-- 55 < gas pedal 06 < 59 57
-- 5A < gas pedal 07 < 5E 5C
-- 5F < gas pedal 08 < 63 61
-- ...
-- FA < gas pedal 27 < FE FC
-- FF = gas pedal 28 (FF) FC+4
gas <= gas_r;
steering <= steering_r;
process (clock_40, reset)
begin
if reset = '1' then
gas_r <= x"39";
steering_r <= x"70";
else
if rising_edge(clock_40) then
gas_plus_r <= gas_plus;
gas_minus_r <= gas_minus;
steering_plus_r <= steering_plus;
steering_minus_r <= steering_minus;
vsync_r <= vsync;
-- gas increase/decrease as long as btn is pushed
-- keep current value when no btn is pushed
if gas_r < x"39" then
gas_r <= x"39";
else
if (gas_plus_r = not gas_plus) or
(gas_minus_r = not gas_minus) then
gas_timer <= (others => '0');
else
if vsync_r ='0' and vsync = '1' then
if (gas_timer >= 5 and gas_plus_r = '1') or
(gas_timer >= 2 and gas_minus_r = '1') then --tune inc/dec rate
gas_timer <= (others => '0');
else
gas_timer <= gas_timer + 1;
end if;
end if;
end if;
if vsync_r ='0' and vsync = '1' and gas_timer = 0 then
if gas_plus = '1' then
if gas_r >= x"FC" then gas_r <= x"FF"; else gas_r <= gas_r + 5; end if;
elsif gas_minus = '1' then
if gas_r <= x"3E" then gas_r <= x"39"; else gas_r <= gas_r - 5; end if;
end if;
end if;
end if;
-- steering increase/decrease as long as btn is pushed
-- return to center value when no btn is pushed
if steering_r < x"30" then
steering_r <= x"30";
elsif steering_r > x"B0" then
steering_r <= x"B0";
else
if (steering_plus_r = not steering_plus) or
(steering_minus_r = not steering_minus) then
steering_timer <= (others => '0');
else
if vsync_r ='0' and vsync = '1' then
if (steering_timer >= 5 and (steering_minus_r = '1' or steering_plus_r = '1')) or -- tune btn pushed rate
(steering_timer >= 2 and (steering_minus_r = '0' and steering_plus_r = '0')) then -- tune btn released rate
steering_timer <= (others => '0');
else
steering_timer <= steering_timer + 1;
end if;
end if;
end if;
if vsync_r ='0' and vsync = '1' and steering_timer = 0 then
if steering_plus = '1' then
if steering_r >= x"A8" then steering_r <= x"B0"; else steering_r <= steering_r + 8; end if;
elsif steering_minus = '1' then
if steering_r <= x"38" then steering_r <= x"30"; else steering_r <= steering_r - 8; end if;
else
if steering_r <= x"68" then steering_r <= steering_r + 8; end if;
if steering_r >= x"78" then steering_r <= steering_r - 8; end if;
if (steering_r > x"68") and (steering_r < x"78") then steering_r <= x"70"; end if;
end if;
end if;
end if;
end if;
end if;
end process;
end struct;

2
Arcade_MiST/Nichibutsu Galivan Hardware/rtl/core.v
View File

@@ -286,12 +286,14 @@ always @(posedge clk_sys) begin
endcase
end
// for scroll layer debug
/*
if (real_pause) begin
if (~j1[0] & old_j1[0]) scrollx <= scrollx - 5'd16;
if (~j1[1] & old_j1[1]) scrollx <= scrollx + 5'd16;
if (~j1[2] & old_j1[2]) scrollx <= scrollx - 1'd1;
if (~j1[3] & old_j1[3]) scrollx <= scrollx + 1'd1;
end
*/
end
/******** MCPU DATA BUS ********/

2
Arcade_MiST/Nichibutsu Galivan Hardware/rtl/gfx.v
View File

@@ -128,7 +128,7 @@ reg [7:0] spy;
reg [8:0] code;
wire [7:0] smap_q = smap[spri];
wire [8:0] spy_next = v_flip ? smap_q - 1'd1 : 8'd239 - smap_q;
wire [8:0] spy_next = v_flip ? smap_q : 8'd239 - smap_q;
wire [7:0] spxa = spx[7:0] - 8'd128;
wire [7:0] sdy = vv - spy;
wire [3:0] sdyf = (!v_flip ^ attr[7]) ? sdy[3:0] : 4'd15 - sdy[3:0];

6
Arcade_MiST/Nintendo Radar Scope Hardware/DKong.qsf
View File

@@ -249,9 +249,9 @@ set_global_assignment -name VERILOG_FILE rtl/dkong_bram.v
set_global_assignment -name VERILOG_FILE rtl/dkong_adec.v
set_global_assignment -name VERILOG_FILE rtl/radarscp_stars.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE ../../../common/CPU/t48/T48.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/CPU/t48/T48.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name SIGNALTAP_FILE output_files/dkong.stp
set_global_assignment -name SIGNALTAP_FILE output_files/dl.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stars.stp

31
Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/Prehisle.qpf Normal file
View File

@@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
# Date created = 04:04:47 October 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "Prehisle"

221
Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/Prehisle.qsf Normal file
View File

@@ -0,0 +1,221 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 05:08:48 November 15, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Arcade-Scramble_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY Prehisle_MiST
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# ----------------------
# start ENTITY(Prehisle)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Prehisle)
# --------------------
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/spr.stp
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name FORCE_SYNCH_CLEAR ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Prehisle_MiST.sv
set_global_assignment -name QIP_FILE rtl/pll_mist.qip
set_global_assignment -name VERILOG_FILE rtl/video_timing.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/prehisle.sv
set_global_assignment -name VHDL_FILE rtl/math.vhd
set_global_assignment -name VHDL_FILE rtl/dual_port_ram.vhd
set_global_assignment -name VERILOG_FILE rtl/chip_select.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/Sound/jtopl/jtopl2.qip
set_global_assignment -name QIP_FILE ../../../common/Sound/jt7759/jt7759.qip
set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
set_global_assignment -name SIGNALTAP_FILE output_files/z80.stp
set_global_assignment -name SIGNALTAP_FILE output_files/spr.stp
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

138
Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/Prehisle.sdc Normal file
View File

@@ -0,0 +1,138 @@
## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from {prehisle:prehisle|T80pa:z80|T80:u0|*} -setup 2
set_multicycle_path -from {prehisle:prehisle|T80pa:z80|T80:u0|*} -hold 1
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

12
Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/README.md Normal file
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@@ -0,0 +1,12 @@
# SNK M68000 (Prehistoric Isle in 1930) FPGA Implementation
FPGA compatible core of SNK M68000 (Prehistoric Isle in 1930 based) arcade hardware, originally written by [**Darren Olafson**](https://twitter.com/Darren__O).
Support the original author via [**Ko-fi**](https://ko-fi.com/darreno). While it isn't necessary, it's greatly appreciated.
MiST port, new SDRAM controller, clocking and other fixes, graphics rewrite by Gyorgy Szombathelyi.
# Licensing
Contact the author for special licensing needs. Otherwise follow the GPLv2 license attached.

56
Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/meta/Prehistoric Isle in 1930 (World).mra Normal file
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@@ -0,0 +1,56 @@
<misterromdescription>
<name>Prehistoric Isle in 1930 (World)</name>
<setname>prehisle</setname>
<mameversion>0245</mameversion>
<year>1989</year>
<manufacturer>SNK</manufacturer>
<region>World</region>
<rbf>prehisle</rbf>
<switches default="04,00" base="16" page_id="1" page_name="Switches">
<!-- DSW0 -->
<dip name="Flip Picture" bits="0" ids="Off,On"/>
<dip name="Level Select" bits="1" ids="Off,On"/>
<dip name="Bonus Life" bits="2" ids="2nd Extend Only,Every Extend"/>
<dip name="Coinage" bits="4,5" ids="1/1,A 2C/1C B 1C/2C,A 3C/1C B 1C/3C,A 4C/1C B 1C/4C"/>
<dip name="Lives" bits="6,7" ids="3,2,4,5"/>
<!-- DSW1 -->
<dip name="Difficulty Level" bits="8,9" ids="Normal,Easy,Hard,Hardest"/>
<dip name="Demo Sound/Cheat" bits="10,11" ids="Sound On,Sound Off,Inf.Lives,Freeze"/>
<dip name="Bonus Life" bits="12,13" ids="100/150K,150/300K,300/500K,None"/>
<dip name="Continue Mode" bits="14" ids="Yes,No"/>
</switches>
<buttons names="Shot,Option,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
<rom index="0" zip="prehisle.zip" md5="None">
<!-- maincpu - starts at 0x0 256K -->
<interleave output="16">
<part name="gt-e2.2h" crc="7083245a" map="01"/>
<part name="gt-e3.3h" crc="6d8cdf58" map="10"/>
</interleave>
<!-- fgtiles - starts at 0x40000 256K -->
<part name="pi8916.h16" crc="7cffe0f6"/>
<!-- bgtiles - starts at 0x80000 256K -->
<part name="pi8914.b14" crc="207d6187"/>
<!-- audiocpu - starts at 0xc0000 64K -->
<part name="gt1.1" crc="80a4c093"/>
<!-- upd - starts at 0xd0000 128K -->
<part name="gt4.4" crc="85dfb9ec"/>
<!-- bgtilemap - starts at 0xf0000 64K -->
<part name="gt11.11" crc="b4f0fcf0"/>
<!-- sprites - starts at 0x100000 1M -->
<part name="pi8910.k14" crc="5a101b0b"/>
<part name="gt5.5" crc="3d3ab273"/>
<part repeat="0x60000"> FF</part>
<!-- chars - starts at 0x200000 32K -->
<part name="gt15.b15" crc="ac652412"/>
</rom>
</misterromdescription>

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//============================================================================
// SNK M68000 HW top-level for MiST
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module Prehisle_MiST
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
inout SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input SPI_SS4,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
//`define DEBUG
`include "rtl\build_id.v"
`define CORE_NAME "PREHISLE"
wire [6:0] core_mod;
localparam CONF_STR = {
`CORE_NAME, ";;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Joystick Swap,Off,On;",
"O7,Pause,Off,On;",
"O8,Service,Off,On;",
"O1,Video Timing,54.1Hz (PCB),59.2Hz (MAME);",
`ifdef DEBUG
"O9,GFX1,On,Off;",
"OA,GFX2,On,Off;",
"OB,GFX3,On,Off;",
"OC,GFX4,On,Off;",
"OD,Flip,Off,On;",
`endif
"DIP;",
"T0,Reset;",
"V,v1.20.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
wire pause = status[7];
wire service = status[8];
wire vidmode = status[1];
reg [7:0] dsw1;
reg [6:0] dsw2;
reg [7:0] p1, p2;
reg [15:0] coin;
reg [1:0] orientation;
wire key_test = m_fire1[3];
always @(*) begin
orientation = 2'b10;
p1 = ~{ m_one_player, m_fire1[2:0], m_right1, m_left1, m_down1, m_up1 };
p2 = ~{ m_two_players, m_fire2[2:0], m_right2, m_left2, m_down2, m_up2 };
dsw1 = ~status[23:16];
dsw2 = ~status[30:24];
coin = { 11'h7ff, ~m_tilt, ~service, ~key_test, ~m_coin1, ~m_coin2 };
end
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_72;
assign SDRAM_CKE = 1;
wire clk_72;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.c0(clk_72),
.locked(pll_locked)
);
// reset generation
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_72) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl;
end
// ARM connection
wire [63:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [31:0] joystick_0;
wire [31:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
user_io #(
.STRLEN($size(CONF_STR)>>3),
.ROM_DIRECT_UPLOAD(1))
user_io(
.clk_sys (clk_72 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io #(.ROM_DIRECT_UPLOAD(1)) data_io(
.clk_sys ( clk_72 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_SS4 ( SPI_SS4 ),
.SPI_DI ( SPI_DI ),
.SPI_DO ( SPI_DO ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
wire [15:0] laudio, raudio;
wire hs, vs;
wire blankn = ~(hb | vb);
wire hb, vb;
wire [3:0] r,b,g;
prehisle prehisle
(
.pll_locked ( pll_locked ),
.clk_sys ( clk_72 ),
.reset ( reset ),
.pause_cpu ( pause ),
.refresh_sel ( vidmode ),
`ifdef DEBUG
.gfx_tx_en ( ~status[9] ),
.gfx_fg_en ( ~status[10]),
.gfx_bg_en ( ~status[11]),
.gfx_sp_en ( ~status[12]),
.test_flip ( status[13] ),
`else
.gfx_tx_en ( 1'b1 ),
.gfx_fg_en ( 1'b1 ),
.gfx_bg_en ( 1'b1 ),
.gfx_sp_en ( 1'b1 ),
.test_flip ( 1'b0 ),
`endif
.p1 ( p1 ),
.p2 ( p2 ),
.dsw1 ( dsw1 ),
.dsw2 ( dsw2 ),
.coin ( coin ),
.hbl ( hb ),
.vbl ( vb ),
.hsync ( hs ),
.vsync ( vs ),
.r ( r ),
.g ( g ),
.b ( b ),
.audio_l ( laudio ),
.audio_r ( raudio ),
.rom_download ( ioctl_downl && ioctl_index == 0),
.ioctl_addr ( ioctl_addr ),
.ioctl_wr ( ioctl_wr ),
.ioctl_dout ( ioctl_dout ),
.SDRAM_A ( SDRAM_A ),
.SDRAM_BA ( SDRAM_BA ),
.SDRAM_DQ ( SDRAM_DQ ),
.SDRAM_DQML ( SDRAM_DQML ),
.SDRAM_DQMH ( SDRAM_DQMH ),
.SDRAM_nCS ( SDRAM_nCS ),
.SDRAM_nCAS ( SDRAM_nCAS ),
.SDRAM_nRAS ( SDRAM_nRAS ),
.SDRAM_nWE ( SDRAM_nWE )
);
mist_video #(.COLOR_DEPTH(4),.SD_HCNT_WIDTH(10)) mist_video(
.clk_sys(clk_72),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : 6'd0),
.G(blankn ? g : 6'd0),
.B(blankn ? b : 6'd0),
.HSync(~hs),
.VSync(~vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.no_csync(no_csync),
.rotate({orientation[1],rotate}),
.ce_divider(1'b0),
.blend(blend),
.scandoubler_disable(scandoublerD),
.scanlines(scanlines),
.ypbpr(ypbpr)
);
dac #(16) dacl(
.clk_i(clk_72),
.res_n_i(1),
.dac_i({~laudio[15], laudio[14:0]}),
.dac_o(AUDIO_L)
);
dac #(16) dacr(
.clk_i(clk_72),
.res_n_i(1),
.dac_i({~raudio[15], raudio[14:0]}),
.dac_o(AUDIO_R)
);
// Common inputs
wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B;
wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
wire [11:0] m_fire1, m_fire2;
arcade_inputs inputs (
.clk ( clk_72 ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( joyswap ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ),
.player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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//
module chip_select
(
input [23:0] m68k_a,
input m68k_as_n,
input m68k_uds_n,
input m68k_lds_n,
input [15:0] z80_addr,
input MREQ_n,
input IORQ_n,
input M1_n,
input RFSH_n,
// M68K selects
output reg m68k_rom_cs,
output reg m68k_ram_cs,
output reg m68k_txt_ram_cs,
output reg m68k_spr_cs,
output reg m68k_pal_cs,
output reg m68k_fg_ram_cs,
output reg input_p1_cs,
output reg input_p2_cs,
output reg input_dsw1_cs,
output reg input_dsw2_cs,
output reg input_coin_cs,
output reg bg_scroll_x_cs,
output reg bg_scroll_y_cs,
output reg fg_scroll_x_cs,
output reg fg_scroll_y_cs,
output reg flip_cs,
output reg m_invert_ctrl_cs,
output reg sound_latch_cs,
// Z80 selects
output reg z80_rom_cs,
output reg z80_ram_cs,
output reg z80_latch_cs,
output reg z80_sound0_cs,
output reg z80_sound1_cs,
output reg z80_upd_cs,
output reg z80_upd_r_cs
);
function m68k_cs;
input [23:0] start_address;
input [23:0] end_address;
begin
m68k_cs = ( m68k_a[23:0] >= start_address && m68k_a[23:0] <= end_address) & !m68k_as_n & ~(m68k_uds_n & m68k_lds_n);
end
endfunction
function z80_mem_cs;
input [15:0] base_address;
input [7:0] width;
begin
z80_mem_cs = ( z80_addr >> width == base_address >> width ) & !MREQ_n & IORQ_n & RFSH_n;
end
endfunction
function z80_io_cs;
input [7:0] address_lo;
begin
z80_io_cs = ( z80_addr[7:0] == address_lo ) && !IORQ_n ;
end
endfunction
always @ (*) begin
// map(0x000000, 0x03ffff).rom();
m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
// map(0x070000, 0x073fff).ram();
m68k_ram_cs = m68k_cs( 24'h070000, 24'h073fff ) ;
// map(0x090000, 0x0907ff).ram().w(FUNC(prehisle_state::tx_vram_w)).share("tx_vram");
m68k_txt_ram_cs = m68k_cs( 24'h090000, 24'h0907ff ) ;
// map(0x0a0000, 0x0a07ff).ram().share("spriteram");
m68k_spr_cs = m68k_cs( 24'h0a0000, 24'h0a07ff ) ;
// map(0x0b0000, 0x0b3fff).ram().w(FUNC(prehisle_state::fg_vram_w)).share("fg_vram");
m68k_fg_ram_cs = m68k_cs( 24'h0b0000, 24'h0b3fff ) ;
// map(0x0d0000, 0x0d07ff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
m68k_pal_cs = m68k_cs( 24'h0d0000, 24'h0d07ff ) ;
// map(0x0e0010, 0x0e0011).portr("P2"); // Player 2
input_p2_cs = m68k_cs( 24'h0e0010, 24'h0e0011 ) ;
// map(0x0e0020, 0x0e0021).portr("COIN"); // Coins, Tilt, Service
input_coin_cs = m68k_cs( 24'h0e0020, 24'h0e0021 ) ;
// map(0x0e0041, 0x0e0041).lr8(NAME([this] () -> u8 { return m_io_p1->read() ^ m_invert_controls; })); // Player 1
input_p1_cs = m68k_cs( 24'h0e0040, 24'h0e0041 ) ;
// map(0x0e0042, 0x0e0043).portr("DSW0"); // DIPs
input_dsw1_cs = m68k_cs( 24'h0e0042, 24'h0e0043 ) ;
// map(0x0e0044, 0x0e0045).portr("DSW1"); // DIPs + VBLANK
input_dsw2_cs = m68k_cs( 24'h0e0044, 24'h0e0045 ) ;
// map(0x0f0000, 0x0f0001).w(FUNC(prehisle_state::fg_scrolly_w));
fg_scroll_y_cs = m68k_cs( 24'h0f0000, 24'h0f0001 ) ;
// map(0x0f0010, 0x0f0011).w(FUNC(prehisle_state::fg_scrollx_w));
fg_scroll_x_cs = m68k_cs( 24'h0f0010, 24'h0f0011 ) ;
// map(0x0f0020, 0x0f0021).w(FUNC(prehisle_state::bg_scrolly_w));
bg_scroll_y_cs = m68k_cs( 24'h0f0020, 24'h0f0021 ) ;
// map(0x0f0030, 0x0f0031).w(FUNC(prehisle_state::bg_scrollx_w));
bg_scroll_x_cs = m68k_cs( 24'h0f0030, 24'h0f0031 ) ;
// map(0x0f0046, 0x0f0047).lw16(NAME([this] (u16 data) { m_invert_controls = data ? 0xff : 0x00; })); // P1 Invert Controls
m_invert_ctrl_cs = m68k_cs( 24'h0f0046, 24'h0f0047 ) ;
flip_cs = m68k_cs( 24'h0f0060, 24'h0f0061 ) ;
// map(0x0f0070, 0x0f0071).w(FUNC(prehisle_state::soundcmd_w));
sound_latch_cs = m68k_cs( 24'h0f0070, 24'h0f0071 ) ;
z80_rom_cs = RFSH_n && !MREQ_n && z80_addr[15:0] < 16'hf000;
z80_ram_cs = RFSH_n && !MREQ_n && z80_addr[15:0] >= 16'hf000 && z80_addr[15:0] < 16'hf800;
z80_latch_cs = RFSH_n && !MREQ_n && z80_addr[15:0] == 16'hf800;
z80_sound0_cs = z80_io_cs(8'h00); // ym3812 address
z80_sound1_cs = z80_io_cs(8'h20); // ym3812 data
z80_upd_cs = z80_io_cs(8'h40); // 7759 write
z80_upd_r_cs = z80_io_cs(8'h80); // 7759 reset
end
// map(0x0f0046, 0x0f0047).lw16(NAME([this] (u16 data) { m_invert_controls = data ? 0xff : 0x00; }));
// map(0x0f0050, 0x0f0051).lw16(NAME([this] (u16 data) { machine().bookkeeping().coin_counter_w(0, data & 1); }));
// map(0x0f0052, 0x0f0053).lw16(NAME([this] (u16 data) { machine().bookkeeping().coin_counter_w(1, data & 1); }));
// map(0x0f0060, 0x0f0061).lw16(NAME([this] (u16 data) { flip_screen_set(data & 0x01); }));
// map(0x0000, 0xefff).rom();
// map(0xf000, 0xf7ff).ram();
// map(0xf800, 0xf800).r(m_soundlatch, FUNC(generic_latch_8_device::read));
// map(0xf800, 0xf800).nopw(); // ???
// map.global_mask(0xff);
// map(0x00, 0x00).rw("ymsnd", FUNC(ym3812_device::status_r), FUNC(ym3812_device::address_w));
// map(0x20, 0x20).w("ymsnd", FUNC(ym3812_device::data_w));
// map(0x40, 0x40).w(FUNC(prehisle_state::upd_port_w));
// map(0x80, 0x80).lw8(NAME([this] (u8 data) { m_upd7759->reset_w(BIT(data, 7)); }));
endmodule

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-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- 2022-05-24 Changed to use word count instead of address width
-- and renamed ports to match quartus IP naming
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--use work.common.all;
use work.math.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity dual_port_ram is
generic (
LEN : natural := 8192;
DATA_WIDTH : natural := 8
);
port (
-- port A
clock_a : in std_logic;
address_a : in unsigned(ilog2(LEN)-1 downto 0);
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
wren_a : in std_logic := '0';
-- port B
clock_b : in std_logic;
address_b : in unsigned(ilog2(LEN)-1 downto 0);
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0);
wren_b : in std_logic := '0'
);
end dual_port_ram;
architecture arch of dual_port_ram is
begin
altsyncram_component : altsyncram
generic map (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => LEN,
numwords_b => LEN,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
width_a => DATA_WIDTH,
width_b => DATA_WIDTH,
width_byteena_a => 1,
width_byteena_b => 1,
widthad_a => ilog2(LEN),
widthad_b => ilog2(LEN),
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
address_a => std_logic_vector(address_a),
address_b => std_logic_vector(address_b),
clock0 => clock_a,
clock1 => clock_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => q_a,
q_b => q_b
);
end architecture arch;

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-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package math is
-- calculates the log2 of the given number
function ilog2(n : natural) return natural;
-- Masks the given range of bits for a vector.
--
-- Only the bits between the MSB and LSB (inclusive) will be kept, all other
-- bits will be masked out.
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector;
end package math;
package body math is
function ilog2(n : natural) return natural is
begin
return natural(ceil(log2(real(n))));
end ilog2;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector is
variable n : natural;
variable mask : std_logic_vector(data'length-1 downto 0);
begin
n := (2**(msb-lsb+1))-1;
mask := std_logic_vector(shift_left(to_unsigned(n, mask'length), lsb));
return std_logic_vector(shift_right(unsigned(data AND mask), lsb));
end mask_bits;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector is
begin
return std_logic_vector(resize(unsigned(mask_bits(data, msb, lsb)), size));
end mask_bits;
end package body math;

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Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/rtl/pll_mist.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]

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Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/rtl/pll_mist.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_mist.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_mist (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 3,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

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Arcade_MiST/SNK M68000 Harware/PrehistoricIsle/rtl/sdram.sv Normal file
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//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019-2022 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
// 1st bank
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
// cpu1 rom/ram
input [21:1] cpu1_rom_addr,
input cpu1_rom_cs,
output reg [15:0] cpu1_rom_q,
output reg cpu1_rom_valid,
input cpu1_ram_req,
output reg cpu1_ram_ack,
input [19:1] cpu1_ram_addr,
input cpu1_ram_we,
input [1:0] cpu1_ram_ds,
input [15:0] cpu1_ram_d,
output reg [15:0] cpu1_ram_q,
// cpu2 rom
input [21:1] cpu2_addr,
input cpu2_rom_cs,
output reg [15:0] cpu2_q,
output reg cpu2_valid,
// cpu3 rom
input [21:1] cpu3_addr,
input cpu3_rom_cs,
output reg [15:0] cpu3_q,
output reg cpu3_valid,
// cpu4 rom
input [21:1] cpu4_addr,
input cpu4_rom_cs,
output reg [15:0] cpu4_q,
output reg cpu4_valid,
// 2nd bank
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [31:0] port2_q,
input [21:2] gfx1_addr,
output reg [31:0] gfx1_q,
input [21:2] gfx2_addr,
output reg [31:0] gfx2_q,
input [21:2] gfx3_addr,
output reg [31:0] gfx3_q,
input [21:2] sp_addr,
input sp_req,
output reg sp_ack,
output reg [31:0] sp_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
2 words burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0
2 data1 returned
3 CAS0 data1 returned
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_DS1b = 3'd0;
localparam STATE_READ1b = 3'd4;
localparam STATE_LAST = 3'd6;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[3];
reg [24:1] addr_latch_next[2];
reg [21:1] addr_last[1:5];
reg [21:2] addr_last2[5];
reg [15:0] din_next;
reg [15:0] din_latch[2];
reg oe_next;
reg [1:0] oe_latch;
reg we_next;
reg [1:0] we_latch;
reg [1:0] ds_next;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
reg cpu1_ram_req_state;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1_ROM = 3'd1;
localparam PORT_CPU1_RAM = 3'd2;
localparam PORT_CPU2 = 3'd3;
localparam PORT_CPU3 = 3'd4;
localparam PORT_CPU4 = 3'd5;
localparam PORT_GFX1 = 3'd1;
localparam PORT_GFX2 = 3'd2;
localparam PORT_GFX3 = 3'd3;
localparam PORT_SP = 3'd4;
localparam PORT_REQ = 3'd6;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
ds_next = 2'b00;
{ oe_next, we_next } = 2'b00;
din_next = 0;
if (refresh) begin
// nothing
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
ds_next = port1_ds;
{ oe_next, we_next } = { ~port1_we, port1_we };
din_next = port1_d;
end else if (/*cpu1_rom_addr != addr_last[PORT_CPU1_ROM] &&*/ cpu1_rom_cs && !cpu1_rom_valid) begin
next_port[0] = PORT_CPU1_ROM;
addr_latch_next[0] = { 3'd0, cpu1_rom_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end else if (cpu1_ram_req ^ cpu1_ram_req_state) begin
next_port[0] = PORT_CPU1_RAM;
addr_latch_next[0] = { 2'b00, 3'b100, cpu1_ram_addr };
ds_next = cpu1_ram_ds;
{ oe_next, we_next } = { ~cpu1_ram_we, cpu1_ram_we };
din_next = cpu1_ram_d;
end else if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 3'd0, cpu2_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end else if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) begin
next_port[0] = PORT_CPU3;
addr_latch_next[0] = { 3'd0, cpu3_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end else if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) begin
next_port[0] = PORT_CPU4;
addr_latch_next[0] = { 3'd0, cpu4_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (gfx1_addr != addr_last2[PORT_GFX1]) begin
next_port[1] = PORT_GFX1;
addr_latch_next[1] = { 1'b1, 2'd0, gfx1_addr, 1'b0 };
end else if (gfx2_addr != addr_last2[PORT_GFX2]) begin
next_port[1] = PORT_GFX2;
addr_latch_next[1] = { 1'b1, 2'd0, gfx2_addr, 1'b0 };
end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin
next_port[1] = PORT_GFX3;
addr_latch_next[1] = { 1'b1, 2'd0, gfx3_addr, 1'b0 };
end else if (sp_req ^ sp_ack) begin
next_port[1] = PORT_SP;
addr_latch_next[1] = { 1'b1, 2'd0, sp_addr, 1'b0 };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
{ cpu1_rom_valid, cpu2_valid, cpu3_valid, cpu4_valid } <= 0;
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
if (!cpu1_rom_cs) cpu1_rom_valid <= 0;
if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) cpu2_valid <= 0;
if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) cpu3_valid <= 0;
if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) cpu4_valid <= 0;
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
end
addr_last[next_port[0]] <= addr_latch_next[0][21:1];
ds[0] <= ds_next;
{ oe_latch[0], we_latch[0] } <= { oe_next, we_next };
din_latch[0] <= din_next;
if (next_port[0] == PORT_REQ) port1_state <= port1_req;
if (next_port[0] == PORT_CPU1_RAM) cpu1_ram_req_state <= cpu1_ram_req;
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][21:2];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
case(port[0])
PORT_REQ: port1_ack <= port1_req;
PORT_CPU1_RAM: cpu1_ram_ack <= cpu1_ram_req;
default: ;
endcase;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1_ROM: begin cpu1_rom_q <= sd_din; cpu1_rom_valid <= 1; end
PORT_CPU1_RAM: begin cpu1_ram_q <= sd_din; cpu1_ram_ack <= cpu1_ram_req; end
PORT_CPU2: begin cpu2_q <= sd_din; cpu2_valid <= 1; end
PORT_CPU3: begin cpu3_q <= sd_din; cpu3_valid <= 1; end
PORT_CPU4: begin cpu4_q <= sd_din; cpu4_valid <= 1; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ : port2_q[15:0] <= sd_din;
PORT_GFX1 : gfx1_q[15:0] <= sd_din;
PORT_GFX2 : gfx2_q[15:0] <= sd_din;
PORT_GFX3 : gfx3_q[15:0] <= sd_din;
PORT_SP : sp_q[15:0] <= sd_din;
default: ;
endcase;
end
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if(t == STATE_READ1b && oe_latch[1]) begin
case(port[1])
PORT_REQ : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
PORT_GFX1 : begin gfx1_q[31:16] <= sd_din; end
PORT_GFX2 : begin gfx2_q[31:16] <= sd_din; end
PORT_GFX3 : begin gfx3_q[31:16] <= sd_din; end
PORT_SP : begin sp_q[31:16] <= sd_din; sp_ack <= sp_req; end
default: ;
endcase;
end
end
end
endmodule

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module video_timing
(
input clk,
input clk_pix,
input reset,
input refresh_mod,
input signed [3:0] hs_offset,
input signed [3:0] vs_offset,
input signed [3:0] hs_width,
input signed [3:0] vs_width,
output [8:0] hc,
output [8:0] vc,
output reg hsync,
output reg vsync,
output reg hbl,
output reg vbl
);
wire [8:0] h_ofs = 0;
wire [8:0] HBL_START = 274;
wire [8:0] HBL_END = 18;
wire [8:0] HS_START = HBL_START + 24 + $signed(hs_offset);
wire [8:0] HS_END = HBL_START + 56 + $signed(hs_offset) + $signed(hs_width);
wire [8:0] HTOTAL = 383;
wire [8:0] v_ofs = 0;
wire [8:0] VBL_START = 240 ;
wire [8:0] VBL_END = 16 ;
wire [8:0] VS_START = VBL_START + ( refresh_mod ? 20 : 10 ) + $signed(vs_offset);
wire [8:0] VS_END = VBL_START + ( refresh_mod ? 24 : 13 )+ $signed(vs_offset) + $signed(vs_width);
wire [8:0] VTOTAL = 288 - ( refresh_mod ? 0 : 25 );
reg [8:0] v;
reg [8:0] h;
assign vc = v - v_ofs;
assign hc = h - h_ofs;
always @ (posedge clk) begin
if (reset) begin
h <= 0;
v <= 0;
hbl <= 0;
vbl <= 0;
hsync <= 0;
vsync <= 0;
end else if ( clk_pix == 1 ) begin
// counter
if (h == HTOTAL) begin
h <= 0;
v <= v + 1'd1;
if ( v == VTOTAL ) begin
v <= 0;
end
end else begin
h <= h + 1'd1;
end
// h signals
if ( h == HBL_START ) begin
hbl <= 1;
end else if ( h == HBL_END ) begin
hbl <= 0;
end
// v signals
if ( v == VBL_START ) begin
vbl <= 1;
end else if ( v == VBL_END ) begin
vbl <= 0;
end
if ( v == (VS_START ) ) begin
vsync <= 1;
end else if ( v == (VS_END ) ) begin
vsync <= 0;
end
if ( h == (HS_START ) ) begin
hsync <= 1;
end else if ( h == (HS_END ) ) begin
hsync <= 0;
end
end
end
endmodule

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# SNK M68000 (Ikari III) FPGA Implementation
FPGA compatible core of SNK M68000 (Ikari III based) arcade hardware originally written by [**Darren Olafson**](https://twitter.com/Darren__O). FPGA implementation has been verified against schematics for Ikari III (A7007). PCB measurements taken from Datsugoku: Prisoners of War (A7008), Street Smart (A8007), and Ikari III: The Rescue (A7007).
Ikari III PCB donated by [**atrac17**](https://github.com/atrac17) / [**DJ Hard Rich**](https://twitter.com/djhardrich) and verified by [**Darren Olafson**](https://twitter.com/Darren__O). Other SNK68K PCB verification done by [**atrac17**](https://github.com/atrac17). The intent is for this core to be a 1:1 playable implementation of SNK M68000 (Ikari III) arcade hardware. Currently in **beta state**, this core is in active development with assistance from [**atrac17**](https://github.com/atrac17).
MiST port, new SDRAM controller, some fixes and enhancements by Gyorgy Szombathelyi.
## Supported Games
| Title | PCB<br>Number | Status | Released | ROM Set |
|-------|---------------|---------|----------|----------|
| [**脱獄: Prisoners of War**](https://en.wikipedia.org/wiki/P.O.W.:_Prisoners_of_War)<br>P.O.W.: Prisoners of War | A7008 | Implemented | Yes | .245 merged |
| [**怒III**](https://en.wikipedia.org/wiki/Ikari_III:_The_Rescue)<br>Ikari III: The Rescue | A7007 | Implemented | W.I.P | .245 merged |
| [**Street Smart**](https://en.wikipedia.org/wiki/Street_Smart_(video_game)) | A7008 / A8007 | Implemented | Yes | .245 merged |
| [**SAR: Search and Rescue**](http://snk.fandom.com/wiki/SAR:_Search_and_Rescue) | A8007 | Implemented | Yes | .245 merged |
## External Modules
|Name| Purpose | Author |
|----|---------|--------|
| [**fx68k**](https://github.com/ijor/fx68k) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Jorge Cwik |
| [**t80**](https://opencores.org/projects/t80) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Daniel Wallner |
| [**jtopl2**](https://github.com/jotego/jtopl) | [**Yamaha OPL 2**](https://en.wikipedia.org/wiki/Yamaha_OPL#OPL2) | Jose Tejada |
| [**jt7759**](https://github.com/jotego/jt7759) | [**NEC uPD7759**](https://github.com/jotego/jt7759) | Jose Tejada |
# PCB Check List
<br>
FPGA implementation has been verified against [**schematics**](https://github.com/va7deo/SNK68/blob/main/doc/A7007%20(Ikari%20III)/Schematic/A7007%20Schematics.pdf) for Ikari III. PCB measurements taken from Datsugoku: Prisoners of War (A7008), Street Smart (A8007), and Ikari III: The Resucue (A7007).
### Clock Information
H-Sync | V-Sync | Source | PCB<br>Number |
------------|-------------|----------|----------------|
15.625kHz | 59.185606Hz | [**DSLogic+**](https://github.com/va7deo/SNK68/blob/main/doc/A7008%20(P.O.W.)/PCB%20Measurements/POW_CSYNC_50MHz.png) | A7008 (P.O.W.) |
15.625kHz | 59.185606Hz | TBD | A7007 (IK3) |
15.625kHz | 59.185606Hz | DSLogic+ | A8007 (SS) |
### Crystal Oscillators
Location | PCB<br>Number | Freq (MHz) | Use |
-----------------------|-----------------------------|------------|---------------------------|
X-4 (4MHZ) | A7008 (P.O.W.) / A8007 (SS) | 4.000 | Z80 / YM3812 / uPD7759 |
X-2 (18MHZ) | A7008 (P.O.W.) / A8007 (SS) | 18.000 | M68000 |
X-1 (24MHz) | A7008 (P.O.W.) / A8007 (SS) | 24.000 | Video / Pixel Clock |
<br>
Location | PCB<br>Number | Freq (MHz) | Use |
-----------------------|---------------------------|------------|---------------------------|
F-18 (4MHZ) | A7007 (IK3) / A8007 (SAR) | 4.000 | Z80 / YM3812 / uPD7759 |
H-17 (18MHZ) | A7007 (IK3) / A8007 (SAR) | 18.000 | M68000 |
E-9 (24MHz) | A7007 (IK3) / A8007 (SAR) | 24.000 | Video / Pixel Clock |
**Pixel clock:** 6.00 MHz
**Estimated geometry:**
383 pixels/line
263 pixels/line
### Main Components
Location | PCB<br>Number | Chip | Use |
---------|---------------|------|-----|
68000 | A7008 (P.O.W.) / A8007 (SS) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU |
Z-80A | A7008 (P.O.W.) / A8007 (SS) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU |
YM3812 | A7008 (P.O.W.) / A8007 (SS) | [**Yamaha YM3812**](https://en.wikipedia.org/wiki/Yamaha_OPL#OPL2) | OPL2 |
7759 | A7008 (P.O.W.) / A8007 (SS) | [**NEC uPD7759**](https://github.com/jotego/jt7759) | ADPCM Decoder |
Location | PCB<br>Number | Chip | Use |
---------|---------------|------|-----|
H-11/12 | A7007 (IK3) / A8007 (SAR) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU |
Z80 | A7007 (IK3) / A8007 (SAR) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU |
YM3812 | A7007 (IK3) / A8007 (SAR) | [**Yamaha YM3812**](https://en.wikipedia.org/wiki/Yamaha_OPL#OPL2) | OPL2 |
C-18 | A7007 (IK3) / A8007 (SAR) | [**NEC uPD7759**](https://github.com/jotego/jt7759) | ADPCM Decoder |
### Custom Components
Location | PCB<br>Number | Chip | Use |
---------|---------------|------|-----|
SNKCLK | A7007 (IK3) / A8007 (SAR) | [**SNK CLK**](https://github.com/va7deo/SNK68/blob/main/doc/Custom%20Components/SNK_CLK.jpg) | Counter |
SNKI/O | A7007 (IK3) / A8007 (SAR) | [**SNK I/O**](https://github.com/va7deo/SNK68/blob/main/doc/Custom%20Components/SNK_IO.jpg) | Rotary |
# Support
Please consider showing support for this and future projects via [**Darren's Ko-fi**](https://ko-fi.com/darreno) and [**atrac17's Patreon**](https://www.patreon.com/atrac17). While it isn't necessary, it's greatly appreciated.
# Licensing
Contact the author for special licensing needs. Otherwise follow the GPLv2 license attached.

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
# Date created = 04:04:47 October 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "SNK68"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 05:08:48 November 15, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Arcade-Scramble_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY SNK68_MiST
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# ----------------------
# start ENTITY(SNK68)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(SNK68)
# --------------------
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/joy.stp
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name FORCE_SYNCH_CLEAR ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/SNK68_MiST.sv
set_global_assignment -name QIP_FILE rtl/pll_mist.qip
set_global_assignment -name VERILOG_FILE rtl/video_timing.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/SNK68.sv
set_global_assignment -name VHDL_FILE rtl/math.vhd
set_global_assignment -name VHDL_FILE rtl/dual_port_ram.vhd
set_global_assignment -name VERILOG_FILE rtl/chip_select.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/Sound/jtopl/jtopl2.qip
set_global_assignment -name QIP_FILE ../../../common/Sound/jt7759/jt7759.qip
set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
set_global_assignment -name SIGNALTAP_FILE output_files/z80.stp
set_global_assignment -name SIGNALTAP_FILE output_files/spr.stp
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SIGNALTAP_FILE output_files/joy.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

138
Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.sdc Normal file
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@@ -0,0 +1,138 @@
## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from {SNK68:SNK68|T80pa:z80|T80:u0|*} -setup 2
set_multicycle_path -from {SNK68:SNK68|T80pa:z80|T80:u0|*} -hold 1
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

88
Arcade_MiST/SNK M68000 Harware/SNK68/meta/Ikari III - The Rescue (World Version 1, 8-Way Joystick).mra Normal file
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@@ -0,0 +1,88 @@
<misterromdescription>
<name>Ikari III - The Rescue (World Version 1, 8-Way Joystick)</name>
<setname>ikari3</setname>
<rbf>SNK68</rbf>
<mameversion>0245</mameversion>
<year>1989</year>
<manufacturer>SNK</manufacturer>
<region>World</region>
<joystick>8-Way</joystick>
<switches default="00,00" base="16" page_id="1" page_name="Switches">
<!-- DSW1 -->
<dip name="Monitor Screen" bits="7" ids="Normal,Invert"/>
<dip name="Blood" bits="6" ids="Off,On"/>
<dip name="Second Bonus" bits="5" ids="20/50K,20/50k(E)"/>
<dip name="Unknown" bits="4" ids="Off,On"/>
<dip name="Play Pricing" bits="2,3" ids="1/1,3/1 - 1/3,2/1 - 1/2,4/1 - 1/4"/>
<dip name="Lives" bits="0,1" ids="3,4,2,5"/>
<!-- DSW2 -->
<dip name="Difficulty" bits="14,15" ids="Easy,Hard,Normal,Hardest"/>
<dip name="Game Mode" bits="12,13" ids="Demo Sound On,Never Finish,Demo Sound Off,Stop Video"/>
<dip name="Extend" bits="10,11" ids="20/50K,60/150K,40/100K,None"/>
<dip name="Continue" bits="9" ids="Yes,No"/>
<dip name="Test Mode" bits="8" ids="Normal Game,Manual Test"/>
</switches>
<buttons names="Kick/Knife/Weapon,Jump,Punch/Weapon,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="ikari3.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="ik3-2-ver1.c10" crc="1bae8023" map="01"/>
<part name="ik3-3-ver1.c9" crc="10e38b66" map="10"/>
</interleave>
<interleave output="16">
<part name="ik3-1.c8" crc="47e4d256" map="01"/>
<part name="ik3-4.c12" crc="a43af6b5" map="10"/>
</interleave>
<part repeat="0x20000"> FF</part>
<!-- soundcpu - starts at 0x80000 -->
<part name="ik3-5.16d" crc="ce6706fc"/>
<part repeat="0x10000"> FF</part>
<!-- upd - starts at 0xA0000 -->
<part name="ik3-6.18e" crc="59d256a4"/>
<!-- gfx1 - starts at 0xC0000 -->
<interleave output="16">
<part name="ik3-7.16l" crc="0b4804df" map="01"/>
<part name="ik3-8.16m" crc="10ab4e50" map="10"/>
</interleave>
<part repeat="0x30000"> FF</part>
<!-- gfx2 - starts at 0x100000 -->
<interleave output="32">
<part name="ik3-23.bin" crc="d0fd5c77" map="0001"/>
<part name="ik3-13.bin" crc="9a56bd32" map="0010"/>
<part name="ik3-14.bin" crc="453bea77" map="0100"/>
<part name="ik3-24.bin" crc="e9b26d68" map="1000"/>
</interleave>
<interleave output="32">
<part name="ik3-22.bin" crc="4878d883" map="0001"/>
<part name="ik3-12.bin" crc="0ce6a10a" map="0010"/>
<part name="ik3-15.bin" crc="781a81fc" map="0100"/>
<part name="ik3-25.bin" crc="073b03f1" map="1000"/>
</interleave>
<interleave output="32">
<part name="ik3-21.bin" crc="50d0fbf0" map="0001"/>
<part name="ik3-11.bin" crc="e4e2be43" map="0010"/>
<part name="ik3-16.bin" crc="80ba400b" map="0100"/>
<part name="ik3-26.bin" crc="9c613561" map="1000"/>
</interleave>
<interleave output="32">
<part name="ik3-20.bin" crc="9a851efc" map="0001"/>
<part name="ik3-10.bin" crc="ac222372" map="0010"/>
<part name="ik3-17.bin" crc="0cc3ce4a" map="0100"/>
<part name="ik3-27.bin" crc="16dd227e" map="1000"/>
</interleave>
<interleave output="32">
<part name="ik3-19.bin" crc="4ebdba89" map="0001"/>
<part name="ik3-9.bin" crc="c33971c2" map="0010"/>
<part name="ik3-18.bin" crc="ba106245" map="0100"/>
<part name="ik3-28.bin" crc="711715ae" map="1000"/>
</interleave>
<!-- Total 0x380000 bytes - 3584 kBytes -->
</rom>
</misterromdescription>

81
Arcade_MiST/SNK M68000 Harware/SNK68/meta/P.O.W. - Prisoners of War (US Version 1).mra Normal file
View File

@@ -0,0 +1,81 @@
<misterromdescription>
<name>P.O.W. - Prisoners of War (US Version 1)</name>
<setname>pow</setname>
<rbf>SNK68</rbf>
<mameversion>0245</mameversion>
<year>1988</year>
<manufacturer>SNK</manufacturer>
<region>US</region>
<switches default="00,00" base="16" page_id="1" page_name="Switches">
<!-- DSW1 -->
<dip name="Monitor Screen" bits="7" ids="Normal,Invert"/>
<dip name="Unknown" bits="6" ids="Off,On"/>
<dip name="Bonus Occurence" bits="5" ids="Second,Every"/>
<dip name="Hero Count" bits="4" ids="Two,Three"/>
<dip name="Play Pricing 1" bits="2,3" ids="1/1,3/1,2/1,4/1"/>
<dip name="Play Pricing 2" bits="0,1" ids="1/1,1/3,1/2,1/4"/>
<!-- DSW2 -->
<dip name="Difficulty" bits="14,15" ids="Standard,Hard,Easy,Hardest"/>
<dip name="Game Mode" bits="12,13" ids="Demo Sound On,Never Finish,Demo Sound Off,Stop Video"/>
<dip name="Extend" bits="10,11" ids="20/50K,60/150K,40/100K,None"/>
<dip name="Continue" bits="9" ids="Yes,No"/>
<dip name="Test Mode" bits="8" ids="Normal Game,Manual Test"/>
</switches>
<buttons names="Kick/Shoot Gun,Jump,Punch/Butt Stroke,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
<rom index="1">
<part>01</part>
</rom>
<rom index="0" zip="pow.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="dg1ver1.j14" crc="8e71a8af" map="01"/>
<part name="dg2ver1.l14" crc="4287affc" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- soundcpu - starts at 0x80000 -->
<part name="dg8.e25" crc="d1d61da3"/>
<part repeat="0x10000"> FF</part>
<!-- upd - starts at 0xA0000 -->
<part name="dg7.d20" crc="aba9a9d3"/>
<part repeat="0x10000"> FF</part>
<!-- gfx1 - starts at 0xC0000 -->
<interleave output="16">
<part name="dg9.l25" crc="df864a08" map="01"/>
<part name="dg10.m25" crc="9e470d53" map="10"/>
</interleave>
<part repeat="0x30000"> FF</part>
<!-- gfx2 - starts at 0x100000 -->
<interleave output="32">
<part name="snk88011a.1a" crc="e70fd906" map="0001"/>
<part name="snk88015a.2a" crc="7a90e957" map="0010"/>
<part name="snk88019a.3a" crc="1775b8dd" map="0100"/>
<part name="snk88023a.4a" crc="adb6ad68" map="1000"/>
</interleave>
<interleave output="32">
<part name="snk88012a.1b" crc="628b1aed" map="0001"/>
<part name="snk88016a.2b" crc="e40a6c13" map="0010"/>
<part name="snk88020a.3b" crc="f8e752ec" map="0100"/>
<part name="snk88024a.4b" crc="dd41865a" map="1000"/>
</interleave>
<interleave output="32">
<part name="snk88013a.1c" crc="19dc8868" map="0001"/>
<part name="snk88017a.2c" crc="c7931cc2" map="0010"/>
<part name="snk88021a.3c" crc="27e9fffe" map="0100"/>
<part name="snk88025a.4c" crc="055759ad" map="1000"/>
</interleave>
<interleave output="32">
<part name="snk88014a.1d" crc="47cd498b" map="0001"/>
<part name="snk88018a.2d" crc="eed72232" map="0010"/>
<part name="snk88022a.3d" crc="aa9c00d8" map="0100"/>
<part name="snk88026a.4d" crc="9bc261c5" map="1000"/>
</interleave>
<part repeat="0x80000"> FF</part>
<!-- plds - starts at 0x380000 -->
<part name="pal20l10.a6" crc="c3d9e729"/>
<!-- Total 0x3800CC bytes - 3584 kBytes -->
</rom>
</misterromdescription>

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<misterromdescription>
<name>SAR - Search And Rescue (World)</name>
<setname>searchar</setname>
<rbf>SNK68</rbf>
<mameversion>0245</mameversion>
<year>1989</year>
<manufacturer>SNK</manufacturer>
<region>World</region>
<switches default="01,00" base="16" page_id="1" page_name="Switches">
<!-- DSW1 -->
<dip name="Monitor Screen" bits="7" ids="Normal,Invert"/>
<dip name="Bonus Occurence" bits="6" ids="Second,Every"/>
<dip name="Play Pricing" bits="4,5" ids="1/1-1/2,3/1-1/5,2/1-1/3,4/1-1/6"/>
<dip name="Hero Count" bits="2,3" ids="3,4,2,5"/>
<dip name="Unknown" bits="1" ids="Off,On"/>
<dip name="Control Type" bits="0" ids="Rotary,8-Way"/>
<!-- DSW2 -->
<dip name="Difficulty" bits="14,15" ids="Normal,Hard,Easy,Hardest"/>
<dip name="Game Mode" bits="12,13" ids="Demo Sound On,Never Finish,Demo Sound Off,Stop Video"/>
<dip name="Extend" bits="10,11" ids="50/100K,90/180K,70/140K,None"/>
<dip name="Continue" bits="9" ids="Yes,No"/>
<dip name="Test Mode" bits="8" ids="Normal Game,Manual Test"/>
</switches>
<buttons names="Fire/Power Up,Jump,-,P1 Start,P2 Start,Coin A,Coin B,Pause,Rotate CW,Rotate CCW" default="A,B,X,Y,R,L,Start,Select,R1,L1"/>
<rom index="1">
<part>08</part>
</rom>
<rom index="0" zip="searchar.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="bhw.2" crc="e1430138" map="01"/>
<part name="bhw.3" crc="ee1f9374" map="10"/>
</interleave>
<interleave output="16">
<part name="bhw.1" crc="62b60066" map="01"/>
<part name="bhw.4" crc="16d8525c" map="10"/>
</interleave>
<!-- soundcpu - starts at 0x80000 -->
<part name="bh.5" crc="53e2fa76"/>
<part repeat="0x10000"> FF</part>
<!-- upd - starts at 0xA0000 -->
<part name="bh.v1" crc="07a6114b"/>
<!-- gfx1 - starts at 0xC0000 -->
<interleave output="16">
<part name="bh.7" crc="b0f1b049" map="01"/>
<part name="bh.8" crc="174ddba7" map="10"/>
</interleave>
<part repeat="0x30000"> FF</part>
<!-- gfx2 - starts at 0x100000 -->
<interleave output="32">
<part name="bh.c1" crc="1fb8f0ae" map="0021"/>
<part name="bh.c2" crc="7c803767" map="2100"/>
</interleave>
<interleave output="32">
<part name="bh.c3" crc="fd8bc407" map="0021"/>
<part name="bh.c4" crc="eede7c43" map="2100"/>
</interleave>
<interleave output="32">
<part name="bh.c5" crc="1d30acc3" map="0021"/>
<part name="bh.c6" crc="9f785cd9" map="2100"/>
</interleave>
<!-- Total 0x400000 bytes - 4096 kBytes -->
</rom>
</misterromdescription>

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<misterromdescription>
<name>Street Smart (US version 2)</name>
<setname>streetsm</setname>
<rbf>SNK68</rbf>
<mameversion>0245</mameversion>
<year>1989</year>
<manufacturer>SNK</manufacturer>
<region>World</region>
<switches default="00,00" base="16" page_id="1" page_name="Switches">
<!-- DSW1 -->
<dip name="Monitor Screen" bits="7" ids="Normal,Invert"/>
<dip name="Unknown" bits="6" ids="Off,On"/>
<dip name="Second Bonus" bits="5" ids="Every Extend,2nd Extend"/>
<dip name="Unknown" bits="4" ids="Off,On"/>
<dip name="Play Pricing" bits="2,3" ids="1/1,3/1 - 1/3,2/1 - 1/2,4/1 - 1/4"/>
<dip name="Lives" bits="0,1" ids="2,3,1,4"/>
<!-- DSW2 -->
<dip name="Difficulty" bits="14,15" ids="Normal,Hard,Easy,Hardest"/>
<dip name="Game Mode" bits="12,13" ids="Demo Sound On,Never Finish,Demo Sound Off,Stop Video"/>
<dip name="Extend" bits="10,11" ids="200/400K,600/800K,400/600K,None"/>
<dip name="Continue" bits="9" ids="Yes,No"/>
<dip name="Test Mode" bits="8" ids="Normal Game,Manual Test"/>
</switches>
<buttons names="Kick,Jump,Punch,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start"/>
<rom index="1">
<part>02</part>
</rom>
<rom index="0" zip="streetsm.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">
<part name="s2-1ver2.14h" crc="655f4773" map="01"/>
<part name="s2-2ver2.14k" crc="efae4823" map="10"/>
</interleave>
<part repeat="0x40000"> FF</part>
<!-- soundcpu - starts at 0x80000 -->
<part name="s2-5.16c" crc="ca4b171e"/>
<part repeat="0x10000"> FF</part>
<!-- upd - starts at 0xA0000 -->
<part name="s2-6.18d" crc="47db1605"/>
<!-- gfx1 - starts at 0xC0000 -->
<interleave output="16">
<part name="s2-9.25l" crc="09b6ac67" map="01"/>
<part name="s2-10.25m" crc="89e4ee6f" map="10"/>
</interleave>
<part repeat="0x30000"> FF</part>
<!-- gfx2 - starts at 0x100000 -->
<interleave output="32">
<part name="stsmart.900" crc="a8279a7e" map="0021"/>
<part name="stsmart.901" crc="c305af12" map="2100"/>
</interleave>
<interleave output="32">
<part name="stsmart.902" crc="2f021aa1" map="0021"/>
<part name="stsmart.903" crc="73c16d35" map="2100"/>
</interleave>
<interleave output="32">
<part name="stsmart.904" crc="167346f7" map="0021"/>
<part name="stsmart.905" crc="a5beb4e2" map="2100"/>
</interleave>
<!-- Total 0x400000 bytes - 4096 kBytes -->
</rom>
</misterromdescription>

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//============================================================================
// SNK M68000 HW top-level for MiST
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module SNK68_MiST
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
inout SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input SPI_SS4,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
//`define DEBUG
`include "build_id.v"
`define CORE_NAME "IKARI3"
wire [6:0] core_mod;
localparam CONF_STR = {
`CORE_NAME, ";;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Joystick Swap,Off,On;",
"O7,Pause,Off,On;",
"O8,Service,Off,On;",
"O1,Video Timing,54.1Hz (PCB),59.2Hz (MAME);",
`ifdef DEBUG
"OD,Flip,Off,On;",
`endif
"DIP;",
"T0,Reset;",
"V,v1.20.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
wire pause = status[7];
wire service = status[8];
wire vidmode = status[1];
reg [7:0] dsw1;
reg [7:0] dsw2;
reg [7:0] p1, p2;
reg [15:0] coin;
reg [1:0] orientation;
wire flipped;
wire key_test = m_fire1[3];
always @(*) begin
orientation[0] = core_mod[3]; // bit3 - tate
orientation[1] = ~flipped;
p1 = ~{ m_one_player, m_fire1[2:0], m_right1, m_left1, m_down1, m_up1 };
p2 = ~{ m_two_players, m_fire2[2:0], m_right2, m_left2, m_down2, m_up2 };
dsw1 = status[23:16];
dsw2 = status[31:24];
coin = ~{ { 2 { 2'b0, m_coin2, m_coin1, 2'b0, service, key_test } } };
end
wire rot1_cw = m_fire1[7] | m_right1B | m_up1B; // R
wire rot1_ccw = m_fire1[6] | m_left1B | m_down1B; // L
wire rot2_cw = m_fire2[7] | m_right2B | m_up2B; // R
wire rot2_ccw = m_fire2[6] | m_left2B | m_down2B; // L
wire [11:0] rotary1;
wire [11:0] rotary2;
rotary_ctrl rot1(clk_72, reset, rot1_cw, rot1_ccw, rotary1);
rotary_ctrl rot2(clk_72, reset, rot2_cw, rot2_ccw, rotary2);
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_72;
assign SDRAM_CKE = 1;
wire clk_72;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.c0(clk_72),
.locked(pll_locked)
);
// reset generation
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_72) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl;
end
// ARM connection
wire [63:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [31:0] joystick_0;
wire [31:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
user_io #(
.STRLEN($size(CONF_STR)>>3),
.ROM_DIRECT_UPLOAD(1))
user_io(
.clk_sys (clk_72 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io #(.ROM_DIRECT_UPLOAD(1)) data_io(
.clk_sys ( clk_72 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_SS4 ( SPI_SS4 ),
.SPI_DI ( SPI_DI ),
.SPI_DO ( SPI_DO ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
wire [15:0] laudio, raudio;
wire hs, vs;
wire blankn = ~(hb | vb);
wire hb, vb;
wire [4:0] r,b,g;
SNK68 SNK68
(
.pll_locked ( pll_locked ),
.clk_sys ( clk_72 ),
.reset ( reset ),
.pcb ( core_mod[2:0] ),
.pause_cpu ( pause ),
.refresh_sel ( vidmode ),
`ifdef DEBUG
.test_flip ( status[13] ),
`else
.test_flip ( 1'b0 ),
`endif
.flip ( flipped ),
.p1 ( p1 ),
.p2 ( p2 ),
.dsw1 ( dsw1 ),
.dsw2 ( dsw2 ),
.coin ( coin ),
.rotary1 ( rotary1 ),
.rotary2 ( rotary2 ),
.hbl ( hb ),
.vbl ( vb ),
.hsync ( hs ),
.vsync ( vs ),
.r ( r ),
.g ( g ),
.b ( b ),
.audio_l ( laudio ),
.audio_r ( raudio ),
.rom_download ( ioctl_downl && ioctl_index == 0),
.ioctl_addr ( ioctl_addr ),
.ioctl_wr ( ioctl_wr ),
.ioctl_dout ( ioctl_dout ),
.SDRAM_A ( SDRAM_A ),
.SDRAM_BA ( SDRAM_BA ),
.SDRAM_DQ ( SDRAM_DQ ),
.SDRAM_DQML ( SDRAM_DQML ),
.SDRAM_DQMH ( SDRAM_DQMH ),
.SDRAM_nCS ( SDRAM_nCS ),
.SDRAM_nCAS ( SDRAM_nCAS ),
.SDRAM_nRAS ( SDRAM_nRAS ),
.SDRAM_nWE ( SDRAM_nWE )
);
mist_video #(.COLOR_DEPTH(5),.SD_HCNT_WIDTH(10)) mist_video(
.clk_sys(clk_72),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : 5'd0),
.G(blankn ? g : 5'd0),
.B(blankn ? b : 5'd0),
.HSync(~hs),
.VSync(~vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.no_csync(no_csync),
.rotate({orientation[1],rotate}),
.ce_divider(3'd5), // pix clock = 72/6
.blend(blend),
.scandoubler_disable(scandoublerD),
.scanlines(scanlines),
.ypbpr(ypbpr)
);
dac #(16) dacl(
.clk_i(clk_72),
.res_n_i(1),
.dac_i({~laudio[15], laudio[14:0]}),
.dac_o(AUDIO_L)
);
dac #(16) dacr(
.clk_i(clk_72),
.res_n_i(1),
.dac_i({~raudio[15], raudio[14:0]}),
.dac_o(AUDIO_R)
);
// Common inputs
wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B;
wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
wire [11:0] m_fire1, m_fire2;
arcade_inputs inputs (
.clk ( clk_72 ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( joyswap ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ),
.player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} )
);
endmodule
module rotary_ctrl
(
input clk_sys,
input reset,
input cw,
input ccw,
output reg [11:0] rotary
);
reg cw_last, ccw_last;
always @ (posedge clk_sys) begin
if (reset) begin
rotary <= 12'h1;
end else begin
cw_last <= cw;
ccw_last <= ccw;
if (cw & ~cw_last)
rotary <= { rotary[0], rotary[11:1] };
if (ccw & ~ccw_last)
rotary <= { rotary[10:0], rotary[11] };
end
end
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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Arcade_MiST/SNK M68000 Harware/SNK68/rtl/chip_select.v Normal file
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//
module chip_select
(
input [3:0] pcb,
input [23:0] m68k_a,
input m68k_as_n,
input m68k_rw,
input m68k_uds_n,
input m68k_lds_n,
input [15:0] z80_addr,
input MREQ_n,
input IORQ_n,
input M1_n,
input RFSH_n,
// M68K selects
output reg m68k_rom_cs,
output reg m68k_rom_2_cs,
output reg m68k_ram_cs,
output reg m68k_spr_cs,
output reg m68k_pal_cs,
output reg m68k_fg_ram_cs,
output reg m68k_scr_flip_cs,
output reg input_p1_cs,
output reg input_p2_cs,
output reg input_dsw1_cs,
output reg input_dsw2_cs,
output reg input_coin_cs,
output reg m68k_rotary1_cs,
output reg m68k_rotary2_cs,
output reg m68k_rotary_lsb_cs,
output reg m_invert_ctrl_cs,
output reg m68k_latch_cs,
output reg z80_latch_read_cs,
// Z80 selects
output reg z80_rom_cs,
output reg z80_ram_cs,
output reg z80_latch_cs,
output reg z80_sound0_cs,
output reg z80_sound1_cs,
output reg z80_upd_cs,
output reg z80_upd_r_cs
);
`include "defs.v"
function m68k_cs;
input [23:0] start_address;
input [23:0] end_address;
begin
m68k_cs = ( m68k_a[23:0] >= start_address && m68k_a[23:0] <= end_address) & !m68k_as_n & !(m68k_uds_n & m68k_lds_n);
end
endfunction
function z80_mem_cs;
input [15:0] base_address;
input [7:0] width;
begin
z80_mem_cs = ( z80_addr >> width == base_address >> width ) & !MREQ_n && RFSH_n;
end
endfunction
function z80_io_cs;
input [7:0] address_lo;
begin
z80_io_cs = ( z80_addr[7:0] == address_lo ) && !IORQ_n && M1_n;
end
endfunction
always @ (*) begin
// Memory mapping based on PCB type
z80_rom_cs = !MREQ_n && RFSH_n && z80_addr[15:0] < 16'hf000;
z80_ram_cs = !MREQ_n && RFSH_n && z80_addr[15:0] >= 16'hf000 && z80_addr[15:0] < 16'hf800;
z80_latch_cs = !MREQ_n && RFSH_n && z80_addr[15:0] == 16'hf800;
case (pcb)
pcb_A7007_A8007: begin
m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff );
m68k_rom_2_cs = m68k_cs( 24'h300000, 24'h33ffff );
m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff );
// write only
m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw;
// read only
input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw;
input_p2_cs = m68k_cs( 24'h080002, 24'h080003 );
input_coin_cs = m68k_cs( 24'h080004, 24'h080005 );
m_invert_ctrl_cs = m68k_cs( 24'h080006, 24'h080007 );
m68k_scr_flip_cs = m68k_cs( 24'h0c0000, 24'h0c0001 );
m68k_rotary1_cs = m68k_cs( 24'h0c0000, 24'h0c0001 );
m68k_rotary2_cs = m68k_cs( 24'h0c8000, 24'h0c8001 );
m68k_rotary_lsb_cs = m68k_cs( 24'h0d0000, 24'h0d0001 );
input_dsw1_cs = m68k_cs( 24'h0f0000, 24'h0f0001 ) ;
input_dsw2_cs = m68k_cs( 24'h0f0008, 24'h0f0009 ) ;
z80_latch_read_cs = m68k_cs( 24'h0f8000, 24'h0f8001 ) ;
m68k_spr_cs = m68k_cs( 24'h100000, 24'h107fff ) ;
m68k_fg_ram_cs = m68k_cs( 24'h200000, 24'h200fff ) | m68k_cs( 24'h201000, 24'h201fff ) ;
m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ;
z80_sound0_cs = z80_io_cs(8'h00); // ym3812 address
z80_sound1_cs = z80_io_cs(8'h20); // ym3812 data
z80_upd_cs = z80_io_cs(8'h40); // 7759 write
z80_upd_r_cs = z80_io_cs(8'h80); // 7759 reset
end
pcb_A7008: begin
m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
m68k_rom_2_cs = 0;
m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff ) ;
// read only
input_p2_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
// write only
m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
// read only
input_coin_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & m68k_rw ;
m_invert_ctrl_cs = 0;
// write only
m68k_scr_flip_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & !m68k_rw;
input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) ;
m68k_rotary1_cs = 0;
m68k_rotary2_cs = 0;
m68k_rotary_lsb_cs = 0;
input_dsw1_cs = m68k_cs( 24'h0f0000, 24'h0f0001 ) ;
input_dsw2_cs = m68k_cs( 24'h0f0008, 24'h0f0009 ) ;
m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) | m68k_cs( 24'h101000, 24'h101fff );
m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ;
z80_latch_read_cs = 0;
z80_sound0_cs = z80_io_cs(8'h00); // ym3812 address
z80_sound1_cs = z80_io_cs(8'h20); // ym3812 data
z80_upd_cs = z80_io_cs(8'h40); // 7759 write
z80_upd_r_cs = z80_io_cs(8'h80); // 7759 reset
end
pcb_A7008_SS: begin
m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ;
m68k_rom_2_cs = 0;
m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff ) ;
// read only
input_p2_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ;
// write only
m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ;
// read only
input_coin_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & m68k_rw ;
m_invert_ctrl_cs = 0;
// write only
m68k_scr_flip_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & !m68k_rw;
input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) ;
input_dsw1_cs = m68k_cs( 24'h0f0000, 24'h0f0001 ) ;
input_dsw2_cs = m68k_cs( 24'h0f0008, 24'h0f0009 ) ;
m68k_rotary1_cs = 0;
m68k_rotary2_cs = 0;
m68k_rotary_lsb_cs = 0;
m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ;
m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) | m68k_cs( 24'h101000, 24'h101fff );
m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ;
z80_latch_read_cs = 0;
z80_sound0_cs = z80_io_cs(8'h00); // ym3812 address
z80_sound1_cs = z80_io_cs(8'h20); // ym3812 data
z80_upd_cs = z80_io_cs(8'h40); // 7759 write
z80_upd_r_cs = z80_io_cs(8'h80); // 7759 reset
end
default: begin
m68k_rom_cs = 0;
m68k_rom_2_cs = 0;
m68k_ram_cs = 0;
// write only
m68k_latch_cs = 0;
// read only
input_p1_cs = 0;
input_p2_cs = 0;
input_coin_cs = 0;
m_invert_ctrl_cs = 0;
m68k_scr_flip_cs = 0;
m68k_rotary1_cs = 0;
m68k_rotary2_cs = 0;
m68k_rotary_lsb_cs = 0;
input_dsw1_cs = 0;
input_dsw2_cs = 0;
z80_latch_read_cs = 0;
m68k_spr_cs = 0;
m68k_fg_ram_cs = 0;
m68k_pal_cs = 0;
z80_sound0_cs = 0;
z80_sound1_cs = 0;
z80_upd_cs = 0;
z80_upd_r_cs = 0;
end
endcase
end
endmodule

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localparam pcb_A7007_A8007 = 0; // [ikari3], [searchar], [streetsmj, streetsm1, streetsmw] - Ikari III, S.A.R., and Street Smart V1 (mame nomenclature, would be V2)
localparam pcb_A7008 = 1; // [pow] - P.O.W.
localparam pcb_A7008_SS = 2; // [streetsm] - Street Smart V2 (mame nomenclature, would be V1)

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Arcade_MiST/SNK M68000 Harware/SNK68/rtl/dual_port_ram.vhd Normal file
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-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- 2022-05-24 Changed to use word count instead of address width
-- and renamed ports to match quartus IP naming
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--use work.common.all;
use work.math.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity dual_port_ram is
generic (
LEN : natural := 8192;
DATA_WIDTH : natural := 8
);
port (
-- port A
clock_a : in std_logic;
address_a : in unsigned(ilog2(LEN)-1 downto 0);
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
wren_a : in std_logic := '0';
-- port B
clock_b : in std_logic;
address_b : in unsigned(ilog2(LEN)-1 downto 0);
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0);
wren_b : in std_logic := '0'
);
end dual_port_ram;
architecture arch of dual_port_ram is
begin
altsyncram_component : altsyncram
generic map (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => LEN,
numwords_b => LEN,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
width_a => DATA_WIDTH,
width_b => DATA_WIDTH,
width_byteena_a => 1,
width_byteena_b => 1,
widthad_a => ilog2(LEN),
widthad_b => ilog2(LEN),
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
address_a => std_logic_vector(address_a),
address_b => std_logic_vector(address_b),
clock0 => clock_a,
clock1 => clock_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => q_a,
q_b => q_b
);
end architecture arch;

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@@ -0,0 +1,72 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package math is
-- calculates the log2 of the given number
function ilog2(n : natural) return natural;
-- Masks the given range of bits for a vector.
--
-- Only the bits between the MSB and LSB (inclusive) will be kept, all other
-- bits will be masked out.
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector;
end package math;
package body math is
function ilog2(n : natural) return natural is
begin
return natural(ceil(log2(real(n))));
end ilog2;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector is
variable n : natural;
variable mask : std_logic_vector(data'length-1 downto 0);
begin
n := (2**(msb-lsb+1))-1;
mask := std_logic_vector(shift_left(to_unsigned(n, mask'length), lsb));
return std_logic_vector(shift_right(unsigned(data AND mask), lsb));
end mask_bits;
function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector is
begin
return std_logic_vector(resize(unsigned(mask_bits(data, msb, lsb)), size));
end mask_bits;
end package body math;

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Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]

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Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_mist.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_mist (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 3,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

449
Arcade_MiST/SNK M68000 Harware/SNK68/rtl/sdram.sv Normal file
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//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019-2022 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
// 1st bank
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
// cpu1 rom/ram
input [21:1] cpu1_rom_addr,
input cpu1_rom_cs,
output reg [15:0] cpu1_rom_q,
output reg cpu1_rom_valid,
input cpu1_ram_req,
output reg cpu1_ram_ack,
input [21:1] cpu1_ram_addr,
input cpu1_ram_we,
input [1:0] cpu1_ram_ds,
input [15:0] cpu1_ram_d,
output reg [15:0] cpu1_ram_q,
// cpu2 rom
input [21:1] cpu2_addr,
input cpu2_rom_cs,
output reg [15:0] cpu2_q,
output reg cpu2_valid,
// cpu3 rom
input [21:1] cpu3_addr,
input cpu3_rom_cs,
output reg [15:0] cpu3_q,
output reg cpu3_valid,
// cpu4 rom
input [21:1] cpu4_addr,
input cpu4_rom_cs,
output reg [15:0] cpu4_q,
output reg cpu4_valid,
// 2nd bank
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [31:0] port2_q,
input [21:2] gfx1_addr,
output reg [31:0] gfx1_q,
input [21:2] gfx2_addr,
output reg [31:0] gfx2_q,
input [21:2] gfx3_addr,
output reg [31:0] gfx3_q,
input [21:2] sp_addr,
input sp_req,
output reg sp_ack,
output reg [31:0] sp_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
2 words burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0
2 data1 returned
3 CAS0 data1 returned
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_DS1b = 3'd0;
localparam STATE_READ1b = 3'd4;
localparam STATE_LAST = 3'd6;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[3];
reg [24:1] addr_latch_next[2];
reg [21:1] addr_last[1:5];
reg [21:2] addr_last2[5];
reg [15:0] din_next;
reg [15:0] din_latch[2];
reg oe_next;
reg [1:0] oe_latch;
reg we_next;
reg [1:0] we_latch;
reg [1:0] ds_next;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
reg cpu1_ram_req_state;
reg sp_state;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1_ROM = 3'd1;
localparam PORT_CPU1_RAM = 3'd2;
localparam PORT_CPU2 = 3'd3;
localparam PORT_CPU3 = 3'd4;
localparam PORT_CPU4 = 3'd5;
localparam PORT_GFX1 = 3'd1;
localparam PORT_GFX2 = 3'd2;
localparam PORT_GFX3 = 3'd3;
localparam PORT_SP = 3'd4;
localparam PORT_REQ = 3'd6;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
ds_next = 2'b00;
{ oe_next, we_next } = 2'b00;
din_next = 0;
if (refresh) begin
// nothing
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
ds_next = port1_ds;
{ oe_next, we_next } = { ~port1_we, port1_we };
din_next = port1_d;
end else if (/*cpu1_rom_addr != addr_last[PORT_CPU1_ROM] &&*/ cpu1_rom_cs && !cpu1_rom_valid) begin
next_port[0] = PORT_CPU1_ROM;
addr_latch_next[0] = { 3'd0, cpu1_rom_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end else if (cpu1_ram_req ^ cpu1_ram_req_state) begin
next_port[0] = PORT_CPU1_RAM;
addr_latch_next[0] = { 2'b01, 1'b1, cpu1_ram_addr };
ds_next = cpu1_ram_ds;
{ oe_next, we_next } = { ~cpu1_ram_we, cpu1_ram_we };
din_next = cpu1_ram_d;
end else if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 3'd0, cpu2_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end else if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) begin
next_port[0] = PORT_CPU3;
addr_latch_next[0] = { 3'd0, cpu3_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end else if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) begin
next_port[0] = PORT_CPU4;
addr_latch_next[0] = { 3'd0, cpu4_addr };
ds_next = 2'b11;
{ oe_next, we_next } = 2'b10;
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (gfx1_addr != addr_last2[PORT_GFX1]) begin
next_port[1] = PORT_GFX1;
addr_latch_next[1] = { 1'b1, 2'd0, gfx1_addr, 1'b0 };
end else if (gfx2_addr != addr_last2[PORT_GFX2]) begin
next_port[1] = PORT_GFX2;
addr_latch_next[1] = { 1'b1, 2'd0, gfx2_addr, 1'b0 };
end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin
next_port[1] = PORT_GFX3;
addr_latch_next[1] = { 1'b1, 2'd0, gfx3_addr, 1'b0 };
end else if (sp_req ^ sp_state) begin
next_port[1] = PORT_SP;
addr_latch_next[1] = { 1'b1, 2'd0, sp_addr, 1'b0 };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
{ cpu1_rom_valid, cpu2_valid, cpu3_valid, cpu4_valid } <= 0;
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
if (!cpu1_rom_cs) cpu1_rom_valid <= 0;
if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) cpu2_valid <= 0;
if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) cpu3_valid <= 0;
if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) cpu4_valid <= 0;
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
end
addr_last[next_port[0]] <= addr_latch_next[0][21:1];
ds[0] <= ds_next;
{ oe_latch[0], we_latch[0] } <= { oe_next, we_next };
din_latch[0] <= din_next;
if (next_port[0] == PORT_REQ) port1_state <= port1_req;
if (next_port[0] == PORT_CPU1_RAM) cpu1_ram_req_state <= cpu1_ram_req;
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][21:2];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_SP) sp_state <= sp_req;
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
case(port[0])
PORT_REQ: port1_ack <= port1_req;
PORT_CPU1_RAM: cpu1_ram_ack <= cpu1_ram_req;
default: ;
endcase;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1_ROM: begin cpu1_rom_q <= sd_din; cpu1_rom_valid <= 1; end
PORT_CPU1_RAM: begin cpu1_ram_q <= sd_din; cpu1_ram_ack <= cpu1_ram_req; end
PORT_CPU2: begin cpu2_q <= sd_din; cpu2_valid <= 1; end
PORT_CPU3: begin cpu3_q <= sd_din; cpu3_valid <= 1; end
PORT_CPU4: begin cpu4_q <= sd_din; cpu4_valid <= 1; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ : port2_q[15:0] <= sd_din;
PORT_GFX1 : gfx1_q[15:0] <= sd_din;
PORT_GFX2 : gfx2_q[15:0] <= sd_din;
PORT_GFX3 : gfx3_q[15:0] <= sd_din;
PORT_SP : sp_q[15:0] <= sd_din;
default: ;
endcase;
end
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if(t == STATE_READ1b && oe_latch[1]) begin
case(port[1])
PORT_REQ : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
PORT_GFX1 : begin gfx1_q[31:16] <= sd_din; end
PORT_GFX2 : begin gfx2_q[31:16] <= sd_din; end
PORT_GFX3 : begin gfx3_q[31:16] <= sd_din; end
PORT_SP : begin sp_q[31:16] <= sd_din; sp_ack <= sp_req; end
default: ;
endcase;
end
end
end
endmodule

99
Arcade_MiST/SNK M68000 Harware/SNK68/rtl/video_timing.v Normal file
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module video_timing
(
input clk,
input clk_pix,
input reset,
input refresh_mod,
input signed [3:0] hs_offset,
input signed [3:0] vs_offset,
input signed [3:0] hs_width,
input signed [3:0] vs_width,
output [8:0] hc,
output [8:0] vc,
output reg hsync,
output reg vsync,
output reg hbl,
output reg vbl
);
wire [8:0] h_ofs = 0;
wire [8:0] HBL_START = 266;
wire [8:0] HBL_END = 10;
wire [8:0] HS_START = HBL_START + 16 + $signed(hs_offset);
wire [8:0] HS_END = HBL_START + 48 + $signed(hs_offset) + $signed(hs_width);
wire [8:0] HTOTAL = 383;
wire [8:0] v_ofs = 0;
wire [8:0] VBL_START = 240;
wire [8:0] VBL_END = 16;
wire [8:0] VS_START = VBL_START + ( refresh_mod ? 20 : 10 ) + $signed(vs_offset);
wire [8:0] VS_END = VBL_START + ( refresh_mod ? 24 : 13 )+ $signed(vs_offset) + $signed(vs_width);
wire [8:0] VTOTAL = 288 - ( refresh_mod ? 0 : 25 );
reg [8:0] v;
reg [8:0] h;
assign vc = v - v_ofs;
assign hc = h - h_ofs;
always @ (posedge clk) begin
if (reset) begin
h <= 0;
v <= 0;
hbl <= 0;
vbl <= 0;
hsync <= 0;
vsync <= 0;
end else if ( clk_pix == 1 ) begin
// counter
if (h == HTOTAL) begin
h <= 0;
v <= v + 1'd1;
if ( v == VTOTAL ) begin
v <= 0;
end
end else begin
h <= h + 1'd1;
end
// h signals
if ( h == HBL_START ) begin
hbl <= 1;
end else if ( h == HBL_END ) begin
hbl <= 0;
end
// v signals
if ( v == VBL_START ) begin
vbl <= 1;
end else if ( v == VBL_END ) begin
vbl <= 0;
end
if ( v == (VS_START ) ) begin
vsync <= 1;
end else if ( v == (VS_END ) ) begin
vsync <= 0;
end
if ( h == (HS_START ) ) begin
hsync <= 1;
end else if ( h == (HS_END ) ) begin
hsync <= 0;
end
end
end
endmodule

674
common/Sound/jt7759/LICENSE Normal file
View File

@@ -0,0 +1,674 @@
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This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<https://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<https://www.gnu.org/licenses/why-not-lgpl.html>.

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# JT7759
Verilog module compatible with NEC ADPCM decoder uPD7759
You can show your appreciation through
* [Patreon](https://patreon.com/topapate), by supporting releases
* [Paypal](https://paypal.me/topapate), with a donation
JT775x is an ADPCM sound source written in Verilog, fully compatible with NEC uPD7759.
## Architecture
NEC family of fixed phase playback devices. All use the ADPCM and PCM+waveform element method for synthesis at 5,6 or 8kHz of sampling frequency. The only one using an external memory was uPD7759. Although they all share the same architecture, only uPD7759 seems to be of interest to the classic computing community.
Device | ROM type | ROM size
-------|----------|-----------
7755 | mask | 96 kbit
7756A | mask | 256 kbit
7757 | mask | 516 kbit
7758 | mask | 1024 kbit
7756 | PROM | 256 kbit
7759 | external | 1024 kbit
### Control State Machine
## Port Description
Name | Direction | Width | Purpose
---------|-----------|-------|--------------------------------------
rst | input | | active-high asynchronous reset signal
clk | input | | clock - use the same as the sound CPU
cen | input | | clock enable
din | input | 8 | input data from CPU
dout | output | 8 | output data to CPU
mdn | input | | Mode selection
stn | input | | Start. Used only if mdn is low.
drq | output | | Data request
rom_addr | output | 18 | Memory address to be read
rom_data | input | 8 | Data read
rom_ok | input | 1 | high when rom_data is valid and matches rom_addr
sound | output | 14 | signed sound output
## Usage
uDP7759 ROMs have the following header:
Byte | Usage
------|------------------
0 | Number of samples
1 | Must be 0x5A
2 | Must be 0xA5
3 | Must be 0x69
4 | Must be 0x55
If used in slave mode, tie rom_ok low.
After each reset the number of samples and the signature are read. If the signature is not correct, no samples will be played. If the verilog macro **SIMULATION** is defined, the simulation will stop if the signature is wrong.
If the simulator used supports X values, you need to define the macro **SIMULATION** to avoid X's in the divider module.
If the macro **JT7759_FIFO_DUMP** is defined, each byte read will be displayed during simulation.
### Implemented Features
Feature | Status
------------|------------------
Slave Mode | Implemented
Master Mode | Partially implemented
Features of master mode:
Feature | Status
-------------------|------------------
Signature | Implemented
Silence | Implemented
Play short | Implemented
Play long | Implemented
Address latch port | Not implemented
Repeat silence | Not implemented
Silence length is taken as a reasonable approximation to the 1ms quoted in MAME, which is also a reasonable approximation of the MAME author. In hardware the ~ 1ms is obtained as a 128 count at 640Hz/4, which makes sense from the point of view of implementation (rather than an exact 1ms).
### ROM interface
Port | Direction | Meaning
---------|-----------|----------------------------
rom_cs | output | high when address is valid
rom_addr | output | Addres to be read
rom_data | input | Data read from address
rom_ok | input | Data read is valid
Note that rom_ok is not valid for the clock cycle immediately after rising rom_cs. Or if rom_addr is changed while rom_cs is high. rom_addr must be stable once rom_cs goes high until rom_ok is asserted.
Although this module is designed for usage in systems fully implemented inside an FPGA, it is possible to adapt it to work as a replacement for the original chip. In such a case, the ROM interface would need be changed in order to implement the original signal scheme.
## FPGA arcade cores using this module:
* [Combat School](https://github.com/jotego/jtcontra), by the same author
* [System16](https://github.com/jotego/jts16), by the same author
## Related Projects
Other sound chips from the same author
Chip | Repository
-----------------------|------------
YM2203, YM2612, YM2610 | [JT12](https://github.com/jotego/jt12)
YM2151 | [JT51](https://github.com/jotego/jt51)
YM3526 | [JTOPL](https://github.com/jotego/jtopl)
YM2149 | [JT49](https://github.com/jotego/jt49)
sn76489an | [JT89](https://github.com/jotego/jt89)
OKI 6295 | [JT6295](https://github.com/jotego/jt6295)
OKI MSM5205 | [JT5205](https://github.com/jotego/jt5205)
NEC uPN7759 | [JT7759](https://github.com/jotego/jt7759)
WE DSP16 (QSound) | [JT7759](https://github.com/jotego/jtdsp16)

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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt7759.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt7759_adpcm.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt7759_ctrl.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt7759_div.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt7759_data.v ]

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/* This file is part of JT7759.
JT7759 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT7759 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT7759. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 5-7-2020 */
module jt7759(
input rst,
input clk, // Use same clock as sound CPU
input cen, // 640kHz
input stn, // STart (active low)
input cs,
input mdn, // MODE: 1 for stand alone mode, 0 for slave mode
// see chart in page 13 of PDF
output busyn,
// CPU interface
input wrn, // for slave mode only, 31.7us after drqn is set
input [ 7:0] din,
output drqn, // data request. 50-70us delay after mdn goes low
// ROM interface
output rom_cs, // equivalent to DRQn in original chip
output [16:0] rom_addr,
input [ 7:0] rom_data,
input rom_ok,
// Sound output
output signed [ 8:0] sound
`ifdef DEBUG
,output [3:0] debug_nibble
,output debug_cen_dec
,output debug_dec_rst
`endif
);
wire [ 5:0] divby;
wire cen_dec; // internal clock enable for sound
wire cen_ctl; // cen_dec x4
wire dec_rst;
wire [ 3:0] encoded;
wire ctrl_cs, ctrl_ok, ctrl_flush;
wire [16:0] ctrl_addr;
wire [ 7:0] ctrl_din;
`ifdef DEBUG
assign debug_nibble = encoded;
assign debug_cen_dec = cen_dec;
assign debug_dec_rst = dec_rst;
`endif
jt7759_div u_div(
.clk ( clk ),
.cen ( cen ),
.cen_ctl ( cen_ctl ),
.divby ( divby ),
.cen_dec ( cen_dec )
);
jt7759_ctrl u_ctrl(
.rst ( rst ),
.clk ( clk ),
.cen_ctl ( cen_ctl ),
.cen_dec ( cen_dec ),
.divby ( divby ),
// chip interface
.stn ( stn ),
.cs ( cs ),
.mdn ( mdn ),
.drqn ( drqn ),
.busyn ( busyn ),
.wrn ( wrn ),
.din ( din ),
// ADPCM engine
.dec_rst ( dec_rst ),
.dec_din ( encoded ),
// ROM interface
.rom_cs ( ctrl_cs ),
.rom_addr ( ctrl_addr ),
.rom_data ( ctrl_din ),
.rom_ok ( ctrl_ok ),
.flush ( ctrl_flush)
);
jt7759_data u_data(
.rst ( rst ),
.clk ( clk ),
.cen_ctl ( cen_ctl ),
.cen_dec ( cen_dec ),
.mdn ( mdn ),
// Control interface
.ctrl_flush ( ctrl_flush),
.ctrl_cs ( ctrl_cs ),
.ctrl_addr ( ctrl_addr ),
.ctrl_din ( ctrl_din ),
.ctrl_ok ( ctrl_ok ),
.ctrl_busyn ( busyn ),
// ROM interface
.rom_cs ( rom_cs ),
.rom_addr ( rom_addr ),
.rom_data ( rom_data ),
.rom_ok ( rom_ok ),
// Passive interface
.cs ( cs ),
.wrn ( wrn ),
.din ( din ),
.drqn ( drqn )
);
jt7759_adpcm u_adpcm(
.rst ( dec_rst ),
.clk ( clk ),
.cen_dec ( cen_dec ),
.encoded ( encoded ),
.sound ( sound )
);
`ifdef SIMULATION
integer fsnd;
initial begin
fsnd=$fopen("jt7759.raw","wb");
end
wire signed [15:0] snd_log = { sound, 7'b0 };
always @(posedge cen_dec) begin
$fwrite(fsnd,"%u", {snd_log, snd_log});
end
`endif
endmodule

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/* This file is part of JT7759.
JT7759 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public Licen4se as published by
the Free Software Foundation, either version 3 of the Licen4se, or
(at your option) any later version.
JT7759 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public Licen4se for more details.
You should have received a copy of the GNU General Public Licen4se
along with JT7759. If not, see <http://www.gnu.org/licen4ses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 5-7-2020 */
module jt7759_adpcm #(parameter SW=9) (
input rst,
input clk,
input cen_dec,
input [ 3:0] encoded,
output reg signed [SW-1:0] sound
);
// The look-up table could have been compressed. One obvious way is to realize that one
// half of it is just the negative version of the other.
// However, because it will be synthesized as a 1 kilo word memory of 9-bit words, i.e. 1BRAM
// this is the best choice.
// This is generated by the file doc/lut.c
reg signed [8:0] lut[0:255];
reg signed [3:0] st_lut[0:7];
reg [3:0] st;
reg [3:0] st_delta;
reg signed [5:0] st_next, st_sum;
reg signed [SW:0] next_snd, lut_step;
function [SW:0] sign_ext;
input signed [8:0] din;
sign_ext = { {SW-8{din[8]}}, din };
endfunction
always @(*) begin
st_delta = st_lut[ encoded[2:0] ];
st_sum = {2'b0, st } + {{2{st_delta[3]}}, st_delta };
if( st_sum[5] )
st_next = 6'd0;
else if( st_sum[4] )
st_next = 6'd15;
else
st_next = st_sum;
lut_step = sign_ext( lut[{st,encoded}] );
next_snd = { sound[SW-1], sound } + lut_step;
end
always @(posedge clk, posedge rst ) begin
if( rst ) begin
sound <= {SW{1'd0}};
st <= 4'd0;
end else if(cen_dec) begin
if( next_snd[SW]==next_snd[SW-1] )
sound <= next_snd[SW-1:0];
else sound <= next_snd[SW] ? {1'b1,{SW-1{1'b0}}} : {1'b0,{SW-1{1'b1}}};
st <= st_next[3:0];
end
end
initial begin
st_lut[0]=-4'd1; st_lut[1]=-4'd1; st_lut[2]=4'd0; st_lut[3]=4'd0;
st_lut[4]=4'd1; st_lut[5]=4'd2; st_lut[6]=4'd2; st_lut[7]=4'd3;
end
initial begin
lut[8'h00]=9'd0000; lut[8'h01]=9'd0000; lut[8'h02]=9'd0001; lut[8'h03]=9'd0002;
lut[8'h04]=9'd0003; lut[8'h05]=9'd0005; lut[8'h06]=9'd0007; lut[8'h07]=9'd0010;
lut[8'h08]=9'd0000; lut[8'h09]=9'd0000; lut[8'h0A]=-9'd001; lut[8'h0B]=-9'd002;
lut[8'h0C]=-9'd003; lut[8'h0D]=-9'd005; lut[8'h0E]=-9'd007; lut[8'h0F]=-9'd010;
lut[8'h10]=9'd0000; lut[8'h11]=9'd0001; lut[8'h12]=9'd0002; lut[8'h13]=9'd0003;
lut[8'h14]=9'd0004; lut[8'h15]=9'd0006; lut[8'h16]=9'd0008; lut[8'h17]=9'd0013;
lut[8'h18]=9'd0000; lut[8'h19]=-9'd001; lut[8'h1A]=-9'd002; lut[8'h1B]=-9'd003;
lut[8'h1C]=-9'd004; lut[8'h1D]=-9'd006; lut[8'h1E]=-9'd008; lut[8'h1F]=-9'd013;
lut[8'h20]=9'd0000; lut[8'h21]=9'd0001; lut[8'h22]=9'd0002; lut[8'h23]=9'd0004;
lut[8'h24]=9'd0005; lut[8'h25]=9'd0007; lut[8'h26]=9'd0010; lut[8'h27]=9'd0015;
lut[8'h28]=9'd0000; lut[8'h29]=-9'd001; lut[8'h2A]=-9'd002; lut[8'h2B]=-9'd004;
lut[8'h2C]=-9'd005; lut[8'h2D]=-9'd007; lut[8'h2E]=-9'd010; lut[8'h2F]=-9'd015;
lut[8'h30]=9'd0000; lut[8'h31]=9'd0001; lut[8'h32]=9'd0003; lut[8'h33]=9'd0004;
lut[8'h34]=9'd0006; lut[8'h35]=9'd0009; lut[8'h36]=9'd0013; lut[8'h37]=9'd0019;
lut[8'h38]=9'd0000; lut[8'h39]=-9'd001; lut[8'h3A]=-9'd003; lut[8'h3B]=-9'd004;
lut[8'h3C]=-9'd006; lut[8'h3D]=-9'd009; lut[8'h3E]=-9'd013; lut[8'h3F]=-9'd019;
lut[8'h40]=9'd0000; lut[8'h41]=9'd0002; lut[8'h42]=9'd0003; lut[8'h43]=9'd0005;
lut[8'h44]=9'd0008; lut[8'h45]=9'd0011; lut[8'h46]=9'd0015; lut[8'h47]=9'd0023;
lut[8'h48]=9'd0000; lut[8'h49]=-9'd002; lut[8'h4A]=-9'd003; lut[8'h4B]=-9'd005;
lut[8'h4C]=-9'd008; lut[8'h4D]=-9'd011; lut[8'h4E]=-9'd015; lut[8'h4F]=-9'd023;
lut[8'h50]=9'd0000; lut[8'h51]=9'd0002; lut[8'h52]=9'd0004; lut[8'h53]=9'd0007;
lut[8'h54]=9'd0010; lut[8'h55]=9'd0014; lut[8'h56]=9'd0019; lut[8'h57]=9'd0029;
lut[8'h58]=9'd0000; lut[8'h59]=-9'd002; lut[8'h5A]=-9'd004; lut[8'h5B]=-9'd007;
lut[8'h5C]=-9'd010; lut[8'h5D]=-9'd014; lut[8'h5E]=-9'd019; lut[8'h5F]=-9'd029;
lut[8'h60]=9'd0000; lut[8'h61]=9'd0003; lut[8'h62]=9'd0005; lut[8'h63]=9'd0008;
lut[8'h64]=9'd0012; lut[8'h65]=9'd0016; lut[8'h66]=9'd0022; lut[8'h67]=9'd0033;
lut[8'h68]=9'd0000; lut[8'h69]=-9'd003; lut[8'h6A]=-9'd005; lut[8'h6B]=-9'd008;
lut[8'h6C]=-9'd012; lut[8'h6D]=-9'd016; lut[8'h6E]=-9'd022; lut[8'h6F]=-9'd033;
lut[8'h70]=9'd0001; lut[8'h71]=9'd0004; lut[8'h72]=9'd0007; lut[8'h73]=9'd0010;
lut[8'h74]=9'd0015; lut[8'h75]=9'd0020; lut[8'h76]=9'd0029; lut[8'h77]=9'd0043;
lut[8'h78]=-9'd001; lut[8'h79]=-9'd004; lut[8'h7A]=-9'd007; lut[8'h7B]=-9'd010;
lut[8'h7C]=-9'd015; lut[8'h7D]=-9'd020; lut[8'h7E]=-9'd029; lut[8'h7F]=-9'd043;
lut[8'h80]=9'd0001; lut[8'h81]=9'd0004; lut[8'h82]=9'd0008; lut[8'h83]=9'd0013;
lut[8'h84]=9'd0018; lut[8'h85]=9'd0025; lut[8'h86]=9'd0035; lut[8'h87]=9'd0053;
lut[8'h88]=-9'd001; lut[8'h89]=-9'd004; lut[8'h8A]=-9'd008; lut[8'h8B]=-9'd013;
lut[8'h8C]=-9'd018; lut[8'h8D]=-9'd025; lut[8'h8E]=-9'd035; lut[8'h8F]=-9'd053;
lut[8'h90]=9'd0001; lut[8'h91]=9'd0006; lut[8'h92]=9'd0010; lut[8'h93]=9'd0016;
lut[8'h94]=9'd0022; lut[8'h95]=9'd0031; lut[8'h96]=9'd0043; lut[8'h97]=9'd0064;
lut[8'h98]=-9'd001; lut[8'h99]=-9'd006; lut[8'h9A]=-9'd010; lut[8'h9B]=-9'd016;
lut[8'h9C]=-9'd022; lut[8'h9D]=-9'd031; lut[8'h9E]=-9'd043; lut[8'h9F]=-9'd064;
lut[8'hA0]=9'd0002; lut[8'hA1]=9'd0007; lut[8'hA2]=9'd0012; lut[8'hA3]=9'd0019;
lut[8'hA4]=9'd0027; lut[8'hA5]=9'd0037; lut[8'hA6]=9'd0051; lut[8'hA7]=9'd0076;
lut[8'hA8]=-9'd002; lut[8'hA9]=-9'd007; lut[8'hAA]=-9'd012; lut[8'hAB]=-9'd019;
lut[8'hAC]=-9'd027; lut[8'hAD]=-9'd037; lut[8'hAE]=-9'd051; lut[8'hAF]=-9'd076;
lut[8'hB0]=9'd0002; lut[8'hB1]=9'd0009; lut[8'hB2]=9'd0016; lut[8'hB3]=9'd0024;
lut[8'hB4]=9'd0034; lut[8'hB5]=9'd0046; lut[8'hB6]=9'd0064; lut[8'hB7]=9'd0096;
lut[8'hB8]=-9'd002; lut[8'hB9]=-9'd009; lut[8'hBA]=-9'd016; lut[8'hBB]=-9'd024;
lut[8'hBC]=-9'd034; lut[8'hBD]=-9'd046; lut[8'hBE]=-9'd064; lut[8'hBF]=-9'd096;
lut[8'hC0]=9'd0003; lut[8'hC1]=9'd0011; lut[8'hC2]=9'd0019; lut[8'hC3]=9'd0029;
lut[8'hC4]=9'd0041; lut[8'hC5]=9'd0057; lut[8'hC6]=9'd0079; lut[8'hC7]=9'd0117;
lut[8'hC8]=-9'd003; lut[8'hC9]=-9'd011; lut[8'hCA]=-9'd019; lut[8'hCB]=-9'd029;
lut[8'hCC]=-9'd041; lut[8'hCD]=-9'd057; lut[8'hCE]=-9'd079; lut[8'hCF]=-9'd117;
lut[8'hD0]=9'd0004; lut[8'hD1]=9'd0013; lut[8'hD2]=9'd0024; lut[8'hD3]=9'd0036;
lut[8'hD4]=9'd0050; lut[8'hD5]=9'd0069; lut[8'hD6]=9'd0096; lut[8'hD7]=9'd0143;
lut[8'hD8]=-9'd004; lut[8'hD9]=-9'd013; lut[8'hDA]=-9'd024; lut[8'hDB]=-9'd036;
lut[8'hDC]=-9'd050; lut[8'hDD]=-9'd069; lut[8'hDE]=-9'd096; lut[8'hDF]=-9'd143;
lut[8'hE0]=9'd0004; lut[8'hE1]=9'd0016; lut[8'hE2]=9'd0029; lut[8'hE3]=9'd0044;
lut[8'hE4]=9'd0062; lut[8'hE5]=9'd0085; lut[8'hE6]=9'd0118; lut[8'hE7]=9'd0175;
lut[8'hE8]=-9'd004; lut[8'hE9]=-9'd016; lut[8'hEA]=-9'd029; lut[8'hEB]=-9'd044;
lut[8'hEC]=-9'd062; lut[8'hED]=-9'd085; lut[8'hEE]=-9'd118; lut[8'hEF]=-9'd175;
lut[8'hF0]=9'd0006; lut[8'hF1]=9'd0020; lut[8'hF2]=9'd0036; lut[8'hF3]=9'd0054;
lut[8'hF4]=9'd0076; lut[8'hF5]=9'd0104; lut[8'hF6]=9'd0144; lut[8'hF7]=9'd0214;
lut[8'hF8]=-9'd006; lut[8'hF9]=-9'd020; lut[8'hFA]=-9'd036; lut[8'hFB]=-9'd054;
lut[8'hFC]=-9'd076; lut[8'hFD]=-9'd104; lut[8'hFE]=-9'd144; lut[8'hFF]=-9'd214;
end
endmodule

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/* This file is part of JT7759.
JT7759 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public Licen_ctlse as published by
the Free Software Foundation, either version 3 of the Licen_ctlse, or
(at your option) any later version.
JT7759 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public Licen_ctlse for more details.
You should have received a copy of the GNU General Public Licen_ctlse
along with JT7759. If not, see <http://www.gnu.org/licen_ctlses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 5-7-2020 */
module jt7759_ctrl(
input rst,
input clk,
input cen_ctl,
input cen_dec,
output reg [ 5:0] divby,
input stn, // STart (active low)
input cs,
input mdn, // MODE: 1 for stand alone mode, 0 for slave mode
input drqn,
output busyn,
// CPU interface
input wrn, // for slave mode only
input [ 7:0] din,
// ADPCM engine
output reg dec_rst,
output reg [ 3:0] dec_din,
// ROM interface
output rom_cs, // equivalent to DRQn in original chip
output reg [16:0] rom_addr,
input [ 7:0] rom_data,
input rom_ok,
output reg flush
);
localparam STW = 11;
localparam [STW-1:0] RST =1<<0; // 1
localparam [STW-1:0] IDLE =1<<1; // 2
localparam [STW-1:0] SND_CNT=1<<2; // 4
localparam [STW-1:0] PLAY =1<<3; // 8
localparam [STW-1:0] WAIT =1<<4; // 10
localparam [STW-1:0] GETN =1<<5; // 20
localparam [STW-1:0] MUTED =1<<6; // 40
localparam [STW-1:0] LOAD =1<<7; // 80
localparam [STW-1:0] READCMD=1<<8; // 100
localparam [STW-1:0] READADR=1<<9; // 200
localparam [STW-1:0] SIGN =1<<10; // 400
localparam MTW = 13; // Mute counter 7+6 bits
reg [ 7:0] max_snd; // sound count: total number of sound samples
reg [STW-1:0] st;
reg [ 3:0] next;
reg [MTW-1:0] mute_cnt;
reg [ 8:0] data_cnt;
reg [ 3:0] rep_cnt;
reg [ 15:0] addr_latch;
reg [ 16:0] rep_latch;
reg [ 7:0] sign[0:3];
reg last_wr, getdiv, headerok;
reg signok; // ROM signature ok
wire write, wr_posedge;
wire [ 16:0] next_rom;
wire [ 1:0] sign_addr = rom_addr[1:0]-2'd1;
reg pre_cs, pulse_cs;
assign write = cs && (!mdn || !stn );
assign wr_posedge = !last_wr && write;
assign busyn = st == IDLE || st == RST;
assign next_rom = rom_addr+1'b1;
assign rom_cs = pre_cs & ~pulse_cs;
initial begin
sign[0] = 8'h5a;
sign[1] = 8'ha5;
sign[2] = 8'h69;
sign[3] = 8'h55;
end
// Simulation log
`ifdef SIMULATION
`define JT7759_SILENCE $display("\tjt7759: silence");
`define JT7759_PLAY $display("\tjt7759: play");
`define JT7759_PLAY_LONG $display("\tjt7759: play n");
`define JT7759_REPEAT $display("\tjt7759: repeat");
`define JT7759_DONE $display("\tjt7759: sample done");
`else
`define JT7759_SILENCE
`define JT7759_PLAY
`define JT7759_PLAY_LONG
`define JT7759_REPEAT
`define JT7759_DONE
`endif
always @(posedge clk, posedge rst) begin
if( rst ) begin
max_snd <= 8'd0;
st <= RST;
pre_cs <= 0;
rom_addr <= 17'd0;
divby <= 6'h10; // ~8kHz
last_wr <= 0;
dec_rst <= 1;
dec_din <= 4'd0;
mute_cnt <= 0;
data_cnt <= 9'd0;
signok <= 0;
rep_cnt <= ~4'd0;
rep_latch <= 17'd0;
headerok <= 0;
addr_latch<= 0;
pulse_cs <= 0;
flush <= 0;
end else begin
last_wr <= write;
flush <= 0;
if( pulse_cs ) begin
/*if(cen_ctl)*/ pulse_cs <= 0;
end else begin
case( st )
default: if(cen_ctl) begin // start up process
if( mdn ) begin
rom_addr <= 17'd0;
pre_cs <= 0;
dec_rst <= 1;
//pre_cs <= 1;
//st <= SND_CNT; // Reads the ROM header
st <= IDLE;
end
else st <= IDLE;
end
// Check the chip signature
SIGN: if (cen_ctl) begin
if( !mdn ) begin
st <= READADR;
rom_addr[0] <= ~rom_addr[0];
end else begin
if( rom_ok ) begin
if( rom_data != sign[sign_addr] ) begin
signok <= 0;
st <= IDLE;
`ifdef SIMULATION
$display("Wrong ROM assigned to jt7759");
$finish;
`endif
end
else begin
if( &sign_addr ) begin
signok <= 1;
st<=IDLE;
end
rom_addr<= next_rom;
end
end
end
end
IDLE: begin
flush <= 1;
if( wr_posedge && drqn ) begin
//if( din <= max_snd || !mdn ) begin
pre_cs <= 1;
pulse_cs <= 1;
rom_addr <= { 7'd0, {1'd0, din} + 9'd2, 1'b1 };
st <= READADR;
//end
end else begin
pre_cs <= 0;
dec_rst <= 1;
end
end
SND_CNT: begin
if( rom_ok ) begin
max_snd <= rom_data;
rom_addr<= next_rom;
st <= SIGN;
end
end
READADR: if(cen_ctl) begin
if( rom_ok ) begin
if( rom_addr[0] ) begin
rom_addr <= next_rom;
pulse_cs <= 1;
addr_latch[ 7:0] <= rom_data;
end else begin
addr_latch[15:8] <= addr_latch[7:0];
addr_latch[ 7:0] <= rom_data;
st <= LOAD;
pre_cs <= 0;
end
end
end
LOAD: if(cen_ctl) begin
rom_addr <= { addr_latch, 1'b1 };
headerok <= 0;
st <= READCMD;
pre_cs <= 1;
pulse_cs <= 1;
rep_cnt <= ~4'd0;
if ( mdn ) flush <= 1;
end
READCMD: if(cen_ctl) begin
if( rom_ok ) begin
rom_addr <= next_rom;
pre_cs <= 1;
pulse_cs <= 1;
if( ~&rep_cnt ) begin
rep_cnt <= rep_cnt-1'd1;
end
if(rom_data!=0)
headerok <= 1;
case( rom_data[7:6] )
2'd0: begin // Silence
`JT7759_SILENCE
mute_cnt <= {rom_data[5:0],7'd0};
if( rom_data==0 && headerok) begin
st <= IDLE;
dec_rst <= 1;
`JT7759_DONE
end else begin
st <= MUTED;
end
pre_cs <= 0;
end
2'd1: begin // 256 nibbles
data_cnt <= 9'hff;
divby <= rom_data[5:0];
st <= PLAY;
`JT7759_PLAY
end
2'd2: begin // n nibbles
data_cnt[8] <= 0;
divby <= rom_data[5:0];
st <= GETN;
`JT7759_PLAY_LONG
end
2'd3: begin // repeat loop
rep_cnt <= {1'b0, rom_data[2:0]};
rep_latch <= next_rom;
`JT7759_REPEAT
end
endcase
end
end
GETN: begin
if( rom_ok ) begin
rom_addr <= next_rom;
pre_cs <= 1;
pulse_cs <= 1;
data_cnt <= {1'b0, rom_data};
st <= PLAY;
end
end
MUTED: if( cen_ctl ) begin
if(cen_dec) dec_rst<= 1;
if( mute_cnt != 0 ) begin
mute_cnt <= mute_cnt-1'd1;
end else begin
st <= READCMD;
pre_cs <= 1;
pulse_cs <= 1;
end
end
PLAY: begin
if(cen_dec) begin
if( pre_cs ) begin
if( rom_ok ) begin
{ dec_din, next } <= rom_data;
dec_rst <= 0;
pre_cs <= 0;
data_cnt <= data_cnt-1'd1;
if( data_cnt==0 ) begin
pre_cs <= 1;
pulse_cs <= 1;
st <= READCMD;
end
end
end else begin
dec_din <= next;
rom_addr <= next_rom;
pre_cs <= 1;
pulse_cs <= 1;
data_cnt <= data_cnt-1'd1;
if( data_cnt==0 ) begin
st <= READCMD;
end
end
end
end
endcase
end // pulse_cen
end
end
endmodule

147
common/Sound/jt7759/jt7759_data.v Normal file
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@@ -0,0 +1,147 @@
/* This file is part of JT7759.
JT7759 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public Licen_ctlse as published by
the Free Software Foundation, either version 3 of the Licen_ctlse, or
(at your option) any later version.
JT7759 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public Licen_ctlse for more details.
You should have received a copy of the GNU General Public Licen_ctlse
along with JT7759. If not, see <http://www.gnu.org/licen_ctlses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-7-2021 */
module jt7759_data(
input rst,
input clk,
input cen_ctl,
input cen_dec,
input mdn,
// Control interface
input ctrl_flush,
input ctrl_cs,
input ctrl_busyn,
input [16:0] ctrl_addr,
output reg [ 7:0] ctrl_din,
output reg ctrl_ok,
// ROM interface
output rom_cs,
output reg [16:0] rom_addr,
input [ 7:0] rom_data,
input rom_ok,
// Passive interface
input cs,
input wrn, // for slave mode only
input [ 7:0] din,
output reg drqn
);
reg [7:0] fifo[4];
reg [3:0] fifo_ok;
reg drqn_l, ctrl_cs_l;
reg [1:0] rd_addr, wr_addr;
reg readin, readout, readin_l, good_l;
reg [4:0] drqn_cnt;
wire good = mdn ? rom_ok & ~drqn_l & ~drqn : (cs&~wrn);
wire [7:0] din_mux = mdn ? rom_data : din;
assign rom_cs = mdn && !drqn;
always @(posedge clk, posedge rst) begin
if( rst ) begin
drqn_cnt <= 0;
end else begin
// Minimum time between DRQn pulses
if( readin || good )
drqn_cnt <= ~0;
else if( drqn_cnt!=0 && cen_ctl) drqn_cnt <= drqn_cnt-1'd1;
end
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
rom_addr <= 0;
drqn <= 1;
readin_l <= 0;
good_l <= 0;
end else begin
readin_l <= readin;
good_l <= good;
if( !ctrl_busyn ) begin
if(!readin && readin_l)
rom_addr <= rom_addr + 1;
if(fifo_ok==4'hf || (!readin && readin_l) ) begin
drqn <= 1;
end else if(fifo_ok!=4'hf && !readin && drqn_cnt==0 ) begin
drqn <= 0;
end
end else begin
drqn <= 1;
end
if( ctrl_flush )
rom_addr <= ctrl_addr;
end
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
rd_addr <= 0;
ctrl_cs_l <= 0;
readin <= 0;
readout <= 0;
ctrl_ok <= 0;
fifo_ok <= 0;
wr_addr <= 0;
drqn_l <= 1;
end else begin
ctrl_cs_l <= ctrl_cs;
drqn_l <= drqn;
// read out
if( ctrl_cs && !ctrl_cs_l ) begin
readout <= 1;
ctrl_ok <= 0;
end
if( readout && fifo_ok[rd_addr] ) begin
ctrl_din <= fifo[ rd_addr ];
ctrl_ok <= 1;
rd_addr <= rd_addr + 1'd1;
fifo_ok[ rd_addr ] <= 0;
readout <= 0;
end
if( !ctrl_cs ) begin
readout <= 0;
ctrl_ok <= 0;
end
// read in
if( !drqn && drqn_l ) begin
readin <= 1;
end
if( good && readin ) begin
fifo[ wr_addr ] <= din_mux;
fifo_ok[ wr_addr ] <= 1;
wr_addr <= wr_addr + 1;
readin <= 0;
`ifdef JT7759_FIFO_DUMP
$display("\tjt7759: read %X",din_mux);
`endif
end
if( ctrl_busyn || ctrl_flush ) begin
fifo_ok <= 0;
rd_addr <= 0;
wr_addr <= 0;
end
end
end
endmodule

58
common/Sound/jt7759/jt7759_div.v Normal file
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@@ -0,0 +1,58 @@
/* This file is part of JT7759.
JT7759 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT7759 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT7759. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 5-7-2020 */
module jt7759_div(
input clk,
input cen, // 640kHz
input [5:0] divby,
output reg cen_ctl, // control = 8x faster than decoder
output reg cen_dec
);
reg [1:0] cnt4;
reg [5:0] decdiv, ctldiv, divby_l;
wire eoc_ctl, eoc_dec, eoc_cnt; // end of count
assign eoc_ctl = ctldiv == { 1'b0, divby_l[5:1] };
assign eoc_dec = decdiv == divby_l;
assign eoc_cnt = &cnt4;
`ifdef SIMULATION
initial begin
cnt4 = 2'd0;
divby_l= 0;
decdiv = 6'd3; // bad start numbers to show the auto allignment feature
ctldiv = 6'd7;
end
`endif
always @(posedge clk) if(cen) begin
cnt4 <= cnt4+2'd1;
if( eoc_cnt ) begin
decdiv <= eoc_dec ? 6'd0 : (decdiv+1'd1);
if( eoc_dec ) divby_l <= divby < 9 ? 9 : divby; // The divider is updated only at EOC
end
ctldiv <= eoc_ctl || (eoc_dec && eoc_cnt) ? 6'd0 : (ctldiv+1'd1);
end
always @(posedge clk) begin
cen_ctl <= cen; // && eoc_ctl;
cen_dec <= cen && eoc_dec && eoc_cnt;
end
endmodule

9
common/Sound/jtopl/jtopl_csr.v
View File

@@ -21,7 +21,7 @@
*/
module jtopl_csr #(
parameter LEN=18, W=34
parameter LEN=18, W=34, OPL_TYPE=1
) ( // Circular Shift Register + input mux
input rst,
input clk,
@@ -70,8 +70,9 @@ assign regop_in[31:0] = { // 4 bytes:
up_sl_rr_op ? din : shift_out[ 7: 0]
};
`ifdef JTOPL2
assign regop_in[33:32] = up_wav_I ? din[1:0] : shift_out[33:32];
`endif
generate if (OPL_TYPE == 2) begin
assign regop_in[33:32] = up_wav_I ? din[1:0] : shift_out[33:32];
end
endgenerate
endmodule // jtopl_reg

2
common/Sound/jtopl/jtopl_reg.v
View File

@@ -129,7 +129,7 @@ wire en_sus, rhy_oen;
// Sustained is disabled in rhythm mode for channels in group 2 (i.e. 6,7,8)
assign en_sus_I = rhy_oen ? 1'b0 : en_sus;
jtopl_csr #(.LEN(CH*2),.W(OPCFGW)) u_csr(
jtopl_csr #(.LEN(CH*2),.W(OPCFGW), .OPL_TYPE(OPL_TYPE)) u_csr(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),

28
common/Sound/ym3526/jt26.qip
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@@ -1,28 +0,0 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_csr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_div.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_lfo.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pm.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_ctrl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_final.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_pure.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_step.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_exprom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_logsin.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_inc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_sum.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_rhy.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh_rst.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_single_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_timers.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_noise.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl.v]

253
common/Sound/ym3526/jtopl.v
View File

@@ -1,253 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopl #(parameter OPL_TYPE=1)
(
input wire rst, // rst should be at least 6 clk&cen cycles long
input wire clk, // CPU clock
input wire cen, // optional clock enable, it not needed leave as 1'b1
input wire [ 7:0] din,
input wire addr,
input wire cs_n,
input wire wr_n,
output wire [ 7:0] dout,
output wire irq_n,
// combined output
output wire signed [15:0] snd,
output wire sample
);
//parameter OPL_TYPE=1;
wire cenop;
wire write;
wire [ 1:0] group;
wire [17:0] slot;
wire [ 3:0] trem;
// Timers
wire flag_A, flag_B, flagen_A, flagen_B;
wire [ 7:0] value_A;
wire [ 7:0] value_B;
wire load_A, load_B;
wire clr_flag_A, clr_flag_B;
wire overflow_A;
wire zero; // Single-clock pulse at the begginig of s1_enters
// Phase
wire [ 9:0] fnum_I;
wire [ 2:0] block_I;
wire [ 3:0] mul_II;
wire [ 9:0] phase_IV;
wire pg_rst_II;
wire viben_I;
wire [ 2:0] vib_cnt;
// envelope configuration
wire en_sus_I; // enable sustain
wire [ 3:0] keycode_II;
wire [ 3:0] arate_I; // attack rate
wire [ 3:0] drate_I; // decay rate
wire [ 3:0] rrate_I; // release rate
wire [ 3:0] sl_I; // sustain level
wire ksr_II; // key scale rate - affects rates
wire [ 1:0] ksl_IV; // key scale level - affects amplitude
// envelope operation
wire keyon_I;
wire eg_stop;
// envelope number
wire amen_IV;
wire [ 5:0] tl_IV;
wire [ 9:0] eg_V;
// Global values
wire am_dep, vib_dep, rhy_en;
// Operator
wire [ 2:0] fb_I;
wire [ 1:0] wavsel_I;
wire op, con_I, op_out, con_out;
wire signed [12:0] op_result;
assign write = !cs_n && !wr_n;
assign dout = { ~irq_n, flag_A, flag_B, 5'd6 };
assign eg_stop = 0;
assign sample = zero;
jtopl_mmr #(.OPL_TYPE(OPL_TYPE)) u_mmr(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ), // external clock enable
.cenop ( cenop ), // internal clock enable
.din ( din ),
.write ( write ),
.addr ( addr ),
.zero ( zero ),
.group ( group ),
.op ( op ),
.slot ( slot ),
.rhy_en ( rhy_en ),
// Timers
.value_A ( value_A ),
.value_B ( value_B ),
.load_A ( load_A ),
.load_B ( load_B ),
.flagen_A ( flagen_A ),
.flagen_B ( flagen_B ),
.clr_flag_A ( clr_flag_A ),
.clr_flag_B ( clr_flag_B ),
.flag_A ( flag_A ),
.overflow_A ( overflow_A ),
// Phase Generator
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.mul_II ( mul_II ),
// Operator
.wavsel_I ( wavsel_I ),
// Envelope Generator
.keyon_I ( keyon_I ),
.en_sus_I ( en_sus_I ),
.arate_I ( arate_I ),
.drate_I ( drate_I ),
.rrate_I ( rrate_I ),
.sl_I ( sl_I ),
.ks_II ( ksr_II ),
.tl_IV ( tl_IV ),
.ksl_IV ( ksl_IV ),
.amen_IV ( amen_IV ),
.viben_I ( viben_I ),
// Global Values
.am_dep ( am_dep ),
.vib_dep ( vib_dep ),
// Timbre
.fb_I ( fb_I ),
.con_I ( con_I )
);
jtopl_timers u_timers(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.value_A ( value_A ),
.value_B ( value_B ),
.load_A ( load_A ),
.load_B ( load_B ),
.flagen_A ( flagen_A ),
.flagen_B ( flagen_B ),
.clr_flag_A ( clr_flag_A ),
.clr_flag_B ( clr_flag_B ),
.flag_A ( flag_A ),
.flag_B ( flag_B ),
.overflow_A ( overflow_A ),
.irq_n ( irq_n )
);
jtopl_lfo u_lfo(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.slot ( slot ),
.vib_cnt ( vib_cnt ),
.trem ( trem )
);
jtopl_pg u_pg(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.slot ( slot ),
.rhy_en ( rhy_en ),
// Channel frequency
.fnum_I ( fnum_I ),
.block_I ( block_I ),
// Operator multiplying
.mul_II ( mul_II ),
// phase modulation from LFO (vibrato at 6.4Hz)
.vib_cnt ( vib_cnt ),
.vib_dep ( vib_dep ),
.viben_I ( viben_I ),
// phase operation
.pg_rst_II ( pg_rst_II ),
.keycode_II ( keycode_II ),
.phase_IV ( phase_IV )
);
jtopl_eg u_eg(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.eg_stop ( eg_stop ),
// envelope configuration
.en_sus_I ( en_sus_I ), // enable sustain
.keycode_II ( keycode_II ),
.arate_I ( arate_I ), // attack rate
.drate_I ( drate_I ), // decay rate
.rrate_I ( rrate_I ), // release rate
.sl_I ( sl_I ), // sustain level
.ksr_II ( ksr_II ), // key scale
// envelope operation
.keyon_I ( keyon_I ),
// envelope number
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.lfo_mod ( trem ),
.amsen_IV ( amen_IV ),
.ams_IV ( am_dep ),
.tl_IV ( tl_IV ),
.ksl_IV ( ksl_IV ),
.eg_V ( eg_V ),
.pg_rst_II ( pg_rst_II )
);
jtopl_op #(.OPL_TYPE(OPL_TYPE)) u_op(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
// location of current operator
.group ( group ),
.op ( op ),
.zero ( zero ),
.pg_phase_I ( phase_IV ),
.eg_atten_II( eg_V ), // output from envelope generator
.fb_I ( fb_I ), // voice feedback
.wavsel_I ( wavsel_I ), // sine mask (OPL2)
.con_I ( con_I ),
.op_result ( op_result ),
.op_out ( op_out ),
.con_out ( con_out )
);
jtopl_acc u_acc(
.rst ( rst ),
.clk ( clk ),
.cenop ( cenop ),
.zero ( zero ),
.op_result ( op_result ),
.op ( op_out ),
.con ( con_out ),
.snd ( snd )
);
endmodule

52
common/Sound/ym3526/jtopl2.v
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/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-10-2021
*/
module jtopl2(
input wire rst, // rst should be at least 6 clk&cen cycles long
input wire clk, // CPU clock
input wire cen, // optional clock enable, it not needed leave as 1'b1
input wire [ 7:0] din,
input wire addr,
input wire cs_n,
input wire wr_n,
output wire [ 7:0] dout,
output wire irq_n,
// combined output
output wire signed [15:0] snd,
output wire sample
);
`define JTOPL2
jtopl #(.OPL_TYPE(2)) u_base(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( din ),
.addr ( addr ),
.cs_n ( cs_n ),
.wr_n ( wr_n ),
.dout ( dout ),
.irq_n ( irq_n ),
.snd ( snd ),
.sample ( sample )
);
endmodule

48
common/Sound/ym3526/jtopl_acc.v
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/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 20-6-2020
*/
module jtopl_acc(
input wire rst,
input wire clk,
input wire cenop,
input wire signed [12:0] op_result,
input wire zero,
input wire op, // 0 for modulator operators
input wire con, // 0 for modulated connection
output wire signed [15:0] snd
);
wire sum_en;
assign sum_en = op | con;
// Continuous output
jtopl_single_acc u_acc(
.clk ( clk ),
.cenop ( cenop ),
.op_result ( op_result ),
.sum_en ( sum_en ),
.zero ( zero ),
.snd ( snd )
);
endmodule

77
common/Sound/ym3526/jtopl_csr.v
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/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_csr #(
parameter LEN=18, W=34
) ( // Circular Shift Register + input mux
input wire rst,
input wire clk,
input wire cen,
input wire [ 7:0] din,
output wire [W-1:0] shift_out,
input wire up_mult,
input wire up_ksl_tl,
input wire up_ar_dr,
input wire up_sl_rr,
input wire up_wav,
input wire update_op_I,
input wire update_op_II,
input wire update_op_IV
);
wire [W-1:0] regop_in;
jtopl_sh_rst #(.width(W),.stages(LEN)) u_regch(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( regop_in ),
.drop ( shift_out )
);
wire up_mult_I = up_mult & update_op_I;
wire up_mult_II = up_mult & update_op_II;
wire up_mult_IV = up_mult & update_op_IV;
wire up_ksl_tl_IV = up_ksl_tl & update_op_IV;
wire up_ar_dr_op = up_ar_dr & update_op_I;
wire up_sl_rr_op = up_sl_rr & update_op_I;
wire up_wav_I = up_wav & update_op_I;
assign regop_in[31:0] = { // 4 bytes:
up_mult_IV ? din[7] : shift_out[31], // AM enable
up_mult_I ? din[6:5] : shift_out[30:29], // Vib enable, EG type, KSR
up_mult_II ? din[4:0] : shift_out[28:24], // KSR + Mult
up_ksl_tl_IV? din : shift_out[23:16], // KSL + TL
up_ar_dr_op ? din : shift_out[15: 8],
up_sl_rr_op ? din : shift_out[ 7: 0]
};
// `ifdef JTOPL2
// assign regop_in[33:32] = up_wav_I ? din[1:0] : shift_out[33:32];
// `endif
endmodule // jtopl_reg

48
common/Sound/ym3526/jtopl_div.v
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@@ -1,48 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopl_div #(parameter OPL_TYPE=1)
(
input wire rst,
input wire clk,
input wire cen,
output reg cenop // clock enable at operator rate
);
//parameter OPL_TYPE=1;
localparam W = 2; // OPL_TYPE==2 ? 1 : 2;
reg [W-1:0] cnt;
`ifdef SIMULATION
initial cnt={W{1'b0}};
`endif
always @(posedge clk) if(cen) begin
cnt <= cnt+1'd1;
end
always @(posedge clk) begin
cenop <= cen && (&cnt);
end
endmodule

203
common/Sound/ym3526/jtopl_eg.v
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@@ -1,203 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg (
input wire rst,
input wire clk,
input wire cenop,
input wire zero,
input wire eg_stop,
// envelope configuration
input wire en_sus_I, // enable sustain
input wire [3:0] keycode_II,
input wire [3:0] arate_I, // attack rate
input wire [3:0] drate_I, // decay rate
input wire [3:0] rrate_I, // release rate
input wire [3:0] sl_I, // sustain level
input wire ksr_II, // key scale
// envelope operation
input wire keyon_I,
// envelope number
input wire [9:0] fnum_I,
input wire [2:0] block_I,
input wire [3:0] lfo_mod,
input wire amsen_IV,
input wire ams_IV,
input wire [5:0] tl_IV,
input wire [1:0] ksl_IV,
output reg [9:0] eg_V,
output reg pg_rst_II
);
parameter SLOTS=18;
wire [14:0] eg_cnt;
jtopl_eg_cnt u_egcnt(
.rst ( rst ),
.clk ( clk ),
.cen ( cenop & ~eg_stop ),
.zero ( zero ),
.eg_cnt ( eg_cnt)
);
wire keyon_last_I;
wire keyon_now_I = !keyon_last_I && keyon_I;
wire keyoff_now_I = keyon_last_I && !keyon_I;
wire cnt_in_II, cnt_lsb_II, step_II, pg_rst_I;
wire [2:0] state_in_I, state_next_I;
reg attack_II, attack_III;
wire [4:0] base_rate_I;
reg [4:0] base_rate_II;
wire [5:0] rate_out_II;
reg [5:1] rate_in_III;
reg step_III;
wire sum_out_II;
reg sum_in_III;
wire [9:0] eg_in_I, pure_eg_out_III, eg_next_III, eg_out_IV;
reg [9:0] eg_in_II, eg_in_III, eg_in_IV;
reg [3:0] keycode_III, keycode_IV;
wire [3:0] fnum_IV;
wire [2:0] block_IV;
jtopl_eg_comb u_comb(
///////////////////////////////////
// I
.keyon_now ( keyon_now_I ),
.keyoff_now ( keyoff_now_I ),
.state_in ( state_in_I ),
.eg_in ( eg_in_I ),
// envelope configuration
.en_sus ( en_sus_I ),
.arate ( arate_I ), // attack rate
.drate ( drate_I ), // decay rate
.rrate ( rrate_I ),
.sl ( sl_I ), // sustain level
.base_rate ( base_rate_I ),
.state_next ( state_next_I ),
.pg_rst ( pg_rst_I ),
///////////////////////////////////
// II
.step_attack ( attack_II ),
.step_rate_in ( base_rate_II ),
.keycode ( keycode_II ),
.eg_cnt ( eg_cnt ),
.cnt_in ( cnt_in_II ),
.ksr ( ksr_II ),
.cnt_lsb ( cnt_lsb_II ),
.step ( step_II ),
.step_rate_out ( rate_out_II ),
.sum_up_out ( sum_out_II ),
///////////////////////////////////
// III
.pure_attack ( attack_III ),
.pure_step ( step_III ),
.pure_rate ( rate_in_III[5:1] ),
.pure_eg_in ( eg_in_III ),
.pure_eg_out ( pure_eg_out_III ),
.sum_up_in ( sum_in_III ),
///////////////////////////////////
// IV
.fnum ( fnum_IV ),
.block ( block_IV ),
.lfo_mod ( lfo_mod ),
.amsen ( amsen_IV ),
.ams ( ams_IV ),
.ksl ( ksl_IV ),
.tl ( tl_IV ),
.final_keycode ( keycode_IV ),
.final_eg_in ( eg_in_IV ),
.final_eg_out ( eg_out_IV )
);
always @(posedge clk) if(cenop) begin
eg_in_II <= eg_in_I;
attack_II <= state_next_I[0];
base_rate_II<= base_rate_I;
pg_rst_II <= pg_rst_I;
eg_in_III <= eg_in_II;
attack_III <= attack_II;
rate_in_III <= rate_out_II[5:1];
step_III <= step_II;
sum_in_III <= sum_out_II;
eg_in_IV <= pure_eg_out_III;
eg_V <= eg_out_IV;
keycode_III <= keycode_II;
keycode_IV <= keycode_III;
end
jtopl_sh #( .width(1), .stages(SLOTS) ) u_cntsh(
.clk ( clk ),
.cen ( cenop ),
.din ( cnt_lsb_II),
.drop ( cnt_in_II )
);
jtopl_sh #( .width(4), .stages(3) ) u_fnumsh(
.clk ( clk ),
.cen ( cenop ),
.din ( fnum_I[9:6] ),
.drop ( fnum_IV )
);
jtopl_sh #( .width(3), .stages(3) ) u_blocksh(
.clk ( clk ),
.cen ( cenop ),
.din ( block_I ),
.drop ( block_IV )
);
jtopl_sh_rst #( .width(10), .stages(SLOTS-3), .rstval(1'b1) ) u_egsh(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( eg_in_IV ),
.drop ( eg_in_I )
);
jtopl_sh_rst #( .width(3), .stages(SLOTS), .rstval(1'b1) ) u_egstate(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( state_next_I ),
.drop ( state_in_I )
);
jtopl_sh_rst #( .width(1), .stages(SLOTS), .rstval(1'b0) ) u_konsh(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( keyon_I ),
.drop ( keyon_last_I )
);
endmodule // jtopl_eg

44
common/Sound/ym3526/jtopl_eg_cnt.v
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@@ -1,44 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_cnt(
input wire rst,
input wire clk,
input wire cen,
input wire zero,
output reg [14:0] eg_cnt
);
always @(posedge clk, posedge rst) begin : envelope_counter
if( rst ) begin
eg_cnt <=15'd0;
end
else begin
if( zero && cen ) begin
// envelope counter increases at each zero input
// This is different from OPN/M where it increased
// once every three zero inputs
eg_cnt <= eg_cnt + 1'b1;
end
end
end
endmodule

131
common/Sound/ym3526/jtopl_eg_comb.v
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@@ -1,131 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_comb(
input wire keyon_now,
input wire keyoff_now,
input wire [ 2:0] state_in,
input wire [ 9:0] eg_in,
// envelope configuration
input wire en_sus, // enable sustain
input wire [ 3:0] arate, // attack rate
input wire [ 3:0] drate, // decay rate
input wire [ 3:0] rrate,
input wire [ 3:0] sl, // sustain level
output wire [ 4:0] base_rate,
output wire [ 2:0] state_next,
output wire pg_rst,
///////////////////////////////////
// II
input wire step_attack,
input wire [ 4:0] step_rate_in,
input wire [ 3:0] keycode,
input wire [14:0] eg_cnt,
input wire cnt_in,
input wire ksr,
output wire cnt_lsb,
output wire step,
output wire [ 5:0] step_rate_out,
output wire sum_up_out,
///////////////////////////////////
// III
input wire pure_attack,
input wire pure_step,
input wire [ 5:1] pure_rate,
input wire [ 9:0] pure_eg_in,
output wire [ 9:0] pure_eg_out,
input wire sum_up_in,
///////////////////////////////////
// IV
input wire [ 3:0] lfo_mod,
input wire [ 3:0] fnum,
input wire [ 2:0] block,
input wire amsen,
input wire ams,
input wire [ 5:0] tl,
input wire [ 1:0] ksl,
input wire [ 3:0] final_keycode,
input wire [ 9:0] final_eg_in,
output wire [ 9:0] final_eg_out
);
// I
jtopl_eg_ctrl u_ctrl(
.keyon_now ( keyon_now ),
.keyoff_now ( keyoff_now ),
.state_in ( state_in ),
.eg ( eg_in ),
// envelope configuration
.en_sus ( en_sus ),
.arate ( arate ), // attack rate
.drate ( drate ), // decay rate
.rrate ( rrate ),
.sl ( sl ), // sustain level
.base_rate ( base_rate ),
.state_next ( state_next ),
.pg_rst ( pg_rst )
);
// II
jtopl_eg_step u_step(
.attack ( step_attack ),
.base_rate ( step_rate_in ),
.keycode ( keycode ),
.eg_cnt ( eg_cnt ),
.cnt_in ( cnt_in ),
.ksr ( ksr ),
.cnt_lsb ( cnt_lsb ),
.step ( step ),
.rate ( step_rate_out ),
.sum_up ( sum_up_out )
);
// III
wire [9:0] egin, egout;
jtopl_eg_pure u_pure(
.attack ( pure_attack ),
.step ( pure_step ),
.rate ( pure_rate ),
.eg_in ( pure_eg_in ),
.eg_pure( pure_eg_out ),
.sum_up ( sum_up_in )
);
// IV
jtopl_eg_final u_final(
.fnum ( fnum ),
.block ( block ),
.lfo_mod ( lfo_mod ),
.amsen ( amsen ),
.ams ( ams ),
.tl ( tl ),
.ksl ( ksl ),
.keycode ( final_keycode ),
.eg_pure_in ( final_eg_in ),
.eg_limited ( final_eg_out )
);
endmodule // jtopl_eg_comb

87
common/Sound/ym3526/jtopl_eg_ctrl.v
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@@ -1,87 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_ctrl(
input wire keyon_now,
input wire keyoff_now,
input wire [2:0] state_in,
input wire [9:0] eg,
// envelope configuration
input wire en_sus, // enable sustain
input wire [3:0] arate, // attack rate
input wire [3:0] drate, // decay rate
input wire [3:0] rrate,
input wire [3:0] sl, // sustain level
output reg [4:0] base_rate,
output reg [2:0] state_next,
output reg pg_rst
);
localparam ATTACK = 3'b001,
DECAY = 3'b010,
HOLD = 3'b100,
RELEASE= 3'b000; // default state is release
// wire is_decaying = state_in[1] | state_in[2];
wire [4:0] sustain = { &sl, sl}; //93dB if sl==4'hF
always @(*) begin
pg_rst = keyon_now;
end
always @(*)
casez ( { keyoff_now, keyon_now, state_in} )
5'b01_???: begin // key on
base_rate = {arate,1'b0};
state_next = ATTACK;
end
{2'b00, ATTACK}:
if( eg==10'd0 ) begin
base_rate = {drate,1'b0};
state_next = DECAY;
end
else begin
base_rate = {arate,1'b0};
state_next = ATTACK;
end
{2'b00, DECAY}: begin
if( eg[9:5] >= sustain ) begin
base_rate = en_sus ? 5'd0 : {rrate,1'b0};
state_next = en_sus ? HOLD : RELEASE;
end else begin
base_rate = {drate,1'b0};
state_next = DECAY;
end
end
{2'b00, HOLD}: begin
base_rate = 5'd0;
state_next = HOLD;
end
default: begin // RELEASE, note that keyoff_now==1 will enter this state too
base_rate = {rrate,1'b1};
state_next = RELEASE; // release
end
endcase
endmodule // jtopl_eg_ctrl

70
common/Sound/ym3526/jtopl_eg_final.v
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@@ -1,70 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_final(
input wire [3:0] lfo_mod,
input wire [3:0] fnum,
input wire [2:0] block,
input wire amsen,
input wire ams,
input wire [5:0] tl,
input wire [1:0] ksl, // level damped by pitch
input wire [3:0] keycode,
input wire [9:0] eg_pure_in,
output reg [9:0] eg_limited
);
reg [ 5:0] am_final;
reg [11:0] sum_eg_tl;
reg [11:0] sum_eg_tl_am;
reg [ 8:0] ksl_dB;
reg [ 6:0] ksl_lut[0:15];
reg [ 7:0] ksl_base;
always @(*) begin
ksl_base = {1'b0, ksl_lut[fnum]}- { 1'b0, 4'd8-{1'b0,block}, 3'b0 };
if( ksl_base[7] || ksl==2'b0 ) begin
ksl_dB = 9'd0;
end else begin
ksl_dB = {ksl_base[6:0],2'b0} >> ~ksl;
end
end
always @(*) begin
am_final = amsen ? ( ams ? {lfo_mod, 2'b0} : {2'b0, lfo_mod} ) : 6'd0;
sum_eg_tl = { 2'b0, tl, 3'd0 } +
{ 1'b0, ksl_dB, 1'd0 } +
{ 1'b0, eg_pure_in}; // leading zeros needed to compute correctly
sum_eg_tl_am = sum_eg_tl + { 5'd0, am_final };
end
always @(*) begin
eg_limited = sum_eg_tl_am[11:10]==2'd0 ? sum_eg_tl_am[9:0] : 10'h3ff;
end
initial begin
ksl_lut[ 0] = 7'd00; ksl_lut[ 1] = 7'd32; ksl_lut[ 2] = 7'd40; ksl_lut[ 3] = 7'd45;
ksl_lut[ 4] = 7'd48; ksl_lut[ 5] = 7'd51; ksl_lut[ 6] = 7'd53; ksl_lut[ 7] = 7'd55;
ksl_lut[ 8] = 7'd56; ksl_lut[ 9] = 7'd58; ksl_lut[10] = 7'd59; ksl_lut[11] = 7'd60;
ksl_lut[12] = 7'd61; ksl_lut[13] = 7'd62; ksl_lut[14] = 7'd63; ksl_lut[15] = 7'd64;
end
endmodule

81
common/Sound/ym3526/jtopl_eg_pure.v
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@@ -1,81 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_pure(
input wire attack,
input wire step,
input wire [ 5:1] rate,
input wire [ 9:0] eg_in,
input wire sum_up,
output reg [9:0] eg_pure
);
reg [ 3:0] dr_sum;
reg [ 9:0] dr_adj;
reg [10:0] dr_result;
always @(*) begin : dr_calculation
case( rate[5:2] )
4'b1100: dr_sum = { 2'b0, step, ~step }; // 12
4'b1101: dr_sum = { 1'b0, step, ~step, 1'b0 }; // 13
4'b1110: dr_sum = { step, ~step, 2'b0 }; // 14
4'b1111: dr_sum = 4'd8;// 15
default: dr_sum = { 2'b0, step, 1'b0 };
endcase
// Decay rate attenuation is multiplied by 4 for SSG operation
dr_adj = {6'd0, dr_sum};
dr_result = dr_adj + eg_in;
end
reg [ 7:0] ar_sum0;
reg [ 8:0] ar_sum1;
reg [10:0] ar_result;
reg [ 9:0] ar_sum;
always @(*) begin : ar_calculation
casez( rate[5:2] )
default: ar_sum0 = {2'd0, eg_in[9:4]};
4'b1101: ar_sum0 = {1'd0, eg_in[9:3]};
4'b111?: ar_sum0 = eg_in[9:2];
endcase
ar_sum1 = ar_sum0+9'd1;
if( rate[5:4] == 2'b11 )
ar_sum = step ? { ar_sum1, 1'b0 } : { 1'b0, ar_sum1 };
else
ar_sum = step ? { 1'b0, ar_sum1 } : 10'd0;
ar_result = eg_in-ar_sum;
end
///////////////////////////////////////////////////////////
// rate not used below this point
reg [9:0] eg_pre_fastar; // pre fast attack rate
always @(*) begin
if(sum_up) begin
if( attack )
eg_pre_fastar = ar_result[10] ? 10'd0: ar_result[9:0];
else
eg_pre_fastar = dr_result[10] ? 10'h3FF : dr_result[9:0];
end
else eg_pre_fastar = eg_in;
eg_pure = (attack&rate[5:1]==5'h1F) ? 10'd0 : eg_pre_fastar;
end
endmodule

108
common/Sound/ym3526/jtopl_eg_step.v
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@@ -1,108 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 17-6-2020
*/
module jtopl_eg_step(
input wire attack,
input wire [ 4:0] base_rate,
input wire [ 3:0] keycode,
input wire [14:0] eg_cnt,
input wire cnt_in,
input wire ksr,
output wire cnt_lsb,
output reg step,
output reg [ 5:0] rate,
output reg sum_up
);
reg [6:0] pre_rate;
always @(*) begin : pre_rate_calc
if( base_rate == 5'd0 )
pre_rate = 7'd0;
else
pre_rate = { 1'b0, base_rate, 1'b0 } + (ksr ?
{ 3'b0, keycode }:
{ 5'b0, keycode[3:2] });
end
always @(*)
rate = pre_rate>=7'b1111_00 ? 6'b1111_11 : pre_rate[5:0];
reg [2:0] cnt;
reg [4:0] mux_sel;
always @(*) begin
mux_sel = attack ? (rate[5:2]+4'd1): {1'b0,rate[5:2]};
end
always @(*)
case( mux_sel )
5'h0: cnt = eg_cnt[14:12];
5'h1: cnt = eg_cnt[13:11];
5'h2: cnt = eg_cnt[12:10];
5'h3: cnt = eg_cnt[11: 9];
5'h4: cnt = eg_cnt[10: 8];
5'h5: cnt = eg_cnt[ 9: 7];
5'h6: cnt = eg_cnt[ 8: 6];
5'h7: cnt = eg_cnt[ 7: 5];
5'h8: cnt = eg_cnt[ 6: 4];
5'h9: cnt = eg_cnt[ 5: 3];
5'ha: cnt = eg_cnt[ 4: 2];
5'hb: cnt = eg_cnt[ 3: 1];
default: cnt = eg_cnt[ 2: 0];
endcase
////////////////////////////////
reg [7:0] step_idx;
always @(*) begin : rate_step
if( rate[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate[5:2]==4'hf && attack)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate[5:2]==4'd0 && !attack)
step_idx = 8'b11111110; // limit slowest decay rate
else
case( rate[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate of zero keeps the level still
step = rate[5:1]==5'd0 ? 1'b0 : step_idx[ cnt ];
end
assign cnt_lsb = cnt[0];
always @(*) begin
sum_up = cnt[0] != cnt_in;
end
endmodule // eg_step

305
common/Sound/ym3526/jtopl_exprom.v
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@@ -1,305 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 20-6-2020
*/
// Yamaha used the same table for OPN, OPM and OPL
// Originally written in more compact way that required some logic to decompress
// Not really worth compressing when the target is an FPGA as one BRAM will be
// used in either case. So it's better to leave it uncompress and save the
// decoding logic
// altera message_off 10030
module jtopl_exprom
(
input wire [7:0] addr,
input wire clk,
input wire cen,
output reg [9:0] exp
);
reg [9:0] explut_jt51[255:0];
initial
begin
explut_jt51[8'd000] = 10'd1018;
explut_jt51[8'd001] = 10'd1013;
explut_jt51[8'd002] = 10'd1007;
explut_jt51[8'd003] = 10'd1002;
explut_jt51[8'd004] = 10'd0996;
explut_jt51[8'd005] = 10'd0991;
explut_jt51[8'd006] = 10'd0986;
explut_jt51[8'd007] = 10'd0980;
explut_jt51[8'd008] = 10'd0975;
explut_jt51[8'd009] = 10'd0969;
explut_jt51[8'd010] = 10'd0964;
explut_jt51[8'd011] = 10'd0959;
explut_jt51[8'd012] = 10'd0953;
explut_jt51[8'd013] = 10'd0948;
explut_jt51[8'd014] = 10'd0942;
explut_jt51[8'd015] = 10'd0937;
explut_jt51[8'd016] = 10'd0932;
explut_jt51[8'd017] = 10'd0927;
explut_jt51[8'd018] = 10'd0921;
explut_jt51[8'd019] = 10'd0916;
explut_jt51[8'd020] = 10'd0911;
explut_jt51[8'd021] = 10'd0906;
explut_jt51[8'd022] = 10'd0900;
explut_jt51[8'd023] = 10'd0895;
explut_jt51[8'd024] = 10'd0890;
explut_jt51[8'd025] = 10'd0885;
explut_jt51[8'd026] = 10'd0880;
explut_jt51[8'd027] = 10'd0874;
explut_jt51[8'd028] = 10'd0869;
explut_jt51[8'd029] = 10'd0864;
explut_jt51[8'd030] = 10'd0859;
explut_jt51[8'd031] = 10'd0854;
explut_jt51[8'd032] = 10'd0849;
explut_jt51[8'd033] = 10'd0844;
explut_jt51[8'd034] = 10'd0839;
explut_jt51[8'd035] = 10'd0834;
explut_jt51[8'd036] = 10'd0829;
explut_jt51[8'd037] = 10'd0824;
explut_jt51[8'd038] = 10'd0819;
explut_jt51[8'd039] = 10'd0814;
explut_jt51[8'd040] = 10'd0809;
explut_jt51[8'd041] = 10'd0804;
explut_jt51[8'd042] = 10'd0799;
explut_jt51[8'd043] = 10'd0794;
explut_jt51[8'd044] = 10'd0789;
explut_jt51[8'd045] = 10'd0784;
explut_jt51[8'd046] = 10'd0779;
explut_jt51[8'd047] = 10'd0774;
explut_jt51[8'd048] = 10'd0770;
explut_jt51[8'd049] = 10'd0765;
explut_jt51[8'd050] = 10'd0760;
explut_jt51[8'd051] = 10'd0755;
explut_jt51[8'd052] = 10'd0750;
explut_jt51[8'd053] = 10'd0745;
explut_jt51[8'd054] = 10'd0741;
explut_jt51[8'd055] = 10'd0736;
explut_jt51[8'd056] = 10'd0731;
explut_jt51[8'd057] = 10'd0726;
explut_jt51[8'd058] = 10'd0722;
explut_jt51[8'd059] = 10'd0717;
explut_jt51[8'd060] = 10'd0712;
explut_jt51[8'd061] = 10'd0708;
explut_jt51[8'd062] = 10'd0703;
explut_jt51[8'd063] = 10'd0698;
explut_jt51[8'd064] = 10'd0693;
explut_jt51[8'd065] = 10'd0689;
explut_jt51[8'd066] = 10'd0684;
explut_jt51[8'd067] = 10'd0680;
explut_jt51[8'd068] = 10'd0675;
explut_jt51[8'd069] = 10'd0670;
explut_jt51[8'd070] = 10'd0666;
explut_jt51[8'd071] = 10'd0661;
explut_jt51[8'd072] = 10'd0657;
explut_jt51[8'd073] = 10'd0652;
explut_jt51[8'd074] = 10'd0648;
explut_jt51[8'd075] = 10'd0643;
explut_jt51[8'd076] = 10'd0639;
explut_jt51[8'd077] = 10'd0634;
explut_jt51[8'd078] = 10'd0630;
explut_jt51[8'd079] = 10'd0625;
explut_jt51[8'd080] = 10'd0621;
explut_jt51[8'd081] = 10'd0616;
explut_jt51[8'd082] = 10'd0612;
explut_jt51[8'd083] = 10'd0607;
explut_jt51[8'd084] = 10'd0603;
explut_jt51[8'd085] = 10'd0599;
explut_jt51[8'd086] = 10'd0594;
explut_jt51[8'd087] = 10'd0590;
explut_jt51[8'd088] = 10'd0585;
explut_jt51[8'd089] = 10'd0581;
explut_jt51[8'd090] = 10'd0577;
explut_jt51[8'd091] = 10'd0572;
explut_jt51[8'd092] = 10'd0568;
explut_jt51[8'd093] = 10'd0564;
explut_jt51[8'd094] = 10'd0560;
explut_jt51[8'd095] = 10'd0555;
explut_jt51[8'd096] = 10'd0551;
explut_jt51[8'd097] = 10'd0547;
explut_jt51[8'd098] = 10'd0542;
explut_jt51[8'd099] = 10'd0538;
explut_jt51[8'd100] = 10'd0534;
explut_jt51[8'd101] = 10'd0530;
explut_jt51[8'd102] = 10'd0526;
explut_jt51[8'd103] = 10'd0521;
explut_jt51[8'd104] = 10'd0517;
explut_jt51[8'd105] = 10'd0513;
explut_jt51[8'd106] = 10'd0509;
explut_jt51[8'd107] = 10'd0505;
explut_jt51[8'd108] = 10'd0501;
explut_jt51[8'd109] = 10'd0496;
explut_jt51[8'd110] = 10'd0492;
explut_jt51[8'd111] = 10'd0488;
explut_jt51[8'd112] = 10'd0484;
explut_jt51[8'd113] = 10'd0480;
explut_jt51[8'd114] = 10'd0476;
explut_jt51[8'd115] = 10'd0472;
explut_jt51[8'd116] = 10'd0468;
explut_jt51[8'd117] = 10'd0464;
explut_jt51[8'd118] = 10'd0460;
explut_jt51[8'd119] = 10'd0456;
explut_jt51[8'd120] = 10'd0452;
explut_jt51[8'd121] = 10'd0448;
explut_jt51[8'd122] = 10'd0444;
explut_jt51[8'd123] = 10'd0440;
explut_jt51[8'd124] = 10'd0436;
explut_jt51[8'd125] = 10'd0432;
explut_jt51[8'd126] = 10'd0428;
explut_jt51[8'd127] = 10'd0424;
explut_jt51[8'd128] = 10'd0420;
explut_jt51[8'd129] = 10'd0416;
explut_jt51[8'd130] = 10'd0412;
explut_jt51[8'd131] = 10'd0409;
explut_jt51[8'd132] = 10'd0405;
explut_jt51[8'd133] = 10'd0401;
explut_jt51[8'd134] = 10'd0397;
explut_jt51[8'd135] = 10'd0393;
explut_jt51[8'd136] = 10'd0389;
explut_jt51[8'd137] = 10'd0385;
explut_jt51[8'd138] = 10'd0382;
explut_jt51[8'd139] = 10'd0378;
explut_jt51[8'd140] = 10'd0374;
explut_jt51[8'd141] = 10'd0370;
explut_jt51[8'd142] = 10'd0367;
explut_jt51[8'd143] = 10'd0363;
explut_jt51[8'd144] = 10'd0359;
explut_jt51[8'd145] = 10'd0355;
explut_jt51[8'd146] = 10'd0352;
explut_jt51[8'd147] = 10'd0348;
explut_jt51[8'd148] = 10'd0344;
explut_jt51[8'd149] = 10'd0340;
explut_jt51[8'd150] = 10'd0337;
explut_jt51[8'd151] = 10'd0333;
explut_jt51[8'd152] = 10'd0329;
explut_jt51[8'd153] = 10'd0326;
explut_jt51[8'd154] = 10'd0322;
explut_jt51[8'd155] = 10'd0318;
explut_jt51[8'd156] = 10'd0315;
explut_jt51[8'd157] = 10'd0311;
explut_jt51[8'd158] = 10'd0308;
explut_jt51[8'd159] = 10'd0304;
explut_jt51[8'd160] = 10'd0300;
explut_jt51[8'd161] = 10'd0297;
explut_jt51[8'd162] = 10'd0293;
explut_jt51[8'd163] = 10'd0290;
explut_jt51[8'd164] = 10'd0286;
explut_jt51[8'd165] = 10'd0283;
explut_jt51[8'd166] = 10'd0279;
explut_jt51[8'd167] = 10'd0276;
explut_jt51[8'd168] = 10'd0272;
explut_jt51[8'd169] = 10'd0268;
explut_jt51[8'd170] = 10'd0265;
explut_jt51[8'd171] = 10'd0262;
explut_jt51[8'd172] = 10'd0258;
explut_jt51[8'd173] = 10'd0255;
explut_jt51[8'd174] = 10'd0251;
explut_jt51[8'd175] = 10'd0248;
explut_jt51[8'd176] = 10'd0244;
explut_jt51[8'd177] = 10'd0241;
explut_jt51[8'd178] = 10'd0237;
explut_jt51[8'd179] = 10'd0234;
explut_jt51[8'd180] = 10'd0231;
explut_jt51[8'd181] = 10'd0227;
explut_jt51[8'd182] = 10'd0224;
explut_jt51[8'd183] = 10'd0220;
explut_jt51[8'd184] = 10'd0217;
explut_jt51[8'd185] = 10'd0214;
explut_jt51[8'd186] = 10'd0210;
explut_jt51[8'd187] = 10'd0207;
explut_jt51[8'd188] = 10'd0204;
explut_jt51[8'd189] = 10'd0200;
explut_jt51[8'd190] = 10'd0197;
explut_jt51[8'd191] = 10'd0194;
explut_jt51[8'd192] = 10'd0190;
explut_jt51[8'd193] = 10'd0187;
explut_jt51[8'd194] = 10'd0184;
explut_jt51[8'd195] = 10'd0181;
explut_jt51[8'd196] = 10'd0177;
explut_jt51[8'd197] = 10'd0174;
explut_jt51[8'd198] = 10'd0171;
explut_jt51[8'd199] = 10'd0168;
explut_jt51[8'd200] = 10'd0164;
explut_jt51[8'd201] = 10'd0161;
explut_jt51[8'd202] = 10'd0158;
explut_jt51[8'd203] = 10'd0155;
explut_jt51[8'd204] = 10'd0152;
explut_jt51[8'd205] = 10'd0148;
explut_jt51[8'd206] = 10'd0145;
explut_jt51[8'd207] = 10'd0142;
explut_jt51[8'd208] = 10'd0139;
explut_jt51[8'd209] = 10'd0136;
explut_jt51[8'd210] = 10'd0133;
explut_jt51[8'd211] = 10'd0130;
explut_jt51[8'd212] = 10'd0126;
explut_jt51[8'd213] = 10'd0123;
explut_jt51[8'd214] = 10'd0120;
explut_jt51[8'd215] = 10'd0117;
explut_jt51[8'd216] = 10'd0114;
explut_jt51[8'd217] = 10'd0111;
explut_jt51[8'd218] = 10'd0108;
explut_jt51[8'd219] = 10'd0105;
explut_jt51[8'd220] = 10'd0102;
explut_jt51[8'd221] = 10'd0099;
explut_jt51[8'd222] = 10'd0096;
explut_jt51[8'd223] = 10'd0093;
explut_jt51[8'd224] = 10'd0090;
explut_jt51[8'd225] = 10'd0087;
explut_jt51[8'd226] = 10'd0084;
explut_jt51[8'd227] = 10'd0081;
explut_jt51[8'd228] = 10'd0078;
explut_jt51[8'd229] = 10'd0075;
explut_jt51[8'd230] = 10'd0072;
explut_jt51[8'd231] = 10'd0069;
explut_jt51[8'd232] = 10'd0066;
explut_jt51[8'd233] = 10'd0063;
explut_jt51[8'd234] = 10'd0060;
explut_jt51[8'd235] = 10'd0057;
explut_jt51[8'd236] = 10'd0054;
explut_jt51[8'd237] = 10'd0051;
explut_jt51[8'd238] = 10'd0048;
explut_jt51[8'd239] = 10'd0045;
explut_jt51[8'd240] = 10'd0042;
explut_jt51[8'd241] = 10'd0040;
explut_jt51[8'd242] = 10'd0037;
explut_jt51[8'd243] = 10'd0034;
explut_jt51[8'd244] = 10'd0031;
explut_jt51[8'd245] = 10'd0028;
explut_jt51[8'd246] = 10'd0025;
explut_jt51[8'd247] = 10'd0022;
explut_jt51[8'd248] = 10'd0020;
explut_jt51[8'd249] = 10'd0017;
explut_jt51[8'd250] = 10'd0014;
explut_jt51[8'd251] = 10'd0011;
explut_jt51[8'd252] = 10'd0008;
explut_jt51[8'd253] = 10'd0006;
explut_jt51[8'd254] = 10'd0003;
explut_jt51[8'd255] = 10'd0000;
end
always @ (posedge clk) if(cen)
exp <= explut_jt51[addr];
endmodule

80
common/Sound/ym3526/jtopl_lfo.v
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@@ -1,80 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-6-2020
*/
// Follows OPLL Reverse Engineering from Nuked
// https://github.com/nukeykt/Nuked-OPLL
// The AM logic renders a triangular waveform. The logic for it is rather
// obscure, but apparently that's how the original was done
module jtopl_lfo(
input wire rst,
input wire clk,
input wire cenop,
input wire [17:0] slot,
output wire [ 2:0] vib_cnt,
output reg [ 3:0] trem
);
parameter [6:0] LIM=7'd60;
reg [12:0] cnt;
reg am_inc, am_incen, am_dir, am_step;
reg [ 1:0] am_bit;
reg am_carry;
reg [ 8:0] am_cnt;
wire [12:0] next = cnt+1'b1;
assign vib_cnt = cnt[12:10];
always @(*) begin
am_inc = (slot[0] | am_dir ) & am_step & am_incen;
am_bit = {1'b0, am_cnt[0]} + {1'b0, am_inc} + {1'b0, am_carry & am_incen};
end
always @(posedge clk) begin
if( rst ) begin
cnt <= 13'd0;
am_incen <= 1;
am_dir <= 0;
am_carry <= 0;
am_cnt <= 9'd0;
am_step <= 0;
end else if( cenop ) begin
if( slot[17] ) begin
cnt <= next;
am_step <= &next[5:0];
am_incen <= 1;
end
else if(slot[8]) am_incen <= 0;
am_cnt <= { am_bit[0], am_cnt[8:1] };
am_carry <= am_bit[1];
if( slot[0] ) begin
if( am_dir && am_cnt[6:0]==7'd0 ) am_dir <= 0;
else
if( !am_dir && ( (am_cnt[6:0]&7'h69) == 7'h69) ) am_dir <= 1;
end
// output
if( slot[0] ) trem <= am_cnt[6:3];
end
end
endmodule

297
common/Sound/ym3526/jtopl_logsin.v
View File

@@ -1,297 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
//altera message_off 10030
module jtopl_logsin(
input wire clk,
input wire cen,
input wire [ 7:0] addr,
output reg [11:0] logsin
);
reg [11:0] sinelut[255:0];
initial begin
sinelut[8'd000] = 12'h000;
sinelut[8'd001] = 12'h000;
sinelut[8'd002] = 12'h000;
sinelut[8'd003] = 12'h000;
sinelut[8'd004] = 12'h000;
sinelut[8'd005] = 12'h000;
sinelut[8'd006] = 12'h000;
sinelut[8'd007] = 12'h000;
sinelut[8'd008] = 12'h001;
sinelut[8'd009] = 12'h001;
sinelut[8'd010] = 12'h001;
sinelut[8'd011] = 12'h001;
sinelut[8'd012] = 12'h001;
sinelut[8'd013] = 12'h001;
sinelut[8'd014] = 12'h001;
sinelut[8'd015] = 12'h002;
sinelut[8'd016] = 12'h002;
sinelut[8'd017] = 12'h002;
sinelut[8'd018] = 12'h002;
sinelut[8'd019] = 12'h003;
sinelut[8'd020] = 12'h003;
sinelut[8'd021] = 12'h003;
sinelut[8'd022] = 12'h004;
sinelut[8'd023] = 12'h004;
sinelut[8'd024] = 12'h004;
sinelut[8'd025] = 12'h005;
sinelut[8'd026] = 12'h005;
sinelut[8'd027] = 12'h005;
sinelut[8'd028] = 12'h006;
sinelut[8'd029] = 12'h006;
sinelut[8'd030] = 12'h007;
sinelut[8'd031] = 12'h007;
sinelut[8'd032] = 12'h007;
sinelut[8'd033] = 12'h008;
sinelut[8'd034] = 12'h008;
sinelut[8'd035] = 12'h009;
sinelut[8'd036] = 12'h009;
sinelut[8'd037] = 12'h00a;
sinelut[8'd038] = 12'h00a;
sinelut[8'd039] = 12'h00b;
sinelut[8'd040] = 12'h00c;
sinelut[8'd041] = 12'h00c;
sinelut[8'd042] = 12'h00d;
sinelut[8'd043] = 12'h00d;
sinelut[8'd044] = 12'h00e;
sinelut[8'd045] = 12'h00f;
sinelut[8'd046] = 12'h00f;
sinelut[8'd047] = 12'h010;
sinelut[8'd048] = 12'h011;
sinelut[8'd049] = 12'h011;
sinelut[8'd050] = 12'h012;
sinelut[8'd051] = 12'h013;
sinelut[8'd052] = 12'h014;
sinelut[8'd053] = 12'h014;
sinelut[8'd054] = 12'h015;
sinelut[8'd055] = 12'h016;
sinelut[8'd056] = 12'h017;
sinelut[8'd057] = 12'h017;
sinelut[8'd058] = 12'h018;
sinelut[8'd059] = 12'h019;
sinelut[8'd060] = 12'h01a;
sinelut[8'd061] = 12'h01b;
sinelut[8'd062] = 12'h01c;
sinelut[8'd063] = 12'h01d;
sinelut[8'd064] = 12'h01e;
sinelut[8'd065] = 12'h01f;
sinelut[8'd066] = 12'h020;
sinelut[8'd067] = 12'h021;
sinelut[8'd068] = 12'h022;
sinelut[8'd069] = 12'h023;
sinelut[8'd070] = 12'h024;
sinelut[8'd071] = 12'h025;
sinelut[8'd072] = 12'h026;
sinelut[8'd073] = 12'h027;
sinelut[8'd074] = 12'h028;
sinelut[8'd075] = 12'h029;
sinelut[8'd076] = 12'h02a;
sinelut[8'd077] = 12'h02b;
sinelut[8'd078] = 12'h02d;
sinelut[8'd079] = 12'h02e;
sinelut[8'd080] = 12'h02f;
sinelut[8'd081] = 12'h030;
sinelut[8'd082] = 12'h031;
sinelut[8'd083] = 12'h033;
sinelut[8'd084] = 12'h034;
sinelut[8'd085] = 12'h035;
sinelut[8'd086] = 12'h037;
sinelut[8'd087] = 12'h038;
sinelut[8'd088] = 12'h039;
sinelut[8'd089] = 12'h03b;
sinelut[8'd090] = 12'h03c;
sinelut[8'd091] = 12'h03e;
sinelut[8'd092] = 12'h03f;
sinelut[8'd093] = 12'h040;
sinelut[8'd094] = 12'h042;
sinelut[8'd095] = 12'h043;
sinelut[8'd096] = 12'h045;
sinelut[8'd097] = 12'h046;
sinelut[8'd098] = 12'h048;
sinelut[8'd099] = 12'h04a;
sinelut[8'd100] = 12'h04b;
sinelut[8'd101] = 12'h04d;
sinelut[8'd102] = 12'h04e;
sinelut[8'd103] = 12'h050;
sinelut[8'd104] = 12'h052;
sinelut[8'd105] = 12'h053;
sinelut[8'd106] = 12'h055;
sinelut[8'd107] = 12'h057;
sinelut[8'd108] = 12'h059;
sinelut[8'd109] = 12'h05b;
sinelut[8'd110] = 12'h05c;
sinelut[8'd111] = 12'h05e;
sinelut[8'd112] = 12'h060;
sinelut[8'd113] = 12'h062;
sinelut[8'd114] = 12'h064;
sinelut[8'd115] = 12'h066;
sinelut[8'd116] = 12'h068;
sinelut[8'd117] = 12'h06a;
sinelut[8'd118] = 12'h06c;
sinelut[8'd119] = 12'h06e;
sinelut[8'd120] = 12'h070;
sinelut[8'd121] = 12'h072;
sinelut[8'd122] = 12'h074;
sinelut[8'd123] = 12'h076;
sinelut[8'd124] = 12'h078;
sinelut[8'd125] = 12'h07a;
sinelut[8'd126] = 12'h07d;
sinelut[8'd127] = 12'h07f;
sinelut[8'd128] = 12'h081;
sinelut[8'd129] = 12'h083;
sinelut[8'd130] = 12'h086;
sinelut[8'd131] = 12'h088;
sinelut[8'd132] = 12'h08a;
sinelut[8'd133] = 12'h08d;
sinelut[8'd134] = 12'h08f;
sinelut[8'd135] = 12'h092;
sinelut[8'd136] = 12'h094;
sinelut[8'd137] = 12'h097;
sinelut[8'd138] = 12'h099;
sinelut[8'd139] = 12'h09c;
sinelut[8'd140] = 12'h09f;
sinelut[8'd141] = 12'h0a1;
sinelut[8'd142] = 12'h0a4;
sinelut[8'd143] = 12'h0a7;
sinelut[8'd144] = 12'h0a9;
sinelut[8'd145] = 12'h0ac;
sinelut[8'd146] = 12'h0af;
sinelut[8'd147] = 12'h0b2;
sinelut[8'd148] = 12'h0b5;
sinelut[8'd149] = 12'h0b8;
sinelut[8'd150] = 12'h0bb;
sinelut[8'd151] = 12'h0be;
sinelut[8'd152] = 12'h0c1;
sinelut[8'd153] = 12'h0c4;
sinelut[8'd154] = 12'h0c7;
sinelut[8'd155] = 12'h0ca;
sinelut[8'd156] = 12'h0cd;
sinelut[8'd157] = 12'h0d1;
sinelut[8'd158] = 12'h0d4;
sinelut[8'd159] = 12'h0d7;
sinelut[8'd160] = 12'h0db;
sinelut[8'd161] = 12'h0de;
sinelut[8'd162] = 12'h0e2;
sinelut[8'd163] = 12'h0e5;
sinelut[8'd164] = 12'h0e9;
sinelut[8'd165] = 12'h0ec;
sinelut[8'd166] = 12'h0f0;
sinelut[8'd167] = 12'h0f4;
sinelut[8'd168] = 12'h0f8;
sinelut[8'd169] = 12'h0fb;
sinelut[8'd170] = 12'h0ff;
sinelut[8'd171] = 12'h103;
sinelut[8'd172] = 12'h107;
sinelut[8'd173] = 12'h10b;
sinelut[8'd174] = 12'h10f;
sinelut[8'd175] = 12'h114;
sinelut[8'd176] = 12'h118;
sinelut[8'd177] = 12'h11c;
sinelut[8'd178] = 12'h121;
sinelut[8'd179] = 12'h125;
sinelut[8'd180] = 12'h129;
sinelut[8'd181] = 12'h12e;
sinelut[8'd182] = 12'h133;
sinelut[8'd183] = 12'h137;
sinelut[8'd184] = 12'h13c;
sinelut[8'd185] = 12'h141;
sinelut[8'd186] = 12'h146;
sinelut[8'd187] = 12'h14b;
sinelut[8'd188] = 12'h150;
sinelut[8'd189] = 12'h155;
sinelut[8'd190] = 12'h15b;
sinelut[8'd191] = 12'h160;
sinelut[8'd192] = 12'h166;
sinelut[8'd193] = 12'h16b;
sinelut[8'd194] = 12'h171;
sinelut[8'd195] = 12'h177;
sinelut[8'd196] = 12'h17c;
sinelut[8'd197] = 12'h182;
sinelut[8'd198] = 12'h188;
sinelut[8'd199] = 12'h18f;
sinelut[8'd200] = 12'h195;
sinelut[8'd201] = 12'h19b;
sinelut[8'd202] = 12'h1a2;
sinelut[8'd203] = 12'h1a9;
sinelut[8'd204] = 12'h1b0;
sinelut[8'd205] = 12'h1b7;
sinelut[8'd206] = 12'h1be;
sinelut[8'd207] = 12'h1c5;
sinelut[8'd208] = 12'h1cd;
sinelut[8'd209] = 12'h1d4;
sinelut[8'd210] = 12'h1dc;
sinelut[8'd211] = 12'h1e4;
sinelut[8'd212] = 12'h1ec;
sinelut[8'd213] = 12'h1f5;
sinelut[8'd214] = 12'h1fd;
sinelut[8'd215] = 12'h206;
sinelut[8'd216] = 12'h20f;
sinelut[8'd217] = 12'h218;
sinelut[8'd218] = 12'h222;
sinelut[8'd219] = 12'h22c;
sinelut[8'd220] = 12'h236;
sinelut[8'd221] = 12'h240;
sinelut[8'd222] = 12'h24b;
sinelut[8'd223] = 12'h256;
sinelut[8'd224] = 12'h261;
sinelut[8'd225] = 12'h26d;
sinelut[8'd226] = 12'h279;
sinelut[8'd227] = 12'h286;
sinelut[8'd228] = 12'h293;
sinelut[8'd229] = 12'h2a0;
sinelut[8'd230] = 12'h2af;
sinelut[8'd231] = 12'h2bd;
sinelut[8'd232] = 12'h2cd;
sinelut[8'd233] = 12'h2dc;
sinelut[8'd234] = 12'h2ed;
sinelut[8'd235] = 12'h2ff;
sinelut[8'd236] = 12'h311;
sinelut[8'd237] = 12'h324;
sinelut[8'd238] = 12'h339;
sinelut[8'd239] = 12'h34e;
sinelut[8'd240] = 12'h365;
sinelut[8'd241] = 12'h37e;
sinelut[8'd242] = 12'h398;
sinelut[8'd243] = 12'h3b5;
sinelut[8'd244] = 12'h3d3;
sinelut[8'd245] = 12'h3f5;
sinelut[8'd246] = 12'h41a;
sinelut[8'd247] = 12'h443;
sinelut[8'd248] = 12'h471;
sinelut[8'd249] = 12'h4a6;
sinelut[8'd250] = 12'h4e4;
sinelut[8'd251] = 12'h52e;
sinelut[8'd252] = 12'h58b;
sinelut[8'd253] = 12'h607;
sinelut[8'd254] = 12'h6c3;
sinelut[8'd255] = 12'h859;
end
always @ (posedge clk) if(cen) begin
logsin <= sinelut[addr];
end
endmodule

277
common/Sound/ym3526/jtopl_mmr.v
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@@ -1,277 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-6-2020
*/
module jtopl_mmr #(parameter OPL_TYPE=1)
(
input wire rst,
input wire clk,
input wire cen,
output wire cenop,
input wire [ 7:0] din,
input wire write,
input wire addr,
// location
output wire zero,
output wire [ 1:0] group,
output wire op,
output wire [17:0] slot,
output reg rhy_en,
// Timers
output reg [ 7:0] value_A,
output reg [ 7:0] value_B,
output reg load_A,
output reg load_B,
output reg flagen_A,
output reg flagen_B,
output reg clr_flag_A,
output reg clr_flag_B,
input wire flag_A,
input wire overflow_A,
// Phase Generator
output wire [ 9:0] fnum_I,
output wire [ 2:0] block_I,
output wire [ 3:0] mul_II,
output wire viben_I,
// Operator
output wire [ 1:0] wavsel_I,
// Envelope Generator
output wire keyon_I,
output wire en_sus_I, // enable sustain
output wire [ 3:0] arate_I, // attack rate
output wire [ 3:0] drate_I, // decay rate
output wire [ 3:0] rrate_I, // release rate
output wire [ 3:0] sl_I, // sustain level
output wire ks_II, // key scale
output wire [ 5:0] tl_IV,
output wire amen_IV,
// global values
output reg am_dep,
output reg vib_dep,
output wire [ 1:0] ksl_IV,
// Operator configuration
output wire [ 2:0] fb_I,
output wire con_I
);
//parameter OPL_TYPE=1;
jtopl_div #(OPL_TYPE) u_div (
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.cenop ( cenop )
);
localparam [7:0] REG_TESTYM = 8'h01,
REG_CLKA = 8'h02,
REG_CLKB = 8'h03,
REG_TIMER = 8'h04,
REG_CSM = 8'h08,
REG_RYTHM = 8'hBD;
reg [ 7:0] selreg; // selected register
reg [ 7:0] din_copy;
reg csm, effect;
reg [ 1:0] sel_group; // group to update
reg [ 2:0] sel_sub; // subslot to update
reg up_fnumlo, up_fnumhi, up_fbcon,
up_mult, up_ksl_tl, up_ar_dr, up_sl_rr,
up_wav;
reg wave_mode, // 1 if waveform selection is enabled (OPL2)
csm_en,
note_sel; // keyboard split, not implemented
reg [ 4:0] rhy_kon;
// this runs at clk speed, no clock gating here
// if I try to make this an async rst it fails to map it
// as flip flops but uses latches instead. So I keep it as sync. reset
always @(posedge clk) begin
if( rst ) begin
selreg <= 8'h0;
sel_group <= 2'd0;
sel_sub <= 3'd0;
// Updaters
up_fbcon <= 0;
up_fnumlo <= 0;
up_fnumhi <= 0;
up_mult <= 0;
up_ksl_tl <= 0;
up_ar_dr <= 0;
up_sl_rr <= 0;
up_wav <= 0;
// Rhythms
rhy_en <= 0;
rhy_kon <= 5'd0;
// sensitivity to LFO
am_dep <= 0;
vib_dep <= 0;
csm_en <= 0;
note_sel <= 0;
// OPL2 waveforms
wave_mode <= 0;
// timers
{ value_A, value_B } <= 16'd0;
{ clr_flag_B, clr_flag_A, load_B, load_A } <= 4'd0;
flagen_A <= 1;
flagen_B <= 1;
din_copy <= 8'd0;
end else begin
// WRITE IN REGISTERS
if( write ) begin
if( !addr ) begin
$display ("[[[ YM3526 ]]] READ_VALUE:%02h t=%0t", din , $realtime);
selreg <= din;
end else begin
// Global registers
din_copy <= din;
up_fnumhi <= 0;
up_fnumlo <= 0;
up_fbcon <= 0;
up_mult <= 0;
up_ksl_tl <= 0;
up_ar_dr <= 0;
up_sl_rr <= 0;
up_wav <= 0;
// General control (<0x20 registers)
casez( selreg )
REG_TESTYM: if(OPL_TYPE>1) wave_mode <= din[5];
REG_CLKA: begin value_A <= din; $display ("[[[ YM3526 ]]] REG_CLKA t=%0t" , $realtime); end
REG_CLKB: begin value_B <= din; $display ("[[[ YM3526 ]]] REG_CLKB t=%0t" , $realtime); end
REG_TIMER: begin
$display ("[[[ YM3526 ]]] REG_TIMER t=%0t" , $realtime);
clr_flag_A <= din[7];
clr_flag_B <= din[7];
if (~din[7]) begin
flagen_A <= ~din[6];
flagen_B <= ~din[5];
{ load_B, load_A } <= din[1:0];
end
end
REG_CSM: begin {csm_en, note_sel} <= din[7:6]; $display ("[[[ YM3526 ]]] REG_CSM t=%0t" , $realtime); end
default:;
endcase
// Operator registers
if( selreg >= 8'h20 &&
(selreg < 8'hA0 || (selreg>=8'hE0 && OPL_TYPE>1) ) &&
selreg[2:0]<=3'd5 && selreg[4:3]!=2'b11) begin
sel_group <= selreg[4:3];
sel_sub <= selreg[2:0];
$display ("[[[ YM3526 ]]] OPERATOR REGISTERS t=%0t" , $realtime);
case( selreg[7:5] )
3'b001: up_mult <= 1;
3'b010: up_ksl_tl <= 1;
3'b011: up_ar_dr <= 1;
3'b100: up_sl_rr <= 1;
3'b111: up_wav <= OPL_TYPE!=1;
default:;
endcase
end
// Channel registers
if( selreg[3:0]<=4'd8) begin
$display ("[[[ YM3526 ]]] CHANNEL REGISTERS t=%0t", $realtime);
case( selreg[7:4] )
4'hA: up_fnumlo <= 1;
4'hB: up_fnumhi <= 1;
4'hC: up_fbcon <= 1;
default:;
endcase
end
if( selreg[7:4]>=4'hA && selreg[7:4]<4'hd
&& selreg[3:0]<=8 ) begin
$display ("[[[ YM3526 ]]] SEL_GROUP,SUB REGISTERS t=%0t", $realtime);
sel_group <= selreg[3:0] < 4'd3 ? 2'd0 :
( selreg[3:0] < 4'd6 ? 2'd1 :
( selreg[3:0] < 4'd9 ? 2'd2 : 2'd3) );
sel_sub <= selreg[3:0] < 4'd6 ? selreg[2:0] :
{ 1'b0, ~&selreg[2:1], selreg[0] };
end
// Global register
if( selreg==REG_RYTHM ) begin
$display ("[[[ YM3526 ]]] REG_RYTHM t=%0t" , $realtime);
am_dep <= din[7];
vib_dep <= din[6];
rhy_en <= din[5];
rhy_kon <= din[4:0];
end
end
end
else if(cenop) begin /* clear once-only bits */
{ clr_flag_B, clr_flag_A } <= 2'd0;
end
end
end
jtopl_reg #(.OPL_TYPE(OPL_TYPE)) u_reg(
.rst ( rst ),
.clk ( clk ),
.cen ( cenop ),
.din ( din_copy ),
.write ( write ),
// Pipeline order
.zero ( zero ),
.group ( group ),
.op ( op ),
.slot ( slot ),
.sel_group ( sel_group ), // group to update
.sel_sub ( sel_sub ), // subslot to update
.rhy_en ( rhy_en ),
.rhy_kon ( rhy_kon ),
//input csm,
//input flag_A,
//input overflow_A,
.up_fbcon ( up_fbcon ),
.up_fnumlo ( up_fnumlo ),
.up_fnumhi ( up_fnumhi ),
.up_mult ( up_mult ),
.up_ksl_tl ( up_ksl_tl ),
.up_ar_dr ( up_ar_dr ),
.up_sl_rr ( up_sl_rr ),
.up_wav ( up_wav ),
// PG
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.mul_II ( mul_II ),
.viben_I ( viben_I ),
// OP
.wavsel_I ( wavsel_I ),
.wave_mode ( wave_mode ),
// EG
.keyon_I ( keyon_I ),
.en_sus_I ( en_sus_I ),
.arate_I ( arate_I ),
.drate_I ( drate_I ),
.rrate_I ( rrate_I ),
.sl_I ( sl_I ),
.ks_II ( ks_II ),
.ksl_IV ( ksl_IV ),
.amen_IV ( amen_IV ),
.tl_IV ( tl_IV ),
// Timbre - Neiro
.fb_I ( fb_I ),
.con_I ( con_I )
);
endmodule

47
common/Sound/ym3526/jtopl_noise.v
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@@ -1,47 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 24-6-2020
*/
module jtopl_noise(
input wire rst, // rst should be at least 6 clk&cen cycles long
input wire clk, // CPU clock
input wire cen, // optional clock enable, it not needed leave as 1'b1
output wire noise
);
reg [22:0] no;
reg nbit;
assign noise = no[0];
always @(*) begin
nbit = no[0] ^ no[14];
nbit = nbit | (no==23'd0);
end
always @(posedge clk, posedge rst) begin
if( rst )
no <= 23'd1<<22;
else if(cen) begin
no <= { nbit, no[22:1] };
end
end
endmodule

263
common/Sound/ym3526/jtopl_op.v
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@@ -1,263 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 19-6-2020
*/
module jtopl_op #(parameter OPL_TYPE=1)
(
input wire rst,
input wire clk,
input wire cenop,
// these signals need be delayed
input wire [1:0] group,
input wire op, // 0 for modulator operators
input wire con_I,
input wire [2:0] fb_I, // voice feedback
input wire zero,
input wire [9:0] pg_phase_I,
input wire [1:0] wavsel_I,
input wire [9:0] eg_atten_II, // output from envelope generator
output reg signed [12:0] op_result,
output wire op_out,
output wire con_out
);
//parameter OPL_TYPE=1;
localparam OPW=13, // Operator Width
PW=OPW*2; // Previous data Width
reg [11:0] level_II;
reg signbit_II, signbit_III;
reg nullify_II;
wire [ 8:0] ctrl_in, ctrl_dly;
wire [ 1:0] group_d;
wire op_d, con_I_d;
wire [ 1:0] wavsel_d;
wire [ 2:0] fb_I_d;
reg [PW-1:0] prev, prev0_din, prev1_din, prev2_din;
wire [PW-1:0] prev0, prev1, prev2;
assign ctrl_in = { wavsel_I, group, op, con_I, fb_I };
assign { wavsel_d, group_d, op_d, con_I_d, fb_I_d } = ctrl_dly;
jtopl_sh #( .width(9), .stages(3)) u_delay(
.clk ( clk ),
.cen ( cenop ),
.din ( ctrl_in ),
.drop ( ctrl_dly )
);
jtopl_sh #( .width(2), .stages(3)) u_condly(
.clk ( clk ),
.cen ( cenop ),
.din ( {op_d, con_I_d} ),
.drop ( {op_out, con_out} )
);
always @(*) begin
prev0_din = op_d && group_d==2'd0 ? { prev0[OPW-1:0], op_result } : prev0;
prev1_din = op_d && group_d==2'd1 ? { prev1[OPW-1:0], op_result } : prev1;
prev2_din = op_d && group_d==2'd2 ? { prev2[OPW-1:0], op_result } : prev2;
case( group_d )
default: prev = prev0;
2'd1: prev = prev1;
2'd2: prev = prev2;
endcase
end
jtopl_sh #( .width(PW), .stages(3)) u_csr0(
.clk ( clk ),
.cen ( cenop ),
.din ( prev0_din ),
.drop ( prev0 )
);
jtopl_sh #( .width(PW), .stages(3)) u_csr1(
.clk ( clk ),
.cen ( cenop ),
.din ( prev1_din ),
.drop ( prev1 )
);
jtopl_sh #( .width(PW), .stages(3)) u_csr2(
.clk ( clk ),
.cen ( cenop ),
.din ( prev2_din ),
.drop ( prev2 )
);
reg [ 10:0] subtresult;
reg [OPW-1:0] shifter;
wire signed [OPW-1:0] fb1 = prev[PW-1:OPW];
wire signed [OPW-1:0] fb0 = prev[OPW-1:0];
// REGISTER/CYCLE 1
// Creation of phase modulation (FM) feedback signal, before shifting
reg signed [OPW-1:0] modmux_I;
reg signed [OPW-1:0] fbmod_I;
always @(*) begin
modmux_I = op_d ? op_result : fb1+fb0;
// OPL-L shifts by 8-FB
// OPL3 shifts by 9-FB
// OPLL seems to use lower resolution for OPW so it makes
// sense that it shifts by one fewer
fbmod_I = modmux_I>>>(4'd9-{1'b0,fb_I_d});
end
reg signed [9:0] phasemod_I;
always @(*) begin
// Shift FM feedback signal
if (op_d)
phasemod_I = con_I_d ? 10'd0 : modmux_I[9:0];
else
phasemod_I = fb_I_d==3'd0 ? 10'd0 : fbmod_I[9:0];
end
reg [ 9:0] phase;
reg [ 7:0] aux_I;
always @(*) begin
phase = phasemod_I + pg_phase_I;
aux_I = phase[7:0] ^ {8{~phase[8]}};
end
// REGISTER/CYCLE 1
always @(posedge clk) if( cenop ) begin
if( OPL_TYPE==1 ) begin
signbit_II <= phase[9];
nullify_II <= 0;
end else begin
signbit_II <= wavsel_d==0 && phase[9];
nullify_II <= (wavsel_d==2'b01 && phase[9]) || (wavsel_d==2'b11 && phase[8]);
end
end
wire [11:0] logsin_II;
jtopl_logsin u_logsin (
.clk ( clk ),
.cen ( cenop ),
.addr ( aux_I[7:0] ),
.logsin ( logsin_II )
);
// REGISTER/CYCLE 2
// Sine table
// Main sine table body
always @(*) begin
subtresult = eg_atten_II + logsin_II[11:2];
level_II = { subtresult[9:0], logsin_II[1:0] } | {12{subtresult[10]}};
if( nullify_II ) begin
level_II = ~12'h0;
end
end
wire [9:0] mantissa_III;
reg [3:0] exponent_III;
jtopl_exprom u_exprom(
.clk ( clk ),
.cen ( cenop ),
.addr ( level_II[7:0] ),
.exp ( mantissa_III )
);
always @(posedge clk) if( cenop ) begin
exponent_III <= level_II[11:8];
signbit_III <= signbit_II;
end
// REGISTER/CYCLE 3
// 2's complement & Carry-out discarded
always @(*) begin
// Floating-point to integer, and incorporating sign bit
shifter = { 2'b01, mantissa_III,1'b0 } >> exponent_III;
end
// It looks like OPLL and OPL3 don't do full 2's complement but just bit inversion
always @(posedge clk) if( cenop ) begin
op_result <= ( shifter ^ {OPW{signbit_III}});// + {13'd0,signbit_III};
end
`ifdef SIMULATION
reg signed [OPW-1:0] op_sep0_0;
reg signed [OPW-1:0] op_sep1_0;
reg signed [OPW-1:0] op_sep2_0;
reg signed [OPW-1:0] op_sep0_1;
reg signed [OPW-1:0] op_sep1_1;
reg signed [OPW-1:0] op_sep2_1;
reg signed [OPW-1:0] op_sep4_0;
reg signed [OPW-1:0] op_sep5_0;
reg signed [OPW-1:0] op_sep6_0;
reg signed [OPW-1:0] op_sep4_1;
reg signed [OPW-1:0] op_sep5_1;
reg signed [OPW-1:0] op_sep6_1;
reg signed [OPW-1:0] op_sep7_0;
reg signed [OPW-1:0] op_sep8_0;
reg signed [OPW-1:0] op_sep9_0;
reg signed [OPW-1:0] op_sep7_1;
reg signed [OPW-1:0] op_sep8_1;
reg signed [OPW-1:0] op_sep9_1;
reg [ 4:0] sepcnt;
always @(posedge clk) if(cenop) begin
sepcnt <= zero ? 5'd0 : sepcnt+5'd1;
case( (sepcnt+3)%18 )
0: op_sep0_0 <= op_result;
1: op_sep1_0 <= op_result;
2: op_sep2_0 <= op_result;
3: op_sep0_1 <= op_result;
4: op_sep1_1 <= op_result;
5: op_sep2_1 <= op_result;
6: op_sep4_0 <= op_result;
7: op_sep5_0 <= op_result;
8: op_sep6_0 <= op_result;
9: op_sep4_1 <= op_result;
10: op_sep5_1 <= op_result;
11: op_sep6_1 <= op_result;
12: op_sep7_0 <= op_result;
13: op_sep8_0 <= op_result;
14: op_sep9_0 <= op_result;
15: op_sep7_1 <= op_result;
16: op_sep8_1 <= op_result;
17: op_sep9_1 <= op_result;
endcase
end
`endif
endmodule

129
common/Sound/ym3526/jtopl_pg.v
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/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_pg(
input wire rst,
input wire clk,
input wire cenop,
input wire [17:0] slot,
input wire rhy_en,
// Channel frequency
input wire [ 9:0] fnum_I,
input wire [ 2:0] block_I,
// Operator multiplying
input wire [ 3:0] mul_II,
// phase modulation from LFO (vibrato at 6.4Hz)
input wire [ 2:0] vib_cnt,
input wire vib_dep,
input wire viben_I,
// phase operation
input wire pg_rst_II,
output reg [ 3:0] keycode_II,
output wire [ 9:0] phase_IV
);
parameter CH=9;
wire [ 3:0] keycode_I;
wire [16:0] phinc_I;
reg [16:0] phinc_II;
wire [18:0] phase_drop, phase_in;
wire [ 9:0] phase_II;
wire noise;
reg [ 9:0] hh, tc;
reg rm_xor;
wire hh_en, sd_en, tc_en;
always @(posedge clk) if(cenop) begin
keycode_II <= keycode_I;
phinc_II <= phinc_I;
end
// Rhythm phase
always @(posedge clk, posedge rst) begin
if( rst ) begin
hh <= 10'd0;
tc <= 10'd0;
end else begin
if( slot[13] ) hh <= phase_drop[18:9];
if( slot[17] ) tc <= phase_drop[18:9];
rm_xor <= (hh[2]^hh[7]) | (hh[3]^tc[5]) | (tc[3]^tc[5]);
end
end
assign hh_en = rhy_en & slot[14]; // 13+1
assign sd_en = rhy_en & slot[17]; // 16+1
assign tc_en = rhy_en & slot[ 0]; // (17+1)%18
jtopl_noise u_noise(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.noise ( noise )
);
jtopl_pg_comb u_comb(
.block ( block_I ),
.fnum ( fnum_I ),
// Phase Modulation
.vib_cnt ( vib_cnt ),
.vib_dep ( vib_dep ),
.viben ( viben_I ),
.keycode ( keycode_I ),
// Phase increment
.phinc_out ( phinc_I ),
// Phase add
.mul ( mul_II ),
.phase_in ( phase_drop ),
.pg_rst ( pg_rst_II ),
.phinc_in ( phinc_II ),
// Rhythm
.hh_en ( hh_en ),
.sd_en ( sd_en ),
.tc_en ( tc_en ),
.rm_xor ( rm_xor ),
.noise ( noise ),
.hh ( hh ),
.phase_out ( phase_in ),
.phase_op ( phase_II )
);
jtopl_sh_rst #( .width(19), .stages(2*CH) ) u_phsh(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( phase_in ),
.drop ( phase_drop)
);
jtopl_sh_rst #( .width(10), .stages(2) ) u_pad(
.clk ( clk ),
.cen ( cenop ),
.rst ( rst ),
.din ( phase_II ),
.drop ( phase_IV )
);
endmodule

95
common/Sound/ym3526/jtopl_pg_comb.v
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@@ -1,95 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_pg_comb (
input wire [ 2:0] block,
input wire [ 9:0] fnum,
// Phase Modulation
input wire [ 2:0] vib_cnt,
input wire vib_dep,
input wire viben,
output wire [ 3:0] keycode,
// Phase increment
output wire [16:0] phinc_out,
// Phase add
input wire [ 3:0] mul,
input wire [18:0] phase_in,
input wire pg_rst,
// input signed [7:0] pm_in,
input wire [16:0] phinc_in,
// Rhythm
input wire noise,
input wire [ 9:0] hh,
input wire hh_en,
input wire tc_en,
input wire sd_en,
input wire rm_xor,
output wire [18:0] phase_out,
output wire [ 9:0] phase_op
);
wire signed [3:0] pm_offset;
wire [9:0] phase_pre;
assign keycode = { block, fnum[9] };
/* pm and pg_inc operate in parallel */
jtopl_pm u_pm(
.vib_cnt ( vib_cnt ),
.fnum ( fnum ),
.vib_dep ( vib_dep ),
.viben ( viben ),
.pm_offset ( pm_offset )
);
jtopl_pg_inc u_inc(
.block ( block ),
.fnum ( fnum ),
.pm_offset ( pm_offset ),
.phinc_pure ( phinc_out )
);
// pg_sum uses the output from the previous blocks
jtopl_pg_sum u_sum(
.mul ( mul ),
.phase_in ( phase_in ),
.pg_rst ( pg_rst ),
.phinc_pure ( phinc_in ),
.phase_out ( phase_out ),
.phase_op ( phase_pre )
);
jtopl_pg_rhy u_rhy(
.phase_pre ( phase_pre ),
// Rhythm
.noise ( noise ),
.hh ( hh ),
.hh_en ( hh_en ),
.tc_en ( tc_en ),
.sd_en ( sd_en ),
.rm_xor ( rm_xor ),
.phase_op ( phase_op )
);
endmodule // jtopl_pg_comb

38
common/Sound/ym3526/jtopl_pg_inc.v
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@@ -1,38 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_pg_inc (
input wire [ 2:0] block,
input wire [ 9:0] fnum,
input wire signed [ 3:0] pm_offset,
output reg [16:0] phinc_pure
);
reg [16:0] freq;
always @(*) begin
freq = { 7'd0, fnum } + { {13{pm_offset[3]}}, pm_offset };
// Add PM here
freq = freq << block;
phinc_pure = freq >> 1;
end
endmodule // jtopl_pg_inc

49
common/Sound/ym3526/jtopl_pg_rhy.v
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@@ -1,49 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 25-6-2020
*/
module jtopl_pg_rhy (
input wire [ 9:0] phase_pre,
// Rhythm
input wire noise,
input wire [ 9:0] hh,
input wire hh_en,
input wire tc_en,
input wire sd_en,
input wire rm_xor,
output reg [ 9:0] phase_op
);
always @(*) begin
if( hh_en ) begin
phase_op = {rm_xor, 9'd0 };
if( rm_xor ^ noise )
phase_op = phase_op | 10'hd0;
else
phase_op = phase_op | 10'h34;
end else if( sd_en ) begin
phase_op = { hh[8], hh[8]^noise, 8'd0 };
end else if( tc_en ) begin
phase_op = { rm_xor, 9'h80 };
end else
phase_op = phase_pre;
end
endmodule // jtopl_pg_sum

52
common/Sound/ym3526/jtopl_pg_sum.v
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@@ -1,52 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
// Original hardware uses an adder to do the multiplication
// but I think it will take less resources of the FPGA to
// use a real multiplier instead
module jtopl_pg_sum (
input wire [ 3:0] mul,
input wire [18:0] phase_in,
input wire pg_rst,
input wire [16:0] phinc_pure,
output reg [18:0] phase_out,
output reg [ 9:0] phase_op
);
reg [21:0] phinc_mul;
reg [ 4:0] factor[0:15];
always @(*) begin
phinc_mul = { 5'b0, phinc_pure} * factor[mul];
phase_out = pg_rst ? 'd0 : (phase_in + phinc_mul[19:1]);
phase_op = phase_out[18:9];
end
initial begin
factor[ 0] = 5'd01; factor[ 1] = 5'd02; factor[ 2] = 5'd04; factor[ 3] = 5'd06;
factor[ 4] = 5'd08; factor[ 5] = 5'd10; factor[ 6] = 5'd12; factor[ 7] = 5'd14;
factor[ 8] = 5'd16; factor[ 9] = 5'd18; factor[10] = 5'd20; factor[11] = 5'd20;
factor[12] = 5'd24; factor[13] = 5'd24; factor[14] = 5'd30; factor[15] = 5'd30;
end
endmodule // jtopl_pg_sum

47
common/Sound/ym3526/jtopl_pm.v
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@@ -1,47 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-6-2020
*/
// Based on Nuked's work on OPLL and OPL3
module jtopl_pm (
input wire [ 2:0] vib_cnt,
input wire [ 9:0] fnum,
input wire vib_dep,
input wire viben,
output reg [ 3:0] pm_offset
);
reg [2:0] range;
always @(*) begin
if( vib_cnt[1:0]==2'b00 )
range = 3'd0;
else begin
range = fnum[9:7]>>vib_cnt[0];
if(!vib_dep) range = range>>1;
end
if( vib_cnt[2] )
pm_offset = ~{1'b0, range } + 4'd1;
else
pm_offset = {1'b0, range };
if(!viben) pm_offset = 4'd0;
end
endmodule

270
common/Sound/ym3526/jtopl_reg.v
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@@ -1,270 +0,0 @@
/* This file is part of JTOPL
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
module jtopl_reg #(parameter OPL_TYPE=1)
(
input wire rst,
input wire clk,
input wire cen,
input wire [7:0] din,
input wire write,
// Pipeline order
output wire zero,
output reg [1:0] group,
output reg op, // 0 for modulator operators
output reg [17:0] slot, // hot one encoding of active slot
input wire [1:0] sel_group, // group to update
input wire [2:0] sel_sub, // subslot to update
input wire rhy_en, // rhythm enable
input wire [4:0] rhy_kon, // key-on for each rhythm instrument
//input csm,
//input flag_A,
//input overflow_A,
input wire up_fbcon,
input wire up_fnumlo,
input wire up_fnumhi,
input wire up_mult,
input wire up_ksl_tl,
input wire up_ar_dr,
input wire up_sl_rr,
input wire up_wav,
// PG
output wire [9:0] fnum_I,
output wire [2:0] block_I,
// channel configuration
output wire [2:0] fb_I,
output wire [3:0] mul_II, // frequency multiplier
output wire [1:0] ksl_IV, // key shift level
output wire amen_IV,
output wire viben_I,
// OP
output wire [1:0] wavsel_I,
input wire wave_mode,
// EG
output wire keyon_I,
output wire [5:0] tl_IV,
output wire en_sus_I, // enable sustain
output wire [3:0] arate_I, // attack rate
output wire [3:0] drate_I, // decay rate
output wire [3:0] rrate_I, // release rate
output wire [3:0] sl_I, // sustain level
output wire ks_II, // key scale
output wire con_I
);
//parameter OPL_TYPE=1;
localparam CH=9;
// Each group contains three channels
// and each subslot contains six operators
reg [2:0] subslot;
reg [5:0] rhy_csr;
reg rhy_oen;
`ifdef SIMULATION
// These signals need to operate during rst
// initial state is not relevant (or critical) in real life
// but we need a clear value during simulation
initial begin
group = 2'd0;
subslot = 3'd0;
slot = 18'd1;
end
`endif
wire match = { group, subslot } == { sel_group, sel_sub};
wire [2:0] next_sub = subslot==3'd5 ? 3'd0 : (subslot+3'd1);
wire [1:0] next_group = subslot==3'd5 ? (group==2'b10 ? 2'b00 : group+2'b1) : group;
// channel data
wire [2:0] fb_in = din[3:1];
wire con_in = din[0];
wire up_fnumlo_ch = up_fnumlo & match,
up_fnumhi_ch = up_fnumhi & match,
up_fbcon_ch = up_fbcon & match,
update_op_I = !write && sel_group == group && sel_sub == subslot;
reg update_op_II, update_op_III, update_op_IV;
assign zero = slot[0];
always @(posedge clk) begin : up_counter
if( cen ) begin
{ group, subslot } <= { next_group, next_sub };
if( { next_group, next_sub }==5'd0 ) begin
slot <= 18'd1;
end else begin
slot <= { slot[16:0], 1'b0 };
end
op <= next_sub >= 3'd3;
end
end
always @(posedge clk) begin
if(write) begin
update_op_II <= 0;
update_op_III <= 0;
update_op_IV <= 0;
end else if( cen ) begin
update_op_II <= update_op_I;
update_op_III <= update_op_II;
update_op_IV <= update_op_III;
end
end
localparam OPCFGW = 4*8 + (OPL_TYPE!=1 ? 2 : 0);
wire [OPCFGW-1:0] shift_out;
wire en_sus;
// Sustained is disabled in rhythm mode for channels in group 2 (i.e. 6,7,8)
assign en_sus_I = rhy_oen ? 1'b0 : en_sus;
jtopl_csr #(.LEN(CH*2),.W(OPCFGW)) u_csr(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( din ),
.shift_out ( shift_out ),
.up_mult ( up_mult ),
.up_ksl_tl ( up_ksl_tl ),
.up_ar_dr ( up_ar_dr ),
.up_sl_rr ( up_sl_rr ),
.up_wav ( up_wav ),
.update_op_I ( update_op_I ),
.update_op_II ( update_op_II ),
.update_op_IV ( update_op_IV )
);
assign { amen_IV, viben_I, en_sus, ks_II, mul_II,
ksl_IV, tl_IV,
arate_I, drate_I,
sl_I, rrate_I } = shift_out[4*8-1:0];
generate
if( OPL_TYPE==1 )
assign wavsel_I = 0;
else
assign wavsel_I = shift_out[OPCFGW-1:OPCFGW-2] & {2{wave_mode}};
endgenerate
// Memory for CH registers
localparam KONW = 1,
FNUMW = 10,
BLOCKW = 3,
FBW = 3,
CONW = 1;
localparam CHCSRW = KONW+FNUMW+BLOCKW+FBW+CONW;
wire [CHCSRW-1:0] chcfg0_out, chcfg1_out, chcfg2_out;
reg [CHCSRW-1:0] chcfg, chcfg0_in, chcfg1_in, chcfg2_in;
wire [CHCSRW-1:0] chcfg_inmux;
wire keyon_csr, con_csr;
wire disable_con;
assign chcfg_inmux = {
up_fnumhi_ch ? din[5:0] : { keyon_csr, block_I, fnum_I[9:8] },
up_fnumlo_ch ? din : fnum_I[7:0],
up_fbcon_ch ? { fb_in, con_in } : { fb_I, con_csr }
};
assign disable_con = rhy_oen && !slot[12] && !slot[13];
assign con_I = !rhy_en || !disable_con ? con_csr : 1'b1;
always @(*) begin
case( group )
default: chcfg = chcfg0_out;
2'd1: chcfg = chcfg1_out;
2'd2: chcfg = chcfg2_out;
endcase
chcfg0_in = group==2'b00 ? chcfg_inmux : chcfg0_out;
chcfg1_in = group==2'b01 ? chcfg_inmux : chcfg1_out;
chcfg2_in = group==2'b10 ? chcfg_inmux : chcfg2_out;
end
`ifdef SIMULATION
reg [CHCSRW-1:0] chsnap0, chsnap1,chsnap2;
always @(posedge clk) if(zero) begin
chsnap0 <= chcfg0_out;
chsnap1 <= chcfg1_out;
chsnap2 <= chcfg2_out;
end
`endif
assign { keyon_csr, block_I, fnum_I, fb_I, con_csr } = chcfg;
// Rhythm key-on CSR
localparam BD=4, SD=3, TOM=2, TC=1, HH=0;
always @(posedge clk, posedge rst) begin
if( rst ) begin
rhy_csr <= 6'd0;
rhy_oen <= 0;
end else if(cen) begin
if(slot[11]) rhy_oen <= rhy_en;
if(slot[17]) begin
rhy_csr <= { rhy_kon[BD], rhy_kon[HH], rhy_kon[TOM],
rhy_kon[BD], rhy_kon[SD], rhy_kon[TC] };
rhy_oen <= 0;
end else
rhy_csr <= { rhy_csr[4:0], rhy_csr[5] };
end
end
assign keyon_I = rhy_oen ? rhy_csr[5] : keyon_csr;
jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group0(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( chcfg0_in ),
.drop ( chcfg0_out )
);
jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group1(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( chcfg1_in ),
.drop ( chcfg1_out )
);
jtopl_sh_rst #(.width(CHCSRW),.stages(3)) u_group2(
.clk ( clk ),
.cen ( cen ),
.rst ( rst ),
.din ( chcfg2_in ),
.drop ( chcfg2_out )
);
endmodule

42
common/Sound/ym3526/jtopl_sh.v
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@@ -1,42 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 19-6-2020
*/
// stages must be greater than 2
module jtopl_sh #(parameter width=5, stages=24 )
(
input wire clk,
input wire cen,
input wire [width-1:0] din,
output wire [width-1:0] drop
);
reg [stages-1:0] bits[width-1:0];
genvar i;
generate
for (i=0; i < width; i=i+1) begin: bit_shifter
always @(posedge clk) if(cen) begin
bits[i] <= {bits[i][stages-2:0], din[i]};
end
assign drop[i] = bits[i][stages-1];
end
endgenerate
endmodule

54
common/Sound/ym3526/jtopl_sh_rst.v
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@@ -1,54 +0,0 @@
/* This file is part of JTOPL.
JTOPL is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 13-6-2020
*/
// stages must be greater than 2
module jtopl_sh_rst #(parameter width=5, stages=18, rstval=1'b0 )
(
input wire rst,
input wire clk,
input wire cen,
input wire [width-1:0] din,
output wire [width-1:0] drop
);
reg [stages-1:0] bits[width-1:0];
genvar i;
integer k;
generate
initial
for (k=0; k < width; k=k+1) begin
bits[k] = { stages{rstval}};
end
endgenerate
generate
for (i=0; i < width; i=i+1) begin: bit_shifter
always @(posedge clk, posedge rst)
if( rst ) begin
bits[i] <= {stages{rstval}};
end else if(cen) begin
bits[i] <= {bits[i][stages-2:0], din[i]};
end
assign drop[i] = bits[i][stages-1];
end
endgenerate
endmodule

61
common/Sound/ym3526/jtopl_single_acc.v
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@@ -1,61 +0,0 @@
/* This file is part of JTOPL.
JTOPL program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTOPL program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 20-6-2020
*/
// Accumulates an arbitrary number of inputs with saturation
// restart the sum when input "zero" is high
module jtopl_single_acc #(parameter
INW=13, // input data width
OUTW=16 // output data width
)(
input wire clk,
input wire cenop,
input wire [INW-1:0] op_result,
input wire sum_en,
input wire zero,
output reg [OUTW-1:0] snd
);
// for full resolution use INW=14, OUTW=16
// for cut down resolution use INW=9, OUTW=12
// OUTW-INW should be > 0
reg signed [OUTW-1:0] next, acc, current;
reg overflow;
wire [OUTW-1:0] plus_inf = { 1'b0, {(OUTW-1){1'b1}} }; // maximum positive value
wire [OUTW-1:0] minus_inf = { 1'b1, {(OUTW-1){1'b0}} }; // minimum negative value
always @(*) begin
current = sum_en ? { {(OUTW-INW){op_result[INW-1]}}, op_result } : {OUTW{1'b0}};
next = zero ? current : current + acc;
overflow = !zero &&
(current[OUTW-1] == acc[OUTW-1]) &&
(acc[OUTW-1]!=next[OUTW-1]);
end
always @(posedge clk) if( cenop ) begin
acc <= overflow ? (acc[OUTW-1] ? minus_inf : plus_inf) : next;
if(zero) snd <= acc;
end
endmodule

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