mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-28 09:07:40 +00:00
Update BluePrint add Games
This commit is contained in:
Marcel
@@ -18,7 +18,7 @@
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 13:46:56 February 19, 2026
|
||||
# Date created = 02:58:09 February 23, 2026
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
|
||||
@@ -41,13 +41,6 @@ set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [ge
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
|
||||
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
|
||||
|
||||
# SDRAM delays
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
|
||||
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
|
||||
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
|
||||
|
||||
|
||||
set_multicycle_path -to {VGA_*[*]} -setup 2
|
||||
set_multicycle_path -to {VGA_*[*]} -hold 1
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
<manufacturer>Zilec Electronics / Bally Midway</manufacturer>
|
||||
<category>Maze</category>
|
||||
|
||||
<setname>blueprnt</setname>
|
||||
<setname>blueprntj</setname>
|
||||
<parent>blueprnt</parent>
|
||||
<mameversion>0220</mameversion>
|
||||
<rbf>BluePrint</rbf>
|
||||
@@ -25,7 +25,7 @@
|
||||
<joystick>4-way</joystick>
|
||||
<special_controls></special_controls>
|
||||
<num_buttons>1</num_buttons>
|
||||
<button_names></button_names>
|
||||
<button_names>Run</button_names>
|
||||
|
||||
<switches default="00,00">
|
||||
<!-- DIP Switch 1 -->
|
||||
@@ -44,9 +44,12 @@
|
||||
<part crc="c34981bb" name="bp-3j.1p"/>
|
||||
<part crc="525e77b5" name="bp-4j.1r"/>
|
||||
<part crc="431a015f" name="bp-5j.1s"/>
|
||||
<part repeat="0x1000">FF</part> // BluePrint Doesn't Use 6th Rom Slot
|
||||
<!-- Tile ROMs (2× 4KB = 8KB) -->
|
||||
<part crc="43718c34" name="bg-1j.3c"/>
|
||||
<part crc="d3ce077d" name="bg-2j.3d"/>
|
||||
<part crc="43718c34" name="bg-1j.3c" length="0x800"/>
|
||||
<part repeat="0x800">FF</part>
|
||||
<part crc="d3ce077d" name="bg-2j.3d" length="0x800"/>
|
||||
<part repeat="0x800">FF</part>
|
||||
<!-- Sprite ROMs (3× 4KB = 12KB, R/B/G bitplanes) -->
|
||||
<part crc="83da108f" name="redj.17d"/>
|
||||
<part crc="b440f32f" name="bluej.18d"/>
|
||||
@@ -57,6 +60,16 @@
|
||||
<part crc="fd38777a" name="snd-1.3u"/>
|
||||
<part crc="33d5bf5b" name="snd-2.3v"/>
|
||||
</rom>
|
||||
<rom index="2"></rom>
|
||||
<rom index="3" md5="none">
|
||||
<part>
|
||||
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
|
||||
00 00 01 00 00 40 00 00
|
||||
</part>
|
||||
</rom>
|
||||
<rom index="4"></rom>
|
||||
|
||||
<nvram index="4" size="40"></nvram>
|
||||
|
||||
<remark></remark>
|
||||
<mratimestamp>20260213000000</mratimestamp>
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
<joystick>4-way</joystick>
|
||||
<special_controls></special_controls>
|
||||
<num_buttons>1</num_buttons>
|
||||
<button_names></button_names>
|
||||
<button_names>Run</button_names>
|
||||
|
||||
<switches default="00,00">
|
||||
<!-- DIP Switch 1 -->
|
||||
@@ -44,6 +44,7 @@
|
||||
<part crc="6866ca07" name="bp-3.1p"/>
|
||||
<part crc="5d3cfac3" name="bp-4.1r"/>
|
||||
<part crc="a556cac4" name="bp-5.1s"/>
|
||||
<part repeat="0x1000">FF</part> // BluePrint Doesn't Use 6th Rom Slot
|
||||
<!-- Tile ROMs (2× 4KB = 8KB) -->
|
||||
<part crc="ac2a61bc" name="bg-1.3c"/>
|
||||
<part crc="81fe85d7" name="bg-2.3d"/>
|
||||
@@ -57,6 +58,16 @@
|
||||
<part crc="fd38777a" name="snd-1.3u"/>
|
||||
<part crc="33d5bf5b" name="snd-2.3v"/>
|
||||
</rom>
|
||||
<rom index="2"></rom>
|
||||
<rom index="3" md5="none">
|
||||
<part>
|
||||
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
|
||||
00 00 01 00 00 40 00 00
|
||||
</part>
|
||||
</rom>
|
||||
<rom index="4"></rom>
|
||||
|
||||
<nvram index="4" size="40"></nvram>
|
||||
|
||||
<remark></remark>
|
||||
<mratimestamp>20260213000000</mratimestamp>
|
||||
|
||||
67
Arcade_MiST/Zilec BluePrint/meta/Grasspin (Jaleco).mra
Normal file
67
Arcade_MiST/Zilec BluePrint/meta/Grasspin (Jaleco).mra
Normal file
@@ -0,0 +1,67 @@
|
||||
<misterromdescription>
|
||||
<name>Grasspin (Zilec)</name>
|
||||
<region>World</region>
|
||||
<homebrew>no</homebrew>
|
||||
<bootleg>no</bootleg>
|
||||
<version></version>
|
||||
<alternative></alternative>
|
||||
<platform></platform>
|
||||
<series></series>
|
||||
<year>1983</year>
|
||||
<manufacturer>Zilec Electronics / Jaleco</manufacturer>
|
||||
<category>Maze</category>
|
||||
<setname>grasspin</setname>
|
||||
<parent>grasspin</parent>
|
||||
<mameversion>0220</mameversion>
|
||||
<rbf>BluePrint</rbf>
|
||||
<about></about>
|
||||
<resolution>15kHz</resolution>
|
||||
<rotation>vertical (ccw)</rotation>
|
||||
<flip>no</flip>
|
||||
<players>2 (alternating)</players>
|
||||
<joystick>8-way</joystick>
|
||||
<special_controls></special_controls>
|
||||
<num_buttons>2</num_buttons>
|
||||
<button_names>Fire</button_names>
|
||||
<switches default="60,03">
|
||||
<!-- DIP Switch 1 -->
|
||||
<dip bits="5,6" name="Coinage" ids="2c/1cr,1c/2cr,1c/1cr,2c/3cr"/>
|
||||
<dip bits="7" name="Freeze" ids="Off,On"/>
|
||||
<!-- DIP Switch 2 -->
|
||||
<dip bits="8,9" name="Lives" ids="2,5,4,3"/>
|
||||
<dip bits="13" name="Cabinet" ids="Upright,Cocktail"/>
|
||||
<dip bits="14" name="Freeze (Flip Screen)" ids="Off,On"/>
|
||||
</switches>
|
||||
<rom index="0" md5="none" zip="blueprnt.zip|grasspin.zip">
|
||||
<!-- Main CPU ROMs (5x 4KB = 20KB) -->
|
||||
<part crc="6fd50509" name="prom_1.4b"/>
|
||||
<part crc="cd319007" name="jaleco-2.4c"/>
|
||||
<part crc="ac73ccc2" name="jaleco-3.4d"/>
|
||||
<part crc="41f6279d" name="jaleco-4.4f"/>
|
||||
<part crc="d20aead9" name="jaleco-5.4h"/>
|
||||
<part repeat="0x1000">FF</part> // Grasspin Doesn't Use 6th Rom Slot
|
||||
<!-- Tile ROMs (2x 2KB, padded to 4KB each) -->
|
||||
<part crc="bccca24c" name="jaleco-9.4p"/>
|
||||
<part crc="9d6185ca" name="jaleco-8.3p"/>
|
||||
<!-- Sprite ROMs (3x 4KB = 12KB, R/B/G bitplanes) -->
|
||||
<part crc="3a0765c6" name="jaleco-10.5p"/>
|
||||
<part crc="cccfbeb4" name="jaleco-11.6p"/>
|
||||
<part crc="615b3299" name="jaleco-12.7p"/>
|
||||
</rom>
|
||||
<rom index="1" md5="none" zip="blueprnt.zip|grasspin.zip">
|
||||
<!-- Sound CPU ROMs (2x 4KB = 8KB) -->
|
||||
<part crc="f58bf3b0" name="jaleco-6.4j"/>
|
||||
<part crc="2d587653" name="jaleco-7.4l"/>
|
||||
</rom>
|
||||
<rom index="2"></rom>
|
||||
<rom index="3" md5="none">
|
||||
<part>
|
||||
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
|
||||
00 00 07 00 00 50 50 FD
|
||||
</part>
|
||||
</rom>
|
||||
<rom index="4"></rom>
|
||||
<nvram index="4" size="50"></nvram>
|
||||
<remark></remark>
|
||||
<mratimestamp>20260221000000</mratimestamp>
|
||||
</misterromdescription>
|
||||
73
Arcade_MiST/Zilec BluePrint/meta/Saturn (Zilec).mra
Normal file
73
Arcade_MiST/Zilec BluePrint/meta/Saturn (Zilec).mra
Normal file
@@ -0,0 +1,73 @@
|
||||
<misterromdescription>
|
||||
<n>Saturn (Zilec)</n>
|
||||
<region>World</region>
|
||||
<homebrew>no</homebrew>
|
||||
<bootleg>no</bootleg>
|
||||
<version></version>
|
||||
<alternative></alternative>
|
||||
<platform></platform>
|
||||
<series></series>
|
||||
<year>1983</year>
|
||||
<manufacturer>Zilec Electronics / Jaleco</manufacturer>
|
||||
<category>Maze</category>
|
||||
|
||||
<setname>saturn</setname>
|
||||
<parent>blueprnt</parent>
|
||||
<mameversion>0220</mameversion>
|
||||
<rbf>BluePrint</rbf>
|
||||
<about></about>
|
||||
|
||||
<resolution>15kHz</resolution>
|
||||
<rotation>vertical (ccw)</rotation>
|
||||
<flip>no</flip>
|
||||
|
||||
<players>2 (alternating)</players>
|
||||
<joystick>4-way</joystick>
|
||||
<special_controls></special_controls>
|
||||
<num_buttons>2</num_buttons>
|
||||
<button_names>Fire,Double Fire</button_names>
|
||||
|
||||
<switches default="00,00">
|
||||
<!-- DIP Switch 1 -->
|
||||
<dip bits="1" name="Cabinet" ids="Upright,Cocktail"/>
|
||||
<dip bits="6,7" name="Lives" ids="3,4,5,6"/>
|
||||
<!-- DIP Switch 2 -->
|
||||
<dip bits="9" name="Coinage" ids="A 1/1 B 1/6,A 2/1 B 1/3"/>
|
||||
<dip bits="10" name="Demo Sounds" ids="Off,On"/>
|
||||
</switches>
|
||||
|
||||
<rom index="0" md5="none" zip="blueprnt.zip|saturnzi.zip">
|
||||
<!-- Main CPU ROMs (6× 4KB = 24KB) -->
|
||||
<part crc="18a6d68e" name="r1"/>
|
||||
<part crc="a7dd2665" name="r2"/>
|
||||
<part crc="b9cfa791" name="r3"/>
|
||||
<part crc="c5a997e7" name="r4"/>
|
||||
<part crc="43444d00" name="r5"/>
|
||||
<part crc="4d4821f6" name="r6"/>
|
||||
<!-- Tile ROMs (2× 4KB = 8KB) -->
|
||||
<part crc="35987d61" name="r10"/>
|
||||
<part crc="ca6a7fda" name="r9"/>
|
||||
<!-- Sprite ROMs (3× 4KB = 12KB, R/B/G bitplanes) -->
|
||||
<part crc="6e4e6e5d" name="r11"/>
|
||||
<part crc="46fc049e" name="r12"/>
|
||||
<part crc="8b3e8c32" name="r13"/>
|
||||
</rom>
|
||||
<rom index="1" md5="none" zip="blueprnt.zip|saturnzi.zip">
|
||||
<!-- Sound CPU ROMs (2× 4KB = 8KB) -->
|
||||
<part crc="dd43e02f" name="r7"/>
|
||||
<part crc="7f9d0877" name="r8"/>
|
||||
</rom>
|
||||
<rom index="2"></rom>
|
||||
<rom index="3" md5="none">
|
||||
<part>
|
||||
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
|
||||
00 00 03 80 00 28 00 2D
|
||||
</part>
|
||||
</rom>
|
||||
<rom index="4"></rom>
|
||||
|
||||
<nvram index="4" size="28"></nvram>
|
||||
|
||||
<remark></remark>
|
||||
<mratimestamp>20260213000000</mratimestamp>
|
||||
</misterromdescription>
|
||||
@@ -100,16 +100,15 @@ wire [4:0] r, g, b;
|
||||
wire [ 3:0] hoffset, voffset;
|
||||
assign { voffset, hoffset } = status[31:24];
|
||||
|
||||
wire [7:0] p1_controls = {m_down, m_up, m_right, m_left, m_fireA, m_fireB, m_one_player, m_coin1};
|
||||
wire [7:0] p2_controls = {m_down2, m_up2, m_right2, m_left2, m_fire2A, m_fire2B, m_two_players, m_coin2};
|
||||
|
||||
// DIP SWITCHES
|
||||
reg [7:0] dip_sw[8]; // Active-LOW
|
||||
always @(posedge clk_sys) begin
|
||||
if(ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3])
|
||||
dip_sw[ioctl_addr[2:0]] <= ioctl_dout;
|
||||
end
|
||||
|
||||
wire [7:0] p1_controls = {m_down, m_up, m_right, m_left, m_fireA, 1'b0, m_one_player, m_coin1};
|
||||
wire [7:0] p2_controls = {m_down2, m_up2, m_right2, m_left2, m_fire2A, 1'b0, m_two_players, m_coin2};
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
|
||||
@@ -49,7 +49,7 @@ module BluePrint_CPU
|
||||
input [3:0] h_center, v_center,
|
||||
|
||||
// ROM loading
|
||||
input main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i,
|
||||
input main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i, main6_cs_i,
|
||||
input tile0_cs_i, tile1_cs_i,
|
||||
input spr_r_cs_i, spr_b_cs_i, spr_g_cs_i,
|
||||
input [24:0] ioctl_addr,
|
||||
@@ -99,30 +99,32 @@ assign ce_pix = cen_5m;
|
||||
|
||||
// H counter 0-319, V counter 0-263
|
||||
// From MAME: set_raw(5MHz, 320, 0, 256, 264, 16, 240)
|
||||
reg [8:0] h_cnt = 9'd0;
|
||||
reg [8:0] base_h_cnt = 9'd0;
|
||||
reg [8:0] v_cnt = 9'd0;
|
||||
always_ff @(posedge clk_49m) begin
|
||||
if (cen_5m) begin
|
||||
if (h_cnt == 9'd319) begin
|
||||
h_cnt <= 9'd0;
|
||||
if (base_h_cnt == 9'd319) begin
|
||||
base_h_cnt <= 9'd0;
|
||||
v_cnt <= (v_cnt == 9'd263) ? 9'd0 : v_cnt + 9'd1;
|
||||
end else
|
||||
h_cnt <= h_cnt + 9'd1;
|
||||
base_h_cnt <= base_h_cnt + 9'd1;
|
||||
end
|
||||
end
|
||||
|
||||
wire [8:0] h_cnt = (base_h_cnt <= 9'd248) ? base_h_cnt : 9'd248;
|
||||
|
||||
// Blanking
|
||||
wire hblk = (h_cnt >= 9'd256);
|
||||
wire hblk = (base_h_cnt >= 9'd256);
|
||||
wire vblk = (v_cnt < 9'd16) | (v_cnt >= 9'd240);
|
||||
assign video_hblank = hblk;
|
||||
assign video_vblank = vblk;
|
||||
|
||||
// Sync generation with screen centering offsets
|
||||
wire [8:0] hs_start = 9'd280 + {5'd0, h_center};
|
||||
wire [8:0] hs_start = 9'd280 + {5'd0, h_center}; // Was 9'd280 + {5'd0, h_center};
|
||||
wire [8:0] hs_end = hs_start + 9'd32;
|
||||
wire [8:0] vs_start = 9'd248 + {5'd0, v_center};
|
||||
wire [8:0] vs_end = vs_start + 9'd4;
|
||||
assign video_hsync = (h_cnt >= hs_start && h_cnt < hs_end);
|
||||
assign video_hsync = (base_h_cnt >= hs_start && base_h_cnt < hs_end);
|
||||
assign video_vsync = (v_cnt >= vs_start && v_cnt < vs_end);
|
||||
assign video_csync = ~(video_hsync ^ video_vsync);
|
||||
|
||||
@@ -186,12 +188,13 @@ wire cs_cram = mem_valid & (z80_A[15:12] == 4'hF); // 0xF000-0x
|
||||
//------------------------------------------------------------ ROMs ------------------------------------------------------------//
|
||||
|
||||
// Main program ROMs (5x 4KB)
|
||||
wire [7:0] rom1_D, rom2_D, rom3_D, rom4_D, rom5_D;
|
||||
wire [7:0] rom1_D, rom2_D, rom3_D, rom4_D, rom5_D, rom6_D;
|
||||
eprom_4k main_rom1(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main1_cs_i), .WR(ioctl_wr), .DATA(rom1_D));
|
||||
eprom_4k main_rom2(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main2_cs_i), .WR(ioctl_wr), .DATA(rom2_D));
|
||||
eprom_4k main_rom3(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main3_cs_i), .WR(ioctl_wr), .DATA(rom3_D));
|
||||
eprom_4k main_rom4(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main4_cs_i), .WR(ioctl_wr), .DATA(rom4_D));
|
||||
eprom_4k main_rom5(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main5_cs_i), .WR(ioctl_wr), .DATA(rom5_D));
|
||||
eprom_4k main_rom6(.CLK(clk_49m), .ADDR(z80_A[11:0]), .CLK_DL(clk_49m), .ADDR_DL(ioctl_addr), .DATA_IN(ioctl_data), .CS_DL(main6_cs_i), .WR(ioctl_wr), .DATA(rom6_D));
|
||||
|
||||
// ROM data mux based on address
|
||||
wire [7:0] rom_D = (z80_A[14:12] == 3'd0) ? rom1_D :
|
||||
@@ -199,6 +202,7 @@ wire [7:0] rom_D = (z80_A[14:12] == 3'd0) ? rom1_D :
|
||||
(z80_A[14:12] == 3'd2) ? rom3_D :
|
||||
(z80_A[14:12] == 3'd3) ? rom4_D :
|
||||
(z80_A[14:12] == 3'd4) ? rom5_D :
|
||||
(z80_A[14:12] == 3'd4) ? rom6_D :
|
||||
8'hFF;
|
||||
|
||||
// Tile ROMs (2x 4KB) — addressed by rendering pipeline
|
||||
@@ -476,11 +480,11 @@ reg spr_flipy; // flipY for current sprite (from previous sprite'
|
||||
reg prev_sprite_flipy; // Carry flipY forward
|
||||
reg [7:0] spr_rom_r_lat, spr_rom_b_lat, spr_rom_g_lat;
|
||||
reg [2:0] spr_pix_cnt;
|
||||
reg [7:0] spr_clear_addr;
|
||||
|
||||
reg [7:0] next_scanline; // v_cnt of the line being prepared
|
||||
|
||||
localparam SPR_IDLE = 4'd0;
|
||||
localparam SPR_CLEAR = 4'd1;
|
||||
|
||||
localparam SPR_INIT_RD = 4'd2;
|
||||
localparam SPR_INIT_LAT = 4'd3;
|
||||
localparam SPR_RD_B0 = 4'd4;
|
||||
@@ -498,28 +502,15 @@ always_ff @(posedge clk_49m) begin
|
||||
spr_state <= SPR_IDLE;
|
||||
spr_idx <= 6'd0;
|
||||
prev_sprite_flipy <= 1'b0;
|
||||
spr_clear_addr <= 8'd0;
|
||||
end else begin
|
||||
case (spr_state)
|
||||
|
||||
SPR_IDLE: begin
|
||||
if (cen_5m && h_cnt == 9'd256) begin
|
||||
if (cen_5m && base_h_cnt == 9'd256) begin
|
||||
next_scanline <= v_cnt[7:0] + 8'd1;
|
||||
spr_clear_addr <= 8'd0;
|
||||
spr_state <= SPR_CLEAR;
|
||||
end
|
||||
end
|
||||
|
||||
SPR_CLEAR: begin
|
||||
if (~linebuf_sel)
|
||||
linebuf1[spr_clear_addr] <= 3'd0;
|
||||
else
|
||||
linebuf0[spr_clear_addr] <= 3'd0;
|
||||
if (spr_clear_addr == 8'd255) begin
|
||||
sprite_scan_addr <= 8'hFE; // sprite 63, byte 2
|
||||
sprite_scan_addr <= 8'hFE;
|
||||
spr_state <= SPR_INIT_RD;
|
||||
end else
|
||||
spr_clear_addr <= spr_clear_addr + 8'd1;
|
||||
end
|
||||
end
|
||||
|
||||
SPR_INIT_RD: begin
|
||||
@@ -580,7 +571,6 @@ always_ff @(posedge clk_49m) begin
|
||||
end
|
||||
|
||||
SPR_ROMWAIT: begin
|
||||
// ROM data valid this cycle; latch all three planes
|
||||
spr_state <= SPR_ROMWAIT2;
|
||||
end
|
||||
|
||||
@@ -588,8 +578,6 @@ always_ff @(posedge clk_49m) begin
|
||||
spr_rom_r_lat <= spr_r_D;
|
||||
spr_rom_b_lat <= spr_b_D;
|
||||
spr_rom_g_lat <= spr_g_D;
|
||||
spr_pix_cnt <= 3'd0;
|
||||
spr_state <= SPR_PIXELS;
|
||||
spr_pix_cnt <= 3'd0;
|
||||
spr_state <= SPR_PIXELS;
|
||||
end
|
||||
@@ -602,7 +590,7 @@ always_ff @(posedge clk_49m) begin
|
||||
// flipX: bit0 first (pixel 0 = LSB); normal: bit7 first (pixel 0 = MSB)
|
||||
bit_pos = spr_byte2[6] ? spr_pix_cnt : (3'd7 - spr_pix_cnt);
|
||||
pixel_val = {spr_rom_g_lat[bit_pos], spr_rom_b_lat[bit_pos], spr_rom_r_lat[bit_pos]};
|
||||
x_pos = spr_byte3 + {5'd0, spr_pix_cnt} + 8'd2;
|
||||
x_pos = spr_byte3 + {5'd0, spr_pix_cnt} + 8'd0; // + 8'd2
|
||||
if (pixel_val != 3'd0) begin
|
||||
if (~linebuf_sel)
|
||||
linebuf1[x_pos] <= pixel_val;
|
||||
@@ -631,9 +619,21 @@ always_ff @(posedge clk_49m) begin
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//--- Sprite pixel readout ---
|
||||
|
||||
wire [2:0] sprite_pixel = linebuf_sel ? linebuf1[h_cnt[7:0]] : linebuf0[h_cnt[7:0]];
|
||||
//wire [2:0] sprite_pixel = linebuf_sel ? linebuf1[h_cnt[7:0]] : linebuf0[h_cnt[7:0]];
|
||||
wire [2:0] sprite_pixel = linebuf_sel ? linebuf1[h_cnt[7:0] - 8'd3] : linebuf0[h_cnt[7:0] - 8'd3];
|
||||
// Clear display buffer as we read (becomes write buffer next line)
|
||||
always_ff @(posedge clk_49m) begin
|
||||
if (cen_5m && visible_line) begin
|
||||
if (linebuf_sel)
|
||||
linebuf1[h_cnt[7:0] - 8'd3] <= 3'd0;
|
||||
else
|
||||
linebuf0[h_cnt[7:0] - 8'd3] <= 3'd0;
|
||||
end
|
||||
end
|
||||
|
||||
wire sprite_transparent = (sprite_pixel == 3'b000);
|
||||
|
||||
// Sprite pixel bits: bit0=R, bit1=B, bit2=G (full brightness only)
|
||||
|
||||
@@ -72,7 +72,7 @@ wire [7:0] dipsw_readback_from_snd;
|
||||
wire [7:0] dipsw_readback = dipsw_readback_from_snd;
|
||||
|
||||
// ROM loader signals for MISTer (loads ROMs from SD card)
|
||||
wire main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i;
|
||||
wire main1_cs_i, main2_cs_i, main3_cs_i, main4_cs_i, main5_cs_i, main6_cs_i;
|
||||
wire tile0_cs_i, tile1_cs_i;
|
||||
wire spr_r_cs_i, spr_b_cs_i, spr_g_cs_i;
|
||||
|
||||
@@ -93,6 +93,7 @@ selector DLSEL
|
||||
.main3_cs(main3_cs_i),
|
||||
.main4_cs(main4_cs_i),
|
||||
.main5_cs(main5_cs_i),
|
||||
.main6_cs(main6_cs_i),
|
||||
.tile0_cs(tile0_cs_i),
|
||||
.tile1_cs(tile1_cs_i),
|
||||
.spr_r_cs(spr_r_cs_i),
|
||||
@@ -131,6 +132,7 @@ BluePrint_CPU main_pcb
|
||||
.main3_cs_i(main3_cs_i),
|
||||
.main4_cs_i(main4_cs_i),
|
||||
.main5_cs_i(main5_cs_i),
|
||||
.main6_cs_i(main6_cs_i),
|
||||
.tile0_cs_i(tile0_cs_i),
|
||||
.tile1_cs_i(tile1_cs_i),
|
||||
.spr_r_cs_i(spr_r_cs_i),
|
||||
|
||||
@@ -29,22 +29,24 @@
|
||||
// 0x2000 - 0x2FFF = main_rom3 (bp-3.1p)
|
||||
// 0x3000 - 0x3FFF = main_rom4 (bp-4.1r)
|
||||
// 0x4000 - 0x4FFF = main_rom5 (bp-5.1s)
|
||||
// 0x5000 - 0x5FFF = tile_rom0 (bg-1.3c)
|
||||
// 0x6000 - 0x6FFF = tile_rom1 (bg-2.3d)
|
||||
// 0x7000 - 0x7FFF = spr_rom_r (red.17d)
|
||||
// 0x8000 - 0x8FFF = spr_rom_b (blue.18d)
|
||||
// 0x9000 - 0x9FFF = spr_rom_g (green.20d)
|
||||
// 0x4000 - 0x5FFF = main_rom6 (bp-5.1s)
|
||||
|
||||
// 0x6000 - 0x6FFF = tile_rom0 (bg-1.3c)
|
||||
// 0x7000 - 0x7FFF = tile_rom1 (bg-2.3d)
|
||||
// 0x8000 - 0x8FFF = spr_rom_r (red.17d)
|
||||
// 0x9000 - 0x9FFF = spr_rom_b (blue.18d)
|
||||
// 0xA000 - 0xAFFF = spr_rom_g (green.20d)
|
||||
// Sound board ROMs loaded separately via index 1
|
||||
|
||||
module selector
|
||||
(
|
||||
input logic [24:0] ioctl_addr,
|
||||
output logic main1_cs, main2_cs, main3_cs, main4_cs, main5_cs,
|
||||
output logic main1_cs, main2_cs, main3_cs, main4_cs, main5_cs, main6_cs,
|
||||
output logic tile0_cs, tile1_cs,
|
||||
output logic spr_r_cs, spr_b_cs, spr_g_cs
|
||||
);
|
||||
always_comb begin
|
||||
{main1_cs, main2_cs, main3_cs, main4_cs, main5_cs,
|
||||
{main1_cs, main2_cs, main3_cs, main4_cs, main5_cs, main6_cs,
|
||||
tile0_cs, tile1_cs, spr_r_cs, spr_b_cs, spr_g_cs} = 0;
|
||||
|
||||
if(ioctl_addr < 'h1000) main1_cs = 1;
|
||||
@@ -52,11 +54,13 @@ module selector
|
||||
else if(ioctl_addr < 'h3000) main3_cs = 1;
|
||||
else if(ioctl_addr < 'h4000) main4_cs = 1;
|
||||
else if(ioctl_addr < 'h5000) main5_cs = 1;
|
||||
else if(ioctl_addr < 'h6000) tile0_cs = 1;
|
||||
else if(ioctl_addr < 'h7000) tile1_cs = 1;
|
||||
else if(ioctl_addr < 'h8000) spr_r_cs = 1;
|
||||
else if(ioctl_addr < 'h9000) spr_b_cs = 1;
|
||||
else if(ioctl_addr < 'hA000) spr_g_cs = 1;
|
||||
else if(ioctl_addr < 'h6000) main6_cs = 1;
|
||||
|
||||
else if(ioctl_addr < 'h7000) tile0_cs = 1;
|
||||
else if(ioctl_addr < 'h8000) tile1_cs = 1;
|
||||
else if(ioctl_addr < 'h9000) spr_r_cs = 1;
|
||||
else if(ioctl_addr < 'hA000) spr_b_cs = 1;
|
||||
else if(ioctl_addr < 'hB000) spr_g_cs = 1;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
Reference in New Issue
Block a user