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New Arcade

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Gehstock
2018-09-13 22:33:52 +02:00
parent b0c3b931ac
commit a46177d639
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37
Arcade_MiST/Atari-Hardware/Dominos_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del /s c5_pin_model_dump.txt
del /s PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

30
Arcade_MiST/Atari-Hardware/Dominos_MiST/dominos.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 19:51:47 November 12, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "19:51:47 November 12, 2017"
# Revisions
PROJECT_REVISION = "dominos"

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Arcade_MiST/Atari-Hardware/Dominos_MiST/dominos.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 21:02:30 September 12, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# dominos_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16 OCTOBER 10, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY dominos_mist
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------------
# start ENTITY(dominos_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(dominos_mist)
# ------------------------
set_global_assignment -name SDC_FILE dominos.sdc
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dominos_mist.sv
set_global_assignment -name VHDL_FILE rtl/dominos.vhd
set_global_assignment -name VHDL_FILE rtl/dominos_sound.vhd
set_global_assignment -name VHDL_FILE rtl/playfield.vhd
set_global_assignment -name VHDL_FILE rtl/Inputs.vhd
set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd
set_global_assignment -name VHDL_FILE rtl/sync.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
set_global_assignment -name VHDL_FILE rtl/oscillator.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

456
Arcade_MiST/Atari-Hardware/Dominos_MiST/dominos.sdc Normal file
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## Generated SDC file "dominos.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
## DATE "Wed Sep 12 21:23:53 2018"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {CLOCK_27} -period 37.037 -waveform { 0.000 18.518 } [get_ports {CLOCK_27}]
create_clock -name {dominos:dominos|synchronizer:Vid_sync|h_counter[4]} -period 1.000 -waveform { 0.000 0.500 } [get_registers {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}]
create_clock -name {dominos:dominos|synchronizer:Vid_sync|h_counter[6]} -period 1.000 -waveform { 0.000 0.500 } [get_registers {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}]
create_clock -name {SPI_SCK} -period 1.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
create_clock -name {dominos:dominos|synchronizer:Vid_sync|hsync_int} -period 1.000 -waveform { 0.000 0.500 } [get_registers {dominos:dominos|synchronizer:Vid_sync|hsync_int}]
create_clock -name {dominos:dominos|synchronizer:Vid_sync|h_counter[0]} -period 1.000 -waveform { 0.000 0.500 } [get_registers {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}]
create_clock -name {dominos:dominos|CPU_mem:CPU|Q5} -period 1.000 -waveform { 0.000 0.500 } [get_registers {dominos:dominos|CPU_mem:CPU|Q5}]
create_clock -name {dominos:dominos|synchronizer:Vid_sync|v_counter[7]} -period 1.000 -waveform { 0.000 0.500 } [get_registers {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}]
create_clock -name {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk} -period 1.000 -waveform { 0.000 0.500 } [get_registers {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 112 -divide_by 125 -master_clock {CLOCK_27} [get_pins {pll|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 56 -divide_by 125 -master_clock {CLOCK_27} [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {pll|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 28 -divide_by 125 -master_clock {CLOCK_27} [get_pins {pll|altpll_component|auto_generated|pll1|clk[2]}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] 0.010
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] 0.010
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLOCK_27}] 0.010
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLOCK_27}] 0.010
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {CLOCK_27}] -rise_to [get_clocks {SPI_SCK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {CLOCK_27}] -rise_to [get_clocks {SPI_SCK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {CLOCK_27}] -fall_to [get_clocks {SPI_SCK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {CLOCK_27}] -fall_to [get_clocks {SPI_SCK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {CLOCK_27}] -rise_to [get_clocks {SPI_SCK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {CLOCK_27}] -rise_to [get_clocks {SPI_SCK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {CLOCK_27}] -fall_to [get_clocks {SPI_SCK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {CLOCK_27}] -fall_to [get_clocks {SPI_SCK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {CLOCK_27}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {CLOCK_27}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {SPI_SCK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {SPI_SCK}] 0.020
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.030
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.030
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.030
set_clock_uncertainty -rise_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.030
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {CLOCK_27}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {CLOCK_27}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {SPI_SCK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {SPI_SCK}] 0.020
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.030
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.030
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.030
set_clock_uncertainty -fall_from [get_clocks {SPI_SCK}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.030
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.010
set_clock_uncertainty -rise_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.010
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.010
set_clock_uncertainty -fall_from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 0.010
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|hsync_int}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.010
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.010
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.010
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.010
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] 0.010
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] 0.010
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {CLOCK_27}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {CLOCK_27}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] 0.010
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|audio:Sound|Oscillator:Tone_pulse|Osc_Clk}] 0.010
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -rise_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[6]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|v_counter[7]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|synchronizer:Vid_sync|h_counter[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -rise_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
set_clock_uncertainty -fall_from [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] -fall_to [get_clocks {dominos:dominos|CPU_mem:CPU|Q5}] 0.020
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_SS3}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[3]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[4]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_B[5]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[3]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[4]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_G[5]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_HS}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[0]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[1]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[2]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[3]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[4]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_R[5]}]
set_output_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {VGA_VS}]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

11
Arcade_MiST/Atari-Hardware/Dominos_MiST/dominos.srf Normal file
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@@ -0,0 +1,11 @@
{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13004 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 113007 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 113015 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}

BIN
Arcade_MiST/Atari-Hardware/Dominos_MiST/release/dominos.rbf Normal file
View File

Binary file not shown.

142
Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/Inputs.vhd Normal file
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@@ -0,0 +1,142 @@
-- Input block for Atari Dominos
-- 2018 James Sweet
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity control_inputs is
port(
SW1 : in std_logic_vector(7 downto 0); -- DIP switches
Coin1_n : in std_logic; -- Coin switches
Coin2_n : in std_logic;
Start1 : in std_logic; -- 1 and 2 player start switches
Start2 : in std_logic;
Left1 : in std_logic; -- Gas pedals, these are simple on/off switches
Up1 : in std_logic;
Right1 : in std_logic; -- Player 1 and 2 gear select levers
Down1 : in std_logic;
Left2 : in std_logic;
Right2 : in std_logic;
Up2 : in std_logic;
Down2 : in std_logic;
Self_Test : in std_logic; -- Self test switch
Adr : in std_logic_vector(9 downto 0); -- Adress bus, only the lower 9 bits used by IO circuitry
Inputs : out std_logic_vector(1 downto 0) -- Out to data bus, only upper two bits used
);
end control_inputs;
architecture rtl of control_inputs is
signal A8_8 : std_logic;
signal F9_Q_n : std_logic;
signal H9_Q_n : std_logic;
signal H8_en : std_logic;
signal Coin1 : std_logic;
signal Coin2 : std_logic;
signal SW1_bank1 : std_logic;
signal SW1_bank2 : std_logic;
signal DipSW : std_logic_vector(7 downto 0);
signal E8_in : std_logic_vector(3 downto 0);
signal J9_out : std_logic_vector(7 downto 0);
signal E8_out : std_logic_vector(9 downto 0);
begin
-- Inputs
M8: process(Adr, A8_8, SW1_bank2, Coin2_n, Coin1_n)
begin
case Adr(7 downto 6) is
when "00" => Inputs <= A8_8 & SW1_bank2; -- There is actually an inverter N9 fed by A8_8 so we will just account for that
when "01" => Inputs <= Coin2_n & Coin1_n;
when others => Inputs <= "11";
end case;
end process;
-- Inputs are active-high in real hardware, using inverted output of demux
F9: process(Adr, Up1, Down1, Left1, Right1)
begin
if Adr(5) = '0' then -- Adr(5) is connected to enable
case Adr(2 downto 0) is
when "000" => F9_Q_n <= not Up1;
when "001" => F9_Q_n <= not Right1;
when "010" => F9_Q_n <= not Down1;
when "011" => F9_Q_n <= not Left1;
when others => F9_Q_n <= '1';
end case;
else
F9_Q_n <= '1';
end if;
end process;
H9: process(Adr, Up2, Down2, Right2, Left2, Self_Test, Start1, Start2)
begin
if Adr(4) = '0' then -- Adr(4) is connected to enable
case Adr(2 downto 0) is
when "000" => H9_Q_n <= not Up2;
when "001" => H9_Q_n <= not Right2;
when "010" => H9_Q_n <= not Down2;
when "011" => H9_Q_n <= not Left2;
when "100" => H9_Q_n <= not Start2;
when "101" => H9_Q_n <= not Start1;
when "110" => H9_Q_n <= not Self_Test;
when others => H9_Q_n <= '1';
end case;
else
H9_Q_n <= '1';
end if;
end process;
-- The way the dip switches are wired in the real hardware requires OR logic
-- to achieve the same result while using standard active-low switch inputs.
-- Switches are split into two banks, each bank fed from half of selector J9.
J9: process(Adr)
begin
if Adr(3) = '1' then
J9_out <= "11111111";
else
case Adr(1 downto 0) is
when "00" => J9_out <= "11101110";
when "01" => J9_out <= "11011101";
when "10" => J9_out <= "10111011";
when "11" => J9_out <= "01110111";
end case;
end if;
end process;
-- Re-order the dip switch signals to match the physical order of the switches
-- Bank 1
DipSW(7) <= J9_out(7) or SW1(1);
DipSW(6) <= J9_out(6) or SW1(3);
DipSW(5) <= J9_out(5) or SW1(5);
DipSW(4) <= J9_out(4) or SW1(7);
--Bank 2
DipSW(3) <= J9_out(3) or SW1(0);
DipSW(2) <= J9_out(2) or SW1(2);
DipSW(1) <= J9_out(1) or SW1(4);
DipSW(0) <= J9_out(0) or SW1(6);
-- Outputs from each switch bank are tied together, logical AND since they are active low
SW1_bank1 <= DipSW(7) and DipSW(6) and DipSW(5) and DipSW(4);
SW1_bank2 <= DipSW(3) and DipSW(2) and DipSW(1) and DipSW(0);
-- Bank 1 of dip switches is multiplexed with player inputs connected to selectors F9 and H9
A8_8 <= SW1_bank1 and F9_Q_n and H9_Q_n;
end rtl;

564
Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/T65/T65.vhd Normal file
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@@ -0,0 +1,564 @@
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
--if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
-- P(Flag_B) <= '1';
--end if;
--if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
-- P(Flag_I) <= '1';
-- P(Flag_B) <= B_o;
--end if;
-- B=1 always on the 6502
P(Flag_B) <= '1';
if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
if MCycle = "011" then
-- B=0 in *copy* of P pushed onto the stack
P(Flag_B) <= '0';
elsif MCycle = "100" then
P(Flag_I) <= '1';
end if;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;

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`define BUILD_DATE "180913"
`define BUILD_TIME "214058"

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.sv"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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-- CPU, RAM, ROM and address decoder for Atari Dominos
-- Based upon work done previously for Sprint 2
-- (c) 2018 James Sweet
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity CPU_mem is
port(
CLK12 : in std_logic;
CLK6 : in std_logic; -- 6MHz on schematic
Reset_I : in std_logic;
Reset_n : buffer std_logic;
VCount : in std_logic_vector(7 downto 0);
HCount : in std_logic_vector(8 downto 0);
Vblank_s : in std_logic; -- Vblank* on schematic
Vreset : in std_logic;
Hsync_n : in std_logic;
Test_n : in std_logic;
Attract : buffer std_logic;
Tumble : out std_logic;
Lamp1 : out std_logic;
Lamp2 : out std_logic;
PHI1_O : out std_logic;
PHI2_O : out std_logic;
DISPLAY : out std_logic_vector(7 downto 0);
IO_Adr : out std_logic_vector(9 downto 0);
Inputs : in std_logic_vector(1 downto 0)
);
end CPU_mem;
architecture rtl of CPU_mem is
signal cpu_clk : std_logic;
signal PHI1 : std_logic;
signal PHI2 : std_logic;
signal Q5 : std_logic;
signal Q6 : std_logic;
signal A7_2 : std_logic;
signal A7_5 : std_logic;
signal A7_7 : std_logic;
signal A8_6 : std_logic;
signal H256 : std_logic;
signal H256_n : std_logic;
signal H128 : std_logic;
signal H64 : std_logic;
signal H32 : std_logic;
signal H16 : std_logic;
signal H8 : std_logic;
signal H4 : std_logic;
signal V128 : std_logic;
signal V64 : std_logic;
signal V32 : std_logic;
signal V16 : std_logic;
signal V8 : std_logic;
signal IRQ_n : std_logic;
signal NMI_n : std_logic;
signal RW_n : std_logic;
signal RnW : std_logic;
signal A : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(9 downto 0);
signal cpuDin : std_logic_vector(7 downto 0);
signal cpuDout : std_logic_vector(7 downto 0);
signal DBUS_n : std_logic_vector(7 downto 0);
signal DBUS : std_logic_vector(7 downto 0);
signal ROM3_dout : std_logic_vector(7 downto 0);
signal ROM4_dout : std_logic_vector(7 downto 0);
signal ROM_dout : std_logic_vector(7 downto 0);
signal ROM1 : std_logic;
signal ROM2 : std_logic;
signal ROM3 : std_logic;
signal ROM4 : std_logic;
signal ROM_ce : std_logic;
signal ROM_mux_in : std_logic_vector(3 downto 0);
signal cpuRAM_dout : std_logic_vector(7 downto 0);
signal Vram_dout : std_logic_vector(7 downto 0);
signal RAM_addr : std_logic_vector(9 downto 0) := (others => '0');
signal Vram_addr : std_logic_vector(9 downto 0) := (others => '0');
signal Scanbus : std_logic_vector(9 downto 0) := (others => '0');
signal RAM_dout : std_logic_vector(7 downto 0);
signal RAM_we : std_logic := '0';
signal RAM_RW_n : std_logic := '1';
signal RAM_ce_n : std_logic := '1';
signal RAM_n : std_logic := '1';
signal WRAM : std_logic := '0';
signal WRITE_n : std_logic := '1';
signal F2_in : std_logic_vector(3 downto 0) := "0000";
signal F2_out : std_logic_vector(9 downto 0) := "1111111111";
signal D2_in : std_logic_vector(3 downto 0) := "0000";
signal D2_out : std_logic_vector(9 downto 0) := "1111111111";
signal E8_in : std_logic_vector(3 downto 0) := "0000";
signal E8_out : std_logic_vector(9 downto 0) := "1111111111";
signal P3_8 : std_logic := '0';
signal Sync : std_logic := '0';
signal Sync_n : std_logic := '1';
signal Switch_n : std_logic := '1';
signal Display_n : std_logic := '1';
signal Addec_bus : std_logic_vector(7 downto 0);
signal Timer_Reset_n : std_logic := '1';
signal J6_5 : std_logic := '0';
signal J6_9 : std_logic := '0';
signal Coin1 : std_logic := '0';
signal Coin2 : std_logic := '0';
signal Input_mux : std_logic := '0';
signal A8_8 : std_logic := '0';
signal H9_Q_n : std_logic := '1';
signal J9_out : std_logic_vector(7 downto 0);
signal H8_en : std_logic := '0';
signal WDog_Clear : std_logic := '0';
signal WDog_count : std_logic_vector(3 downto 0) := "0000";
begin
H8 <= HCount(3);
H16 <= HCount(4);
H32 <= HCount(5);
H64 <= HCount(6);
H128 <= HCount(7);
H256 <= HCount(8);
H256_n <= (not HCount(8));
V8 <= VCount(3);
V16 <= VCount(4);
V32 <= VCount(5);
V64 <= VCount(6);
V128 <= VCount(7);
-- Watchdog timer, counts pulses from V128 and resets CPU if not cleared by Timer_Reset_n
Watchdog: process(V128, WDog_Clear, Reset_I)
begin
if Reset_I = '0' then
WDog_count <= "1111";
elsif Wdog_Clear = '1' then
WDog_count <= "0000";
elsif rising_edge(V128) then
WDog_count <= WDog_count + 1;
end if;
end process;
WDog_Clear <= (Test_n nand Timer_Reset_n);
Reset_n <= (not WDog_count(3));
CPU: entity work.T65
port map(
Enable => '1',
Mode => "00",
Res_n => reset_n,
Clk => phi1,
Rdy => '1',
Abort_n => '1',
IRQ_n => '1',
NMI_n => NMI_n,
SO_n => '1',
R_W_n => RW_n,
A(15 downto 0) => A,
DI => cpuDin,
DO => cpuDout
);
DBUS_n <= (not cpuDout); -- Data bus to video RAM is inverted
ADR(9 downto 7) <= (A(9) or WRAM) & (A(8) or WRAM) & (A(7) or WRAM);
ADR(6 downto 0) <= A(6 downto 0);
RnW <= (not RW_n);
IO_Adr <= Adr;
NMI_n <= not (Vblank_s and Test_n);
-- CPU clock
H4 <= Hcount(2);
CPU_clock: process(clk12, H4, Q5, Q6)
begin
if rising_edge(clk12) then
Q5 <= H4;
Q6 <= Q5;
end if;
phi1 <= not (Q5 or Q6); --?
end process;
PHI2 <= (not PHI1);
PHI1_O <= PHI1;
PHI2_O <= PHI2;
A8_6 <= not(RnW and PHI2 and H4 and WRITE_n);
A7: process(clk12, A8_6) -- Shift register chain of 4 DFF's clocked by clk12, creates a delayed WRITE_n
begin
if rising_edge(clk12) then
A7_2 <= A8_6;
A7_5 <= A7_2;
A7_7 <= A7_5;
WRITE_n <= A7_7;
end if;
end process;
D1: entity work.sprom
generic map(
widthad_a => 11,
width_a => 8,
init_file =>"roms/7352-02.d1.hex"
)
port map(
address => A(10) & ADR(9 downto 0),
clock => clk6,
q => rom3_dout
);
E1: entity work.sprom
generic map(
widthad_a => 11,
width_a => 8,
init_file =>"roms/7438-02.e1.hex"
)
port map(
address => A(10) & ADR(9 downto 0),
clock => clk6,
q => rom4_dout
);
-- ROM data mux
ROM_mux_in <= (ROM1 & ROM2 & ROM3 & ROM4);
ROM_mux: process(ROM_mux_in, rom3_dout, rom4_dout)
begin
ROM_dout <= (others => '0');
case ROM_mux_in is
when "0010" => rom_dout <= rom3_dout;
when "0001" => rom_dout <= rom4_dout;
when others => null;
end case;
end process;
-- RAM
-- The original hardware multiplexes access to the RAM between the CPU and video hardware. Here we are
-- just using dual-ported RAM
RAM: entity work.dpram
generic map(
widthad_a => 10,
width_a => 8)
port map(
clock_a => clk6,
-- CPU side
address_a => adr(9 downto 0),
wren_a => ram_we,
data_a => DBUS_n,
q_a=> CPUram_dout,
-- Video side
clock_b => clk6,
address_b => Vram_addr,
wren_b => '0',
data_b => x"FF",
q_b => Vram_dout
);
Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 and H256) & (V8 and H256) & H128 & H64 & H32 & H16 & H8;
-- Real hardware has both WE and CE which are selected by K2 according to the state of the phase 2 clock
-- Altera block RAM has active high WE, original RAM had active low WE
ram_we <= (not Write_n) and (not Display_n) and Phi2;
-- Rising edge of phi2 clock latches inverted output of VRAM data bus
F5: process(phi2)
begin
if rising_edge(phi2) then
display <= not Vram_dout;
end if;
end process;
E2: entity work.sprom
generic map(
widthad_a => 5,
width_a => 8,
init_file =>"roms/6401-01.e2.hex"
)
port map(
address => A(13 downto 9),
clock => clk12,
q => addec_bus
);
F2_in <= addec_bus(0) & addec_bus(1) & addec_bus(2) & addec_bus(3);
WRAM <= addec_bus(4);
D2_in <= RnW & addec_bus(5) & addec_bus(6) & addec_bus(7);
-- Decoder code could be cleaned up a bit, unused decoder states are not explicitly implemented
F2: process(F2_in)
begin
case F2_in is
when "0000" =>
F2_out <= "1111111110";
when "0001" =>
F2_out <= "1111111101";
when "0010" =>
F2_out <= "1111111011";
when "0011" =>
F2_out <= "1111110111";
when "0100" =>
F2_out <= "1111101111";
when "0101" =>
F2_out <= "1111011111";
when "0110" =>
F2_out <= "1110111111";
when "0111" =>
F2_out <= "1101111111";
when others =>
F2_out <= "1111111111";
end case;
end process;
ROM1 <= (F2_out(0) nand F2_out(1));
ROM2 <= (F2_out(2) nand F2_out(3));
ROM3 <= (F2_out(4) nand F2_out(5));
ROM4 <= (F2_out(6) nand F2_out(7));
ROM_ce <= (ROM1 or ROM2 or ROM3 or ROM4);
D2: process(D2_in)
begin
case D2_in is
when "0000" =>
D2_out <= "1111111110";
when "0001" =>
D2_out <= "1111111101";
when "0010" =>
D2_out <= "1111111011";
when "0011" =>
D2_out <= "1111110111";
when "0100" =>
D2_out <= "1111101111";
when "1000" =>
D2_out <= "1011111111";
when "1001" =>
D2_out <= "0111111111";
when others =>
D2_out <= "1111111111";
end case;
end process;
RAM_n <= D2_out(0);
SYNC_n <= D2_out(1);
SYNC <= (not SYNC_n);
SWITCH_n <= D2_out(2);
DISPLAY_n <= (D2_out(0) and D2_out(8));
P3_8 <= (D2_out(9) or WRITE_n);
E8_in <= P3_8 & ADR(9 downto 7);
E8: process(E8_in)
begin
case E8_in is
when "0000" =>
E8_out <= "1111111110";
when "0001" =>
E8_out <= "1111111101";
when "0010" =>
E8_out <= "1111111011";
when "0011" =>
E8_out <= "1111110111";
when "0100" =>
E8_out <= "1111101111";
when "0101" =>
E8_out <= "1111011111";
when "0110" =>
E8_out <= "1110111111";
when others =>
E8_out <= "1111111111";
end case;
end process;
H8_en <= E8_out(0);
Timer_Reset_n <= E8_out(1);
-- H8 9334
H8_dec: process(clk6, Adr)
begin
if rising_edge(clk6) then
if (H8_en = '0') then
case Adr(6 downto 4) is
when "000" => Attract <= Adr(0);
when "001" => Tumble <= Adr(0);
when "010" => null;
when "011" => LAMP1 <= Adr(0);
when "100" => LAMP2 <= Adr(0);
when "101" => null;
when "110" => null;
when "111" => null;
when others => null;
end case;
end if;
end if;
end process;
-- CPU Din mux
cpuDin <= ROM_dout when rom_ce = '1' else
(not CPUram_dout) when Display_n = '0' else -- Remember RAM data is inverted
VCount(7) & VBlank_s & Vreset & Attract & "1111" when Sync_n = '0' else -- Using V128 (VCount(7)) in place of 60Hz mains reference
Inputs & "111111" when SWITCH_n = '0' else
x"FF";
end rtl;

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//
// PWM DAC
//
// MSBI is the highest bit number. NOT amount of bits!
//
module dac #(parameter MSBI=6, parameter INV=1'b1)
(
output reg DACout, //Average Output feeding analog lowpass
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
input CLK,
input RESET
);
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
always @(*) DeltaAdder = DACin + DeltaB;
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge CLK or posedge RESET) begin
if(RESET) begin
SigmaLatch <= 1'b1 << (MSBI+1);
DACout <= INV;
end else begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[MSBI+2] ^ INV;
end
end
endmodule

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-- Top level file for Atari Dominos
-- (c) 2018 James Sweet
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
-- See Dominos manual pg. 40 for video output details. Resistor values listed here have been scaled
-- for 3.3V logic.
-- R48 1k Ohm
-- R49 1k Ohm
-- R50 680R
-- R51 330R
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity dominos is
port(
clk_12 : in std_logic; -- 50MHz input clock
Reset_I : in std_logic; -- Reset button (Active low)
Hs : out std_logic;
Vs : out std_logic;
Vb : out std_logic;
Hb : out std_logic;
Video : out std_logic;
Audio : out std_logic_vector(6 downto 0); -- Ideally this should have a simple low pass filter
Coin1_I : in std_logic; -- Coin switches (Active low)
Coin2_I : in std_logic;
Start1_I : in std_logic; -- Start buttons
Start2_I : in std_logic;
Up1 : in std_logic; -- Player controls
Down1 : in std_logic;
Left1 : in std_logic;
Right1 : in std_logic;
Up2 : in std_logic;
Down2 : in std_logic;
Left2 : in std_logic;
Right2 : in std_logic;
Test_I : in std_logic;
Lamp1_O : out std_logic; -- Player 1 and 2 start button LEDs
Lamp2_O : out std_logic
);
end dominos;
architecture rtl of dominos is
signal clk_6 : std_logic;
signal phi1 : std_logic;
signal phi2 : std_logic;
signal reset_n : std_logic;
signal Hcount : std_logic_vector(8 downto 0) := (others => '0');
signal H256 : std_logic;
signal H256_s : std_logic;
signal H256_n : std_logic;
signal H128 : std_logic;
signal H64 : std_logic;
signal H32 : std_logic;
signal H16 : std_logic;
signal H8 : std_logic;
signal H8_n : std_logic;
signal H4 : std_logic;
signal H4_n : std_logic;
signal H2 : std_logic;
signal H1 : std_logic;
signal Hsync : std_logic;
signal Vsync : std_logic;
signal Vcount : std_logic_vector(7 downto 0) := (others => '0');
signal V128 : std_logic;
signal V64 : std_logic;
signal V32 : std_logic;
signal V16 : std_logic;
signal V8 : std_logic;
signal V4 : std_logic;
signal V2 : std_logic;
signal V1 : std_logic;
signal Vblank : std_logic;
signal Vreset : std_logic;
signal Vblank_s : std_logic;
signal Vblank_n_s : std_logic;
signal HBlank : std_logic;
signal CompBlank_s : std_logic;
signal CompSync_n_s : std_logic;
signal WhitePF_n : std_logic;
signal BlackPF_n : std_logic;
signal Display : std_logic_vector(7 downto 0);
-- Address decoder
signal addec_bus : std_logic_vector(7 downto 0);
signal RnW : std_logic;
signal Write_n : std_logic;
signal ROM1 : std_logic;
signal ROM2 : std_logic;
signal ROM3 : std_logic;
signal WRAM : std_logic;
signal RAM_n : std_logic;
signal Sync_n : std_logic;
signal Switch_n : std_logic;
signal Display_n : std_logic;
signal TimerReset_n : std_logic;
signal Attract : std_logic := '0';
signal Tumble : std_logic := '0';
signal Lamp1 : std_logic;
signal Lamp2 : std_logic;
signal NMI_n : std_logic;
signal Adr : std_logic_vector(9 downto 0);
signal SW1 : std_logic_vector(3 downto 0);
signal Inputs : std_logic_vector(1 downto 0);
begin
-- Configuration DIP switches, these can be brought out to external switches if desired
-- See dominos 2 manual page 11 for complete information. Active low (0 = On, 1 = Off)
-- 1 2 Points to win (00 - 3, 01 - 4, 10 - 5, 11 - 6)
-- 3 4 Game Cost (10 - 1 Coin per player)
-- 5 6 7 8 Unused
SW1 <= "1010"; -- Config dip switches 1-4
Vid_sync: entity work.synchronizer
port map(
clk_12 => clk_12,
clk_6 => clk_6,
hcount => hcount,
vcount => vcount,
hsync => hsync,
hblank => hblank,
vblank_s => vblank_s,
vblank_n_s => vblank_n_s,
vblank => vblank,
vsync => vsync,
vreset => vreset
);
Background: entity work.playfield
port map(
clk6 => clk_6,
display => display,
HCount => HCount,
VCount => VCount,
HBlank => HBlank,
H256_s => H256_s,
VBlank => VBlank,
VBlank_n_s => Vblank_n_s,
HSync => Hsync,
VSync => VSync,
CompSync_n_s => CompSync_n_s,
CompBlank_s => CompBlank_s,
WhitePF_n => WhitePF_n,
BlackPF_n => BlackPF_n
);
CPU: entity work.cpu_mem
port map(
Clk12 => clk_12,
Clk6 => clk_6,
Reset_I => Reset_I,
Reset_n => reset_n,
VCount => VCount,
HCount => HCount,
Hsync_n => not Hsync,
Vblank_s => Vblank_s,
Vreset => Vreset,
Test_n => not Test_I,
Attract => Attract,
Tumble => Tumble,
Lamp1 => Lamp1_O,
Lamp2 => Lamp2_O,
Phi1_o => Phi1,
Phi2_o => Phi2,
Display => Display,
IO_Adr => Adr,
Inputs => Inputs
);
Input: entity work.Control_Inputs
port map(
SW1 => SW1 & "0000", -- DIP switches
Coin1_n => Coin1_I,
Coin2_n => Coin2_I,
Start1 => not Start1_I, -- Inputs are active-high in real hardware, inverting these makes more sense with the FPGA
Start2 => not Start2_I,
Left1 => not Left1,
Up1 => not Up1,
Right1 => not Right1,
Down1 => not Down1,
Left2 => not Left2,
Right2 => not Right2,
Up2 => not Up2,
Down2 => not Down2,
Self_test => not Test_I,
Adr => Adr,
Inputs => Inputs
);
Sound: entity work.audio
port map(
Clk_6 => Clk_6,
Reset_n => Reset_n,
Attract => Attract,
Tumble => Tumble,
Display => Display,
HCount => HCount,
VCount => VCount,
Audio => Audio
);
Vb <= VBLANK;
Hb <= HBLANK;
Hs <= Hsync;
Vs <= Vsync;
Video <= (not (BlackPF_n and WhitePF_n)) nor CompBlank_s;
end rtl;

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//Dominos from james10952001 Port to Mist by Gehstock
module dominos_mist(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.sv"
localparam CONF_STR = {
"Dominos;;",
"O1,Self_Test,Off,On;",
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"T6,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [11:0] kbjoy;
wire [7:0] joy0;
wire [7:0] joy1;
wire scandoubler_disable;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire [6:0] audio;
wire video;
wire clk_24, clk_12, clk_6;
wire locked;
pll pll
(
.inclk0(CLOCK_27),
.c0(clk_24),//24.192
.c1(clk_12),//12.096
.c2(clk_6),//6.048
.locked(locked)
);
wire LED1, LED2;
assign LED = ~(LED1 | LED2);
dominos dominos (
.clk_12(clk_12),
.Reset_I(~(status[0] | status[6] | buttons[1])),
.Hs(hs),
.Vs(vs),
.Vb(vb),
.Hb(hb),
.Video(video),
.Audio(audio),
.Coin1_I(~kbjoy[7]),
.Coin2_I(~kbjoy[7]),
.Start1_I(~(kbjoy[5] | joy0[4])),
.Start2_I(~(kbjoy[6] | joy1[4])),
.Up1(~(kbjoy[3] | joy0[3])),
.Down1(~(kbjoy[2] | joy0[2])),
.Left1(~(kbjoy[1] | joy0[1])),
.Right1(~(kbjoy[0] | joy0[0])),
.Up2(~(kbjoy[11] | joy1[3])),
.Down2(~(kbjoy[10] | joy1[2])),
.Left2(~(kbjoy[9] | joy1[1])),
.Right2(~(kbjoy[8] | joy1[0])),
.Test_I(~status[1]),
.Lamp1_O(LED1),
.Lamp2_O(LED2)
);
dac dac (
.CLK(clk_24),
.RESET(1'b0),
.DACin(audio),
.DACout(AUDIO_L)
);
assign AUDIO_R = AUDIO_L;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
(
.clk_sys(clk_24),
.ce_pix(clk_6),
.ce_pix_actual(clk_6),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? {video,video,video} : "000"),
.G(blankn ? {video,video,video} : "000"),
.B(blankn ? {video,video,video} : "000"),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.scandoubler_disable(scandoubler_disable),
.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
.hq2x(status[4:3]==1),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
(
.clk_sys (clk_24 ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable(scandoubler_disable),
.ypbpr (ypbpr ),
.ps2_kbd_clk (ps2_kbd_clk ),
.ps2_kbd_data (ps2_kbd_data ),
.joystick_0 (joy0 ),
.joystick_1 (joy1 ),
.status (status )
);
keyboard keyboard(
.clk(clk_24),
.reset(),
.ps2_kbd_clk(ps2_kbd_clk),
.ps2_kbd_data(ps2_kbd_data),
.joystick(kbjoy)
);
endmodule

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-- Audio for Atari Dominos
-- Based upon work done for Sprint 2 which uses very similar
-- hardware. There may be room for improvement as
-- I do not have a real board to compare.
-- (c) 2018 James Sweet
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity audio is
port(
Clk_6 : in std_logic;
Reset_n : in std_logic;
Attract : in std_logic;
Tumble : in std_logic;
Display : in std_logic_vector(7 downto 0);
HCount : in std_logic_vector(8 downto 0);
VCount : in std_logic_vector(7 downto 0);
Audio : out std_logic_vector(6 downto 0)
);
end audio;
architecture rtl of audio is
signal reset : std_logic;
signal H4 : std_logic;
signal H8 : std_logic;
signal H16 : std_logic;
signal H32 : std_logic;
signal H64 : std_logic;
signal H256 : std_logic;
signal V2 : std_logic;
signal V4 : std_logic;
signal Amp_n : std_logic;
signal Freq_n : std_logic;
signal Tone_freq : std_logic_vector(3 downto 0);
signal Tone : std_logic_vector(3 downto 0);
signal Pulse : std_logic;
signal Topple : std_logic;
signal ena_count : std_logic_vector(10 downto 0);
signal ena_3k : std_logic;
signal tone_prefilter : std_logic_vector(3 downto 0);
signal tone_filter_t1 : std_logic_vector(3 downto 0);
signal tone_filter_t2 : std_logic_vector(3 downto 0);
signal tone_filter_t3 : std_logic_vector(3 downto 0);
signal tone_filtered : std_logic_vector(5 downto 0);
begin
-- HCount
-- (0) 1H 3 MHz
-- (1) 2H 1.5MHz
-- (2) 4H 750 kHz
-- (3) 8H 375 kHz
-- (4) 16H 187 kHz
-- (5) 32H 93 kHz
-- (6) 64H 46 kHz
-- (7) 128H 23 kHz
-- (8) 256H 12 kHz
reset <= (not reset_n);
H4 <= HCount(2);
H8 <= HCount(3);
H16 <= HCount(4);
H32 <= HCount(5);
H64 <= HCount(6);
H256 <= HCount(8);
V2 <= VCount(1);
V4 <= VCount(2);
-- These signals latch the frequency and amplitude data from the Display bus
-- Decoding corresponds to locations in RAM when addressed by video hardware
Freq_n <= '0' when (H32 and (not H16) and H8 and (not H4) and (not H64) and (not H256)) = '1' else '1';
Amp_n <= '0' when (H32 and H16 and H8 and (not H4) and (not H64) and (not H256)) = '1' else '1';
-- Generate the 3kHz clock enable used by the filter
Enable: process(clk_6)
begin
if rising_edge(CLK_6) then
ena_count <= ena_count + "1";
ena_3k <= '0';
if (ena_count(10 downto 0) = "00000000000") then
ena_3k <= '1';
end if;
end if;
end process;
Tone_sound: process(amp_n, display, pulse, tone)
begin
if amp_n = '0' then
tone <= display(3 downto 0);
end if;
if pulse = '1' then
tone_prefilter <= tone;
else
tone_prefilter <= "0000";
end if;
end process;
---- Very simple low pass filter, borrowed from MikeJ's Asteroids code
Filter: process(clk_6)
begin
if rising_edge(clk_6) then
if (ena_3k = '1') then
tone_filter_t1 <= tone_prefilter;
tone_filter_t2 <= tone_filter_t1;
tone_filter_t3 <= tone_filter_t2;
end if;
tone_filtered <= ("00" & tone_filter_t1) +
('0' & tone_filter_t2 & '0') +
("00" & tone_filter_t3);
end if;
end process;
Freq_latch: process(Freq_n, Display)
begin
if Freq_n = '0' then
tone_freq <= Display(3 downto 0);
end if;
end process;
Tone_pulse: entity work.Oscillator
generic map(
Freq_tune => 50 -- Tuning pot for frequency
)
port map(
Clk_6 => clk_6,
Ena_3k => ena_3k,
Freqdata => tone_freq,
Output => pulse
);
Topple <= Tumble and (not V4);
--Audio mixer, also mutes sound in attract mode
Audio <= "0000" & ("00" & topple) + ('0' & tone_filtered) when attract = '0'
else "0000000";
end rtl;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

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//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output [DWIDTH:0] q
);
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b(q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH+1){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUMWORDS,
altsyncram_component.numwords_b = NUMWORDS,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = AWIDTH+1,
altsyncram_component.widthad_b = AWIDTH+1,
altsyncram_component.width_a = DWIDTH+1,
altsyncram_component.width_b = DWIDTH+1,
altsyncram_component.width_byteena_a = 1;
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module DiffCheck
(
input [17:0] rgb1,
input [17:0] rgb2,
output result
);
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
wire [6:0] t = $signed(r) + $signed(b);
wire [6:0] gx = {g[5], g};
wire [7:0] y = $signed(t) + $signed(gx);
wire [6:0] u = $signed(r) - $signed(b);
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
// if y is inside (-24..24)
wire y_inside = (y < 8'h18 || y >= 8'he8);
// if u is inside (-4, 4)
wire u_inside = (u < 7'h4 || u >= 7'h7c);
// if v is inside (-6, 6)
wire v_inside = (v < 8'h6 || v >= 8'hfA);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [5:0] A,
input [5:0] B,
input [5:0] C,
output [5:0] O
);
function [8:0] mul6x3;
input [5:0] op1;
input [2:0] op2;
begin
mul6x3 = 9'd0;
if(op2[0]) mul6x3 = mul6x3 + op1;
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [8:0] Amul = mul6x3(A, Op[7:5]);
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
wire [8:0] At = Amul;
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[9:4];
endmodule
module Blend
(
input [5:0] rule,
input disable_hq2x,
input [17:0] E,
input [17:0] A,
input [17:0] B,
input [17:0] D,
input [17:0] F,
input [17:0] H,
output [17:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = 11'bx;
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [17:0] Input1 = E;
wire [17:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
reg [17:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
wire curbuf = y[0];
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [17:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [17:0] h2rgb;
input [8:0] v;
begin
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
end
endfunction
function [8:0] rgb2h;
input [17:0] v;
begin
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
(
.clk(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wren(wrout_en)
);
always @(posedge clk) begin
reg [AWIDTH:0] offs;
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
offs <= offs + 1'd1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
prevbuf <= curbuf;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
prevbuf <= 0;
end
end
old_reset_line <= reset_line;
end
end
endmodule // Hq2x

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module keyboard
(
input clk,
input reset,
input ps2_kbd_clk,
input ps2_kbd_data,
output reg[11:0] joystick
);
reg [11:0] shift_reg = 12'hFFF;
wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
wire [7:0] kcode = kdata[9:2];
reg release_btn = 0;
reg [7:0] code;
reg input_strobe = 0;
always @(negedge clk) begin
reg old_reset = 0;
old_reset <= reset;
if(~old_reset & reset)begin
joystick <= 0;
end
if(input_strobe) begin
case(code)
'h75: joystick[3] <= ~release_btn; // arrow up
'h72: joystick[2] <= ~release_btn; // arrow down
'h6B: joystick[1] <= ~release_btn; // arrow left
'h74: joystick[0] <= ~release_btn; // arrow right
//player2
'h1D: joystick[11] <= ~release_btn; // W
'h1B: joystick[10] <= ~release_btn; // S
'h1C: joystick[9] <= ~release_btn; // A
'h23: joystick[8] <= ~release_btn; // D
'h29: joystick[4] <= ~release_btn; // Space
'h05: joystick[5] <= ~release_btn; // F1
'h06: joystick[6] <= ~release_btn; // F2
'h76: joystick[7] <= ~release_btn; // Escape
endcase
end
end
always @(posedge clk) begin
reg [3:0] prev_clk = 0;
reg old_reset = 0;
reg action = 0;
old_reset <= reset;
input_strobe <= 0;
if(~old_reset & reset)begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
end else begin
prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
if(prev_clk == 1) begin
if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
shift_reg <= 12'hFFF;
if (kcode == 8'he0) ;
// Extended key code follows
else if (kcode == 8'hf0)
// Release code follows
action <= 1;
else begin
// Cancel extended/release flags for next time
action <= 0;
release_btn <= action;
code <= kcode;
input_strobe <= 1;
end
end else begin
shift_reg <= kdata;
end
end
end
end
endmodule

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//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
input ps2_caps_led,
// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output ioctl_wr,
output reg [23:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] b_data;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
wire [7:0] spi_dout = { sbuf, SPI_DI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
// drive MISO only when transmitting core id
always@(negedge SPI_SCK) begin
if(!CONF_DATA0) begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
spi_do <= core_type[~bit_cnt];
end else begin
case(cmd)
// reading config string
8'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else spi_do <= 0;
end
// reading sd card status
8'h16: begin
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else spi_do <= 0;
end
// reading sd card write data
8'h18:
spi_do <= b_data[~bit_cnt];
// reading keyboard LED status
8'h1f:
spi_do <= kbd_led[~bit_cnt];
default:
spi_do <= 0;
endcase
end
end
end
reg b_wr2,b_wr3;
always @(negedge clk_sys) begin
b_wr3 <= b_wr2;
sd_buff_wr <= b_wr3;
end
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
if(CONF_DATA0) begin
b_wr2 <= 0;
bit_cnt <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
end else begin
b_wr2 <= 0;
sbuf <= spi_dout[6:0];
bit_cnt <= bit_cnt + 1'd1;
if(bit_cnt == 5) begin
if (byte_cnt == 0) sd_buff_addr <= 0;
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
end
// finished reading command byte
if(bit_cnt == 7) begin
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
if(byte_cnt == 0) begin
cmd <= spi_dout;
if(spi_dout == 8'h19) begin
sd_ack_conf <= 1;
sd_buff_addr <= 0;
end
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
sd_ack <= 1;
sd_buff_addr <= 0;
end
if(spi_dout == 8'h18) b_data <= sd_buff_din;
mount_strobe <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_dout;
8'h02: joystick_0 <= spi_dout;
8'h03: joystick_1 <= spi_dout;
// store incoming ps2 mouse bytes
8'h04: begin
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_dout;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_dout;
b_wr2 <= 1;
end
8'h18: b_data <= sd_buff_din;
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
end
end
// notify image selection
8'h1c: mount_strobe <= 1;
// send image info
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
// status, 32bit version
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
default: ;
endcase
end
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [23:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [23:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
assign ioctl_wr = |ioctl_wrd;
reg [1:0] ioctl_wrd;
always@(negedge clk_sys) begin
reg rclkD, rclkD2;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wrd<= {ioctl_wrd[0],1'b0};
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wrd <= 2'b11;
end
end
endmodule

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-- Oscillator for Atari Dominos
-- Based on engine sound generator developed for Sprint 2
-- (c) 2018 James Sweet
--
-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
-- a four bit binary value. The output of this oscillator drives a counter to divide down the frequency
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity Oscillator is
generic(
constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the oscillator frequency
);
port(
Clk_6 : in std_logic;
Ena_3k : in std_logic;
FreqData : in std_logic_vector(3 downto 0);
output : out std_logic
);
end Oscillator;
architecture rtl of Oscillator is
signal Freq_val : integer range 1 to 350;
signal Ramp_term_unfilt : integer range 1 to 80000;
signal Ramp_Count : integer range 0 to 80000;
signal Ramp_term : integer range 1 to 80000;
signal Freq_mod : integer range 0 to 400;
signal Osc_Clk : std_logic;
signal Counter_A : std_logic;
signal Counter_B : unsigned(2 downto 0);
signal Counter_A_clk : std_logic;
begin
-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
-- The output of this DAC has a capacitor to smooth out the frequency variation.
-- The constants assigned to Freq_val can be tweaked to adjust the frequency curve
Speed_select: process(Clk_6)
begin
if rising_edge(Clk_6) then
case FreqData is
when "0000" => Freq_val <= 280;
when "0001" => Freq_val <= 245;
when "0010" => Freq_val <= 230;
when "0011" => Freq_val <= 205;
when "0100" => Freq_val <= 190;
when "0101" => Freq_val <= 175;
when "0110" => Freq_val <= 160;
when "0111" => Freq_val <= 145;
when "1000" => Freq_val <= 130;
when "1001" => Freq_val <= 115;
when "1010" => Freq_val <= 100;
when "1011" => Freq_val <= 85;
when "1100" => Freq_val <= 70;
when "1101" => Freq_val <= 55;
when "1110" => Freq_val <= 40;
when "1111" => Freq_val <= 25;
end case;
end if;
end process;
-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
-- not truly accurate but should be close enough. Sprint used 10uF, Dominos uses only 0.1uF so the time constant
-- is much shorter.
RC_filt: process(clk_6, ena_3k, ramp_term_unfilt)
begin
if rising_edge(clk_6) then
if ena_3k = '1' then
if ramp_term_unfilt > ramp_term then
ramp_term <= ramp_term + 500;
elsif ramp_term_unfilt = ramp_term then
ramp_term <= ramp_term;
else
ramp_term <= ramp_term - 300;
end if;
end if;
end if;
end process;
-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
-- the frequency. Freq_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
-- to simulate the function of the frequency adjustment pot in the original hardware.
ramp_term_unfilt <= ((200 - freq_tune) * Freq_val);
-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
Ramp_osc: process(clk_6)
begin
if rising_edge(clk_6) then
Osc_Clk <= '1';
ramp_count <= ramp_count + 1;
if ramp_count > ramp_term then
ramp_count <= 0;
Osc_Clk <= '0';
end if;
end if;
end process;
-- 7492 counter has two sections, one div-by-2 and one div-by-6
-- Sprint uses this to generate the irregular thumping sound to simulate an engine
-- Dominos only uses div-by-6
Engine_counter: process(Osc_Clk, counter_A_clk, counter_B)
begin
if rising_edge(Osc_Clk) then
Counter_B <= Counter_B + '1';
end if;
end process;
Output <= Counter_B(0);
end rtl;

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// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule

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-- Playfield generation circuitry for Atari Dominos
-- (c) 2018 James Sweet
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity playfield is
port(
clk6 : in std_logic;
display : in std_logic_vector(7 downto 0);
HCount : in std_logic_vector(8 downto 0);
VCount : in std_logic_vector(7 downto 0);
H256_s : out std_logic;
HBlank : in std_logic;
VBlank : in std_logic;
VBlank_n_s : in std_logic; -- VBLANK* on the schematic
HSync : in std_logic;
VSync : in std_logic;
CompSync_n_s : out std_logic; -- COMP SYNC* on schematic
CompBlank_s : out std_logic; -- COMP BLANK* on schematic
WhitePF_n : out std_logic; -- White playfield objects
BlackPF_n : out std_logic -- Black playfield objects
);
end playfield;
architecture rtl of playfield is
signal H1 : std_logic;
signal H2 : std_logic;
signal H4 : std_logic;
signal H256 : std_logic;
signal H256_n : std_logic;
signal V1 : std_logic;
signal V2 : std_logic;
signal V4 : std_logic;
signal char_addr : std_logic_vector(8 downto 0) := (others => '0');
signal char_data : std_logic_vector(7 downto 0) := (others => '0');
signal shift_data : std_logic_vector(7 downto 0) := (others => '0');
signal QH : std_logic;
signal R2_reg : std_logic_vector(3 downto 0) := (others => '0');
-- These signals are based off the schematic and are formatted as Designator_PinNumber
signal R7_12 : std_logic;
signal P3_3 : std_logic;
signal P2_13 : std_logic;
signal P3_6 : std_logic;
signal A6_6 : std_logic;
signal A6_3 : std_logic;
begin
-- Video synchronization signals
H1 <= Hcount(0);
H2 <= Hcount(1);
H4 <= Hcount(2);
H256 <= Hcount(8);
H256_n <= not(Hcount(8));
V1 <= Vcount(0);
V2 <= Vcount(1);
V4 <= Vcount(2);
-- Some glue logic, may be re-written later to be cleaner and easier to follow without referring to schematic
R7_12 <= not(H1 and H2 and H4);
P3_3 <= (H256_n or R7_12);
P2_13 <= (HSync nor VSync);
P3_6 <= (HBlank or VBlank);
char_addr <= display(5 downto 0) & V4 & V2 & V1;
R4: entity work.sprom
generic map(
widthad_a => 9,
width_a => 4,
init_file =>"roms/7440-01.r4.hex"
)
port map(
address => char_addr,
clock => clk6,
q => char_data(3 downto 0)
);
P4: entity work.sprom
generic map(
widthad_a => 9,
width_a => 4,
init_file =>"roms/7439-01.p4.hex"
)
port map(
address => char_addr,
clock => clk6,
q => char_data(7 downto 4)
);
-- 74LS166 video shift register
R3: process(clk6, P3_3, VBlank_n_s, char_data, shift_data)
begin
if VBlank_n_s = '0' then -- Connected Clear input
shift_data <= (others => '0');
elsif rising_edge(clk6) then
if P3_3 = '0' then -- Parallel load
shift_data <= char_data(7 downto 0);
else
shift_data <= shift_data(6 downto 0) & '0';
end if;
end if;
QH <= shift_data(7);
end process;
-- 9316 counter at R2
-- CEP and CET tied to ground, counter is used only as a synchronous latch
R2: process(clk6, R7_12, display, H256, P2_13, P3_6)
begin
if rising_edge(clk6) then
if R7_12 = '0' then
R2_reg <= (H256 & display(7) & P3_6 & P2_13);
end if;
end if;
end process;
H256_s <= R2_reg(3);
CompBlank_s <= R2_reg(1);
CompSync_n_s <= R2_reg(0);
A6_6 <= (R2_reg(2) and QH);
A6_3 <= ((not R2_reg(2)) and QH);
WhitePF_n <= (not A6_6);
BlackPF_n <= (not A6_3);
end rtl;

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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 125,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 112,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 125,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 56,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 125,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 28,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

17
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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
input ce_pix_actual,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input line_start,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
assign vs_out = vs_in;
reg [2:0] phase;
reg [2:0] ce_div;
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
wire ls_in = hs_in | line_start;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
phase <= phase + 1'd1;
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
phase <= phase + 1'd1;
ce_cnt <= ce_cnt + 1'd1;
if(ce_pix_actual) begin
phase <= 0;
ce_div <= ce_cnt + 1'd1;
ce_cnt <= 0;
req_line_reset <= 0;
end
if(ls_in) req_line_reset <= 1;
end
end
reg ce_sd;
always @(*) begin
case(ce_div)
2: ce_sd = !phase[0];
4: ce_sd = !phase[1:0];
default: ce_sd <= 1;
endcase
end
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4 & ce_sd),
.inputpixel({b_in,g_in,r_in}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h_actual),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h_actual;
always @(*) begin
case(ce_div)
2: sd_h_actual = sd_h[10:1];
4: sd_h_actual = sd_h[10:2];
default: sd_h_actual = sd_h;
endcase
end
reg [10:0] sd_h;
reg [1:0] sd_line;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise,hs_ls;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg hs, hs2, vs, ls;
if(ce_x1) begin
hs <= hs_in;
ls <= ls_in;
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
if(sd_hcnt == hs_ls) sd_h <= 0;
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
end
end
endmodule

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

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-- Video synchronizer circuit for Atari Dominos
-- Similar circuit used in many other Atari and Kee Games arcade games
-- (c) 2018 James Sweet
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity synchronizer is
port(
clk_12 : in std_logic;
clk_6 : out std_logic;
hcount : out std_logic_vector(8 downto 0);
vcount : out std_logic_vector(7 downto 0);
hsync : out std_logic;
hblank : out std_logic;
vblank_s : out std_logic;
vblank_n_s : out std_logic;
vblank : out std_logic;
vsync : out std_logic;
vreset : out std_logic);
end synchronizer;
architecture rtl of synchronizer is
signal h_counter : std_logic_vector(9 downto 0) := (others => '0');
signal H256 : std_logic;
signal H256_n : std_logic;
signal H128 : std_logic;
signal H64 : std_logic;
signal H32 : std_logic;
signal H16 : std_logic;
signal H8 : std_logic;
signal H8_n : std_logic;
signal H4 : std_logic;
signal H4_n : std_logic;
signal H2 : std_logic;
signal H1 : std_logic;
signal v_counter : std_logic_vector(7 downto 0) := (others => '0');
signal V128 : std_logic;
signal V64 : std_logic;
signal V32 : std_logic;
signal V16 : std_logic;
signal V8 : std_logic;
signal V4 : std_logic;
signal V2 : std_logic;
signal V1 : std_logic;
signal sync_bus : std_logic_vector(3 downto 0) := (others => '0');
signal sync_reg : std_logic_vector(3 downto 0) := (others => '0');
signal vblank_int : std_logic := '0';
signal vreset_n : std_logic := '0';
signal hblank_int : std_logic := '0';
signal hsync_int : std_logic := '0';
signal hsync_reset : std_logic := '0';
begin
-- Horizontal counter is 9 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128
-- using only the last three count states
H_count: process(clk_12)
begin
if rising_edge(clk_12) then
if h_counter = "1111111111" then
h_counter <= "0100000000";
else
h_counter <= h_counter + 1;
end if;
end if;
end process;
-- Vertical counter is 8 bits, clocked by the rising edge of H256 at the end of each horizontal line
V_count: process(hsync_int)
begin
if rising_edge(Hsync_int) then
if vreset_n = '0' then
v_counter <= (others => '0');
else
v_counter <= v_counter + '1';
end if;
end if;
end process;
M2: entity work.sprom
generic map(
widthad_a => 8,
width_a => 4,
init_file =>"roms/6400-01.m2.hex"
)
port map(
address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
clock => clk_12,
q => sync_bus
);
-- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals
sync_register: process(hsync_int)
begin
if rising_edge(hsync_int) then
sync_reg <= sync_bus;
end if;
end process;
-- Outputs of sync PROM
vblank_s <= sync_reg(3);
vblank_n_s <= not sync_reg(3);
vreset <= sync_reg(2);
vreset_n <= not sync_reg(2);
vblank <= sync_reg(1);
vsync <= sync_reg(0);
-- A pair of D type flip-flops that generate the Hsync signal
Hsync_1: process(H256_n, H32)
begin
if H256_n = '0' then
hblank_int <= '0';
else
if rising_edge(H32) then
hblank_int <= not H64;
end if;
end if;
end process;
Hsync_2: process(hblank_int, H8)
begin
if hblank_int = '0' then
hsync_int <= '0';
else
if rising_edge(H8) then
hsync_int <= H32;
end if;
end if;
end process;
-- Assign various signals
clk_6 <= h_counter(0);
H1 <= h_counter(1);
H2 <= h_counter(2);
H4 <= h_counter(3);
H8 <= h_counter(4);
H16 <= h_counter(5);
H32 <= h_counter(6);
H64 <= h_counter(7);
H128 <= h_counter(8);
H256 <= h_counter(9);
H4_n <= not H4;
H8_n <= not H8;
H256_n <= not H256;
V1 <= v_counter(0);
V2 <= v_counter(1);
V4 <= v_counter(2);
V8 <= v_counter(3);
V16 <= v_counter(4);
V32 <= v_counter(5);
V64 <= v_counter(6);
V128 <= v_counter(7);
hcount <= h_counter(9 downto 1);
vcount <= v_counter;
hsync <= hsync_int;
hblank <= hblank_int;
end rtl;

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//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 3 bits per component
// For half depth 6 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0,
parameter OSD_COLOR = 3'd4,
parameter OSD_X_OFFSET = 10'd0,
parameter OSD_Y_OFFSET = 10'd0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
// Some systems have multiple resolutions.
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
input ce_pix_actual,
// OSD SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// 0 = HVSync 31KHz, 1 = CSync 15KHz
input scandoubler_disable,
// High quality 2x scaling
input hq2x,
// YPbPr always uses composite sync
input ypbpr,
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// interlace sync. Positive pulses.
input HSync,
input VSync,
// Falling of this signal means start of informative part of line.
// It can be horizontal blank signal.
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
// before first informative pixel.
input line_start,
// MiST video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_VS,
output VGA_HS
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.r_in(R),
.g_in(G),
.b_in(B),
.hs_out(hs_sd),
.vs_out(vs_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
generate
if(HALF_DEPTH) begin
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [5:0] r = rt;
wire [5:0] g = gt;
wire [5:0] b = bt;
end
endgenerate
wire hs = (scandoubler_disable ? HSync : hs_sd);
wire vs = (scandoubler_disable ? VSync : vs_sd);
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire [5:0] r_out, g_out, b_out;
always @(*) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
end
2: begin // reduce 50% = 1/2
r_out = {1'b0, r[5:1]};
g_out = {1'b0, g[5:1]};
b_out = {1'b0, b[5:1]};
end
3: begin // reduce 75% = 1/4
r_out = {2'b00, r[5:2]};
g_out = {2'b00, g[5:2]};
b_out = {2'b00, b[5:2]};
end
default: begin
r_out = r;
g_out = g;
b_out = b;
end
endcase
end
wire [5:0] red, green, blue;
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
(
.*,
.R_in(r_out),
.G_in(g_out),
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.R_out(red),
.G_out(green),
.B_out(blue)
);
wire [5:0] yuv_full[225] = '{
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
6'd63
};
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
endmodule