1
0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-03-10 04:24:25 +00:00

Update single_port_rom.vhd

This commit is contained in:
Marcel
2023-07-13 12:03:34 +02:00
parent 3da627aa0b
commit a93adf06c2

View File

@@ -70,7 +70,7 @@ begin
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => INIT_FILE,
intended_device_family => "Cyclone V",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**ADDR_WIDTH,