New Core : Jin

2026-02-03 07:10:20 +00:00 · 2019-06-09 21:56:13 +02:00
parent ecbde2a186
commit b362c4d3f8
27 changed files with 15477 additions and 0 deletions
--- a/Hardware/Jin/Jin_MiST.qpf
+++ b/Hardware/Jin/Jin_MiST.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
+# Date created = 04:04:47  October 16, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.0"
+DATE = "04:04:47  October 16, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "Jin_MiST"
--- a/Hardware/Jin/Jin_MiST.qsf
+++ b/Hardware/Jin/Jin_MiST.qsf
@@ -0,0 +1,203 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 18:04:04  June 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Defender_MiST_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13  JUNE 04, 2019"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Jin_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/defender.vhd
+set_global_assignment -name VHDL_FILE rtl/defender_sound_board.vhd
+set_global_assignment -name VHDL_FILE rtl/defender_sound.vhd
+set_global_assignment -name VHDL_FILE rtl/defender_decoder_3.vhd
+set_global_assignment -name VHDL_FILE rtl/defender_decoder_2.vhd
+set_global_assignment -name VHDL_FILE rtl/defender_cmos_ram.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
+set_global_assignment -name VHDL_FILE rtl/pia6821.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu09l_128.vhd
+set_global_assignment -name QIP_FILE rtl/pll_mist.qip
+set_global_assignment -name VERILOG_FILE rtl/data_io.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY Jin_MiST
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ---------------------------
+# start ENTITY(Defender_MiST)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(Defender_MiST)
+# -------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/Hardware/Jin/Jin_MiST.sdc
+++ b/Hardware/Jin/Jin_MiST.sdc
@@ -0,0 +1,137 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2
+set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
--- a/Hardware/Jin/ReadMe.txt
+++ b/Hardware/Jin/ReadMe.txt
@@ -0,0 +1,8 @@
+Williams Jin
+
+Port to MiST
+
+JIN.ROM is required at the root of the SD-Card.
+
+I dont know how its should work need feedback.
+
--- a/Hardware/Jin/Release/JIN.ROM
+++ b/Hardware/Jin/Release/JIN.ROM
--- a/Hardware/Jin/Release/Jin_MiST.rbf
+++ b/Hardware/Jin/Release/Jin_MiST.rbf
--- a/Hardware/Jin/clean.bat
+++ b/Hardware/Jin/clean.bat
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
--- a/Hardware/Jin/rtl/Jin_MiST.sv
+++ b/Hardware/Jin/rtl/Jin_MiST.sv
@@ -0,0 +1,244 @@
+//============================================================================
+//  Arcade: Jin
+//
+
+module Jin_MiST(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27,
+
+	output [12:0] SDRAM_A,
+	inout  [15:0] SDRAM_DQ,
+	output        SDRAM_DQML,
+	output        SDRAM_DQMH,
+	output        SDRAM_nWE,
+	output        SDRAM_nCAS,
+	output        SDRAM_nRAS,
+	output        SDRAM_nCS,
+	output  [1:0] SDRAM_BA,
+	output        SDRAM_CLK,
+	output        SDRAM_CKE
+);
+
+`include "rtl/build_id.v" 
+
+localparam CONF_STR = {
+	"JIN;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.0.0",`BUILD_DATE
+};
+
+assign LED = 1;
+
+wire clk_sys, clock_6, clock_1p79, clock_0p89;
+wire pll_locked;
+pll_mist pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_sys),//36
+	.c1(clock_6),//6
+	.c2(clock_1p79),//1.79
+	.c3(clock_0p89),//0.89
+	.locked(pll_locked)
+	);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire [10:0] ps2_key;
+wire [7:0] audio;
+wire        hs, vs;
+wire        blankn;
+wire  [2:0] g,b;
+wire  [1:0] r;
+
+wire [14:0] cart_addr;
+wire [15:0] sdram_do;
+wire        cart_rd;
+wire        ioctl_downl;
+wire  [7:0] ioctl_index;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire  [7:0] ioctl_dout;
+
+data_io data_io (
+	.clk_sys       ( clk_sys      ),
+	.SPI_SCK       ( SPI_SCK      ),
+	.SPI_SS2       ( SPI_SS2      ),
+	.SPI_DI        ( SPI_DI       ),
+	.ioctl_download( ioctl_downl  ),
+	.ioctl_index   ( ioctl_index  ),
+	.ioctl_wr      ( ioctl_wr     ),
+	.ioctl_addr    ( ioctl_addr   ),
+	.ioctl_dout    ( ioctl_dout   )
+);
+
+assign SDRAM_CLK = clk_sys;
+		
+sdram cart
+(
+	.*,
+	.init          ( ~pll_locked  ),
+	.clk           ( clk_sys      ),
+	.wtbt          ( 2'b00        ),
+	.dout          ( sdram_do     ),
+	.din           ( {ioctl_dout, ioctl_dout} ),
+	.addr          ( ioctl_downl ? ioctl_addr : cart_addr ),
+	.we            ( ioctl_downl & ioctl_wr ),
+	.rd            ( !ioctl_downl),
+	.ready()
+);
+
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_sys) begin
+	reg ioctl_downlD;
+	ioctl_downlD <= ioctl_downl;
+
+	if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+	reset <= status[0] | buttons[1] | status[6] | ~rom_loaded;
+end
+
+defender defender (
+	.clock_6			(clock_6),
+	.clk_1p79		(clock_1p79),
+	.clk_0p89		(clock_0p89),
+	.reset        ( reset ),
+
+	.video_r      ( r               ),
+	.video_g      ( g               ),
+	.video_b      ( b               ),
+   .video_hs     ( hs              ),
+	.video_vs     ( vs              ),
+	.video_blankn ( blankn          ),
+
+	.audio_out    ( audio           ),
+	
+	.roms_addr ( cart_addr       ),
+	.roms_do   ( sdram_do[7:0]   ),
+
+	.btn_two_players       ( btn_two_players ),
+	.btn_one_player       ( btn_one_player  ),
+	.btn_left_coin        ( btn_coin        ),
+
+	.btn_fire(m_fire),
+	.btn_fire2(m_bomb),
+
+	.btn_left(m_left),
+	.btn_right(m_right),
+	.btn_down(m_down),
+	.btn_up(m_up)
+);
+
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
+	.clk_sys        ( clk_sys          ),
+	.SPI_SCK        ( SPI_SCK          ),
+	.SPI_SS3        ( SPI_SS3          ),
+	.SPI_DI         ( SPI_DI           ),
+	.R              ( blankn ? {r, r[1] } : 0 ),
+	.G              ( blankn ? g : 0   ),
+	.B              ( blankn ? b : 0   ),
+	.HSync          ( hs               ),
+	.VSync          ( vs               ),
+	.VGA_R          ( VGA_R            ),
+	.VGA_G          ( VGA_G            ),
+	.VGA_B          ( VGA_B            ),
+	.VGA_VS         ( VGA_VS           ),
+	.VGA_HS         ( VGA_HS           ),
+	.rotate         ( {1'b1,status[2]} ),
+	.scandoubler_disable( scandoublerD ),
+	.scanlines      ( status[4:3]      ),
+	.ypbpr          ( ypbpr            )
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+wire dac_o;
+assign AUDIO_L = dac_o;
+assign AUDIO_R = dac_o;
+
+dac #(
+	.C_bits(15))
+dac(
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i({audio,audio}),
+	.dac_o(dac_o)
+	);
+
+//											Rotated														Normal
+wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+wire       key_pressed;
+wire [7:0] key_code;
+wire       key_strobe;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+endmodule 
--- a/Hardware/Jin/rtl/YM2149.sv
+++ b/Hardware/Jin/rtl/YM2149.sv
@@ -0,0 +1,329 @@
+//
+// Copyright (c) MikeJ - Jan 2005
+// Copyright (c) 2016-2018 Sorgelig
+//
+// All rights reserved
+//
+// Redistribution and use in source and synthezised forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in synthesized form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+
+// BDIR  BC  MODE
+//   0   0   inactive
+//   0   1   read value
+//   1   0   write value
+//   1   1   set address
+//
+
+module YM2149
+(
+	input        CLK,       // Global clock
+	input        CE,        // PSG Clock enable
+	input        RESET,     // Chip RESET (set all Registers to '0', active hi)
+	input        BDIR,      // Bus Direction (0 - read , 1 - write)
+	input        BC,        // Bus control
+	input        A8,
+	input        A9_L,
+	input  [7:0] DI,        // Data In
+	output [7:0] DO,        // Data Out
+	output [7:0] CHANNEL_A, // PSG Output channel A
+	output [7:0] CHANNEL_B, // PSG Output channel B
+	output [7:0] CHANNEL_C, // PSG Output channel C
+
+	input        SEL,
+	input        MODE,
+	
+	output [5:0] ACTIVE,
+
+	input  [7:0] IOA_in,
+	output [7:0] IOA_out,
+
+	input  [7:0] IOB_in,
+	output [7:0] IOB_out
+);
+
+assign ACTIVE  = ~ymreg[7][5:0];
+assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff;
+assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff;
+
+reg [7:0] addr;
+reg [7:0] ymreg[16];
+wire      cs = !A9_L & A8;
+
+// Write to PSG
+reg env_reset;
+always @(posedge CLK) begin
+	if(RESET) begin
+		ymreg     <= '{default:0};
+		ymreg[7]  <= '1;
+		addr      <= '0;
+		env_reset <= 0;
+	end else begin
+		env_reset <= 0;
+		if(cs & BDIR) begin
+			if(BC) addr <= DI;
+			else if(!addr[7:4]) begin
+				ymreg[addr[3:0]] <= DI;
+				env_reset <= (addr == 13);
+			end
+		end
+	end
+end
+
+// Read from PSG
+assign DO = dout;
+reg [7:0] dout;
+always_comb begin
+	dout = 8'hFF;
+	if(cs & ~BDIR & BC & !addr[7:4]) begin
+		case(addr[3:0])
+			 0: dout = ymreg[0];
+			 1: dout = ymreg[1][3:0];
+			 2: dout = ymreg[2];
+			 3: dout = ymreg[3][3:0];
+			 4: dout = ymreg[4];
+			 5: dout = ymreg[5][3:0];
+			 6: dout = ymreg[6][4:0];
+			 7: dout = ymreg[7];
+			 8: dout = ymreg[8][4:0];
+			 9: dout = ymreg[9][4:0];
+			10: dout = ymreg[10][4:0];
+			11: dout = ymreg[11];
+			12: dout = ymreg[12];
+			13: dout = ymreg[13][3:0];
+			14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
+			15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
+		endcase
+	end
+end
+
+reg ena_div;
+reg ena_div_noise;
+
+//  p_divider
+always @(posedge CLK) begin
+	reg [3:0]  cnt_div;
+	reg        noise_div;
+
+	if(CE) begin
+		ena_div <= 0;
+		ena_div_noise <= 0;
+		if(!cnt_div) begin
+			cnt_div <= {SEL, 3'b111};
+			ena_div <= 1;
+            
+			noise_div <= (~noise_div);
+			if (noise_div) ena_div_noise <= 1;
+		end else begin
+			cnt_div <= cnt_div - 1'b1;
+		end
+	end
+end
+
+
+reg [2:0] noise_gen_op;
+
+//  p_noise_gen
+always @(posedge CLK) begin
+	reg [16:0] poly17;
+	reg [4:0]  noise_gen_cnt;
+
+	if(CE) begin
+		if (ena_div_noise) begin
+			if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
+				noise_gen_cnt <= 0;
+				poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
+			end else begin
+				noise_gen_cnt <= noise_gen_cnt + 1'd1;
+			end
+			noise_gen_op <= {3{poly17[0]}};
+		end
+	end
+end
+
+wire [11:0] tone_gen_freq[1:3];
+assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
+assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
+assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
+
+reg [3:1] tone_gen_op;
+
+//p_tone_gens
+always @(posedge CLK) begin
+	integer i;
+	reg [11:0] tone_gen_cnt[1:3];
+
+	if(CE) begin
+		// looks like real chips count up - we need to get the Exact behaviour ..
+	
+		for (i = 1; i <= 3; i = i + 1) begin
+			if(ena_div) begin
+				if (tone_gen_freq[i]) begin
+					if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
+						tone_gen_cnt[i] <= 0;
+						tone_gen_op[i]  <= ~tone_gen_op[i];
+					end else begin
+						tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
+					end
+				end else begin
+					tone_gen_op[i] <= ymreg[7][i];
+					tone_gen_cnt[i] <= 0;
+				end
+			end
+		end
+	end
+end
+
+reg env_ena;
+wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
+
+//p_envelope_freq
+always @(posedge CLK) begin
+	reg [15:0] env_gen_cnt;
+
+	if(CE) begin
+		env_ena <= 0;
+		if(ena_div) begin
+			if (env_gen_cnt >= env_gen_comp) begin
+				env_gen_cnt <= 0;
+				env_ena <= 1;
+			end else begin
+				env_gen_cnt <= (env_gen_cnt + 1'd1);
+			end
+		end
+	end
+end
+
+reg [4:0] env_vol;
+
+wire is_bot    = (env_vol == 5'b00000);
+wire is_bot_p1 = (env_vol == 5'b00001);
+wire is_top_m1 = (env_vol == 5'b11110);
+wire is_top    = (env_vol == 5'b11111);
+
+always @(posedge CLK) begin
+	reg env_hold;
+	reg env_inc;
+
+	// envelope shapes
+	// C AtAlH
+	// 0 0 x x  \___
+	//
+	// 0 1 x x  /___
+	//
+	// 1 0 0 0  \\\\
+	//
+	// 1 0 0 1  \___
+	//
+	// 1 0 1 0  \/\/
+	//           ___
+	// 1 0 1 1  \
+	//
+	// 1 1 0 0  ////
+	//           ___
+	// 1 1 0 1  /
+	//
+	// 1 1 1 0  /\/\
+	//
+	// 1 1 1 1  /___
+
+	if(env_reset | RESET) begin
+		// load initial state
+		if(!ymreg[13][2]) begin		// attack
+			env_vol <= 5'b11111;
+			env_inc <= 0;		// -1
+		end else begin
+			env_vol <= 5'b00000;
+			env_inc <= 1;		// +1
+		end
+		env_hold <= 0;
+	end
+	else if(CE) begin
+		if (env_ena) begin
+			if (!env_hold) begin
+				if (env_inc) env_vol <= (env_vol + 5'b00001);
+					else env_vol <= (env_vol + 5'b11111);
+			end
+
+			// envelope shape control.
+			if(!ymreg[13][3]) begin
+				if(!env_inc) begin	// down
+					if(is_bot_p1) env_hold <= 1;
+				end else if (is_top) env_hold <= 1;
+			end else if(ymreg[13][0]) begin		// hold = 1
+				if(!env_inc) begin	// down
+					if(ymreg[13][1]) begin		// alt
+						if(is_bot) env_hold <= 1;
+					end else if(is_bot_p1) env_hold <= 1;
+				end else if(ymreg[13][1]) begin	// alt
+					if(is_top) env_hold <= 1;
+				end else if(is_top_m1) env_hold <= 1;
+			end else if(ymreg[13][1]) begin		// alternate
+				if(env_inc == 1'b0) begin		// down
+					if(is_bot_p1) env_hold <= 1;
+					if(is_bot) begin
+						env_hold <= 0;
+						env_inc  <= 1;
+					end
+				end else begin
+					if(is_top_m1) env_hold <= 1;
+					if(is_top) begin
+						env_hold <= 0;
+						env_inc  <= 0;
+					end
+				end
+			end
+		end
+	end
+end
+
+reg [5:0] A,B,C;
+always @(posedge CLK) begin
+	A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4]  ? env_vol[4:0] : { ymreg[8][3:0],  ymreg[8][3]}};
+	B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4]  ? env_vol[4:0] : { ymreg[9][3:0],  ymreg[9][3]}};
+	C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
+end
+
+wire [7:0] volTable[64] = '{
+	//YM2149
+	8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, 
+	8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, 
+	8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, 
+	8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
+
+	//AY8910
+	8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, 
+	8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, 
+	8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, 
+	8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff 
+};
+
+assign CHANNEL_A = volTable[A];
+assign CHANNEL_B = volTable[B];
+assign CHANNEL_C = volTable[C];
+
+endmodule
--- a/Hardware/Jin/rtl/build_id.tcl
+++ b/Hardware/Jin/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
--- a/Hardware/Jin/rtl/cpu09l_128.vhd
+++ b/Hardware/Jin/rtl/cpu09l_128.vhd
--- a/Hardware/Jin/rtl/cpu68.vhd
+++ b/Hardware/Jin/rtl/cpu68.vhd
--- a/Hardware/Jin/rtl/dac.vhd
+++ b/Hardware/Jin/rtl/dac.vhd
@@ -0,0 +1,48 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity dac is
+	generic (
+		C_bits  : integer := 10
+	);
+	port (
+		clk_i   : in  std_logic;
+		res_n_i : in  std_logic;
+		dac_i   : in  std_logic_vector(C_bits-1 downto 0);
+		dac_o   : out std_logic
+	);
+end dac;
+
+architecture rtl of dac is
+	signal sig_in: unsigned(C_bits downto 0);
+begin
+	seq: process(clk_i, res_n_i)
+	begin
+		if res_n_i = '0' then
+			sig_in <= to_unsigned(2**C_bits, sig_in'length);
+			dac_o  <= '0';
+		elsif rising_edge(clk_i) then
+		        -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
+			--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
+			sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
+			dac_o  <= sig_in(C_bits);
+		end if;
+	end process seq;
+end rtl;
--- a/Hardware/Jin/rtl/data_io.v
+++ b/Hardware/Jin/rtl/data_io.v
@@ -0,0 +1,115 @@
+//
+// data_io.v
+//
+// data_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+module data_io
+(
+	input             clk_sys,
+	input             SPI_SCK,
+	input             SPI_SS2,
+	input             SPI_DI,
+
+	// ARM -> FPGA download
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output            ioctl_wr,
+	output reg [24:0] ioctl_addr,
+	output reg  [7:0] ioctl_dout
+);
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+reg  [7:0] data_w;
+reg [24:0] addr_w;
+reg        rclk   = 0;
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+
+// data_io has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS2) begin
+	reg  [6:0] sbuf;
+	reg  [7:0] cmd;
+	reg  [4:0] cnt;
+	reg [24:0] addr;
+
+	if(SPI_SS2) cnt <= 0;
+	else begin
+		rclk <= 0;
+
+		// don't shift in last bit. It is evaluated directly
+		// when writing to ram
+		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
+
+		// increase target address after write
+		if(rclk) addr <= addr + 1'd1;
+
+		// count 0-7 8-15 8-15 ... 
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		// finished command byte
+		if(cnt == 7) cmd <= {sbuf, SPI_DI};
+
+		// prepare/end transmission
+		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
+			// prepare 
+			if(SPI_DI) begin
+				addr <= 0;
+				ioctl_download <= 1; 
+			end else begin
+				addr_w <= addr;
+				ioctl_download <= 0;
+			end
+		end
+
+		// command 0x54: UIO_FILE_TX
+		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
+			addr_w <= addr;
+			data_w <= {sbuf, SPI_DI};
+			rclk <= 1;
+		end
+
+		// expose file (menu) index
+		if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
+	end
+end
+
+assign ioctl_wr = |ioctl_wrd;
+reg [1:0] ioctl_wrd;
+
+always@(negedge clk_sys) begin
+	reg        rclkD, rclkD2;
+
+	rclkD    <= rclk;
+	rclkD2   <= rclkD;
+	ioctl_wrd<= {ioctl_wrd[0],1'b0};
+
+	if(rclkD & ~rclkD2) begin
+		ioctl_dout <= data_w;
+		ioctl_addr <= addr_w;
+		ioctl_wrd  <= 2'b11;
+	end
+end
+
+endmodule
--- a/Hardware/Jin/rtl/defender.vhd
+++ b/Hardware/Jin/rtl/defender.vhd
@@ -0,0 +1,780 @@
+---------------------------------------------------------------------------------
+-- Defender by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+-------------------------------- 
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- cpu09l - Version : 0128
+-- Synthesizable 6809 instruction compatible VHDL CPU core
+-- Copyright (C) 2003 - 2010 John Kent
+---------------------------------------------------------------------------------
+-- cpu68 - Version 9th Jan 2004 0.8
+-- 6800/01 compatible CPU core 
+-- GNU public license - December 2002 : John E. Kent
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Version 0.0 -- 15/10/2017 -- 
+--		    initial version
+---------------------------------------------------------------------------------
+--  Features :
+--   TV 15KHz mode only (atm)
+--   Cocktail mode : OK 
+-- 
+--  Use with MAME roms from defender.zip
+--
+--  Use make_defender_proms.bat to build vhd file and bin from binaries
+--
+--  Defender Hardware caracteristics :
+--
+--    1x6809 CPU accessing program rom and shared ram/devices
+--      3x16Ko video and working ram
+--      26Ko program roms
+--      1 pia for player I/O
+--      1 pia service switches, irq and sound selection to sound board
+--
+--    384 pixels x 260 line video scan, 16 colors per pixel
+--    Ram palette 16 colors among 256 colors (3 red bits,3 green bits, 2 blue bits)
+--
+--    2 decoder proms for video scan and cocktail/upright flip
+--
+--    No sprites, no char tiles 
+--
+--    128x4 cmos ram (see defender_cmos_ram.vhd for initial values)
+--    No save when power off (see also defender_cmos_ram.vhd)
+--
+--    1x6808/02
+--      128x8 working ram
+--      4k program rom 
+--      1 pia for sound selection cmd input and audio samples output
+
+---------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------
+-- defender cmos data (see also defender_cmos_ram.vhd)
+-- (ram is 128x4 => only 4 bits/address, that is only 1 hex digit/address)
+--
+-- @      values             - (fonction) meaning
+
+--	0       0                 - ?
+-- 1       0005              - (01) coins left
+-- 5       0000              - (02) coins center
+-- 9       0000              - (03) coins right
+-- 13      0005              - (04) total paid
+-- 17      0000              - (05) ships won
+---21      0000              - (06) total time
+-- 25      0003              - (07) total ships
+
+-- -- 8 entries of 6 digits highscore + 3 ascii letters
+
+-- 29      021270 44 52 4A   
+-- 41      018315 53 41 4D
+-- 53      015920 4C 45 44
+-- 65      014285 50 47 44
+-- 77      012520 43 52 42
+-- 89      011035 4D 52 53
+-- 101     008265 53 53 52
+-- 113     006010 54 4D 48 
+
+-- 125     00                - credits
+-- 127     5                 - ?
+
+-- -- protected data writeable only with coin door opened 
+
+-- 128     A                 - ?
+-- 129     0100              - (08) bonus ship level
+-- 133     03                - (09) nb ships
+-- 135     03                - (10) coinage select
+-- 137     01                - (11) left coin mult
+-- 139     04                - (12) center coin mult
+-- 141     01                - (13) right coin mult
+-- 143     01                - (14) coins for credit
+-- 145     00                - (15) coins for bonus
+-- 147     00                - (16) minimum coins
+-- 149     00                - (17) free play
+-- 151     05                - (18) game adjust 1  Stating difficulty 0=lib; 1=mod; 2=cons
+-- 153     15                - (19) game adjust 2  Progessive wave diff. limit > 4-25
+-- 155     01                - (20) game adjust 3  Background sound 0=off; 1=on
+-- 157     05                - (21) game adjust 4  Planet restore wave number
+-- 159     00                - (22) game adjust 5
+-- 161     00                - (23) game adjust 6
+-- 163     00                - (24) game adjust 7
+-- 165     00                - (25) game adjust 8
+-- 167     00                - (26) game adjust 9
+-- 169     00                - (27) game adjust 10
+
+-- 171     00000             - ?
+-- 176     0000000000000000  - ?
+-- 192     0000000000000000  - ?
+--	208     0000000000000000  - ?
+--	224     0000000000000000  - ?
+--	240     0000000000000000  - ?
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity defender is
+port(
+ clk_sys        : in std_logic;
+ clock_6     	 : in std_logic;
+ clk_1p79       : in std_logic;
+ clk_0p89       : in std_logic;
+ reset          : in std_logic;
+ 
+ dbg_cpu_addr   : out std_logic_vector(15 downto 0);
+-- tv15Khz_mode : in std_logic;
+ video_r        : out std_logic_vector(2 downto 0);
+ video_g        : out std_logic_vector(2 downto 0);
+ video_b        : out std_logic_vector(1 downto 0);
+-- video_clk      : out std_logic;
+ video_csync    : out std_logic;
+ video_blankn   : out std_logic;
+ video_hs       : out std_logic;
+ video_vs       : out std_logic;
+ 
+ audio_out      : out std_logic_vector(7 downto 0);
+ 
+ roms_addr   : out std_logic_vector(14 downto 0);
+ roms_do     : in  std_logic_vector( 7 downto 0);
+
+ btn_left_coin  : in std_logic;
+ btn_one_player : in std_logic;
+ btn_two_players: in std_logic;
+
+ btn_fire       : in std_logic;
+ btn_fire2     : in std_logic;
+ btn_right : in std_logic;
+ btn_left    : in std_logic;
+ btn_down       : in std_logic;
+ btn_up         : in std_logic;
+
+ sw_coktail_table : in std_logic;
+
+ cmd_select_players_btn : out std_logic
+
+);
+end defender;
+
+architecture struct of defender is
+
+ signal reset_n: std_logic;
+ signal clock_div : std_logic_vector(1 downto 0);
+
+ signal clock_6n  : std_logic;
+
+ signal cpu_clock  : std_logic;
+ signal cpu_addr   : std_logic_vector(15 downto 0);
+ signal cpu_di     : std_logic_vector( 7 downto 0);
+ signal cpu_do     : std_logic_vector( 7 downto 0);
+ signal cpu_rw     : std_logic;
+ signal cpu_irq    : std_logic;
+
+ signal wram_addr  : std_logic_vector(13 downto 0);
+ signal wram_we    : std_logic;
+ signal wram0_do   : std_logic_vector( 7 downto 0);
+ signal wram0_we   : std_logic;
+ signal wram1_do   : std_logic_vector( 7 downto 0);
+ signal wram1_we   : std_logic;
+ signal wram2_do   : std_logic_vector( 7 downto 0);
+ signal wram2_we   : std_logic;
+ 
+ --signal roms_addr  : std_logic_vector(14 downto 0);
+ --signal roms_do    : std_logic_vector( 7 downto 0);
+
+ signal roms_io_do : std_logic_vector( 7 downto 0);
+
+ signal io_we   : std_logic;
+ signal io_CS   : std_logic;
+
+ signal rom_page : std_logic_vector( 2 downto 0);
+ signal rom_page_we : std_logic;
+ 
+ signal screen_ctrl    : std_logic;
+ signal screen_ctrl_we : std_logic;
+
+ signal cmos_do   : std_logic_vector(3 downto 0);
+ signal cmos_we   : std_logic;
+
+ signal palette_addr : std_logic_vector(3 downto 0);
+ signal palette_we : std_logic;
+ signal palette_di : std_logic_vector( 7 downto 0);
+ signal palette_do : std_logic_vector( 7 downto 0);
+ 
+ signal pias_clock  : std_logic;
+ 
+-- pia io port a
+--      bit 0  Fire
+--      bit 1  Thrust
+--      bit 2  Smart Bomb
+--      bit 3  HyperSpace
+--      bit 4  2 Players
+--      bit 5  1 Player
+--      bit 6  Reverse
+--      bit 7  Down
+
+-- pia io port b
+--      bit 0  Up
+--      bit 7  1 for coktail table, 0 for upright cabinet
+--      other <= GND
+
+-- pia io ca/cb
+--      ca1, ca2, cb1 <= GND
+--      cb2  ouput + w2_jumper => select player 1/2 buttons for COCktail table
+ 
+ signal pia_io_CS     : std_logic;
+ signal pia_io_rw_n   : std_logic;
+ signal pia_io_do     : std_logic_vector( 7 downto 0);
+ signal pia_io_pa_i   : std_logic_vector( 7 downto 0);
+ signal pia_io_pb_i   : std_logic_vector( 7 downto 0);
+ signal pia_io_cb2_o  : std_logic;
+ 
+-- pia rom board port a
+--      bit 0  Auto Up / manual Down
+--      bit 1  Advance
+--      bit 2  Right Coin (nc)
+--      bit 3  High Score Reset
+--      bit 4  Left Coin
+--      bit 5  Center Coin (nc)
+--      bit 6  led 2 (output)
+--      bit 7  led 1 (output)
+
+-- pia rom board port b
+--      bit 0-5 to sound board (output)
+--      bit 6  led 4 (output)
+--      bit 7  led 3 (output)
+
+-- pia rom board ca/cb
+--      ca1 count 240
+--      ca2 coin door pin 7 (nc) 
+--      cb1 4ms
+--      cb2 sound board pin 8 (H5-nc)
+ 
+ signal pia_ROM_CS    : std_logic;
+ signal pia_rom_rw_n  : std_logic;
+ signal pia_rom_do    : std_logic_vector( 7 downto 0);
+ signal pia_rom_irqa  : std_logic;
+ signal pia_rom_irqb  : std_logic;
+ signal pia_rom_pa_i  : std_logic_vector( 7 downto 0);
+ signal pia_rom_pa_o  : std_logic_vector( 7 downto 0);
+ signal pia_rom_pb_o  : std_logic_vector( 7 downto 0);
+ 
+ signal vcnt_240 : std_logic;
+ signal cnt_4ms  : std_logic;
+ 
+ signal cpu_to_video_addr : std_logic_vector(8 downto 0);
+ signal cpu_to_video_do : std_logic_vector(7 downto 0);
+
+ signal video_scan_addr : std_logic_vector(8 downto 0);
+ signal video_scan_do : std_logic_vector(7 downto 0); 
+
+ signal pixel_cnt : std_logic_vector(2 downto 0);
+ signal hcnt : std_logic_vector(5 downto 0);
+ signal vcnt : std_logic_vector(8 downto 0);
+
+ signal pixels : std_logic_vector(23 downto 0);
+ 
+ signal hsync0,hsync1,hsync2,csync,hblank,vblank : std_logic;
+ 
+ signal select_sound : std_logic_vector(5 downto 0);
+
+begin
+
+clock_6n  <= not clock_6;
+reset_n   <= not reset;
+
+-- for debug
+dbg_cpu_addr <= cpu_addr;
+		
+		
+-- make pixels counters and cpu clock
+-- in original hardware cpu clock = 1us = 6pixels
+-- here one make 2 cpu clock within 1us
+process (reset, clock_6n)
+begin
+	if reset='1' then
+		pixel_cnt <= "000";
+		cpu_clock <= '0';
+	else 
+		if rising_edge(clock_6n) then
+		
+			if pixel_cnt = "101" then
+				pixel_cnt <= "000";
+				cpu_clock <= '0';
+			else
+				pixel_cnt <= pixel_cnt + '1';
+			end if;
+			
+			if pixel_cnt = "010" then 
+				cpu_clock <= '1';
+			end if;
+			
+			if pixel_cnt = "011" then   -- speed up processor (two clocks / 1us)
+				cpu_clock <= '0';
+			end if;
+			
+			if pixel_cnt = "100" then 
+				cpu_clock <= '1';
+			end if;
+
+						
+		end if;
+	end if;
+end process;
+
+-- make hcnt and vcnt video scanner from pixel clocks and counts
+-- 
+--  pixels   |0|1|2|3|4|5|0|1|2|3|4|5|
+--  hcnt     |     N     |  N+1      | 
+--
+--  hcnt [0..63] => 64 x 6 = 384 pixels,  1 pixel is 1us => 1 line is 64us (15.625KHz)
+--  vcnt [252..255,256..511] => 260 lines, 1 frame is 260 x 64us = 16.640ms (60.1Hz)
+--
+process (reset, clock_6n)
+begin
+	if reset='1' then
+		hcnt <= "000000";
+		vcnt <= '0'&X"FC";
+	else 
+		if rising_edge(clock_6n) then
+		
+			if pixel_cnt = "101" then
+				hcnt <= hcnt + '1';
+				if hcnt = "111111" then
+					if vcnt = '1'&X"FF" then
+						vcnt <= '0'&X"FC";
+					else
+						vcnt <= vcnt + '1';
+					end if;
+				end if;
+			end if;
+									
+		end if;
+	end if;
+end process;
+
+-- rom address multiplexer
+-- should reflect content of defender_prog.bin
+--
+-- 4k 0000-0FFF  cpu_space D000-DFFF defend.1 + defend.4  
+-- 4k 1000-1FFF            E000-EFFF defend.2
+-- 4k 2000-2FFF            F000-FFFF defend.3
+-- 4k 3000-3FFF  page=1    C000-CFFF defend.9 + defend.12 
+-- 4k 4000-4FFF  page=2    C000-CFFF defend.8 + defend.11 
+-- 4k 5000-5FFF  page=3    C000-CFFF defend.7 + defend.10 
+-- 4k 6000-6FFF  page=7    C000-C7FF defend.6 + 2k empty
+-- 4k 7000-7FFF            N.A       4k empty
+
+roms_addr <= 
+	"011" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "001" else 
+	"100" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "010" else 
+	"101" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "011" else 
+	"110" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"C" and rom_page = "111" else 
+	"000" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"D" else 
+	"001" & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = X"E" else 
+	"010" & cpu_addr(11 downto 0) ;--when cpu_addr(15 downto 12) = X"F"; 
+
+-- encoded cpu addr (decoder.2) and encoded scan addr (decoder.3)
+-- and screen control for cocktail table flip
+cpu_to_video_addr <= screen_ctrl & cpu_addr(15 downto 8);
+video_scan_addr   <= screen_ctrl & vcnt(7 downto 0);
+
+-- mux cpu addr/scan addr to wram
+wram_addr <= 
+	cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_clock = '1' else
+	video_scan_do & hcnt;	
+
+--	mux cpu addr/pixels data to palette addr
+palette_addr <=
+	cpu_addr(3 downto 0) when palette_we = '1' else 
+	pixels(23 downto 20) when screen_ctrl = '0' else pixels(3 downto 0);
+
+-- only cpu can write to palette	
+palette_di <= cpu_do;
+
+-- palette output to colors bits
+video_r <= palette_do(2 downto 0);
+video_g <= palette_do(5 downto 3);
+video_b <= palette_do(7 downto 6);
+	
+
+-- 24 bits pixels shift register
+-- 6 pixels of 4 bits
+process (clock_6) 
+begin
+	if rising_edge(clock_6) then 
+		if screen_ctrl = '0' then
+			if pixel_cnt = "001" then
+				pixels <= wram0_do & wram1_do & wram2_do;
+			else
+				pixels <= pixels(19 downto 0) & X"0" ;		
+			end if;
+		else
+			if pixel_cnt = "001" then
+				pixels <= wram2_do & wram1_do & wram0_do;
+			else
+				pixels <= X"0" & pixels(23 downto 4);		
+			end if;
+		end if;
+	end if;
+end process;
+
+-- pias cs
+io_cs   <=      '1' when cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; 	
+pia_rom_cs <=   '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '0'; -- CC00-CC03
+pia_io_cs <=    '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '0'; -- CC04-CC07
+	
+-- write enables
+wram_we <=        '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) < X"C" else '0';
+io_we   <=        '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; 	
+rom_page_we <=    '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"D" else '0';
+
+palette_we <=     '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '0' else '0'; -- C000-C00F
+screen_ctrl_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '1' else '0'; -- C010-C01F
+cmos_we <=        '1' when io_we = '1' and cpu_addr(11 downto 10) = "01"                       else '0'; -- C400-C7FF
+pia_rom_rw_n <=   '0' when io_we = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '1'; -- CC00-CC03
+pia_io_rw_n <=    '0' when io_we = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '1'; -- CC04-CC07
+
+-- mux io data between cmos/video register/pias/c000_rom_page
+roms_io_do <= 
+	X"0"&cmos_do          when rom_page = "000" and cpu_addr(11 downto 10) = "01" else -- C400-C7FF
+	vcnt(7 downto 2)&"00" when rom_page = "000" and cpu_addr(11 downto 10) = "10" else -- C800-cBFF
+	pia_rom_do            when rom_page = "000" and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else -- CC00-CC03 (A2n.A3n.A4n)
+	pia_io_do             when rom_page = "000" and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else -- CC04-CC07 (A2.A3n)
+	roms_do;
+
+-- mux cpu in data between roms/io/wram
+cpu_di <=
+	roms_do    when cpu_addr(15 downto 12) >= X"D" else
+	roms_io_do when cpu_addr(15 downto 12) >= X"C" else
+	wram0_do   when cpu_to_video_do(7 downto 6)  = "00" else
+	wram1_do   when cpu_to_video_do(7 downto 6)  = "01" else
+	wram2_do   when cpu_to_video_do(7 downto 6)  = "10" else X"00";
+
+	
+-- dispatch cpu we to devices with respect to decoder2 bits 7-6
+wram0_we  <= '1' when wram_we = '1' and cpu_to_video_do(7 downto 6)  = "00" else '0';
+wram1_we  <= '1' when wram_we = '1' and cpu_to_video_do(7 downto 6)  = "01" else '0';
+wram2_we  <= '1' when wram_we = '1' and cpu_to_video_do(7 downto 6)  = "10" else '0';
+
+
+-- rom bank page (and IO) select register
+-- screen control register
+process (reset, clock_6) 
+begin
+ if reset='1' then
+	rom_page <= "000";
+	screen_ctrl <= '0';
+ else 
+  if rising_edge(clock_6) then 
+		if rom_page_we = '1' then rom_page <= cpu_do(2 downto 0); end if;
+		if screen_ctrl_we = '1' then screen_ctrl <= cpu_do(0); end if;
+  end if;
+ end if;
+end process;
+
+-- pia rom board port a
+--      bit 0  Auto Up / manual Down
+--      bit 1  Advance
+--      bit 2  Right Coin (nc)
+--      bit 3  High Score Reset
+--      bit 4  Left Coin
+--      bit 5  Center Coin (nc)
+--      bit 6  led 2 (output)
+--      bit 7  led 1 (output)
+
+pias_clock <= clock_6; --not cpu_clock;
+
+pia_rom_pa_i(0) <= '0';
+pia_rom_pa_i(1) <= '0';
+pia_rom_pa_i(2) <= '0';
+pia_rom_pa_i(3) <= '0';
+pia_rom_pa_i(4) <= btn_left_coin;
+pia_rom_pa_i(5) <= '0';
+pia_rom_pa_i(6) <= '0';
+pia_rom_pa_i(7) <= '0';
+
+-- IN0
+pia_io_pa_i(0) <= btn_up;
+pia_io_pa_i(1) <= btn_down;
+pia_io_pa_i(2) <= btn_left;
+pia_io_pa_i(3) <= btn_right;
+pia_io_pa_i(4) <= btn_two_players;
+pia_io_pa_i(5) <= btn_one_player;
+pia_io_pa_i(6) <= btn_fire;
+pia_io_pa_i(7) <= btn_fire2;
+
+-- IN1
+pia_io_pb_i <= "00000000";--unknown/Level completed/Level completed/unknown/Lives/Coinage/Coinage/Coinage
+
+-- IN2
+-- pia io ca/cb
+cmd_select_players_btn <= pia_io_cb2_o; 
+
+-- pia rom ca1/Cb1
+vcnt_240 <= '1' when vcnt(7 downto 4) = X"F" else '0';
+cnt_4ms  <= vcnt(5);
+
+-- pia rom irqs to cpu
+cpu_irq  <= pia_rom_irqa or pia_rom_irqb;
+
+-- pia rom to sound board
+select_sound <= pia_rom_pb_o(5 downto 0);
+
+
+-- microprocessor 6809
+main_cpu : entity work.cpu09
+port map(	
+	clk      => cpu_clock,-- E clock input (falling edge)
+	rst      => reset,    -- reset input (active high)
+	vma      => open,     -- valid memory address (active high)
+   lic_out  => open,     -- last instruction cycle (active high)
+   ifetch   => open,     -- instruction fetch cycle (active high)
+   opfetch  => open,     -- opcode fetch (active high)
+   ba       => open,     -- bus available (high on sync wait or DMA grant)
+   bs       => open,     -- bus status (high on interrupt or reset vector fetch or DMA grant)
+	addr     => cpu_addr, -- address bus output
+	rw       => cpu_rw,   -- read not write output
+	data_out => cpu_do,   -- data bus output
+	data_in  => cpu_di,   -- data bus input
+	irq      => cpu_irq,  -- interrupt request input (active high)
+	firq     => '0',      -- fast interrupt request input (active high)
+	nmi      => '0',      -- non maskable interrupt request input (active high)
+	halt     => '0',      -- halt input (active high) grants DMA
+	hold     => '0'       -- hold input (active high) extend bus cycle
+);
+
+-- cpu program rom
+-- 4k D000-DFFF
+-- 4k E000-EFFF
+-- 4k F000-FFFF
+-- 4K C000-CFFF page=1
+-- 4K C000-CFFF page=2
+-- 4K C000-CFFF page=3
+-- 2K C000-C7FF page=7
+-- 6K N.A. 
+
+
+
+--cpu_prog_rom : entity work.defender_prog
+--port map(
+-- clk  => clock_6,
+-- addr => roms_addr(14 downto 0),
+-- data => roms_do
+--);
+
+-- cpu/video wram 0
+cpu_video_ram0 : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 14)
+port map(
+ clk  => clock_6,
+ we   => wram0_we,
+ addr => wram_addr(13 downto 0),
+ d    => cpu_do,
+ q    => wram0_do
+);
+
+-- cpu/video wram 1
+cpu_video_ram1 : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 14)
+port map(
+ clk  => clock_6,
+ we   => wram1_we,
+ addr => wram_addr(13 downto 0),
+ d    => cpu_do,
+ q    => wram1_do
+);
+
+-- cpu/video wram 2
+cpu_video_ram2 : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 14)
+port map(
+ clk  => clock_6,
+ we   => wram2_we,
+ addr => wram_addr(13 downto 0),
+ d    => cpu_do,
+ q    => wram2_do
+);
+
+-- palette ram 
+palette_ram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 4)
+port map(
+ clk  => clock_6,
+ we   => palette_we,
+ addr => palette_addr,
+ d    => palette_di,
+ q    => palette_do
+);
+
+-- cmos ram 
+cmos_ram : entity work.defender_cmos_ram
+generic map( dWidth => 4, aWidth => 8)
+port map(
+ clk  => clock_6,
+ we   => cmos_we,
+ addr => cpu_addr(7 downto 0),
+ d    => cpu_do(3 downto 0),
+ q    => cmos_do
+);
+
+-- cpu to video addr decoder
+cpu_video_addr_decoder : entity work.defender_decoder_2
+port map(
+ clk  => clock_6,
+ addr => cpu_to_video_addr,
+ data => cpu_to_video_do
+);
+
+-- video scan addr decoder
+video_scan_addr_decoder : entity work.defender_decoder_3
+port map(
+ clk  => clock_6,
+ addr => video_scan_addr,
+ data => video_scan_do
+);
+
+-- pia i/O board
+pia_io : entity work.pia6821
+port map
+(	
+	clk       	=> pias_clock,            -- rising edge
+	rst       	=> reset,                 -- active high
+	cs        	=> pia_io_cs,
+	rw        	=> pia_io_rw_n,           -- write low
+	addr      	=> cpu_addr(1 downto 0),
+	data_in   	=> cpu_do,
+	data_out  	=> pia_io_do,
+	irqa      	=> open,                  -- active high
+	irqb      	=> open,                  -- active high
+	pa_i      	=> pia_io_pa_i,
+	pa_o        => open,
+	pa_oe       => open,
+	ca1       	=> '0',
+	ca2_i      	=> '0',
+	ca2_o       => open,
+	ca2_oe      => open,
+	pb_i      	=> pia_io_pb_i,
+	pb_o        => open,
+	pb_oe       => open,
+	cb1       	=> '0',
+	cb2_i      	=> '0',
+	cb2_o       => pia_io_cb2_o,
+	cb2_oe      => open
+);
+
+-- pia rom board
+pia_rom : entity work.pia6821
+port map
+(	
+	clk       	=> pias_clock,
+	rst       	=> reset,
+	cs        	=> pia_rom_cs,
+	rw        	=> pia_rom_rw_n,
+	addr      	=> cpu_addr(1 downto 0),
+	data_in   	=> cpu_do,
+	data_out  	=> pia_rom_do,
+	irqa      	=> pia_rom_irqa,
+	irqb      	=> pia_rom_irqb,
+	pa_i      	=> pia_rom_pa_i,
+	pa_o        => open,
+	pa_oe       => open,
+	ca1       	=> vcnt_240,
+	ca2_i      	=> '0',
+	ca2_o       => open,
+	ca2_oe      => open,
+	pb_i      	=> (others => '0'),
+	pb_o        => pia_rom_pb_o,
+	pb_oe       => open,
+	cb1       	=> cnt_4ms,
+	cb2_i      	=> '0',
+	cb2_o       => open,
+	cb2_oe      => open
+);
+
+-- video syncs and blanks
+video_csync <= csync;
+
+process(clock_6n)
+	constant hcnt_base : integer := 54;
+	variable vsync_cnt : std_logic_vector(3 downto 0);
+begin
+
+if rising_edge(clock_6n) then
+
+  if    hcnt = hcnt_base+0 then hsync0 <= '0';
+  elsif hcnt = hcnt_base+6 then hsync0 <= '1';
+  end if;
+
+  if    hcnt = hcnt_base+0     then hsync1 <= '0';
+  elsif hcnt = hcnt_base+3     then hsync1 <= '1';
+  elsif hcnt = hcnt_base+32-64 then hsync1 <= '0';
+  elsif hcnt = hcnt_base+35-64 then hsync1 <= '1';
+  end if;
+
+  if    hcnt = hcnt_base+0        then hsync2 <= '0';
+  elsif hcnt = hcnt_base+32-3-64  then hsync2 <= '1';
+  elsif hcnt = hcnt_base+32-64    then hsync2 <= '0';
+  elsif hcnt = hcnt_base+64-3-128 then hsync2 <= '1';
+  end if;
+  
+  if hcnt = 63 and pixel_cnt = 5 then
+	 if vcnt = 495 then                     -- 503 with vcnt max = F4
+	   vsync_cnt := X"0";                   -- 499 with F8, 495 with FC
+    else
+      if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + '1'; end if;
+    end if;
+  end if;	 
+
+  if    vsync_cnt = 0 then csync <= hsync1;
+  elsif vsync_cnt = 1 then csync <= hsync1;
+  elsif vsync_cnt = 2 then csync <= hsync1;
+  elsif vsync_cnt = 3 then csync <= hsync2;
+  elsif vsync_cnt = 4 then csync <= hsync2;
+  elsif vsync_cnt = 5 then csync <= hsync2;
+  elsif vsync_cnt = 6 then csync <= hsync1;
+  elsif vsync_cnt = 7 then csync <= hsync1;
+  elsif vsync_cnt = 8 then csync <= hsync1;
+  else                     csync <= hsync0;
+  end if;
+
+  if    hcnt = hcnt_base-2     then hblank <= '1'; 
+  elsif hcnt = hcnt_base+11-64 then hblank <= '0';
+  end if;
+
+  if    vcnt = 492 then vblank <= '1';   -- 492 ok
+  elsif vcnt = 262 then vblank <= '0';   -- 262 ok 
+  end if;
+
+  -- external sync and blank outputs
+  video_blankn <= not (hblank or vblank);
+
+  video_hs <= hsync0;
+  
+  if    vsync_cnt = 0 then video_vs <= '0';
+  elsif vsync_cnt = 8 then video_vs <= '1';
+  end if;
+
+end if;
+end process;
+
+-- sound board
+defender_sound_board : entity work.defender_sound_board
+port map(
+ clk_1p79      => clk_1p79,
+ clk_0p89      => clk_0p89,
+ reset         => reset,
+ select_sound  => select_sound,
+ audio_out     => audio_out,
+ 
+ dbg_cpu_addr  => open --dbg_cpu_addr
+);
+
+end struct;
--- a/Hardware/Jin/rtl/defender_cmos_ram.vhd
+++ b/Hardware/Jin/rtl/defender_cmos_ram.vhd
@@ -0,0 +1,163 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr) 
+-- http://darfpga.blogspot.fr
+--   Remove address register when writing
+--
+-- Modifies Octiber 2017 by Dar 
+--   Add init data with defender cmos value
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd init with defender cmos value
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity defender_cmos_ram is
+	generic (
+		dWidth : integer := 8;  -- must be 4 for defender_cmos_ram
+		aWidth : integer := 10  -- must be 8 for defender_cmos_ram
+	);
+	port (
+		clk : in std_logic;
+		we : in std_logic;
+		addr : in std_logic_vector((aWidth-1) downto 0);
+		d : in std_logic_vector((dWidth-1) downto 0);
+		q : out std_logic_vector((dWidth-1) downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+-- defender cmos data
+-- (ram is 128x4 => only 4 bits/address, that is only 1 hex digit/address)
+--
+-- @      values             - (fonction) meaning
+
+--	0       0                 - ?
+-- 1       0005              - (01) coins left
+-- 5       0000              - (02) coins center
+-- 9       0000              - (03) coins right
+-- 13      0005              - (04) total paid
+-- 17      0000              - (05) ships won
+---21      0000              - (06) total time
+-- 25      0003              - (07) total ships
+
+-- -- 8 entries of 6 digits highscore + 3 ascii letters
+
+-- 29      021270 44 52 4A   
+-- 41      018315 53 41 4D
+-- 53      015920 4C 45 44
+-- 65      014285 50 47 44
+-- 77      012520 43 52 42
+-- 89      011035 4D 52 53
+-- 101     008265 53 53 52
+-- 113     006010 54 4D 48 
+
+-- 125     00                - credits
+-- 127     5                 - ?
+
+-- -- protected data writeable only with coin door opened 
+
+-- 128     A                 - ?
+-- 129     0100              - (08) bonus ship level
+-- 133     03                - (09) nb ships
+-- 135     03                - (10) coinage select
+-- 137     01                - (11) left coin mult
+-- 139     04                - (12) center coin mult
+-- 141     01                - (13) right coin mult
+-- 143     01                - (14) coins for credit
+-- 145     00                - (15) coins for bonus
+-- 147     00                - (16) minimum coins
+-- 149     00                - (17) free play
+-- 151     05                - (18) game adjust 1  Stating difficulty 0=lib; 1=mod; 2=cons
+-- 153     15                - (19) game adjust 2  Progessive wave diff. limit > 4-25
+-- 155     01                - (20) game adjust 3  Background sound 0=off; 1=on
+-- 157     05                - (21) game adjust 4  Planet restore wave number
+-- 159     00                - (22) game adjust 5
+-- 161     00                - (23) game adjust 6
+-- 163     00                - (24) game adjust 7
+-- 165     00                - (25) game adjust 8
+-- 167     00                - (26) game adjust 9
+-- 169     00                - (27) game adjust 10
+
+-- 171     00000             - ?
+-- 176     0000000000000000  - ?
+-- 192     0000000000000000  - ?
+--	208     0000000000000000  - ?
+--	224     0000000000000000  - ?
+--	240     0000000000000000  - ?
+
+
+architecture rtl of defender_cmos_ram is
+	subtype addressRange is integer range 0 to ((2**aWidth)-1);
+	type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+	
+	signal ram: ramDef := (
+	   X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"2",X"1",
+		X"2",X"7",X"0",X"4",X"4",X"5",X"2",X"4",X"A",X"0",X"1",X"8",X"3",X"1",X"5",X"5",
+		X"3",X"4",X"1",X"4",X"D",X"0",X"1",X"5",X"9",X"2",X"0",X"4",X"C",X"4",X"5",X"4",
+		X"4",X"0",X"1",X"4",X"2",X"8",X"5",X"5",X"0",X"4",X"7",X"4",X"4",X"0",X"1",X"2",
+		X"5",X"2",X"0",X"4",X"3",X"5",X"2",X"4",X"2",X"0",X"1",X"1",X"0",X"3",X"5",X"4",
+		X"D",X"5",X"2",X"5",X"3",X"0",X"0",X"8",X"2",X"6",X"5",X"5",X"3",X"5",X"3",X"5",
+		X"2",X"0",X"0",X"6",X"0",X"1",X"0",X"5",X"4",X"4",X"D",X"4",X"8",X"0",X"0",X"5",
+		X"A",X"0",X"1",X"0",X"0",X"0",X"3",X"0",X"3",X"0",X"1",X"0",X"4",X"0",X"1",X"0",
+		X"1",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"5",X"1",X"5",X"0",X"1",X"0",X"5",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0");
+
+	
+	signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+	signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+--	q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if we = '1' then
+				ram(to_integer(unsigned(addr))) <= d;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+	begin
+		if rising_edge(clk) then
+--			qReg <= ram(to_integer(unsigned(rAddrReg)));
+--			rAddrReg <= addr;
+----			qReg <= ram(to_integer(unsigned(addr)));
+      q <= ram(to_integer(unsigned(addr)));
+		end if;
+	end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+
--- a/Hardware/Jin/rtl/defender_decoder_2.vhd
+++ b/Hardware/Jin/rtl/defender_decoder_2.vhd
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity defender_decoder_2 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(8 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of defender_decoder_2 is
+	type rom is array(0 to  511) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"40",X"80",X"01",X"41",X"81",X"02",X"42",X"82",X"03",X"43",X"83",X"04",X"44",X"84",X"05",
+		X"45",X"85",X"06",X"46",X"86",X"07",X"47",X"87",X"08",X"48",X"88",X"09",X"49",X"89",X"0A",X"4A",
+		X"8A",X"0B",X"4B",X"8B",X"0C",X"4C",X"8C",X"0D",X"4D",X"8D",X"0E",X"4E",X"8E",X"0F",X"4F",X"8F",
+		X"10",X"50",X"90",X"11",X"51",X"91",X"12",X"52",X"92",X"13",X"53",X"93",X"14",X"54",X"94",X"15",
+		X"55",X"95",X"16",X"56",X"96",X"17",X"57",X"97",X"18",X"58",X"98",X"19",X"59",X"99",X"1A",X"5A",
+		X"9A",X"1B",X"5B",X"9B",X"1C",X"5C",X"9C",X"1D",X"5D",X"9D",X"1E",X"5E",X"9E",X"1F",X"5F",X"9F",
+		X"20",X"60",X"A0",X"21",X"61",X"A1",X"22",X"62",X"A2",X"23",X"63",X"A3",X"24",X"64",X"A4",X"25",
+		X"65",X"A5",X"26",X"66",X"A6",X"27",X"67",X"A7",X"28",X"68",X"A8",X"29",X"69",X"A9",X"2A",X"6A",
+		X"AA",X"2B",X"6B",X"AB",X"2C",X"6C",X"AC",X"2D",X"6D",X"AD",X"2E",X"6E",X"AE",X"2F",X"6F",X"AF",
+		X"30",X"70",X"B0",X"31",X"71",X"B1",X"32",X"72",X"B2",X"33",X"73",X"B3",X"34",X"74",X"B4",X"35",
+		X"75",X"B5",X"36",X"76",X"B6",X"37",X"77",X"B7",X"38",X"78",X"B8",X"39",X"79",X"B9",X"3A",X"7A",
+		X"BA",X"3B",X"7B",X"BB",X"3C",X"7C",X"BC",X"3D",X"7D",X"BD",X"3E",X"7E",X"BE",X"3F",X"7F",X"BF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"40",X"80",X"01",X"41",X"72",X"32",X"B1",X"71",X"31",X"B0",X"70",X"30",X"AF",X"6F",X"2F",
+		X"AE",X"6E",X"2E",X"AD",X"6D",X"2D",X"AC",X"6C",X"2C",X"AB",X"6B",X"2B",X"AA",X"6A",X"2A",X"A9",
+		X"69",X"29",X"A8",X"68",X"28",X"A7",X"67",X"27",X"A6",X"66",X"26",X"A5",X"65",X"25",X"A4",X"64",
+		X"24",X"A3",X"63",X"23",X"A2",X"62",X"22",X"A1",X"61",X"21",X"A0",X"60",X"20",X"9F",X"5F",X"1F",
+		X"9E",X"5E",X"1E",X"9D",X"5D",X"1D",X"9C",X"5C",X"1C",X"9B",X"5B",X"1B",X"9A",X"5A",X"1A",X"99",
+		X"59",X"19",X"98",X"58",X"18",X"97",X"57",X"17",X"96",X"56",X"16",X"95",X"55",X"15",X"94",X"54",
+		X"14",X"93",X"53",X"13",X"92",X"52",X"12",X"91",X"51",X"11",X"90",X"50",X"10",X"8F",X"4F",X"0F",
+		X"8E",X"4E",X"0E",X"8D",X"4D",X"0D",X"8C",X"4C",X"0C",X"8B",X"4B",X"0B",X"8A",X"4A",X"0A",X"89",
+		X"49",X"09",X"88",X"48",X"08",X"87",X"47",X"07",X"86",X"46",X"06",X"85",X"45",X"05",X"84",X"44",
+		X"04",X"83",X"43",X"03",X"82",X"42",X"02",X"81",X"B2",X"33",X"73",X"B3",X"34",X"74",X"B4",X"35",
+		X"75",X"B5",X"36",X"76",X"B6",X"37",X"77",X"B7",X"38",X"78",X"B8",X"39",X"79",X"B9",X"3A",X"7A",
+		X"BA",X"3B",X"7B",X"BB",X"3C",X"7C",X"BC",X"3D",X"7D",X"BD",X"3E",X"7E",X"BE",X"3F",X"7F",X"BF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
--- a/Hardware/Jin/rtl/defender_decoder_3.vhd
+++ b/Hardware/Jin/rtl/defender_decoder_3.vhd
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity defender_decoder_3 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(8 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of defender_decoder_3 is
+	type rom is array(0 to  511) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",
+		X"10",X"11",X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19",X"1A",X"1B",X"1C",X"1D",X"1E",X"1F",
+		X"20",X"21",X"22",X"23",X"24",X"25",X"26",X"27",X"28",X"29",X"2A",X"2B",X"2C",X"2D",X"2E",X"2F",
+		X"30",X"31",X"32",X"33",X"34",X"35",X"36",X"37",X"38",X"39",X"3A",X"3B",X"3C",X"3D",X"3E",X"3F",
+		X"40",X"41",X"42",X"43",X"44",X"45",X"46",X"47",X"48",X"49",X"4A",X"4B",X"4C",X"4D",X"4E",X"4F",
+		X"50",X"51",X"52",X"53",X"54",X"55",X"56",X"57",X"58",X"59",X"5A",X"5B",X"5C",X"5D",X"5E",X"5F",
+		X"60",X"61",X"62",X"63",X"64",X"65",X"66",X"67",X"68",X"69",X"6A",X"6B",X"6C",X"6D",X"6E",X"6F",
+		X"70",X"71",X"72",X"73",X"74",X"75",X"76",X"77",X"78",X"79",X"7A",X"7B",X"7C",X"7D",X"7E",X"7F",
+		X"80",X"81",X"82",X"83",X"84",X"85",X"86",X"87",X"88",X"89",X"8A",X"8B",X"8C",X"8D",X"8E",X"8F",
+		X"90",X"91",X"92",X"93",X"94",X"95",X"96",X"97",X"98",X"99",X"9A",X"9B",X"9C",X"9D",X"9E",X"9F",
+		X"A0",X"A1",X"A2",X"A3",X"A4",X"A5",X"A6",X"A7",X"A8",X"A9",X"AA",X"AB",X"AC",X"AD",X"AE",X"AF",
+		X"B0",X"B1",X"B2",X"B3",X"B4",X"B5",X"B6",X"B7",X"B8",X"B9",X"BA",X"BB",X"BC",X"BD",X"BE",X"BF",
+		X"C0",X"C1",X"C2",X"C3",X"C4",X"C5",X"C6",X"C7",X"C8",X"C9",X"CA",X"CB",X"CC",X"CD",X"CE",X"CF",
+		X"D0",X"D1",X"D2",X"D3",X"D4",X"D5",X"D6",X"D7",X"D8",X"D9",X"DA",X"DB",X"DC",X"DD",X"DE",X"DF",
+		X"E0",X"E1",X"E2",X"E3",X"E4",X"E5",X"E6",X"E7",X"E8",X"E9",X"EA",X"EB",X"EC",X"ED",X"EE",X"EF",
+		X"F0",X"F1",X"F2",X"F3",X"F4",X"F5",X"F6",X"F7",X"F8",X"F9",X"FA",X"FB",X"FC",X"FD",X"FE",X"FF",
+		X"FB",X"FA",X"F9",X"F8",X"F7",X"F6",X"F5",X"F4",X"F3",X"F2",X"F1",X"F0",X"EF",X"EE",X"ED",X"EC",
+		X"EB",X"EA",X"E9",X"E8",X"E7",X"E6",X"E5",X"E4",X"E3",X"E2",X"E1",X"E0",X"DF",X"DE",X"DD",X"DC",
+		X"DB",X"DA",X"D9",X"D8",X"D7",X"D6",X"D5",X"D4",X"D3",X"D2",X"D1",X"D0",X"CF",X"CE",X"CD",X"CC",
+		X"CB",X"CA",X"C9",X"C8",X"C7",X"C6",X"C5",X"C4",X"C3",X"C2",X"C1",X"C0",X"BF",X"BE",X"BD",X"BC",
+		X"BB",X"BA",X"B9",X"B8",X"B7",X"B6",X"B5",X"B4",X"B3",X"B2",X"B1",X"B0",X"AF",X"AE",X"AD",X"AC",
+		X"AB",X"AA",X"A9",X"A8",X"A7",X"A6",X"A5",X"A4",X"A3",X"A2",X"A1",X"A0",X"9F",X"9E",X"9D",X"9C",
+		X"9B",X"9A",X"99",X"98",X"97",X"96",X"95",X"94",X"93",X"92",X"91",X"90",X"8F",X"8E",X"8D",X"8C",
+		X"8B",X"8A",X"89",X"88",X"87",X"86",X"85",X"84",X"83",X"82",X"81",X"80",X"7F",X"7E",X"7D",X"7C",
+		X"7B",X"7A",X"79",X"78",X"77",X"76",X"75",X"74",X"73",X"72",X"71",X"70",X"6F",X"6E",X"6D",X"6C",
+		X"6B",X"6A",X"69",X"68",X"67",X"66",X"65",X"64",X"63",X"62",X"61",X"60",X"5F",X"5E",X"5D",X"5C",
+		X"5B",X"5A",X"59",X"58",X"57",X"56",X"55",X"54",X"53",X"52",X"51",X"50",X"4F",X"4E",X"4D",X"4C",
+		X"4B",X"4A",X"49",X"48",X"47",X"46",X"45",X"44",X"43",X"42",X"41",X"40",X"3F",X"3E",X"3D",X"3C",
+		X"3B",X"3A",X"39",X"38",X"37",X"36",X"35",X"34",X"33",X"32",X"31",X"30",X"2F",X"2E",X"2D",X"2C",
+		X"2B",X"2A",X"29",X"28",X"27",X"26",X"25",X"24",X"23",X"22",X"21",X"20",X"1F",X"1E",X"1D",X"1C",
+		X"1B",X"1A",X"19",X"18",X"17",X"16",X"15",X"14",X"13",X"12",X"11",X"10",X"0F",X"0E",X"0D",X"0C",
+		X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00",X"FC",X"FD",X"FE",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
--- a/Hardware/Jin/rtl/defender_prog.vhd
+++ b/Hardware/Jin/rtl/defender_prog.vhd
--- a/Hardware/Jin/rtl/defender_sound.vhd
+++ b/Hardware/Jin/rtl/defender_sound.vhd
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity defender_sound is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of defender_sound is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"FF",X"0F",X"8E",X"00",X"7F",X"CE",X"04",X"00",X"6F",X"01",X"6F",X"03",X"86",X"FF",X"A7",X"00",
+		X"6F",X"02",X"86",X"37",X"A7",X"03",X"86",X"3C",X"A7",X"01",X"97",X"09",X"4F",X"97",X"07",X"97",
+		X"04",X"97",X"05",X"97",X"06",X"97",X"08",X"0E",X"20",X"FE",X"16",X"48",X"48",X"48",X"1B",X"CE",
+		X"00",X"13",X"DF",X"0F",X"CE",X"FD",X"76",X"BD",X"FD",X"21",X"C6",X"09",X"7E",X"FB",X"0A",X"96",
+		X"1B",X"B7",X"04",X"00",X"96",X"13",X"97",X"1C",X"96",X"14",X"97",X"1D",X"DE",X"18",X"96",X"1C",
+		X"73",X"04",X"00",X"09",X"27",X"10",X"4A",X"26",X"FA",X"73",X"04",X"00",X"96",X"1D",X"09",X"27",
+		X"05",X"4A",X"26",X"FA",X"20",X"E8",X"B6",X"04",X"00",X"2B",X"01",X"43",X"8B",X"00",X"B7",X"04",
+		X"00",X"96",X"1C",X"9B",X"15",X"97",X"1C",X"96",X"1D",X"9B",X"16",X"97",X"1D",X"91",X"17",X"26",
+		X"CB",X"96",X"1A",X"27",X"06",X"9B",X"13",X"97",X"13",X"26",X"B9",X"39",X"86",X"01",X"97",X"1A",
+		X"C6",X"03",X"20",X"0A",X"86",X"FE",X"97",X"1A",X"86",X"C0",X"C6",X"10",X"20",X"00",X"97",X"19",
+		X"86",X"FF",X"B7",X"04",X"00",X"D7",X"15",X"D6",X"15",X"96",X"0A",X"44",X"44",X"44",X"98",X"0A",
+		X"44",X"76",X"00",X"09",X"76",X"00",X"0A",X"24",X"03",X"73",X"04",X"00",X"96",X"19",X"4A",X"26",
+		X"FD",X"5A",X"26",X"E5",X"96",X"19",X"9B",X"1A",X"97",X"19",X"26",X"DB",X"39",X"86",X"20",X"97",
+		X"15",X"97",X"18",X"86",X"01",X"CE",X"00",X"01",X"C6",X"FF",X"20",X"00",X"97",X"13",X"DF",X"16",
+		X"D7",X"14",X"D6",X"15",X"96",X"0A",X"44",X"44",X"44",X"98",X"0A",X"44",X"76",X"00",X"09",X"76",
+		X"00",X"0A",X"86",X"00",X"24",X"02",X"96",X"14",X"B7",X"04",X"00",X"DE",X"16",X"09",X"26",X"FD",
+		X"5A",X"26",X"E1",X"D6",X"14",X"D0",X"13",X"27",X"09",X"DE",X"16",X"08",X"96",X"18",X"27",X"D0",
+		X"20",X"CC",X"39",X"C6",X"01",X"D7",X"04",X"4F",X"97",X"19",X"20",X"14",X"4F",X"97",X"19",X"C6",
+		X"03",X"20",X"0D",X"86",X"01",X"97",X"19",X"CE",X"03",X"E8",X"86",X"01",X"C6",X"FF",X"20",X"00",
+		X"97",X"18",X"D7",X"13",X"DF",X"16",X"7F",X"00",X"15",X"DE",X"16",X"B6",X"04",X"00",X"16",X"54",
+		X"54",X"54",X"D8",X"0A",X"54",X"76",X"00",X"09",X"76",X"00",X"0A",X"D6",X"13",X"7D",X"00",X"19",
+		X"27",X"02",X"D4",X"09",X"D7",X"14",X"D6",X"15",X"91",X"0A",X"22",X"12",X"09",X"27",X"26",X"B7",
+		X"04",X"00",X"DB",X"15",X"99",X"14",X"25",X"16",X"91",X"0A",X"23",X"F0",X"20",X"10",X"09",X"27",
+		X"14",X"B7",X"04",X"00",X"D0",X"15",X"92",X"14",X"25",X"04",X"91",X"0A",X"22",X"F0",X"96",X"0A",
+		X"B7",X"04",X"00",X"20",X"B9",X"D6",X"18",X"27",X"B5",X"96",X"13",X"D6",X"15",X"44",X"56",X"44",
+		X"56",X"44",X"56",X"43",X"50",X"82",X"FF",X"DB",X"15",X"99",X"13",X"D7",X"15",X"97",X"13",X"26",
+		X"98",X"C1",X"07",X"26",X"94",X"39",X"86",X"FD",X"97",X"0F",X"CE",X"00",X"64",X"DF",X"0B",X"DB",
+		X"0C",X"96",X"11",X"99",X"0B",X"97",X"11",X"DE",X"0B",X"25",X"04",X"20",X"00",X"20",X"03",X"08",
+		X"27",X"11",X"DF",X"0B",X"84",X"0F",X"8B",X"9A",X"97",X"10",X"DE",X"0F",X"A6",X"00",X"B7",X"04",
+		X"00",X"20",X"DC",X"39",X"4F",X"B7",X"04",X"00",X"97",X"11",X"4F",X"91",X"11",X"26",X"03",X"73",
+		X"04",X"00",X"C6",X"12",X"5A",X"26",X"FD",X"4C",X"2A",X"F1",X"73",X"04",X"00",X"7C",X"00",X"11",
+		X"2A",X"E8",X"39",X"CE",X"00",X"13",X"6F",X"00",X"08",X"8C",X"00",X"1B",X"26",X"F8",X"86",X"40",
+		X"97",X"13",X"CE",X"00",X"13",X"86",X"80",X"97",X"11",X"5F",X"A6",X"01",X"AB",X"00",X"A7",X"01",
+		X"2A",X"02",X"DB",X"11",X"74",X"00",X"11",X"08",X"08",X"8C",X"00",X"1B",X"26",X"EC",X"F7",X"04",
+		X"00",X"7C",X"00",X"12",X"26",X"DC",X"CE",X"00",X"13",X"5F",X"A6",X"00",X"27",X"0B",X"81",X"37",
+		X"26",X"04",X"C6",X"41",X"E7",X"02",X"6A",X"00",X"5C",X"08",X"08",X"8C",X"00",X"1B",X"26",X"EA",
+		X"5D",X"26",X"BF",X"39",X"7A",X"00",X"08",X"39",X"7F",X"00",X"08",X"97",X"11",X"CE",X"FD",X"AA",
+		X"A6",X"00",X"27",X"2D",X"7A",X"00",X"11",X"27",X"06",X"4C",X"BD",X"FD",X"21",X"20",X"F1",X"08",
+		X"DF",X"0F",X"BD",X"FD",X"21",X"DF",X"0D",X"DE",X"0F",X"A6",X"00",X"97",X"15",X"A6",X"01",X"EE",
+		X"02",X"DF",X"13",X"8D",X"3E",X"DE",X"0F",X"08",X"08",X"08",X"08",X"DF",X"0F",X"9C",X"0D",X"26",
+		X"E8",X"7E",X"FD",X"0E",X"86",X"03",X"97",X"08",X"39",X"7A",X"00",X"08",X"27",X"0C",X"D6",X"15",
+		X"58",X"58",X"58",X"58",X"1B",X"97",X"15",X"4F",X"20",X"FE",X"4A",X"81",X"0B",X"23",X"01",X"4F",
+		X"CE",X"FE",X"41",X"BD",X"FD",X"21",X"A6",X"00",X"CE",X"FF",X"FF",X"DF",X"13",X"8D",X"04",X"8D",
+		X"2A",X"20",X"FC",X"CE",X"00",X"16",X"81",X"00",X"27",X"15",X"81",X"03",X"27",X"09",X"C6",X"01",
+		X"E7",X"00",X"08",X"80",X"02",X"20",X"EF",X"C6",X"91",X"E7",X"00",X"6F",X"01",X"08",X"08",X"C6",
+		X"7E",X"E7",X"00",X"C6",X"FA",X"E7",X"01",X"C6",X"DD",X"E7",X"02",X"DE",X"13",X"4F",X"F6",X"00",
+		X"12",X"5C",X"D7",X"12",X"D4",X"15",X"54",X"89",X"00",X"54",X"89",X"00",X"54",X"89",X"00",X"54",
+		X"89",X"00",X"54",X"89",X"00",X"54",X"89",X"00",X"54",X"89",X"00",X"1B",X"48",X"48",X"48",X"48",
+		X"B7",X"04",X"00",X"09",X"27",X"03",X"7E",X"00",X"16",X"39",X"36",X"A6",X"00",X"DF",X"0D",X"DE",
+		X"0F",X"A7",X"00",X"08",X"DF",X"0F",X"DE",X"0D",X"08",X"5A",X"26",X"EF",X"32",X"39",X"4F",X"97",
+		X"04",X"97",X"05",X"39",X"7F",X"00",X"04",X"96",X"05",X"84",X"7F",X"81",X"1D",X"26",X"01",X"4F",
+		X"4C",X"97",X"05",X"39",X"86",X"0E",X"BD",X"FB",X"81",X"96",X"05",X"48",X"48",X"43",X"BD",X"FC",
+		X"39",X"7C",X"00",X"17",X"BD",X"FC",X"3B",X"20",X"F8",X"86",X"03",X"BD",X"F8",X"2A",X"D6",X"06",
+		X"C1",X"1F",X"26",X"01",X"5F",X"5C",X"D7",X"06",X"86",X"20",X"10",X"5F",X"81",X"14",X"23",X"05",
+		X"CB",X"0E",X"4A",X"20",X"F7",X"CB",X"05",X"4A",X"26",X"FB",X"D7",X"13",X"BD",X"F8",X"3F",X"20",
+		X"FB",X"96",X"07",X"26",X"09",X"7C",X"00",X"07",X"86",X"0D",X"8D",X"05",X"20",X"69",X"7E",X"FC",
+		X"2E",X"16",X"58",X"1B",X"1B",X"1B",X"CE",X"FE",X"EC",X"BD",X"FD",X"21",X"A6",X"00",X"16",X"84",
+		X"0F",X"97",X"14",X"54",X"54",X"54",X"54",X"D7",X"13",X"A6",X"01",X"16",X"54",X"54",X"54",X"54",
+		X"D7",X"15",X"84",X"0F",X"97",X"11",X"DF",X"0B",X"CE",X"FE",X"4D",X"7A",X"00",X"11",X"2B",X"08",
+		X"A6",X"00",X"4C",X"BD",X"FD",X"21",X"20",X"F3",X"DF",X"18",X"BD",X"FC",X"75",X"DE",X"0B",X"A6",
+		X"02",X"97",X"1A",X"BD",X"FC",X"87",X"DE",X"0B",X"A6",X"03",X"97",X"16",X"A6",X"04",X"97",X"17",
+		X"A6",X"05",X"16",X"A6",X"06",X"CE",X"FF",X"55",X"BD",X"FD",X"21",X"17",X"DF",X"1B",X"7F",X"00",
+		X"23",X"BD",X"FD",X"21",X"DF",X"1D",X"39",X"96",X"13",X"97",X"22",X"DE",X"1B",X"DF",X"0D",X"DE",
+		X"0D",X"A6",X"00",X"9B",X"23",X"97",X"21",X"9C",X"1D",X"27",X"26",X"D6",X"14",X"08",X"DF",X"0D",
+		X"CE",X"00",X"24",X"96",X"21",X"4A",X"26",X"FD",X"A6",X"00",X"B7",X"04",X"00",X"08",X"9C",X"1F",
+		X"26",X"F1",X"5A",X"27",X"DA",X"08",X"09",X"08",X"09",X"08",X"09",X"08",X"09",X"01",X"01",X"20",
+		X"DF",X"96",X"15",X"8D",X"62",X"7A",X"00",X"22",X"26",X"C1",X"96",X"07",X"26",X"46",X"96",X"16",
+		X"27",X"42",X"7A",X"00",X"17",X"27",X"3D",X"9B",X"23",X"97",X"23",X"DE",X"1B",X"5F",X"96",X"23",
+		X"7D",X"00",X"16",X"2B",X"06",X"AB",X"00",X"25",X"08",X"20",X"0B",X"AB",X"00",X"27",X"02",X"25",
+		X"05",X"5D",X"27",X"08",X"20",X"0F",X"5D",X"26",X"03",X"DF",X"1B",X"5C",X"08",X"9C",X"1D",X"26",
+		X"DD",X"5D",X"26",X"01",X"39",X"DF",X"1D",X"96",X"15",X"27",X"06",X"8D",X"08",X"96",X"1A",X"8D",
+		X"16",X"7E",X"FB",X"E7",X"39",X"CE",X"00",X"24",X"DF",X"0F",X"DE",X"18",X"E6",X"00",X"08",X"BD",
+		X"FB",X"0A",X"DE",X"0F",X"DF",X"1F",X"39",X"4D",X"27",X"2B",X"DE",X"18",X"DF",X"0D",X"CE",X"00",
+		X"24",X"97",X"12",X"DF",X"0F",X"DE",X"0D",X"D6",X"12",X"D7",X"11",X"E6",X"01",X"54",X"54",X"54",
+		X"54",X"08",X"DF",X"0D",X"DE",X"0F",X"A6",X"00",X"10",X"7A",X"00",X"11",X"26",X"FA",X"A7",X"00",
+		X"08",X"9C",X"1F",X"26",X"DE",X"39",X"8E",X"00",X"7F",X"B6",X"04",X"02",X"0E",X"43",X"84",X"1F",
+		X"D6",X"08",X"27",X"09",X"2A",X"03",X"BD",X"FA",X"48",X"4A",X"BD",X"FA",X"89",X"5F",X"81",X"0E",
+		X"27",X"02",X"D7",X"06",X"81",X"12",X"27",X"02",X"D7",X"07",X"F6",X"EF",X"FD",X"C1",X"7E",X"26",
+		X"03",X"BD",X"EF",X"FD",X"4D",X"27",X"27",X"4A",X"81",X"0C",X"22",X"08",X"BD",X"FB",X"81",X"BD",
+		X"FB",X"E7",X"20",X"1A",X"81",X"1B",X"22",X"0E",X"80",X"0D",X"48",X"CE",X"FD",X"58",X"8D",X"21",
+		X"EE",X"00",X"AD",X"00",X"20",X"08",X"80",X"1C",X"BD",X"F8",X"2A",X"BD",X"F8",X"3F",X"96",X"04",
+		X"9A",X"05",X"27",X"FE",X"4F",X"97",X"07",X"96",X"04",X"27",X"03",X"7E",X"F9",X"13",X"7E",X"FB",
+		X"34",X"DF",X"0D",X"9B",X"0E",X"97",X"0E",X"24",X"03",X"7C",X"00",X"0D",X"DE",X"0D",X"39",X"0F",
+		X"8E",X"00",X"7F",X"CE",X"FF",X"FF",X"5F",X"E9",X"00",X"09",X"8C",X"F8",X"00",X"26",X"F8",X"E1",
+		X"00",X"27",X"01",X"3E",X"86",X"01",X"BD",X"F8",X"2A",X"BD",X"F8",X"3F",X"F6",X"EF",X"FA",X"C1",
+		X"7E",X"26",X"DC",X"BD",X"EF",X"FA",X"20",X"D7",X"FB",X"49",X"F9",X"13",X"FB",X"24",X"F8",X"8C",
+		X"FB",X"71",X"FB",X"1E",X"F8",X"CD",X"F8",X"94",X"F9",X"1C",X"F9",X"23",X"F9",X"A6",X"F9",X"D4",
+		X"F9",X"F3",X"FA",X"44",X"FA",X"84",X"40",X"01",X"00",X"10",X"E1",X"00",X"80",X"FF",X"FF",X"28",
+		X"01",X"00",X"08",X"81",X"02",X"00",X"FF",X"FF",X"28",X"81",X"00",X"FC",X"01",X"02",X"00",X"FC",
+		X"FF",X"FF",X"01",X"00",X"18",X"41",X"04",X"80",X"00",X"FF",X"8C",X"5B",X"B6",X"40",X"BF",X"49",
+		X"A4",X"73",X"73",X"A4",X"49",X"BF",X"40",X"B6",X"5B",X"8C",X"0C",X"7F",X"1D",X"0F",X"FB",X"7F",
+		X"23",X"0F",X"15",X"FE",X"08",X"50",X"8B",X"88",X"3E",X"3F",X"02",X"3E",X"7C",X"04",X"03",X"FF",
+		X"3E",X"3F",X"2C",X"E2",X"7C",X"12",X"0D",X"74",X"7C",X"0D",X"0E",X"41",X"7C",X"23",X"0B",X"50",
+		X"7C",X"1D",X"29",X"F2",X"7C",X"3F",X"02",X"3E",X"F8",X"04",X"03",X"FF",X"7C",X"3F",X"2C",X"E2",
+		X"F8",X"12",X"0D",X"74",X"F8",X"0D",X"0E",X"41",X"F8",X"23",X"0B",X"50",X"F8",X"1D",X"2F",X"F2",
+		X"F8",X"23",X"05",X"A8",X"F8",X"12",X"06",X"BA",X"F8",X"04",X"07",X"FF",X"7C",X"37",X"04",X"C1",
+		X"7C",X"23",X"05",X"A8",X"7C",X"12",X"06",X"BA",X"3E",X"04",X"07",X"FF",X"3E",X"37",X"04",X"C1",
+		X"3E",X"23",X"05",X"A8",X"1F",X"12",X"06",X"BA",X"1F",X"04",X"07",X"FF",X"1F",X"37",X"04",X"C1",
+		X"1F",X"23",X"16",X"A0",X"FE",X"1D",X"17",X"F9",X"7F",X"37",X"13",X"06",X"7F",X"3F",X"08",X"FA",
+		X"FE",X"04",X"0F",X"FF",X"FE",X"0D",X"0E",X"41",X"FE",X"23",X"0B",X"50",X"FE",X"1D",X"5F",X"E4",
+		X"00",X"47",X"3F",X"37",X"30",X"29",X"23",X"1D",X"17",X"12",X"0D",X"08",X"04",X"08",X"7F",X"D9",
+		X"FF",X"D9",X"7F",X"24",X"00",X"24",X"08",X"00",X"40",X"80",X"00",X"FF",X"00",X"80",X"40",X"10",
+		X"7F",X"B0",X"D9",X"F5",X"FF",X"F5",X"D9",X"B0",X"7F",X"4E",X"24",X"09",X"00",X"09",X"24",X"4E",
+		X"10",X"7F",X"C5",X"EC",X"E7",X"BF",X"8D",X"6D",X"6A",X"7F",X"94",X"92",X"71",X"40",X"17",X"12",
+		X"39",X"10",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00",
+		X"00",X"00",X"48",X"8A",X"95",X"A0",X"AB",X"B5",X"BF",X"C8",X"D1",X"DA",X"E1",X"E8",X"EE",X"F3",
+		X"F7",X"FB",X"FD",X"FE",X"FF",X"FE",X"FD",X"FB",X"F7",X"F3",X"EE",X"E8",X"E1",X"DA",X"D1",X"C8",
+		X"BF",X"B5",X"AB",X"A0",X"95",X"8A",X"7F",X"75",X"6A",X"5F",X"54",X"4A",X"40",X"37",X"2E",X"25",
+		X"1E",X"17",X"11",X"0C",X"08",X"04",X"02",X"01",X"00",X"01",X"02",X"04",X"08",X"0C",X"11",X"17",
+		X"1E",X"25",X"2E",X"37",X"40",X"4A",X"54",X"5F",X"6A",X"75",X"7F",X"10",X"59",X"7B",X"98",X"AC",
+		X"B3",X"AC",X"98",X"7B",X"59",X"37",X"19",X"06",X"00",X"06",X"19",X"37",X"81",X"24",X"00",X"00",
+		X"00",X"16",X"31",X"12",X"05",X"1A",X"FF",X"00",X"27",X"6D",X"11",X"05",X"11",X"01",X"0F",X"01",
+		X"47",X"11",X"31",X"00",X"01",X"00",X"0D",X"1B",X"F4",X"12",X"00",X"00",X"00",X"14",X"47",X"41",
+		X"45",X"00",X"00",X"00",X"0F",X"5B",X"21",X"35",X"11",X"FF",X"00",X"0D",X"1B",X"15",X"00",X"00",
+		X"FD",X"00",X"01",X"69",X"31",X"11",X"00",X"01",X"00",X"03",X"6A",X"01",X"15",X"01",X"01",X"01",
+		X"01",X"47",X"F6",X"53",X"03",X"00",X"02",X"06",X"94",X"6A",X"10",X"02",X"00",X"02",X"06",X"9A",
+		X"1F",X"12",X"00",X"FF",X"10",X"04",X"69",X"31",X"11",X"00",X"FF",X"00",X"0D",X"00",X"12",X"06",
+		X"00",X"FF",X"01",X"09",X"28",X"A0",X"98",X"90",X"88",X"80",X"78",X"70",X"68",X"60",X"58",X"50",
+		X"44",X"40",X"01",X"01",X"02",X"02",X"04",X"04",X"08",X"08",X"10",X"10",X"30",X"60",X"C0",X"E0",
+		X"01",X"01",X"02",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0C",X"80",X"7C",X"78",
+		X"74",X"70",X"74",X"78",X"7C",X"80",X"01",X"01",X"02",X"02",X"04",X"04",X"08",X"08",X"10",X"20",
+		X"28",X"30",X"38",X"40",X"48",X"50",X"60",X"70",X"80",X"A0",X"B0",X"C0",X"08",X"40",X"08",X"40",
+		X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",X"08",X"40",
+		X"01",X"02",X"04",X"08",X"09",X"0A",X"0B",X"0C",X"0E",X"0F",X"10",X"12",X"14",X"16",X"40",X"10",
+		X"08",X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"03",X"03",X"04",X"04",X"05",X"06",X"08",X"0A",
+		X"0C",X"10",X"14",X"18",X"20",X"30",X"40",X"50",X"40",X"30",X"20",X"10",X"0C",X"0A",X"08",X"07",
+		X"06",X"05",X"04",X"03",X"02",X"02",X"01",X"01",X"01",X"07",X"08",X"09",X"0A",X"0C",X"08",X"17",
+		X"18",X"19",X"1A",X"1B",X"1C",X"00",X"00",X"00",X"FC",X"B6",X"F8",X"01",X"FD",X"2F",X"F8",X"01");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
--- a/Hardware/Jin/rtl/defender_sound_board.vhd
+++ b/Hardware/Jin/rtl/defender_sound_board.vhd
@@ -0,0 +1,186 @@
+---------------------------------------------------------------------------------
+-- Defender sound board by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- gen_ram.vhd 
+-------------------------------- 
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- cpu68 - Version 9th Jan 2004 0.8
+-- 6800/01 compatible CPU core 
+-- GNU public license - December 2002 : John E. Kent
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Version 0.0 -- 15/10/2017 -- 
+--		    initial version
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity defender_sound_board is
+port(
+ clk_1p79     : in std_logic;
+ clk_0p89     : in std_logic;
+ reset        : in std_logic;
+ 
+ select_sound : in std_logic_vector(5 downto 0);
+ audio_out    : out std_logic_vector( 7 downto 0);
+ 
+ dbg_cpu_addr : out std_logic_vector(15 downto 0)
+);
+end defender_sound_board;
+
+architecture struct of defender_sound_board is
+
+ signal reset_n   : std_logic;
+
+ signal cpu_clock  : std_logic;
+ signal cpu_addr   : std_logic_vector(15 downto 0);
+ signal cpu_di     : std_logic_vector( 7 downto 0);
+ signal cpu_do     : std_logic_vector( 7 downto 0);
+ signal cpu_rw     : std_logic;
+ signal cpu_irq    : std_logic;
+
+ signal wram_cs   : std_logic;
+ signal wram_we   : std_logic;
+ signal wram_do   : std_logic_vector( 7 downto 0);
+ 
+ signal rom_cs    : std_logic;
+ signal rom_do    : std_logic_vector( 7 downto 0);
+
+-- pia port a
+--      bit 0-7 audio output
+
+-- pia port b
+--      bit 0-4 select sound input (sel0-4)
+--      bit 5-6 switch sound/notes/speech on/off
+--      bit 7   sel5
+
+-- pia io ca/cb
+--      ca1 vdd
+--      cb1 sound trigger (sel0-5 = 1)
+--      ca2 speech data N/C
+--      cb2 speech clock N/C
+
+ signal pia_clock  : std_logic;
+ signal pia_rw_n   : std_logic;
+ signal pia_cs     : std_logic;
+ signal pia_irqa   : std_logic;
+ signal pia_irqb   : std_logic;
+ signal pia_do     : std_logic_vector( 7 downto 0);
+ signal pia_pa_o   : std_logic_vector( 7 downto 0);
+ signal pia_pb_i   : std_logic_vector( 7 downto 0);
+ signal pia_cb1_i  : std_logic;
+
+begin
+
+reset_n   <= not reset;
+
+dbg_cpu_addr <= cpu_addr;
+cpu_clock <= clk_0p89;
+
+
+-- pia cs
+wram_cs <= '1' when cpu_addr(15 downto  8) = X"00" else '0';                       -- 0000-007F
+pia_cs  <= '1' when cpu_addr(15 downto 12) = X"0" and cpu_addr(10) = '1' else '0'; -- 8400-8403 ? => 0400-0403
+rom_cs  <= '1' when cpu_addr(15 downto 12) = X"F" else '0';                        -- F800-FFFF
+	
+-- write enables
+wram_we <=    '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0';
+pia_rw_n <=   '0' when cpu_rw = '0' and cpu_clock = '1' and pia_cs = '1' else '1'; 
+
+-- mux cpu in data between roms/io/wram
+cpu_di <=
+	wram_do when wram_cs = '1' else
+	pia_do  when pia_cs = '1' else
+	rom_do when rom_cs = '1' else X"55";
+
+-- pia I/O
+pia_clock <= clk_1p79; -- 3p58/2
+audio_out <= pia_pa_o;
+
+pia_pb_i(4 downto 0) <= select_sound(4 downto 0);
+pia_pb_i(6 downto 5) <= "11"; -- assume DS1-1 and DS1-2 open
+pia_pb_i(7) <= '1'; -- Handshake to ? from rom board (drawings are confusing)
+
+-- pia Cb1
+pia_cb1_i <= '0' when select_sound = "111111" else '1';
+
+-- pia irqs to cpu
+cpu_irq  <= pia_irqa or pia_irqb;
+
+-- microprocessor 6800
+main_cpu : entity work.cpu68
+port map(	
+	clk      => cpu_clock,-- E clock input (falling edge)
+	rst      => reset,    -- reset input (active high)
+	rw       => cpu_rw,   -- read not write output
+	vma      => open,     -- valid memory address (active high)
+	address  => cpu_addr, -- address bus output
+	data_in  => cpu_di,   -- data bus input
+	data_out => cpu_do,   -- data bus output
+	hold     => '0',      -- hold input (active high) extend bus cycle
+	halt     => '0',      -- halt input (active high) grants DMA
+	irq      => cpu_irq,  -- interrupt request input (active high)
+	nmi      => '0',      -- non maskable interrupt request input (active high)
+	test_alu => open,
+	test_cc  => open
+);
+
+-- cpu program rom
+cpu_prog_rom : entity work.defender_sound
+port map(
+ clk  => clk_1p79,
+ addr => cpu_addr(10 downto 0),
+ data => rom_do
+);
+
+-- cpu wram 
+cpu_ram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 7)
+port map(
+ clk  => clk_1p79,
+ we   => wram_we,
+ addr => cpu_addr(6 downto 0),
+ d    => cpu_do,
+ q    => wram_do
+);
+
+-- pia 
+pia : entity work.pia6821
+port map
+(	
+	clk       	=> clk_1p79,
+	rst       	=> reset,
+	cs        	=> pia_cs,
+	rw        	=> pia_rw_n,
+	addr      	=> cpu_addr(1 downto 0),
+	data_in   	=> cpu_do,
+	data_out  	=> pia_do,
+	irqa      	=> pia_irqa,
+	irqb      	=> pia_irqb,
+	pa_i      	=> (others => '0'),
+	pa_o        => pia_pa_o,
+	pa_oe       => open,
+	ca1       	=> '1',
+	ca2_i      	=> '0',
+	ca2_o       => open,
+	ca2_oe      => open,
+	pb_i      	=> pia_pb_i,
+	pb_o        => open,
+	pb_oe       => open,
+	cb1       	=> pia_cb1_i,
+	cb2_i      	=> '0',
+	cb2_o       => open,
+	cb2_oe      => open
+);
+
+end struct;
--- a/Hardware/Jin/rtl/gen_ram.vhd
+++ b/Hardware/Jin/rtl/gen_ram.vhd
@@ -0,0 +1,84 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr) 
+-- http://darfpga.blogspot.fr
+--   Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity gen_ram is
+	generic (
+		dWidth : integer := 8;
+		aWidth : integer := 10
+	);
+	port (
+		clk : in std_logic;
+		we : in std_logic;
+		addr : in std_logic_vector((aWidth-1) downto 0);
+		d : in std_logic_vector((dWidth-1) downto 0);
+		q : out std_logic_vector((dWidth-1) downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of gen_ram is
+	subtype addressRange is integer range 0 to ((2**aWidth)-1);
+	type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+	signal ram: ramDef;
+
+	signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+	signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+--	q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if we = '1' then
+				ram(to_integer(unsigned(addr))) <= d;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+	begin
+		if rising_edge(clk) then
+--			qReg <= ram(to_integer(unsigned(rAddrReg)));
+--			rAddrReg <= addr;
+----			qReg <= ram(to_integer(unsigned(addr)));
+      q <= ram(to_integer(unsigned(addr)));
+		end if;
+	end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+
--- a/Hardware/Jin/rtl/pia6821.vhd
+++ b/Hardware/Jin/rtl/pia6821.vhd
@@ -0,0 +1,553 @@
+--===========================================================================--
+--
+--  S Y N T H E Z I A B L E    I/O Port   C O R E
+--
+--  www.OpenCores.Org - May 2004
+--  This core adheres to the GNU public license  
+--
+-- File name      : pia6821.vhd
+--
+-- Purpose        : Implements 2 x 8 bit parallel I/O ports
+--                  with programmable data direction registers
+--                  
+-- Dependencies   : ieee.Std_Logic_1164
+--                  ieee.std_logic_unsigned
+--
+-- Author         : John E. Kent      
+--
+--===========================================================================----
+--
+-- Revision History:
+--
+-- Date:          Revision         Author
+-- 1 May 2004     0.0              John Kent
+-- Initial version developed from ioport.vhd
+--
+--
+-- Unkown date     0.0.1 found at Pacedev repository
+-- remove High Z output and and oe signal
+--
+-- 18 October 2017 0.0.2           DarFpga
+-- Set output to low level when in data is in input mode 
+-- (to avoid infered latch warning)
+--
+--===========================================================================----
+--
+-- Memory Map
+--
+-- IO + $00 - Port A Data & Direction register
+-- IO + $01 - Port A Control register
+-- IO + $02 - Port B Data & Direction Direction Register
+-- IO + $03 - Port B Control Register
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity pia6821 is
+	port (	
+	 	clk       : in    std_logic;
+    rst       : in    std_logic;
+    cs        : in    std_logic;
+    rw        : in    std_logic;
+    addr      : in    std_logic_vector(1 downto 0);
+    data_in   : in    std_logic_vector(7 downto 0);
+	 	data_out  : out   std_logic_vector(7 downto 0);
+	 	irqa      : out   std_logic;
+	 	irqb      : out   std_logic;
+	 	pa_i      : in std_logic_vector(7 downto 0);
+	 	pa_o      : out std_logic_vector(7 downto 0);
+	 	pa_oe     : out std_logic_vector(7 downto 0);
+	 	ca1       : in    std_logic;
+	 	ca2_i     : in std_logic;
+	 	ca2_o     : out std_logic;
+	 	ca2_oe    : out std_logic;
+	 	pb_i      : in std_logic_vector(7 downto 0);
+	 	pb_o      : out std_logic_vector(7 downto 0);
+	 	pb_oe     : out std_logic_vector(7 downto 0);
+	 	cb1       : in    std_logic;
+	 	cb2_i     : in std_logic;
+	 	cb2_o     : out std_logic;
+	 	cb2_oe    : out std_logic
+	 );
+end;
+
+architecture pia_arch of pia6821 is
+
+signal porta_ddr   : std_logic_vector(7 downto 0);
+signal porta_data  : std_logic_vector(7 downto 0);
+signal porta_ctrl  : std_logic_vector(5 downto 0);
+signal porta_read  : std_logic;
+
+signal portb_ddr   : std_logic_vector(7 downto 0);
+signal portb_data  : std_logic_vector(7 downto 0);
+signal portb_ctrl  : std_logic_vector(5 downto 0);
+signal portb_read  : std_logic;
+signal portb_write : std_logic;
+
+signal ca1_del     : std_logic;
+signal ca1_rise    : std_logic;
+signal ca1_fall    : std_logic;
+signal ca1_edge    : std_logic;
+signal irqa1       : std_logic;
+
+signal ca2_del     : std_logic;
+signal ca2_rise    : std_logic;
+signal ca2_fall    : std_logic;
+signal ca2_edge    : std_logic;
+signal irqa2       : std_logic;
+signal ca2_out     : std_logic;
+
+signal cb1_del     : std_logic;
+signal cb1_rise    : std_logic;
+signal cb1_fall    : std_logic;
+signal cb1_edge    : std_logic;
+signal irqb1       : std_logic;
+
+signal cb2_del     : std_logic;
+signal cb2_rise    : std_logic;
+signal cb2_fall    : std_logic;
+signal cb2_edge    : std_logic;
+signal irqb2       : std_logic;
+signal cb2_out     : std_logic;
+
+begin
+
+--------------------------------
+--
+-- read I/O port
+--
+--------------------------------
+
+pia_read : process(	addr,	cs,
+                    irqa1, irqa2, irqb1, irqb2,
+                    porta_ddr,  portb_ddr,
+										porta_data, portb_data,
+										porta_ctrl, portb_ctrl,
+						   			pa_i,       pb_i )
+variable count : integer;
+begin
+      case addr is
+	     when "00" =>
+		    for count in 0 to 7 loop
+			   if porta_ctrl(2) = '0' then
+				  data_out(count) <= porta_ddr(count);
+			     porta_read <= '0';
+            else
+				  if porta_ddr(count) = '1' then
+                data_out(count) <= porta_data(count);
+              else
+                data_out(count) <= pa_i(count);
+              end if;
+			     porta_read <= cs;
+            end if;
+			 end loop;
+			 portb_read <= '0';
+
+	     when "01" =>
+		    data_out <= irqa1 & irqa2 & porta_ctrl;
+			 porta_read <= '0';
+			 portb_read <= '0';
+
+		  when "10" =>
+		    for count in 0 to 7 loop
+			   if portb_ctrl(2) = '0' then
+				  data_out(count) <= portb_ddr(count);
+				  portb_read <= '0';
+            else
+				  if portb_ddr(count) = '1' then
+                data_out(count) <= portb_data(count);
+              else
+                data_out(count) <= pb_i(count);
+				  end if;
+				  portb_read <= cs;
+            end if;
+			 end loop;
+			 porta_read <= '0';
+
+		  when "11" =>
+		    data_out <= irqb1 & irqb2 & portb_ctrl;
+			 porta_read <= '0';
+			 portb_read <= '0';
+
+		  when others =>
+		    data_out <= "00000000";
+			 porta_read <= '0';
+			 portb_read <= '0';
+
+		end case;
+end process;
+
+---------------------------------
+--
+-- Write I/O ports
+--
+---------------------------------
+
+pia_write : process( clk, rst, addr, cs, rw, data_in,
+                        porta_ctrl, portb_ctrl,
+                        porta_data, portb_data,
+						porta_ddr, portb_ddr )
+begin
+  if rst = '1' then
+      porta_ddr   <= "00000000";
+      porta_data  <= "00000000";
+      porta_ctrl  <= "000000";
+      portb_ddr   <= "00000000";
+      portb_data  <= "00000000";
+		portb_ctrl  <= "000000";
+		portb_write <= '0';
+  elsif clk'event and clk = '1' then
+    if cs = '1' and rw = '0' then
+      case addr is
+	     when "00" =>
+		    if porta_ctrl(2) = '0' then
+		       porta_ddr  <= data_in;
+		       porta_data <= porta_data;
+			 else
+		       porta_ddr  <= porta_ddr;
+		       porta_data <= data_in;
+			 end if;
+			 porta_ctrl  <= porta_ctrl;
+		    portb_ddr   <= portb_ddr;
+		    portb_data  <= portb_data;
+			 portb_ctrl  <= portb_ctrl;
+			 portb_write <= '0';
+		  when "01" =>
+		    porta_ddr   <= porta_ddr;
+		    porta_data  <= porta_data;
+			 porta_ctrl  <= data_in(5 downto 0);
+		    portb_ddr   <= portb_ddr;
+		    portb_data  <= portb_data;
+			 portb_ctrl  <= portb_ctrl;
+			 portb_write <= '0';
+	     when "10" =>
+		    porta_ddr   <= porta_ddr;
+		    porta_data  <= porta_data;
+			 porta_ctrl  <= porta_ctrl;
+		    if portb_ctrl(2) = '0' then
+		       portb_ddr   <= data_in;
+		       portb_data  <= portb_data;
+			    portb_write <= '0';
+			 else
+		       portb_ddr   <= portb_ddr;
+		       portb_data  <= data_in;
+			    portb_write <= '1';
+			 end if;
+			 portb_ctrl  <= portb_ctrl;
+		  when "11" =>
+		    porta_ddr   <= porta_ddr;
+		    porta_data  <= porta_data;
+			 porta_ctrl  <= porta_ctrl;
+		    portb_ddr   <= portb_ddr;
+		    portb_data  <= portb_data;
+			 portb_ctrl  <= data_in(5 downto 0);
+			 portb_write <= '0';
+		  when others =>
+		    porta_ddr   <= porta_ddr;
+		    porta_data  <= porta_data;
+			 porta_ctrl  <= porta_ctrl;
+		    portb_ddr   <= portb_ddr;
+		    portb_data  <= portb_data;
+			 portb_ctrl  <= portb_ctrl;
+			 portb_write <= '0';
+		end case;
+	 else
+		    porta_ddr   <= porta_ddr;
+		    porta_data  <= porta_data;
+			 porta_ctrl  <= porta_ctrl;
+		    portb_data  <= portb_data;
+		    portb_ddr   <= portb_ddr;
+			 portb_ctrl  <= portb_ctrl;
+			 portb_write <= '0';
+	 end if;
+  end if;
+end process;
+
+---------------------------------
+--
+-- direction control port a
+--
+---------------------------------
+porta_direction : process ( porta_data, porta_ddr )
+variable count : integer;
+begin
+  for count in 0 to 7 loop
+    if porta_ddr(count) = '1' then
+      pa_o(count) <= porta_data(count);
+		pa_oe(count) <= '1';
+    else
+      pa_o(count) <= '0'; 
+      pa_oe(count) <= '0';
+    end if;
+  end loop;
+end process;
+
+---------------------------------
+--
+-- CA1 Edge detect
+--
+---------------------------------
+ca1_input : process( clk, rst, ca1, ca1_del,
+                     ca1_rise, ca1_fall, ca1_edge,
+							irqa1, porta_ctrl, porta_read )
+begin
+  if rst = '1' then
+    ca1_del  <= '0';
+	 ca1_rise <= '0';
+    ca1_fall <= '0';
+	 ca1_edge <= '0';
+	 irqa1    <= '0';
+  elsif clk'event and clk = '0' then
+    ca1_del  <= ca1;
+    ca1_rise <= (not ca1_del) and ca1;
+    ca1_fall <= ca1_del and (not ca1);
+	 if ca1_edge = '1' then
+	    irqa1 <= '1';
+	 elsif porta_read = '1' then
+	    irqa1 <= '0';
+    else
+	    irqa1 <= irqa1;
+    end if;
+  end if;  
+
+  if porta_ctrl(1) = '0' then
+	 ca1_edge <= ca1_fall;
+  else
+	 ca1_edge <= ca1_rise;
+  end if;
+end process;
+
+---------------------------------
+--
+-- CA2 Edge detect
+--
+---------------------------------
+ca2_input : process( clk, rst, ca2_i, ca2_del,
+                     ca2_rise, ca2_fall, ca2_edge,
+							irqa2, porta_ctrl, porta_read )
+begin
+  if rst = '1' then
+    ca2_del  <= '0';
+	 ca2_rise <= '0';
+    ca2_fall <= '0';
+	 ca2_edge <= '0';
+	 irqa2    <= '0';
+  elsif clk'event and clk = '0' then
+    ca2_del  <= ca2_i;
+    ca2_rise <= (not ca2_del) and ca2_i;
+    ca2_fall <= ca2_del and (not ca2_i);
+	 if porta_ctrl(5) = '0' and ca2_edge = '1' then
+	    irqa2 <= '1';
+	 elsif porta_read = '1' then
+	    irqa2 <= '0';
+    else
+	    irqa2 <= irqa2;
+    end if;
+  end if;  
+
+  if porta_ctrl(4) = '0' then
+	 ca2_edge <= ca2_fall;
+  else
+	 ca2_edge <= ca2_rise;
+  end if;
+end process;
+
+---------------------------------
+--
+-- CA2 output control
+--
+---------------------------------
+ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
+begin
+  if rst='1' then
+    ca2_out <= '0';
+  elsif clk'event and clk='0' then
+    case porta_ctrl(5 downto 3) is
+    when "100" => -- read PA clears, CA1 edge sets
+      if porta_read = '1' then
+	     ca2_out <= '0';
+      elsif ca1_edge = '1' then
+	     ca2_out <= '1';
+      else
+	     ca2_out <= ca2_out;
+      end if;
+    when "101" => -- read PA clears, E sets
+      ca2_out <= not porta_read;
+    when "110" =>	-- set low
+	   ca2_out <= '0';
+    when "111" =>	-- set high
+	   ca2_out <= '1';
+    when others => -- no change
+	   ca2_out <= ca2_out;
+    end case;
+  end if;
+end process;
+
+---------------------------------
+--
+-- CA2 direction control
+--
+---------------------------------
+ca2_direction : process( porta_ctrl, ca2_out )
+begin
+  if porta_ctrl(5) = '0' then
+   ca2_oe <= '0';
+   ca2_o <= '0'; 
+  else
+   ca2_o <= ca2_out;
+	ca2_oe <= '1';
+  end if;
+end process;
+
+---------------------------------
+--
+-- direction control port b
+--
+---------------------------------
+portb_direction : process ( portb_data, portb_ddr )
+variable count : integer;
+begin
+  for count in 0 to 7 loop
+    if portb_ddr(count) = '1' then
+      pb_o(count) <= portb_data(count);
+		pb_oe(count) <= '1';
+    else
+      pb_o(count) <= '0'; 
+      pb_oe(count) <= '0';
+    end if;
+  end loop;
+end process;
+
+---------------------------------
+--
+-- CB1 Edge detect
+--
+---------------------------------
+cb1_input : process( clk, rst, cb1, cb1_del,
+                     cb1_rise, cb1_fall, cb1_edge,
+							irqb1, portb_ctrl, portb_read )
+begin
+  if rst = '1' then
+    cb1_del  <= '0';
+	 cb1_rise <= '0';
+    cb1_fall <= '0';
+	 cb1_edge <= '0';
+	 irqb1    <= '0';
+  elsif clk'event and clk = '0' then
+    cb1_del  <= cb1;
+    cb1_rise <= (not cb1_del) and cb1;
+    cb1_fall <= cb1_del and (not cb1);
+	 if cb1_edge = '1' then
+	    irqb1 <= '1';
+	 elsif portb_read = '1' then
+	    irqb1 <= '0';
+    else
+	    irqb1 <= irqb1;
+    end if;
+  end if;
+    
+  if portb_ctrl(1) = '0' then
+	 cb1_edge <= cb1_fall;
+  else
+	 cb1_edge <= cb1_rise;
+  end if;
+end process;
+
+---------------------------------
+--
+-- CB2 Edge detect
+--
+---------------------------------
+cb2_input : process( clk, rst, cb2_i, cb2_del,
+                     cb2_rise, cb2_fall, cb2_edge,
+							irqb2, portb_ctrl, portb_read )
+begin
+  if rst = '1' then
+    cb2_del  <= '0';
+	 cb2_rise <= '0';
+    cb2_fall <= '0';
+	 cb2_edge <= '0';
+	 irqb2    <= '0';
+  elsif clk'event and clk = '0' then
+    cb2_del  <= cb2_i;
+    cb2_rise <= (not cb2_del) and cb2_i;
+    cb2_fall <= cb2_del and (not cb2_i);
+	 if portb_ctrl(5) = '0' and cb2_edge = '1' then
+	    irqb2 <= '1';
+	 elsif portb_read = '1' then
+	    irqb2 <= '0';
+    else
+	    irqb2 <= irqb2;
+    end if;
+  end if;
+    
+  if portb_ctrl(4) = '0' then
+	 cb2_edge <= cb2_fall;
+  else
+	 cb2_edge <= cb2_rise;
+  end if;
+
+end process;
+
+---------------------------------
+--
+-- CB2 output control
+--
+---------------------------------
+cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
+begin
+  if rst='1' then
+    cb2_out <= '0';
+  elsif clk'event and clk='0' then
+    case portb_ctrl(5 downto 3) is
+    when "100" => -- write PB clears, CA1 edge sets
+      if portb_write = '1' then
+	     cb2_out <= '0';
+      elsif cb1_edge = '1' then
+	     cb2_out <= '1';
+      else
+	     cb2_out <= cb2_out;
+      end if;
+    when "101" => -- write PB clears, E sets
+      cb2_out <= not portb_write;
+    when "110" =>	-- set low
+	   cb2_out <= '0';
+    when "111" =>	-- set high
+	   cb2_out <= '1';
+    when others => -- no change
+	   cb2_out <= cb2_out;
+    end case;
+  end if;
+end process;
+
+---------------------------------
+--
+-- CB2 direction control
+--
+---------------------------------
+cb2_direction : process( portb_ctrl, cb2_out )
+begin
+  if portb_ctrl(5) = '0' then
+    cb2_oe <= '0';
+    cb2_o <=  '0'; 
+  else
+    cb2_o <= cb2_out;
+	 cb2_oe <= '1';
+  end if;
+end process;
+
+---------------------------------
+--
+-- IRQ control
+--
+---------------------------------
+pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
+begin
+  irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
+  irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
+end process;
+
+end pia_arch;
+	
--- a/Hardware/Jin/rtl/pll_mist.ppf
+++ b/Hardware/Jin/rtl/pll_mist.ppf
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_mist" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
--- a/Hardware/Jin/rtl/pll_mist.qip
+++ b/Hardware/Jin/rtl/pll_mist.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
--- a/Hardware/Jin/rtl/pll_mist.vhd
+++ b/Hardware/Jin/rtl/pll_mist.vhd
@@ -0,0 +1,461 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_mist.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_mist IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_mist;
+
+
+ARCHITECTURE SYN OF pll_mist IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(2);
+	sub_wire4    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	locked    <= sub_wire3;
+	c0    <= sub_wire4;
+	c2    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 3,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 4,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 9,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 2,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 181,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 12,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 91,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 3,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire7,
+		clk => sub_wire0,
+		locked => sub_wire3
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "181"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "91"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.790055"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.890110"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.79000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "181"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "91"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
--- a/Hardware/Jin/rtl/sdram.sv
+++ b/Hardware/Jin/rtl/sdram.sv
@@ -0,0 +1,254 @@
+//
+// sdram.v
+//
+// Static RAM controller implementation using SDRAM MT48LC16M16A2
+//
+// Copyright (c) 2015,2016 Sorgelig
+//
+// Some parts of SDRAM code used from project:
+// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version. 
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+// ------------------------------------------
+//
+// v2.1 - Add universal 8/16 bit mode.
+//
+
+module sdram
+(
+   input             init,        // reset to initialize RAM
+   input             clk,         // clock ~100MHz
+                                  //
+                                  // SDRAM_* - signals to the MT48LC16M16 chip
+   inout  reg [15:0] SDRAM_DQ,    // 16 bit bidirectional data bus
+   output reg [12:0] SDRAM_A,     // 13 bit multiplexed address bus
+   output reg        SDRAM_DQML,  // two byte masks
+   output reg        SDRAM_DQMH,  // 
+   output reg  [1:0] SDRAM_BA,    // two banks
+   output            SDRAM_nCS,   // a single chip select
+   output            SDRAM_nWE,   // write enable
+   output            SDRAM_nRAS,  // row address select
+   output            SDRAM_nCAS,  // columns address select
+   output            SDRAM_CKE,   // clock enable
+                                  //
+   input       [1:0] wtbt,        // 16bit mode:  bit1 - write high byte, bit0 - write low byte,
+                                  // 8bit mode:  2'b00 - use addr[0] to decide which byte to write
+                                  // Ignored while reading.
+                                  //
+   input      [24:0] addr,        // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations.
+   output     [15:0] dout,        // data output to cpu
+   input      [15:0] din,         // data input from cpu
+   input             we,          // cpu requests write
+   input             rd,          // cpu requests read
+   output reg        ready        // dout is valid. Ready to accept new read/write.
+);
+
+assign SDRAM_nCS  = command[3];
+assign SDRAM_nRAS = command[2];
+assign SDRAM_nCAS = command[1];
+assign SDRAM_nWE  = command[0];
+assign SDRAM_CKE  = cke;
+
+// no burst configured
+localparam BURST_LENGTH        = 3'b000;   // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE         = 1'b0;     // 0=sequential, 1=interleaved
+localparam CAS_LATENCY         = 3'd2;     // 2 for < 100MHz, 3 for >100MHz
+localparam OP_MODE             = 2'b00;    // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST      = 1'b1;     // 0= write burst enabled, 1=only single access write
+localparam MODE                = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz
+localparam cycles_per_refresh  = 14'd186;  // (64000*36)/8192-1 Calc'd as (64ms @ 36MHz)/8192 rose
+localparam startup_refresh_max = 14'b11111111111111;
+
+// SDRAM commands
+localparam CMD_INHIBIT         = 4'b1111;
+localparam CMD_NOP             = 4'b0111;
+localparam CMD_ACTIVE          = 4'b0011;
+localparam CMD_READ            = 4'b0101;
+localparam CMD_WRITE           = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE       = 4'b0010;
+localparam CMD_AUTO_REFRESH    = 4'b0001;
+localparam CMD_LOAD_MODE       = 4'b0000;
+
+reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
+reg  [3:0] command = CMD_INHIBIT;
+reg        cke     = 0;
+reg [24:0] save_addr;
+reg [15:0] data;
+
+assign dout = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]};
+typedef enum
+{
+	STATE_STARTUP,
+	STATE_OPEN_1,
+	STATE_WRITE,
+	STATE_READ,
+	STATE_IDLE,	  STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
+	STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7
+} state_t;
+
+state_t state = STATE_STARTUP;
+
+always @(posedge clk) begin
+	reg old_we, old_rd;
+	reg [CAS_LATENCY:0] data_ready_delay;
+
+	reg [15:0] new_data;
+	reg  [1:0] new_wtbt;
+	reg        new_we;
+	reg        new_rd;
+	reg        save_we = 1;
+
+
+	command <= CMD_NOP;
+	refresh_count  <= refresh_count+1'b1;
+
+	data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]};
+
+	if(data_ready_delay[0]) data <= SDRAM_DQ;
+
+	case(state)
+		STATE_STARTUP: begin
+			//------------------------------------------------------------------------
+			//-- This is the initial startup state, where we wait for at least 100us
+			//-- before starting the start sequence
+			//-- 
+			//-- The initialisation is sequence is 
+			//--  * de-assert SDRAM_CKE
+			//--  * 100us wait, 
+			//--  * assert SDRAM_CKE
+			//--  * wait at least one cycle, 
+			//--  * PRECHARGE
+			//--  * wait 2 cycles
+			//--  * REFRESH, 
+			//--  * tREF wait
+			//--  * REFRESH, 
+			//--  * tREF wait 
+			//--  * LOAD_MODE_REG 
+			//--  * 2 cycles wait
+			//------------------------------------------------------------------------
+			cke        <= 1;
+			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
+			SDRAM_DQML <= 1;
+			SDRAM_DQMH <= 1;
+			SDRAM_A    <= 0;
+			SDRAM_BA   <= 0;
+
+			// All the commands during the startup are NOPS, except these
+			if(refresh_count == startup_refresh_max-31) begin
+				// ensure all rows are closed
+				command     <= CMD_PRECHARGE;
+				SDRAM_A[10] <= 1;  // all banks
+				SDRAM_BA    <= 2'b00;
+			end else if (refresh_count == startup_refresh_max-23) begin
+				// these refreshes need to be at least tREF (66ns) apart
+				command     <= CMD_AUTO_REFRESH;
+			end else if (refresh_count == startup_refresh_max-15) 
+				command     <= CMD_AUTO_REFRESH;
+			else if (refresh_count == startup_refresh_max-7) begin
+				// Now load the mode register
+				command     <= CMD_LOAD_MODE;
+				SDRAM_A     <= MODE;
+			end
+
+			//------------------------------------------------------
+			//-- if startup is complete then go into idle mode,
+			//-- get prepared to accept a new command, and schedule
+			//-- the first refresh cycle
+			//------------------------------------------------------
+			if(!refresh_count) begin
+				state   <= STATE_IDLE;
+				ready   <= 1;
+				refresh_count <= 0;
+			end
+		end
+
+		STATE_IDLE_7: state <= STATE_IDLE_6;
+		STATE_IDLE_6: state <= STATE_IDLE_5;
+		STATE_IDLE_5: state <= STATE_IDLE_4;
+		STATE_IDLE_4: state <= STATE_IDLE_3;
+		STATE_IDLE_3: state <= STATE_IDLE_2;
+		STATE_IDLE_2: state <= STATE_IDLE_1;
+		STATE_IDLE_1: begin
+			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
+			state      <= STATE_IDLE;
+			// mask possible refresh to reduce colliding.
+			if(refresh_count > cycles_per_refresh) begin
+            //------------------------------------------------------------------------
+            //-- Start the refresh cycle. 
+            //-- This tasks tRFC (66ns), so 2 idle cycles are needed @ 36MHz
+            //------------------------------------------------------------------------
+				state    <= STATE_IDLE_2;
+				command  <= CMD_AUTO_REFRESH;
+				refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
+			end
+		end
+
+		STATE_IDLE: begin
+			// Priority is to issue a refresh if one is outstanding
+			if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1;
+			else if(new_rd | new_we) begin
+				new_we   <= 0;
+				new_rd   <= 0;
+				save_addr<= addr;
+				save_we  <= new_we;
+				state    <= STATE_OPEN_1;
+				command  <= CMD_ACTIVE;
+				SDRAM_A  <= addr[13:1];
+				SDRAM_BA <= addr[24:23];
+			end
+		end
+
+		// ACTIVE-to-READ or WRITE delay >20ns (1 cycle @ 36 MHz)(-75)
+		STATE_OPEN_1: begin
+			SDRAM_A     <= {4'b0010, save_addr[22:14]}; 
+			SDRAM_DQML  <= save_we & (new_wtbt ? ~new_wtbt[0] :  save_addr[0]);
+			SDRAM_DQMH  <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]);
+			state       <= save_we ? STATE_WRITE : STATE_READ;
+		end
+
+		STATE_READ: begin
+			state       <= STATE_IDLE_5;
+			command     <= CMD_READ;
+			SDRAM_DQ    <= 16'bZZZZZZZZZZZZZZZZ;
+
+			// Schedule reading the data values off the bus
+			data_ready_delay[CAS_LATENCY] <= 1;
+		end
+
+		STATE_WRITE: begin
+			state       <= STATE_IDLE_5;
+			command     <= CMD_WRITE;
+			SDRAM_DQ    <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};
+			ready       <= 1;
+		end
+	endcase
+
+	if(init) begin
+		state <= STATE_STARTUP;
+		refresh_count <= startup_refresh_max - sdram_startup_cycles;
+	end
+
+	old_we <= we;
+	old_rd <= rd;
+	if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
+	else
+	if((rd & ~old_rd) || (rd & old_rd & (save_addr != addr))) {ready, new_rd} <= {1'b0, 1'b1};
+
+end
+
+endmodule