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Move Proms to SDRAM

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This commit is contained in:
Marcel 2020-05-25 00:05:31 +02:00
parent da4587edc0
commit b4ad2b3e4f
18 changed files with 169 additions and 162 deletions
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BIN
Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1.rbf Normal file
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Arcade_MiST/Sega System 1 Hardware/System1_MiST/Snapshot/System1_MiST.rbf
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2
Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qpf → Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qpf
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@ -27,5 +27,5 @@ DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "System1_MiST"
PROJECT_REVISION = "System1"

46
Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.qsf → Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.qsf
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@ -1,6 +1,6 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
@ -17,15 +17,15 @@
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 04:44:25 May 18, 2020
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 23:55:41 May 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# System1_MiST_assignment_defaults.qdf
# System1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@ -43,24 +43,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/System1_Top.v
set_global_assignment -name VERILOG_FILE rtl/System1_Main.v
set_global_assignment -name VERILOG_FILE rtl/System1_Video.v
set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v
set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v
set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v
set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v
set_global_assignment -name VERILOG_FILE rtl/SN76496.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
set_global_assignment -name VHDL_FILE rtl/rom/clut.vhd
set_global_assignment -name VHDL_FILE rtl/rom/dec_315_5041.vhd
set_global_assignment -name VHDL_FILE rtl/rom/dec_315_5051.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
@ -234,10 +216,26 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(System1_MiST)
# ------------------------
# ------------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/System1_Top.v
set_global_assignment -name VERILOG_FILE rtl/System1_Main.v
set_global_assignment -name VERILOG_FILE rtl/System1_Video.v
set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v
set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v
set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v
set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v
set_global_assignment -name VERILOG_FILE rtl/SN76496.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

0
Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1_MiST.sdc → Arcade_MiST/Sega System 1 Hardware/System1_MiST/System1.sdc
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4
Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/Flicky.mra
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@ -4,11 +4,11 @@
<mratimestamp>202001010000</mratimestamp>
<year>1984</year>
<manufacturer>Sega</manufacturer>
´ <rbf>System1_MiST</rbf>
´ <rbf>System1</rbf>
<category>Action</category>
<setname>flicky</setname>
<rom index="0" zip="flicky.zip" md5="97c9fdc1c04b6d341e2555663a7b14be" type="merged|nonmerged">
<rom index="1"> <part>0</part> </rom>
<rom index="0" zip="flicky.zip" md5="bb794955615ad5c3fbd30c99ddb35cec" type="merged|nonmerged">
<part name="epr5978a.116"/>
<part name="epr5979a.109"/>
<part repeat="0x8000">FF</part>

4
Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MrViking.mra
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@ -4,11 +4,11 @@
<mratimestamp>202001010000</mratimestamp>
<year>1985</year>
<manufacturer>Sega</manufacturer>
´ <rbf>System1_MiST</rbf>
´ <rbf>System1</rbf>
<category>Action</category>
<setname>mrviking</setname>
<rom index="0" zip="mrviking.zip" md5="15ab241d9f6780f41721916f46e7d4fa" type="merged|nonmerged">
<rom index="1"> <part>7</part> </rom>
<rom index="0" zip="mrviking.zip" md5="0c780578b7ded1c053192b4ec15fd546" type="merged|nonmerged">
<part name="epr-5873.129"/>
<part name="epr-5874.130"/>
<part name="epr-5875.131"/>

4
Arcade_MiST/Sega System 1 Hardware/System1_MiST/meta/MyHero.mra
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@ -4,9 +4,10 @@
<mratimestamp>202001010000</mratimestamp>
<year>1985</year>
<manufacturer>Sega</manufacturer>
´ <rbf>System1_MiST</rbf>
´ <rbf>System1</rbf>
<category>Action</category>
<setname>myhero</setname>
<rom index="1"> <part>5</part> </rom>
<rom index="0" zip="myhero.zip" md5="8b771287a2500090845561d9066f28ac" type="merged|nonmerged">
<part name="epr6963b.116"/>
<part name="epr6964a.109"/>
@ -30,5 +31,4 @@
<part name="pr-5317.76"/>
<part repeat="0x80">FF</part>
</rom>
<rom index="1"> <part>5</part> </rom>
</misterromdescription>

37
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Main.v
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@ -25,7 +25,11 @@ module System1_Main
output SNDRQ,
output [15:0] cpu_rom_addr,
input [7:0] cpu_rom_do
input [7:0] cpu_rom_do,
input [17:0] dl_addr,
input [7:0] dl_data,
input dl_wr,
input dl_clk
);
wire AXSCL = CLK48M;
@ -78,7 +82,7 @@ wire [7:0] cpu_rd_portB = DSW1;
wire [7:0] cpu_rd_mrom;
wire cpu_cs_mrom = (CPUAD[15:12] < 4'b1100);
PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr,cpu_rom_do );
PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr[14:0],cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk );
wire [7:0] cpu_rd_mram;
wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100);
@ -120,7 +124,11 @@ module PRGROM
input [14:0] mrom_ad,
output reg [7:0] mrom_dt,
output [14:0] cpu_rom_addr,
input [7:0] cpu_rom_do
input [7:0] cpu_rom_do,
input [17:0] dl_addr,
input [7:0] dl_data,
input dl_wr,
input dl_clk
);
reg [15:0] madr;
@ -135,19 +143,18 @@ wire [7:0] dectbl;
wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv );
//DLROM #( 7,8) decrom( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16: 7]==10'b1_1110_0001_0) ); // $1E100-$1E17F
dec_315_5051 dec_315_5051(//todo move to sdram
.clk(clk),
.addr(decidx),
.data(dectbl)
);
wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100
dpram#(8,7)decrom(
.clk_a(clk),
.addr_a(decidx),
.q_a(dectbl),
.clk_b(dl_clk),
.addr_b(dl_addr[6:0]),
.we_b(dec_we & dl_wr),
.d_b(dl_data)
);
//DLROM #(15,8) mainir( clk, madr[14:0], mdat, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b0_0) ); // $00000-$07FFF
//prg_rom pgr_rom(
// .clk(clk),
// .addr(madr[14:0]),
// .data(mdat)
//);
assign cpu_rom_addr = madr[15:0];
assign cpu_rom_addr = madr[14:0];
assign mdat = cpu_rom_do;
reg phase = 1'b0;

6
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_MiST.sv
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@ -223,6 +223,7 @@ wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire dl_wr = ioctl_wr && ioctl_addr < 18'h2E180;
data_io data_io(
.clk_sys ( clk_sys ),
@ -275,7 +276,6 @@ sdram sdram(
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
@ -320,6 +320,10 @@ System1_Top System1_Top(
.spr_rom_do(spr_rom_addr[0] ? spr_rom_do[15:8] : spr_rom_do[7:0] ),
.tile_rom_addr(tile_rom_addr),
.tile_rom_do(tile_rom_do),
.dl_addr ( ioctl_addr[17:0] ),
.dl_data ( ioctl_dout ),
.dl_wr ( dl_wr ),
.dl_clk(clk_sys),
.SOUT(audio)
);

1
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Parts.v
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@ -95,7 +95,6 @@ end
endmodule
module DPRAM1024
(
input clk0,

18
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Top.v
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@ -30,7 +30,11 @@ module System1_Top
output [12:0] snd_rom_addr,
input [7:0] snd_rom_do,
output [13:0] tile_rom_addr,
input [23:0] tile_rom_do
input [23:0] tile_rom_do,
input [17:0] dl_addr,
input [7:0] dl_data,
input dl_wr,
input dl_clk
);
// Clocks
@ -63,7 +67,11 @@ System1_Main System1_Main(
.VIDDO(VIDDO),
.SNDRQ(SNDRQ),
.cpu_rom_addr(cpu_rom_addr),
.cpu_rom_do(cpu_rom_do)
.cpu_rom_do(cpu_rom_do),
.dl_addr(dl_addr),
.dl_data(dl_data),
.dl_wr(dl_wr),
.dl_clk(dl_clk)
);
System1_Video System1_Video(
@ -85,7 +93,11 @@ System1_Video System1_Video(
.spr_rom_addr(spr_rom_addr),
.spr_rom_do(spr_rom_do),
.tile_rom_addr(tile_rom_addr),
.tile_rom_do(tile_rom_do)
.tile_rom_do(tile_rom_do),
.dl_addr(dl_addr),
.dl_data(dl_data),
.dl_wr(dl_wr),
.dl_clk(dl_clk)
);
assign PCLK = clk6M;

26
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/System1_Video.v
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@ -24,7 +24,11 @@ module System1_Video
output [15:0] spr_rom_addr,
input [7:0] spr_rom_do,
output [13:0] tile_rom_addr,
input [23:0] tile_rom_do
input [23:0] tile_rom_do,
input [17:0] dl_addr,
input [7:0] dl_data,
input dl_wr,
input dl_clk
);
// CPU Interface
@ -82,11 +86,6 @@ wire [10:0] SPRPX;
wire [15:0] sprchad;
wire [7:0] sprchdt;
//DLROM #(15,8) sprchr(VCLKx8,sprchad,sprchdt, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b0_1)); // $08000-$0FFFF
//spr_rom spr_rom(
// .clk(VCLKx8),
// .addr(sprchad),
// .data(sprchdt)
//);
assign spr_rom_addr = sprchad;
assign sprchdt = spr_rom_do;
@ -122,11 +121,16 @@ BGGEN bg1(VCLK,BG1HP,BG1VP,vram1ad,vram1dt,tile1ad,tile1dt,BG1PX);
// Color Mixer & RGB Output
wire [7:0] cltidx,cltval;
//DLROM #(8,8) clut(VCLKx2, cltidx, cltval, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:8]==9'b1_1110_0000) ); // $1E000-$1E0FF
clut clut(//todo move to sdram
.clk(VCLKx2),
.addr(cltidx),
.data(cltval)
);
wire clut_we = dl_addr[17:8] == 10'b1011100000;//2E000
dpram#(8,8)decrom(
.clk_a(VCLKx2),
.addr_a(cltidx),
.q_a(cltval),
.clk_b(dl_clk),
.addr_b(dl_addr[7:0]),
.we_b(clut_we & dl_wr),
.d_b(dl_data)
);
COLMIX cmix(
VCLK,

81
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/dpram.vhd Normal file
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@ -0,0 +1,81 @@
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- dpram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity dpram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk_a : in std_logic;
we_a : in std_logic := '0';
addr_a : in std_logic_vector((aWidth-1) downto 0);
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_a : out std_logic_vector((dWidth-1) downto 0);
clk_b : in std_logic;
we_b : in std_logic := '0';
addr_b : in std_logic_vector((aWidth-1) downto 0);
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_b : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of dpram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
ram(to_integer(unsigned(addr_a))) <= d_a;
end if;
q_a <= ram(to_integer(unsigned(addr_a)));
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
ram(to_integer(unsigned(addr_b))) <= d_b;
end if;
q_b <= ram(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture;

4
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/pll_mist.v
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@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing

38
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/clut.vhd
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@ -1,38 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity clut is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of clut is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"0C",X"0E",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0E",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"0E",X"0E",X"0E",X"0E",X"0D",X"0D",X"0E",X"0E",X"02",X"0E",X"0E",X"0E",X"01",X"0D",X"0E",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"08",X"0E",X"08",X"0E",X"09",X"0D",X"08",X"0E",X"08",X"0E",X"08",X"0E",X"09",X"0D",X"08",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"0A",X"0E",X"0A",X"0E",X"09",X"0D",X"0A",X"0E",X"0A",X"0E",X"0A",X"0E",X"09",X"0D",X"0A",X"0E",
X"0C",X"0D",X"0C",X"0E",X"0D",X"0D",X"0C",X"0E",X"00",X"0D",X"0C",X"0E",X"01",X"0D",X"0C",X"0E",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

30
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5041.vhd
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@ -1,30 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity dec_315_5041 is
port (
clk : in std_logic;
addr : in std_logic_vector(6 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of dec_315_5041 is
type rom is array(0 to 127) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"28",X"A8",X"08",X"88",X"88",X"80",X"08",X"00",X"88",X"08",X"80",X"00",X"88",X"80",X"08",X"00",
X"28",X"08",X"A8",X"88",X"28",X"A8",X"08",X"88",X"88",X"08",X"80",X"00",X"88",X"08",X"80",X"00",
X"28",X"08",X"A8",X"88",X"88",X"80",X"08",X"00",X"88",X"80",X"08",X"00",X"28",X"A8",X"08",X"88",
X"A0",X"80",X"A8",X"88",X"28",X"08",X"A8",X"88",X"A0",X"80",X"A8",X"88",X"A0",X"80",X"A8",X"88",
X"88",X"80",X"08",X"00",X"88",X"80",X"08",X"00",X"88",X"08",X"80",X"00",X"88",X"80",X"08",X"00",
X"A0",X"80",X"20",X"00",X"28",X"08",X"A8",X"88",X"A0",X"80",X"20",X"00",X"88",X"08",X"80",X"00",
X"28",X"08",X"A8",X"88",X"A0",X"80",X"20",X"00",X"A0",X"80",X"20",X"00",X"A0",X"80",X"20",X"00",
X"A0",X"80",X"A8",X"88",X"28",X"08",X"A8",X"88",X"A0",X"80",X"20",X"00",X"A0",X"80",X"A8",X"88");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

30
Arcade_MiST/Sega System 1 Hardware/System1_MiST/rtl/rom/dec_315_5051.vhd
View File

@ -1,30 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity dec_315_5051 is
port (
clk : in std_logic;
addr : in std_logic_vector(6 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of dec_315_5051 is
type rom is array(0 to 127) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"08",X"88",X"00",X"80",X"A0",X"80",X"A8",X"88",X"80",X"00",X"A0",X"20",X"88",X"80",X"08",X"00",
X"A0",X"80",X"A8",X"88",X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"A0",X"80",X"A8",X"88",
X"08",X"88",X"00",X"80",X"80",X"00",X"A0",X"20",X"80",X"00",X"A0",X"20",X"88",X"80",X"08",X"00",
X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"88",X"80",X"08",X"00",
X"08",X"88",X"00",X"80",X"A8",X"88",X"28",X"08",X"A8",X"88",X"28",X"08",X"80",X"00",X"A0",X"20",
X"28",X"08",X"20",X"00",X"88",X"80",X"08",X"00",X"A8",X"88",X"28",X"08",X"88",X"80",X"08",X"00",
X"08",X"88",X"00",X"80",X"80",X"00",X"A0",X"20",X"A8",X"88",X"28",X"08",X"80",X"00",X"A0",X"20",
X"28",X"08",X"20",X"00",X"28",X"08",X"20",X"00",X"08",X"88",X"00",X"80",X"88",X"80",X"08",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;