Williams rev.2 works

2026-03-05 18:49:01 +00:00 · 2022-03-27 17:00:45 +02:00
parent 4030edd97d
commit b52c8613ea
29 changed files with 2073 additions and 11504 deletions
--- a/Arcade_MiST/Williams
+++ b/Arcade_MiST/Williams
@@ -1,5 +1,5 @@
 -------------------------------------------------------------------------------
-- Turkey shoot by Dar (darfpga@aol.fr) (05 March 2022)
+-- Inferno by Dar (darfpga@aol.fr) (13 March 2022)
 -- http://darfpga.blogspot.fr
 -- https://sourceforge.net/projects/darfpga/files
 -- github.com/darfpga
@@ -38,7 +38,7 @@
 --            17,18  -  gnd   -  8,10 
 --
 -------------------------------------------------------------------------------
-- Version 0.0 -- 05/03/2022 -- 
+-- Version 0.0 -- 13/03/2022 -- 
 --	initial version 
 -------------------------------------------------------------------------------
 --
@@ -57,12 +57,12 @@
 --   F2 : Start 2 players
 --   F1 : Start 1 player
 --   SPACE       : Fire  
--   RIGHT arrow : Move gun right
--   LEFT  arrow : Move gun left
--   UP    arrow : Move gun up 
--   DOWN  arrow : Move gun down
--   CTRL        : Gobble
--   W(Z)        : Grenade
+--   RIGHT arrow : run/aim -- must use separate controls
+--   LEFT  arrow : run/aim -- must use separate controls
+--   UP    arrow : run/aim -- must use separate controls 
+--   DOWN  arrow : run/aim -- must use separate controls
+--   CTRL        : NU
+--   W(Z)        : NU
 --
 -- Keyboard Service inputs French(english) :
 --
@@ -73,61 +73,57 @@
 -- To enter service mode press 'advance' key while in game over screen
 -- Enter service mode to tune game parameters (difficulty ...)
 -- Tuning are lost at power OFF, for permanent tuning edit/set parameters
--   within tshoot_cmos_ram.vhd and recompile.
+--   within inferno_cmos_ram.vhd and recompile.
 --
 -------------------------------------------------------------------------------
-- Use make_tshoot_proms.bat to build vhd file and bin from binaries
+-- Use make_inferno_proms.bat to build vhd file and bin from binaries
 -- Load sdram with external rom bank -> use sdram_loader_de10_lite.sof + key(0)
 -------------------------------------------------------------------------------
-- Program sdram content with this turkey shoot rom bank loader before 
-- programming turkey shoot game core :
+-- Program sdram content with this  inferno rom bank loader before 
+-- programming inferno game core :
 --
-- 1) program DE10_lite with tshoot sdram loader
+-- 1) program DE10_lite with inferno sdram loader
 -- 2) press key(0) at least once (digit blinks during programming)
-- 3) program DE10_lite with tshoot core without switching DE10_lite OFF
+-- 3) program DE10_lite with inferno core without switching DE10_lite OFF
 -------------------------------------------------------------------------------
-- Used ROMs by make_tshoot_proms.bat
+-- Used ROMs by make_inferno_proms.bat

-> turkey_shoot_prog1
-   rom18.ic55 CRC(effc33f1)
+> inferno_prog2
+   ic9.inf  CRC(1a013185)
+   ic10.inf CRC(dbf64a36)

-> turkey_shoot_prog2
-   rom2.ic9"  CRC(fd982687)
-   rom3.ic10" CRC(9617054d)
+> inferno_bank_a
+  None  

-> turkey_shoot_bank_a
-   rom17.ic26 CRC(b02d1ccd)
-   rom15.ic24 CRC(11709935)
+> inferno_bank_b
+   ic25.inf CRC(103a5951)
+   ic23.inf CRC(c04749a0)
+   ic21.inf CRC(c405f853)
+   ic19.inf CRC(ade7645a)   

-> turkey_shoot_bank_b
-   rom16.ic25 CRC(69ce38f8)
-   rom14.ic23 CRC(769a4ae5)
-   rom13.ic21 CRC(ec016c9b)
-   rom12.ic19 CRC(98ae7afa)   
+> inferno_bank_c
+   ic18.inf CRC(95bcf7b1)
+   ic16.inf CRC(8bc4f935)
+   ic14.inf CRC(a70508a7)
+   ic12.inf CRC(7ffb87f9)

-> turkey_shoot_bank_c
-   rom11.ic18 CRC(60d5fab8)
-   rom9.ic16  CRC(a4dd4a0e)
-   rom7.ic14  CRC(f25505e6)
-   rom5.ic12  CRC(94a7c0ed)
+> inferno_bank_d
+   ic17.inf CRC(b4684139)
+   ic15.inf CRC(128a6ad6)
+   ic13.inf CRC(83a9e4d6)
+   ic11.inf CRC(c2e9c909)

-> turkey_shoot_bank_d
-   rom10.ic17 CRC(0f32bad8)
-   rom8.ic15  CRC(e9b6cbf7)
-   rom6.ic13  CRC(a49f617f)
-   rom4.ic11  CRC(b026dc00)
+> inferno_sound
+   ic8.inf  CRC(4e3123b8)

-> turkey_shoot_sound
-   rom1.ic8   CRC(011a94a7)
+> inferno_graph1
+   ic57.inf CRC(65a4ef79)

-> turkey_shoot_graph1
-   rom20.ic57 CRC(c6e1d253)
+> inferno_graph2
+   ic58.inf CRC(4bb1c2a0)

-> turkey_shoot_graph2
-   rom21.ic58 CRC(9874e90f)
-
-> turkey_shoot_graph3
-   rom19.ic41 CRC(b9ce4d2a)
+> inferno_graph3
+   ic41.inf CRC(f3f7238f)

 -------------------------------------------------------------------------------
 -- Misc. info
--- a/Arcade_MiST/Williams
+++ b/Arcade_MiST/Williams
@@ -0,0 +1,54 @@
+# Williams rev.2 hardware games by darfpga
+
+Supported games: Turkey Shoot, Joust 2, Inferno, Mystic Marathon
+
+After loading the RBF (Core), a CMOS clearing happens. When the message 
+"Factory Settings Restored" appears, press the MiST soft RESET button (right).
+
+Later on you can save the CMOS RAM using the "Save NVRAM" OSD option.
+
+## Usage
+
+- Create ROM and ARC files from MAME ROM zip files using the mra utility and the MRA files.
+- Example: mra -A -z /path/to/mame/roms Inferno.mra
+- Copy the RBF and the ARC files to the same folder.
+- Copy the ROM files to the root of the SD Card.
+
+- MRA utilty: https://github.com/sebdel/mra-tools-c
+
+## Controls
+
+### Turkey Shoot
+
+| Function        | Button   |
+| --------------- | -------- |
+| Aim             | Mouse    |
+| Fire            | Button A |
+| Grenade         | Button B |
+| Gobble          | Button C |
+
+### Joust2
+
+| Function        | Button   |
+| --------------- | -------- |
+| Flap            | Button A |
+| Transform/start | Button B |
+| Left            | Left     |
+| Right           | Right    |
+
+### Inferno
+
+| Function        | Button     |
+| --------------- | ---------- |
+| Move            | Left/Right/Down/Up |
+| Aim             | Left/Right/Down/Up on Right Stick (dual stick gamepad only) OR |
+|                 | Button C/D/E/B |
+| Shoot           | Button A       |
+
+### Mystic Marathon
+
+| Function        | Button   |
+| --------------- | -------- |
+| Jump            | Button A |
+| Left            | Left     |
+| Right           | Right    |
--- a/Arcade_MiST/Williams
+++ b/Arcade_MiST/Williams
@@ -1,6 +0,0 @@
-Games that should work on this Hardware
-
-Mystic Marathon
-Turkey Shoot
-Inferno
-Joust 2 - Survival of the Fittest
--- a/Hardware/Williams2.qpf
+++ b/Hardware/Williams2.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
+# Date created = 04:04:47  October 16, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.0"
+DATE = "04:04:47  October 16, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "Williams2"
--- a/Hardware/WilliamsHWv2.qsf
+++ b/Hardware/WilliamsHWv2.qsf
@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2014 Altera Corporation
+# Copyright (C) 1991-2013 Altera Corporation
 # Your use of Altera Corporation's design tools, logic functions 
 # and other software and tools, and its AMPP partner logic 
 # functions, and any output files from any of the foregoing 
@@ -17,15 +17,15 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
-# Date created = 19:39:51  March 07, 2022
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 16:34:25  January 07, 2020
 #
 # -------------------------------------------------------------------------- #
 #
 # Notes:
 #
 # 1) The default values for assignments are stored in the file:
-#		WilliamsHWv2_assignment_defaults.qdf
+#		Williams2_assignment_defaults.qdf
 #    If this file doesn't exist, see file:
 #		assignment_defaults.qdf
 #
@@ -39,24 +39,12 @@

 # Project-Wide Assignments
 # ========================
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13  JUNE 04, 2019"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/WilliamsV2_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/williams2.vhd
-set_global_assignment -name VHDL_FILE rtl/tshoot_sound_board.vhd
-set_global_assignment -name VHDL_FILE rtl/tshoot_cmos_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/rtl_jkent/cpu09l_128.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/turkey_shoot_decoder.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/gray_code.vhd
-set_global_assignment -name VHDL_FILE rtl/rtl_pace/pia6821.vhd
-set_global_assignment -name VHDL_FILE rtl/rtl_jkent/cpu68_2.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
-set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
-set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"

 # Pin & Location Assignments
 # ==========================
@@ -90,6 +78,7 @@ set_location_assignment PIN_126 -to SPI_SCK
 set_location_assignment PIN_127 -to SPI_SS2
 set_location_assignment PIN_91 -to SPI_SS3
 set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
 set_location_assignment PIN_49 -to SDRAM_A[0]
 set_location_assignment PIN_44 -to SDRAM_A[1]
 set_location_assignment PIN_42 -to SDRAM_A[2]
@@ -129,27 +118,20 @@ set_location_assignment PIN_66 -to SDRAM_nWE
 set_location_assignment PIN_59 -to SDRAM_nCS
 set_location_assignment PIN_33 -to SDRAM_CKE
 set_location_assignment PIN_43 -to SDRAM_CLK
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"

 # Classic Timing Assignments
 # ==========================
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON

 # Analysis & Synthesis Assignments
 # ================================
 set_global_assignment -name FAMILY "Cyclone III"
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name VERILOG_MACRO "EXT_ROM=<None>"
-set_global_assignment -name FORCE_SYNCH_CLEAR ON
-set_global_assignment -name TOP_LEVEL_ENTITY WilliamsV2_MiST
+set_global_assignment -name TOP_LEVEL_ENTITY Williams2_MiST

 # Fitter Assignments
 # ==================
@@ -161,30 +143,25 @@ set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
 set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
 set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

 # Assembler Assignments
 # =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
 set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON

 # SignalTap II Assignments
 # ========================
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/tm.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/w2.stp

 # Power Estimation Assignments
 # ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

 # Advanced I/O Timing Assignments
@@ -194,58 +171,71 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

-# -----------------------------
-# start ENTITY(WilliamsV2_MiST)
+# ---------------------------
+# start ENTITY(Williams2_MiST)

 	# Pin & Location Assignments
 	# ==========================
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
-	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
-	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
-	set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]

 	# Fitter Assignments
 	# ==================
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
-	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO

 	# start DESIGN_PARTITION(Top)
 	# ---------------------------

 		# Incremental Compilation Assignments
 		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

 	# end DESIGN_PARTITION(Top)
 	# -------------------------

-# end ENTITY(WilliamsV2_MiST)
-# ---------------------------
+# end ENTITY(Williams2_MiST)
+# -------------------------
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Williams2_MiST.sv
+set_global_assignment -name QIP_FILE rtl/pll_mist.qip
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/williams2.vhd
+set_global_assignment -name VHDL_FILE rtl/williams2_colormix.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/tshoot_sound_board.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/gray_code.vhd
+set_global_assignment -name VHDL_FILE rtl/hc55564.vhd
+set_global_assignment -name VHDL_FILE rtl/williams_cvsd_board.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/williams2_decoder.vhd
+set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
+set_global_assignment -name VHDL_FILE ../../common/IO/pia6821.vhd
+set_global_assignment -name VHDL_FILE ../../common/CPU/6800/cpu68.vhd
+set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809is.v
+set_global_assignment -name QIP_FILE ../../common/Sound/jt51/jt51.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/w2.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/snd.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/Hardware/WilliamsHWv2.sdc
+++ b/Hardware/WilliamsHWv2.sdc
@@ -54,7 +54,9 @@ set_time_format -unit ns -decimal_places 3
 create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]

 set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
-set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[1]"
+set vid_clk   "pll|altpll_component|auto_generated|pll1|clk[1]"
+set game_clk  "pll|altpll_component|auto_generated|pll1|clk[2]"
+
 #**************************************************************
 # Create Generated Clock
 #**************************************************************
@@ -81,18 +83,18 @@ set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [ge
 set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
 set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]

-set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]

 #**************************************************************
 # Set Output Delay
 #**************************************************************

-set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
-set_output_delay -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
-set_output_delay -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
-set_output_delay -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
-set_output_delay -clock [get_clocks $sys_clk]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock [get_clocks $game_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock [get_clocks $game_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock [get_clocks $vid_clk]   1.000 [get_ports {VGA_*}]

 set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
 set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
@@ -113,8 +115,10 @@ set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks
 # Set Multicycle Path
 #**************************************************************

-set_multicycle_path -to {VGA_*[*]} -setup 2
-set_multicycle_path -to {VGA_*[*]} -hold 1
+set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $game_clk] -setup 2
+set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $game_clk] -hold 1
+#set_multicycle_path -to {VGA_*[*]} -setup 3
+#set_multicycle_path -to {VGA_*[*]} -hold 2

 #**************************************************************
 # Set Maximum Delay
--- a/Hardware/WilliamsHWv2.qpf
+++ b/Hardware/WilliamsHWv2.qpf
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 00:21:03  December 03, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "00:21:03  December 03, 2019"
-
-# Revisions
-
-PROJECT_REVISION = "WilliamsHWv2"
-
--- a/Hardware/meta/Inferno.mra
+++ b/Hardware/meta/Inferno.mra
@@ -0,0 +1,57 @@
+<misterromdescription>
+    <name>Inferno (Williams)</name>
+    <mameversion>0216</mameversion>
+    <mratimestamp>201911270000</mratimestamp>
+    <year>1980</year>
+    <manufacturer>Williams</manufacturer>
+    <setname>inferno</setname>
+    <rbf>william2</rbf>
+
+    <rom index="1"><part>2</part></rom>
+
+    <rom index="0" zip="inferno.zip" md5="76fb5decf2b3c4fb0ec08e8bd2a8db21" type="merged|nonmerged">
+	<!-- bank A -->
+	<part repeat="0x8000">00</part>
+
+	<!-- bank B -->
+	<part name="ic25.inf"/>
+	<part name="ic23.inf"/>
+	<part name="ic21.inf"/>
+	<part name="ic19.inf"/>
+
+	<!-- bank C -->
+	<part name="ic18.inf"/>
+	<part name="ic16.inf"/>
+	<part name="ic14.inf"/>
+	<part name="ic12.inf"/>
+
+	<!-- bank D -->
+	<part name="ic17.inf"/>
+	<part name="ic15.inf"/>
+	<part name="ic13.inf"/>
+	<part name="ic11.inf"/>
+
+	<!-- offset: 20000 -->
+
+	<!-- prog2 -->
+	<part name="ic9.inf"/>
+	<part name="ic10.inf"/>
+
+	<!-- prog1 -->
+	<part repeat="0x1000">00</part>
+
+	<!-- sound -->
+	<part name="ic8.inf"/>
+
+	<!-- offset: 25000 -->
+
+	<!-- graph1,2,3 -->
+	<interleave output="32">
+		<part name="ic57.inf" map="0001"/>
+		<part name="ic58.inf" map="0010"/>
+		<part name="ic41.inf" map="0100"/>
+		<part name="ic41.inf" map="1000"/>
+	</interleave>
+
+    </rom>
+</misterromdescription>
--- a/Arcade_MiST/Williams
+++ b/Arcade_MiST/Williams
@@ -0,0 +1,65 @@
+<misterromdescription>
+    <name>Joust 2 - Survival of the Fittest (revision 2)</name>
+    <mameversion>0216</mameversion>
+    <mratimestamp>201911270000</mratimestamp>
+    <year>1980</year>
+    <manufacturer>Williams</manufacturer>
+    <setname>joust2</setname>
+    <rbf>william2</rbf>
+
+    <rom index="1"><part>1</part></rom>
+
+    <rom index="0" zip="joust2.zip" md5="343c8f3f760b87535732525c747ac2b9" type="merged|nonmerged">
+	<!-- bank A -->
+	<part name="cpu_2732_ic26_rom19_rev1.10j"/>
+	<part name="cpu_2732_ic24_rom17_rev1.10h"/>
+	<part name="cpu_2732_ic22_rom15_rev1.9j"/>
+	<part name="cpu_2732_ic20_rom13_rev1.9h"/>
+
+	<!-- bank B -->
+	<part name="cpu_2732_ic25_rom18_rev1.10i"/>
+	<part name="cpu_2732_ic23_rom16_rev1.10g"/>
+	<part name="cpu_2732_ic21_rom14_rev1.9i"/>
+	<part name="cpu_2732_ic19_rom12_rev1.9g"/>
+
+	<!-- bank C -->
+	<part name="cpu_2732_ic18_rom11_rev1.8j"/>
+	<part name="cpu_2732_ic16_rom9_rev2.8h"/>
+	<part name="cpu_2732_ic14_rom7_rev2.6j"/>
+	<part name="cpu_2732_ic12_rom5_rev2.6h"/>
+
+	<!-- bank D -->
+	<part name="cpu_2732_ic17_rom10_rev1.8i"/>
+	<part name="cpu_2732_ic15_rom8_rev1.8g"/>
+	<part name="cpu_2732_ic13_rom6_rev2.6i"/>
+	<part name="cpu_2732_ic13_rom6_rev2.6i"/>
+
+	<!-- offset: 20000 -->
+
+	<!-- prog2 -->
+	<part name="cpu_2732_ic9_rom3_rev2.4d"/>
+	<part name="cpu_2732_ic10_rom4_rev2.4f"/>
+
+	<!-- prog1 -->
+	<part name="cpu_2732_ic55_rom2_rev1.4c"/>
+
+	<!-- sound -->
+	<part name="cpu_2764_ic8_rom1_rev1.0f"/>
+
+	<!-- offset: 25000 -->
+
+	<!-- graph1,2,3 -->
+	<interleave output="32">
+		<part name="vid_27128_ic57_rom20_rev1.8f" map="0001"/>
+		<part name="vid_27128_ic58_rom21_rev1.9f" map="0010"/>
+		<part name="vid_27128_ic41_rom22_rev1.9d" map="0100"/>
+		<part name="vid_27128_ic41_rom22_rev1.9d" map="1000"/>
+	</interleave>
+
+	<!-- extra sound board -->
+	<part name="snd_27256_rom23_rev1.u4"/>
+	<part name="snd_27256_rom24_rev1.u19"/>
+	<part name="snd_27256_rom25_rev1.u20"/>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/meta/Mystic
+++ b/Hardware/meta/Mystic
@@ -0,0 +1,60 @@
+<misterromdescription>
+    <name>Mystic Marathon</name>
+    <mameversion>0216</mameversion>
+    <mratimestamp>201911270000</mratimestamp>
+    <year>1980</year>
+    <manufacturer>Williams</manufacturer>
+    <setname>mysticm</setname>
+    <rbf>william2</rbf>
+
+    <rom index="1"><part>3</part></rom>
+
+    <rom index="0" zip="mysticm.zip" md5="c25943cbeb76af78eb42ff69992fce43" type="merged|nonmerged">
+	<!-- bank A -->
+	<part name="mm18_1.a26"/>
+	<part name="mm16_1.a24"/>
+	<part name="mm14_1.a22"/>
+	<part name="mm14_1.a22"/>
+
+	<!-- bank B -->
+	<part name="mm17_1.a25"/>
+	<part name="mm15_1.a23"/>
+	<part name="mm13_1.a21"/>
+	<part name="mm12_1.a19"/>
+
+	<!-- bank C -->
+	<part name="mm11_1.a18"/>
+	<part name="mm09_1.a16"/>
+	<part name="mm07_1.a14"/>
+	<part name="mm05_1.a12"/>
+
+	<!-- bank D -->
+	<part name="mm10_1.a17"/>
+	<part name="mm08_1.a15"/>
+	<part name="mm06_1.a13"/>
+	<part name="mm04_1.a11"/>
+
+	<!-- offset: 20000 -->
+
+	<!-- prog2 -->
+	<part name="mm02_2.a09"/>
+	<part name="mm03_2.a10"/>
+
+	<!-- prog1 -->
+	<part repeat="0x1000">00</part>
+
+	<!-- sound -->
+	<part name="mm01_1.a08"/>
+
+	<!-- offset: 25000 -->
+
+	<!-- graph1,2,3 -->
+	<interleave output="32">
+		<part name="mm20_1.b57" map="0001"/>
+		<part name="mm21_1.b58" map="0010"/>
+		<part name="mm19_1.b41" map="0100"/>
+		<part name="mm19_1.b41" map="1000"/>
+	</interleave>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/meta/Turkey
+++ b/Hardware/meta/Turkey
@@ -0,0 +1,60 @@
+<misterromdescription>
+    <name>Turkey Shoot</name>
+    <mameversion>0216</mameversion>
+    <mratimestamp>201911270000</mratimestamp>
+    <year>1980</year>
+    <manufacturer>Williams</manufacturer>
+    <setname>tshoot</setname>
+    <rbf>william2</rbf>
+
+    <rom index="1"><part>0</part></rom>
+
+    <rom index="0" zip="tshoot.zip" md5="e729f3020b61ddf39d1c77a649e5249f" type="merged|nonmerged">
+	<!-- bank A -->
+	<part name="rom17.ic26"/>
+	<part name="rom15.ic24"/>
+	<part name="rom17.ic26"/>
+	<part name="rom15.ic24"/>
+
+	<!-- bank B -->
+	<part name="rom16.ic25"/>
+	<part name="rom14.ic23"/>
+	<part name="rom13.ic21"/>
+	<part name="rom12.ic19"/>
+
+	<!-- bank C -->
+	<part name="rom11.ic18"/>
+	<part name="rom9.ic16"/>
+	<part name="rom7.ic14"/>
+	<part name="rom5.ic12"/>
+
+	<!-- bank D -->
+	<part name="rom10.ic17"/>
+	<part name="rom8.ic15"/>
+	<part name="rom6.ic13"/>
+	<part name="rom4.ic11"/>
+
+	<!-- offset: 20000 -->
+
+	<!-- prog2 -->
+	<part name="rom2.ic9"/>
+	<part name="rom3.ic10"/>
+
+	<!-- prog1 -->
+	<part name="rom18.ic55"/>
+
+	<!-- sound -->
+	<part name="rom1.ic8"/>
+
+	<!-- offset: 25000 -->
+
+	<!-- graph1,2,3 -->
+	<interleave output="32">
+		<part name="rom20.ic57" map="0001"/>
+		<part name="rom21.ic58" map="0010"/>
+		<part name="rom19.ic41" map="0100"/>
+		<part name="rom19.ic41" map="1000"/>
+	</interleave>
+
+    </rom>
+</misterromdescription>
--- a/Hardware/rtl/Williams2_MiST.sv
+++ b/Hardware/rtl/Williams2_MiST.sv
@@ -0,0 +1,431 @@
+//============================================================================
+//  Arcade: Williams rev.2
+//
+
+module Williams2_MiST(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27,
+
+	output [12:0] SDRAM_A,
+	inout  [15:0] SDRAM_DQ,
+	output        SDRAM_DQML,
+	output        SDRAM_DQMH,
+	output        SDRAM_nWE,
+	output        SDRAM_nCAS,
+	output        SDRAM_nRAS,
+	output        SDRAM_nCS,
+	output  [1:0] SDRAM_BA,
+	output        SDRAM_CLK,
+	output        SDRAM_CKE
+);
+
+`include "rtl/build_id.v"
+
+`define CORE_NAME "TSHOOT"
+//`define CORE_NAME "JOUST2"
+//`define CORE_NAME "INFERNO"
+//`define CORE_NAME "MYSTICM"
+
+localparam CONF_STR = {
+	`CORE_NAME,";;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Blend,Off,On;",
+	"O6,Joystick Swap,Off,On;",
+	"O7,Auto up,Off,On;",
+	"T8,Advance;",
+	"T9,HS Reset;",
+	"R1024,Save NVRAM;",
+	"T0,Reset;",
+	"V,v1.2.",`BUILD_DATE
+};
+
+wire        rotate    = status[2];
+wire  [1:0] scanlines = status[4:3];
+wire        blend     = status[5];
+wire        joyswap   = status[6];
+wire        autoup    = status[7];
+wire        adv       = status[8];
+wire        hsr       = status[9];
+
+wire advance, hsreset;
+trigger adv_button(clk_sys, adv, advance);
+trigger hsr_button(clk_sys, hsr, hsreset);
+
+wire [6:0] core_mod;
+reg  [7:0] input1;
+reg  [7:0] input2;
+wire       input_sel;
+reg  [1:0] orientation; // [left/right, landscape/portrait]
+wire [5:0] gun_gray_code;
+reg        oneplayer;   // only one joystick
+
+always @(*) begin
+	input1 = 0;
+	input2 = 0;
+	orientation = 2'b10;
+	oneplayer = 1;
+
+	case (core_mod)
+	7'h0: // Turkey Shoot
+	begin
+		input1 = {~(m_fireA | m_fire2A | mouse_flags[0]), 1'b0, gun_gray_code};
+		input2 = { m_two_players, m_one_player, 4'd0, m_fireC | m_fire2C | mouse_flags[2], m_fireB | m_fire2B | mouse_flags[1] };
+	end
+	7'h1: // Joust 2
+	begin
+		oneplayer = 0;
+		orientation = 2'b01;
+		input1[7:4] = { 2'b11, ~m_fireB, ~m_fire2B };
+		input1[3:0] = input_sel ? ~{1'b0, m_fire2A, m_right2, m_left2} : ~{1'b0, m_fireA, m_right, m_left};
+	end
+	7'h2: // Inferno
+	begin
+		oneplayer = 0;
+		input1 = input_sel ? ~{m_down2B | m_fire2E, m_right2B | m_fire2D, m_left2B | m_fire2C, m_up2B | m_fire2B, m_down2, m_right2, m_left2, m_up2} :
+		                     ~{m_downB | m_fireE, m_rightB | m_fireD, m_leftB | m_fireC, m_upB | m_fireB, m_down, m_right, m_left, m_up};
+		input2 = { m_two_players, m_one_player, 4'd0, m_fire2A, m_fireA };
+	end
+	7'h3: // Mystic Marathon
+	begin
+		input1 = { m_fireA, 1'b0, m_two_players, m_one_player, m_left, m_down, m_right, m_up };
+	end
+	default: ;
+	endcase
+
+end
+
+assign LED = ~ioctl_downl;
+assign SDRAM_CLK = clk_mem;
+assign SDRAM_CKE = 1;
+
+wire clk_sys, clk_vid, clk_mem;
+wire pll_locked;
+pll_mist pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_mem),//96
+	.c1(clk_vid),//48
+	.c2(clk_sys),//12
+	.locked(pll_locked)
+	);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire [19:0] joystick_0;
+wire [19:0] joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire        mouse_strobe;
+wire signed [8:0] mouse_x;
+wire signed [8:0] mouse_y;
+wire  [7:0] mouse_flags;
+
+user_io #(
+	.STRLEN($size(CONF_STR)>>3))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.core_mod       (core_mod       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.mouse_strobe   (mouse_strobe   ),
+	.mouse_flags    (mouse_flags    ),
+	.mouse_x        (mouse_x        ),
+	.mouse_y        (mouse_y        ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+wire        ioctl_downl;
+wire        ioctl_upl;
+wire  [7:0] ioctl_index;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire  [7:0] ioctl_dout;
+wire  [7:0] ioctl_din;
+wire        rom_downl = ioctl_downl & ioctl_index == 0;
+
+data_io data_io (
+	.clk_sys       ( clk_mem      ),
+	.SPI_SCK       ( SPI_SCK      ),
+	.SPI_SS2       ( SPI_SS2      ),
+	.SPI_DI        ( SPI_DI       ),
+	.SPI_DO        ( SPI_DO       ),
+	.ioctl_download( ioctl_downl  ),
+	.ioctl_upload  ( ioctl_upl    ),
+	.ioctl_index   ( ioctl_index  ),
+	.ioctl_wr      ( ioctl_wr     ),
+	.ioctl_addr    ( ioctl_addr   ),
+	.ioctl_dout    ( ioctl_dout   ),
+	.ioctl_din     ( ioctl_din    )
+);
+
+reg         port1_req, port2_req;
+wire [17:0] rom_addr;
+reg  [17:0] rom_addr_r;
+wire [15:0] rom_do;
+wire [13:0] gfx_addr;
+wire [31:0] gfx_do;
+wire [12:0] snd_addr;
+reg  [19:0] snd_addr_r;
+wire [15:0] snd_do;
+wire [16:0] snd2_addr;
+reg  [19:0] snd2_addr_r;
+wire [15:0] snd2_do;
+
+wire [24:0] gfx_ioctl_addr = ioctl_addr - 20'h25000;
+
+always @(posedge clk_mem) begin
+	rom_addr_r <= rom_downl ? 18'd0 : rom_addr;
+	snd_addr_r <= rom_downl ? 20'd0 : snd_addr + 20'h23000;
+	snd2_addr_r <= rom_downl ? 20'd0 : snd2_addr + 20'h35000;
+end
+
+sdram #(.MHZ(96)) sdram(
+	.*,
+	.init_n        ( pll_locked   ),
+	.clk           ( clk_mem      ),
+
+	// port1 used for main and sound CPUs
+	.port1_req     ( port1_req    ),
+	.port1_ack     ( ),
+	.port1_a       ( ioctl_addr[23:1] ),
+	.port1_ds      ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+	.port1_we      ( ioctl_downl ),
+	.port1_d       ( {ioctl_dout, ioctl_dout} ),
+	.port1_q       ( ),
+
+	.cpu1_addr     ( rom_addr_r[17:1] ),
+	.cpu1_q        ( rom_do ),
+	.cpu2_addr     ( snd_addr_r[19:1] ),
+	.cpu2_q        ( snd_do ),
+	.cpu3_addr     ( snd2_addr_r[19:1] ),
+	.cpu3_q        ( snd2_do ),
+
+	// port2 for background graphics
+	.port2_req     ( port2_req ),
+	.port2_ack     ( ),
+	.port2_a       ( gfx_ioctl_addr[23:1] ),
+	.port2_ds      ( {gfx_ioctl_addr[0], ~gfx_ioctl_addr[0]} ),
+	.port2_we      ( ioctl_downl ),
+	.port2_d       ( {ioctl_dout, ioctl_dout} ),
+	.port2_q       ( ),
+
+	.sp_addr       ( gfx_addr ),
+	.sp_q          ( gfx_do )
+);
+
+always @(posedge clk_mem) begin
+	reg        ioctl_wr_last = 0;
+
+	ioctl_wr_last <= ioctl_wr;
+	if (rom_downl) begin
+		if (~ioctl_wr_last && ioctl_wr) begin
+			port1_req <= ~port1_req;
+			port2_req <= ~port2_req;
+		end
+	end
+end
+
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_sys) begin
+	reg ioctl_downlD;
+	ioctl_downlD <= ioctl_downl;
+
+	if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+	reset <= status[0] | buttons[1] | ioctl_downl | ~rom_loaded;
+end
+
+wire [16:0] audio_left;
+wire [16:0] audio_right;
+wire        hs, vs;
+wire        blankn;
+wire  [3:0] r,g,b,i;
+
+williams2 williams2 (
+	.clock_12         ( clk_sys         ),
+	.reset            ( reset           ),
+	.hwsel            ( core_mod[1:0]   ),
+
+	.rom_addr         ( rom_addr        ),
+	.rom_do           ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
+	.gfx_rom_addr     ( gfx_addr        ),
+	.gfx_rom_do       ( gfx_do          ),
+	.snd_rom_addr     ( snd_addr        ),
+	.snd_rom_do       ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
+	.snd2_rom_addr    ( snd2_addr        ),
+	.snd2_rom_do      ( snd2_addr[0] ? snd2_do[15:8] : snd2_do[7:0] ),
+
+	.video_r          ( r               ),
+	.video_g      	  ( g               ),
+	.video_b      	  ( b               ),
+	.video_i          ( i               ),
+	.video_hs     	  ( hs              ),
+	.video_vs     	  ( vs              ),
+	.video_blankn 	  ( blankn          ),
+	.audio_left       ( audio_left      ),
+	.audio_right      ( audio_right     ),
+
+	.btn_auto_up      ( autoup          ),
+	.btn_advance      ( advance         ),
+	.btn_high_score_reset ( hsreset     ),
+	.btn_coin         ( m_coin1 | m_coin2 ),
+
+	.input1           ( input1          ),
+	.input2           ( input2          ),
+	.input_sel        ( input_sel       ),
+
+	.dl_clock         ( clk_mem ),
+	.dl_addr          ( ioctl_addr[15:0] ),
+	.dl_data          ( ioctl_dout ),
+	.dl_wr            ( ioctl_wr && ioctl_index == 0 ),
+	.up_data          ( ioctl_din  ),
+	.cmos_wr          ( ioctl_wr && ioctl_index == 8'hff )
+);
+
+wire  [7:0] red;
+wire  [7:0] green;
+wire  [7:0] blue;
+
+williams2_colormix williams2_colormix (
+	.mysticm   ( core_mod[1:0] == 3 ),
+	.r         ( r     ),
+	.g         ( g     ),
+	.b         ( b     ),
+	.intensity ( i     ),
+	.vga_r     ( red   ),
+	.vga_g     ( green ),
+	.vga_b     ( blue  )
+);
+
+mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
+	.clk_sys        ( clk_vid          ),
+	.SPI_SCK        ( SPI_SCK          ),
+	.SPI_SS3        ( SPI_SS3          ),
+	.SPI_DI         ( SPI_DI           ),
+	.R              ( blankn ? red[7:2]   : 0 ),
+	.G              ( blankn ? green[7:2] : 0 ),
+	.B              ( blankn ? blue[7:2]  : 0 ),
+	.HSync          ( hs               ),
+	.VSync          ( vs               ),
+	.VGA_R          ( VGA_R            ),
+	.VGA_G          ( VGA_G            ),
+	.VGA_B          ( VGA_B            ),
+	.VGA_VS         ( VGA_VS           ),
+	.VGA_HS         ( VGA_HS           ),
+	.rotate         ( {orientation[1],rotate} ),
+	.scandoubler_disable( scandoublerD ),
+	.no_csync       ( no_csync         ),
+	.scanlines      ( scanlines        ),
+	.blend          ( blend            ),
+	.ypbpr          ( ypbpr            )
+	);
+
+dac #(
+	.C_bits(17))
+dacl(
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio_left),
+	.dac_o(AUDIO_L)
+	);
+
+dac #(
+	.C_bits(17))
+dacr(
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio_right),
+	.dac_o(AUDIO_R)
+	);
+
+// Turkey shot guns
+reg  signed [8:0] x, y;
+wire [5:0] gun_v = x[8:3], gun_h = y[8:3];
+wire [5:0] gun_bin_code =  input_sel ? gun_v : gun_h;
+
+always @(posedge clk_sys) begin
+	if (mouse_strobe) begin
+		x <= x + mouse_x;
+		y <= y - mouse_y;
+	end
+end
+
+gray_code gun_gray_encoder (
+	.clk(clk_sys),
+	.addr(gun_bin_code),
+	.data(gun_gray_code)
+);
+
+// Common inputs
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF, m_upB, m_downB, m_leftB, m_rightB;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F, m_up2B, m_down2B, m_left2B, m_right2B;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( orientation ),
+	.joyswap     ( joyswap     ),
+	.oneplayer   ( oneplayer   ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_upB, m_downB, m_leftB, m_rightB, 6'd0, m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_up2B, m_down2B, m_left2B, m_right2B, 6'd0, m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+
+endmodule
+
+module trigger (
+	input clk,
+	input btn,
+	output trigger
+);
+
+reg  [23:0] counter;
+assign      trigger = (counter != 0);
+
+always @(posedge clk) begin
+	reg btn_d;
+
+	btn_d <= btn;
+	if (~btn_d & btn) counter <= 24'hfffff;
+	if (counter != 0) counter <= counter - 1'd1;
+end
+
+endmodule
--- a/Hardware/rtl/WilliamsV2_MiST.sv
+++ b/Hardware/rtl/WilliamsV2_MiST.sv
@@ -1,325 +0,0 @@
-//============================================================================
-//  Arcade: Williams V2 Hardware by DarFPGA
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module WilliamsV2_MiST(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	inout         SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         SPI_SS4,
-	input         CONF_DATA0,
-	input         CLOCK_27,
-	output [12:0] SDRAM_A,
-	inout  [15:0] SDRAM_DQ,
-	output        SDRAM_DQML,
-	output        SDRAM_DQMH,
-	output        SDRAM_nWE,
-	output        SDRAM_nCAS,
-	output        SDRAM_nRAS,
-	output        SDRAM_nCS,
-	output  [1:0] SDRAM_BA,
-	output        SDRAM_CLK,
-	output        SDRAM_CKE
-);
-
-`include "rtl/build_id.v"
-
-localparam CONF_STR = {
-	"TurkeyS;rom;",
-	"O2,Rotate Controls,Off,On;",
-	"O5,Blend,Off,On;",
-	"O6,Autoup,Off,On;",
-	"O8,Advance,Off,On;",
-	"T9,Reset Highscores,Off,On;",
-	"T0,Reset;",
-	"V,v0.0.",`BUILD_DATE
-};
-
-wire rotate = status[2];
-wire blend  = status[5];
-wire autoup = status[6];
-wire advance = status[8];
-wire Hreset   = status[9];
-
-assign LED = ~ioctl_downl;
-assign SDRAM_CLK = clk48;
-assign SDRAM_CKE = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk48, clk_sys, clk12;
-wire pll_locked;
-pll_mist pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk48),
-	.c1(clk_sys),//24
-	.c2(clk12),
-	.locked(pll_locked)
-	);
-
-wire [63:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire [31:0] joystick_0;
-wire [31:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire        no_csync;
-wire        key_pressed;
-wire  [7:0] key_code;
-wire        key_strobe;
-
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)),
-	.ROM_DIRECT_UPLOAD(1'b1))
-user_io(
-	.clk_sys        (clk_sys        ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.no_csync       (no_csync       ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-wire        ioctl_downl;
-wire        ioctl_upl;
-wire  [7:0] ioctl_index;
-wire        ioctl_wr;
-wire [24:0] ioctl_addr;
-wire  [7:0] ioctl_dout;
-wire  [7:0] ioctl_din;
-
-data_io #(
-	.ROM_DIRECT_UPLOAD(1'b1))
-data_io(
-	.clk_sys       ( clk_sys      ),
-	.SPI_SCK       ( SPI_SCK      ),
-	.SPI_SS2       ( SPI_SS2      ),
-	.SPI_SS4       ( SPI_SS4      ),
-	.SPI_DI        ( SPI_DI       ),
-	.SPI_DO        ( SPI_DO       ),
-	.ioctl_download( ioctl_downl  ),
-	.ioctl_upload  ( ioctl_upl    ),
-	.ioctl_index   ( ioctl_index  ),
-	.ioctl_wr      ( ioctl_wr     ),
-	.ioctl_addr    ( ioctl_addr   ),
-	.ioctl_dout    ( ioctl_dout   ),
-	.ioctl_din     ( ioctl_din    )
-);
-
-wire [24:0] sp_ioctl_addr = ioctl_addr - 18'h22000;//check
-
-wire [13:0] prg_rom_addr;
-wire [7:0] prg_rom_do;
-wire [12:0] snd_rom_addr;
-wire [7:0] snd_rom_do;
-wire [16:0] bank_rom_addr;
-wire [7:0] bank_rom_do;
-wire [12:0] gfx_rom_addr;
-wire [23:0] gfx_rom_do;
-reg port1_req, port2_req;
-sdram sdram(
-	.*,
-	.init_n        ( pll_locked   ),
-	.clk           ( clk48      ),
-
-	// port1 used for main + sound CPUs
-	.port1_req     ( port1_req    ),
-	.port1_ack     ( ),
-	.port1_a       ( ioctl_addr ),
-	.port1_ds      ( {ioctl_addr[0], ~ioctl_addr[0]} ),
-	.port1_we      ( ioctl_downl ),
-	.port1_d       ( {ioctl_dout, ioctl_dout} ),
-	.port1_q       ( ),
-
-	.cpu1_addr     ( ioctl_downl ? 16'hffff : {1'b0, prg_rom_addr[13:1]} ),
-	.cpu1_q        ( prg_rom_do ),
-
-	.cpu2_addr     ( ioctl_downl ? 16'hffff : (16'h2000 + bank_rom_addr[16:1]) ),
-	.cpu2_q        ( bank_rom_do ),
-	.cpu3_addr     ( ioctl_downl ? 16'hffff : (16'hE000 + snd_rom_addr[12:1]) ),
-	.cpu3_q        ( snd_rom_do ),
-
-	// port2 for sprite graphics
-	.port2_req     ( port2_req ),
-	.port2_ack     ( ),
-	.port2_a       ( {sp_ioctl_addr[23:17], sp_ioctl_addr[14:0], sp_ioctl_addr[16]} ), // merge sprite roms to 32-bit wide words
-	.port2_ds      ( {sp_ioctl_addr[15], ~sp_ioctl_addr[15]} ),
-	.port2_we      ( ioctl_downl ),
-	.port2_d       ( {ioctl_dout, ioctl_dout} ),
-	.port2_q       ( ),
-
-	.sp_addr       ( ioctl_downl ? 15'h7fff : gfx_rom_addr ),//todo
-	.sp_q          ( gfx_rom_do )
-);
-
-// ROM download controller
-always @(posedge clk_sys) begin
-	reg        ioctl_wr_last = 0;
-
-	ioctl_wr_last <= ioctl_wr;
-	if (ioctl_downl) begin
-		if (~ioctl_wr_last && ioctl_wr && ioctl_index == 0) begin
-			port1_req <= ~port1_req;
-			port2_req <= ~port2_req;
-		end
-	end
-end
-
-reg reset = 1;
-reg rom_loaded = 0;
-always @(posedge clk_sys) begin
-	reg ioctl_downlD;
-	ioctl_downlD <= ioctl_downl;
-
-	if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
-	reset <= status[0] | buttons[1] | ~rom_loaded;
-end
-
-
-wire [7:0] audio;
-wire        hs, vs, cs;
-wire        blankn;
-wire  [3:0] g, r, b, intensity;
-
-williams2 williams2(
-	.clock_12			(clk12),
-	.reset				(reset),
-//prg low
-	.prg_rom_addr		(prg_rom_addr),//(13 downto 0);
-	.prg_rom_do			(prg_rom_do),//(7 downto 0);
-//banks 
-	.rom_addr			(bank_rom_addr),//(16 downto 0);
-	.rom_do				(bank_rom_do),//( 7 downto 0);
-	.rom_rd				(),//
-//snd 
-	.snd_rom_addr		(snd_rom_addr),//(12 downto 0);
-	.snd_rom_do			(snd_rom_do),//(7 downto 0);
-//gfx
-	.gfx_rom_addr		(gfx_rom_addr),//(12 downto 0);
-	.gfx_rom_do			(gfx_rom_do),//(23 downto 0);
-//dec			hardcoded for now
-	.dec_rom_addr		(),//(8 downto 0);
-	.dec_rom_do			(),//(7 downto 0);
-
-	.video_r				(r),
-	.video_g				(g),
-	.video_b				(b),
-	.video_i				(intensity),
-	.video_csync		(cs),
-	.video_blankn		(blankn),
-	.video_hs			(hs),
-	.video_vs			(vs),
- 
-	.audio_out			(audio),
- 
-	.btn_auto_up		(autoup),
-	.btn_advance		(advance),
-	.btn_high_score_reset		(Hreset),
-
-	.btn_gobble			(m_fireC),
-	.btn_grenade		(m_fireB),
-	.btn_coin			(m_coin1),
-	.btn_start_2		(m_two_players),
-	.btn_start_1		(m_one_player),
-	.btn_trigger		(m_fireA),
-	.btn_left			(m_left),
-	.btn_right			(m_right),
-	.btn_up				(m_up),
-	.btn_down			(m_down),
- 
-	.sw_coktail_table	(1'b0)
-);
-
-wire [7:0]ri = r*intensity;
-wire [7:0]gi = g*intensity;
-wire [7:0]bi = b*intensity;
-
-mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
-	.clk_sys        ( clk_sys          ),
-	.SPI_SCK        ( SPI_SCK          ),
-	.SPI_SS3        ( SPI_SS3          ),
-	.SPI_DI         ( SPI_DI           ),
-	.R              ( blankn ? ri[7:4] : 0   ),
-	.G              ( blankn ? gi[7:4] : 0   ),
-	.B              ( blankn ? bi[7:4] : 0   ),
-	.HSync          ( hs               ),
-	.VSync          ( vs               ),
-	.VGA_R          ( VGA_R            ),
-	.VGA_G          ( VGA_G            ),
-	.VGA_B          ( VGA_B            ),
-	.VGA_VS         ( VGA_VS           ),
-	.VGA_HS         ( VGA_HS           ),
-	.rotate         ( { 1'b1, rotate } ),
-	.ce_divider     ( 1                ),
-	.blend          ( blend            ),
-	.scandoubler_disable(scandoublerD ),
-	.no_csync       ( 1'b1             ),//todo
-	.ypbpr          ( ypbpr            )
-	);
-
-dac #(
-	.C_bits(8))
-dac_(
-	.clk_i(clk_sys),
-	.res_n_i(1),
-	.dac_i(audio),
-	.dac_o(AUDIO_L)
-	);
-
-wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
-wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
-wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
-
-arcade_inputs inputs (
-	.clk         ( clk_sys     ),
-	.key_strobe  ( key_strobe  ),
-	.key_pressed ( key_pressed ),
-	.key_code    ( key_code    ),
-	.joystick_0  ( joystick_0  ),
-	.joystick_1  ( joystick_1  ),
-	.rotate      ( rotate      ),
-	.orientation ( 2'b11       ),//check
-	.joyswap     ( 1'b0        ),
-	.oneplayer   ( 1'b1        ),
-	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
-	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
-	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
-);
-
-endmodule 
--- a/Hardware/rtl/dpram.vhd
+++ b/Hardware/rtl/dpram.vhd
@@ -0,0 +1,81 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr) 
+-- http://darfpga.blogspot.fr
+--   Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- dpram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity dpram is
+	generic (
+		dWidth : integer := 8;
+		aWidth : integer := 10
+	);
+	port (
+		clk_a : in std_logic;
+		we_a : in std_logic := '0';
+		addr_a : in std_logic_vector((aWidth-1) downto 0);
+		d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+		q_a : out std_logic_vector((dWidth-1) downto 0);
+
+		clk_b : in std_logic;
+		we_b : in std_logic := '0';
+		addr_b : in std_logic_vector((aWidth-1) downto 0);
+		d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+		q_b : out std_logic_vector((dWidth-1) downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of dpram is
+	subtype addressRange is integer range 0 to ((2**aWidth)-1);
+	type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+	signal ram: ramDef;
+	signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
+	signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
+begin
+
+-- -----------------------------------------------------------------------
+	process(clk_a)
+	begin
+		if rising_edge(clk_a) then
+			if we_a = '1' then
+				ram(to_integer(unsigned(addr_a))) <= d_a;
+			end if;
+			q_a <= ram(to_integer(unsigned(addr_a)));
+		end if;
+	end process;
+
+	process(clk_b)
+	begin
+		if rising_edge(clk_b) then
+			if we_b = '1' then
+				ram(to_integer(unsigned(addr_b))) <= d_b;
+			end if;
+			q_b <= ram(to_integer(unsigned(addr_b)));
+		end if;
+	end process;
+	
+end architecture;
+
--- a/Hardware/rtl/gray_code.vhd
+++ b/Hardware/rtl/gray_code.vhd
@@ -0,0 +1,95 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity gray_code is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(5 downto 0);
+	data : out std_logic_vector(5 downto 0)
+);
+end entity;
+
+architecture prom of gray_code is
+	type rom is array(0 to  63) of std_logic_vector(5 downto 0);
+	signal rom_data: rom := (
+		"000000",
+		"000001",
+		"000011",
+		"000010",
+		"000110",
+		"000111",
+		"000101",
+		"000100",
+
+		"001100",
+		"001101",
+		"001111",
+		"001110",
+		"001010",
+		"001011",
+		"001001",
+		"001000",
+
+		"011000",
+		"011001",
+		"011011",
+		"011010",
+		"011110",
+		"011111",
+		"011101",
+		"011100",
+
+		"010100",
+		"010101",
+		"010111",
+		"010110",
+		"010010",
+		"010011",
+		"010001",
+		"010000",
+
+		"110000",
+		"110001",
+		"110011",
+		"110010",
+		"110110",
+		"110111",
+		"110101",
+		"110100",
+
+		"111100",
+		"111101",
+		"111111",
+		"111110",
+		"111010",
+		"111011",
+		"111001",
+		"111000",
+
+		"101000",
+		"101001",
+		"101011",
+		"101010",
+		"101110",
+		"101111",
+		"101101",
+		"101100",
+
+		"100100",
+		"100101",
+		"100111",
+		"100110",
+		"100010",
+		"100011",
+		"100001",
+		"100000"
+		
+		);
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
--- a/Hardware/rtl/hc55564.vhd
+++ b/Hardware/rtl/hc55564.vhd
@@ -0,0 +1,84 @@
+-- HC55516/HC55564 Continuously Variable Slope Delta decoder
+-- (c)2015 vlait
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity hc55564 is 
+port
+(
+	clk        : in std_logic;
+	cen        : in std_logic;
+	rst        : in std_logic;
+	bit_in     : in std_logic;
+	sample_out : out std_logic_vector(15 downto 0)
+);
+ 
+end hc55564;  
+
+architecture hdl of hc55564 is 
+  constant h   	: integer := (1 - 1/8)  *256; --integrator decay (1 - 1/8) * 256 = 224
+  constant b   	: integer := (1 - 1/256)*256; --syllabic decay (1 - 1/256) * 256 = 255
+  
+  constant s_min  : unsigned(15 downto 0) := to_unsigned(40, 16);
+  constant s_max  : unsigned(15 downto 0) := to_unsigned(5120, 16);
+
+  signal runofn_new : std_logic_vector(2 downto 0);
+  signal runofn 	: std_logic_vector(2 downto 0);
+  signal res1 		: unsigned(31 downto 0);
+  signal res2 		: unsigned(31 downto 0);
+  signal x_new		: unsigned(16 downto 0);
+  signal x   		: unsigned(15 downto 0);  --integrator
+  signal s   		: unsigned(15 downto 0);  --syllabic
+  signal old_cen  : std_logic;
+begin
+
+res1 <= x * h;
+res2 <= s * b;
+runofn_new <= runofn(1 downto 0) & bit_in;
+x_new <= ('0'&res1(23 downto 8)) + s when bit_in = '1' else ('0'&res1(23 downto 8)) - s;
+
+process(clk, rst, bit_in)
+begin
+	-- reset ??
+	if rising_edge(clk) then
+		old_cen <= cen;
+		if old_cen = '0' and cen = '1' then
+			runofn <= runofn_new;
+			if runofn_new = "000" or runofn_new = "111" then
+				s <= s + 40;
+				if (s + 40) > s_max then
+					s <= s_max;
+				end if;
+			else 
+				s <= res2(23 downto 8);
+				if res2(23 downto 8) < s_min then
+					s <= s_min;
+				end if;
+			end if;
+
+			if x_new(16) = '1' then
+				x <= (others => bit_in);
+			else
+				x <= x_new(15 downto 0);
+			end if;
+		end if;
+	end if;
+end process;
+
+sample_out <= std_logic_vector(x);
+
+end architecture hdl;
--- a/Hardware/rtl/pll_mist.vhd
+++ b/Hardware/rtl/pll_mist.vhd
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************


@@ -162,7 +162,7 @@ BEGIN
 		clk0_phase_shift => "0",
 		clk1_divide_by => 9,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 8,
+		clk1_multiply_by => 16,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
@@ -249,14 +249,14 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "48.000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -278,22 +278,22 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "32"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -305,7 +305,7 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -349,7 +349,7 @@ END SYN;
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- a/Hardware/rtl/rom/make..bat
+++ b/Hardware/rtl/rom/make..bat
@@ -1,11 +0,0 @@
-make_vhdl_prom.exe 7649.ic60 turkey_shoot_decoder.vhd
-
-copy /B rom17.ic26 + rom15.ic24 turkey_shoot_bank_a.bin
-copy /B rom16.ic25 + rom14.ic23 + rom13.ic21 + rom12.ic19 turkey_shoot_bank_b.bin
-copy /B rom11.ic18 + rom9.ic16 + rom7.ic14 + rom5.ic12 turkey_shoot_bank_c.bin
-copy /B rom10.ic17 + rom8.ic15 + rom6.ic13 + rom4.ic11 turkey_shoot_bank_d.bin
-copy /B rom20.ic57 + rom21.ic58 + rom19.ic41 gfx.bin
-
-copy /b rom18.ic55 + rom2.ic9 + rom3.ic10 + rom3.ic10 + turkey_shoot_bank_a.bin + turkey_shoot_bank_b.bin + turkey_shoot_bank_c.bin + turkey_shoot_bank_d.bin + rom1.ic8 + gfx.bin turkeys.rom
-
-pause
--- a/Hardware/rtl/rom/make_vhdl_prom.exe
+++ b/Hardware/rtl/rom/make_vhdl_prom.exe
--- a/Hardware/rtl/rom/turkey_shoot_decoder.vhd
+++ b/Hardware/rtl/rom/turkey_shoot_decoder.vhd
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;

-entity turkey_shoot_decoder is
+entity williams2_decoder is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(8 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;

-architecture prom of turkey_shoot_decoder is
+architecture prom of williams2_decoder is
 	type rom is array(0 to  511) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"40",X"80",X"01",X"41",X"81",X"02",X"42",X"82",X"03",X"43",X"83",X"04",X"44",X"84",X"05",
--- a/Hardware/rtl/rtl_jkent/cpu09l_128.vhd
+++ b/Hardware/rtl/rtl_jkent/cpu09l_128.vhd
--- a/Hardware/rtl/rtl_jkent/cpu68_2.vhd
+++ b/Hardware/rtl/rtl_jkent/cpu68_2.vhd
--- a/Hardware/rtl/rtl_pace/pia6821.vhd
+++ b/Hardware/rtl/rtl_pace/pia6821.vhd
@@ -1,553 +0,0 @@
--===========================================================================--
--
--  S Y N T H E Z I A B L E    I/O Port   C O R E
--
--  www.OpenCores.Org - May 2004
--  This core adheres to the GNU public license  
--
-- File name      : pia6821.vhd
--
-- Purpose        : Implements 2 x 8 bit parallel I/O ports
--                  with programmable data direction registers
--                  
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--
-- Author         : John E. Kent      
--
--===========================================================================----
--
-- Revision History:
--
-- Date:          Revision         Author
-- 1 May 2004     0.0              John Kent
-- Initial version developed from ioport.vhd
--
--
-- Unkown date     0.0.1 found at Pacedev repository
-- remove High Z output and and oe signal
--
-- 18 October 2017 0.0.2           DarFpga
-- Set output to low level when in data is in input mode 
-- (to avoid infered latch warning)
--
--===========================================================================----
--
-- Memory Map
--
-- IO + $00 - Port A Data & Direction register
-- IO + $01 - Port A Control register
-- IO + $02 - Port B Data & Direction Direction Register
-- IO + $03 - Port B Control Register
--
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity pia6821 is
-	port (	
-	 	clk       : in    std_logic;
-    rst       : in    std_logic;
-    cs        : in    std_logic;
-    rw        : in    std_logic;
-    addr      : in    std_logic_vector(1 downto 0);
-    data_in   : in    std_logic_vector(7 downto 0);
-	 	data_out  : out   std_logic_vector(7 downto 0);
-	 	irqa      : out   std_logic;
-	 	irqb      : out   std_logic;
-	 	pa_i      : in std_logic_vector(7 downto 0);
-	 	pa_o      : out std_logic_vector(7 downto 0);
-	 	pa_oe     : out std_logic_vector(7 downto 0);
-	 	ca1       : in    std_logic;
-	 	ca2_i     : in std_logic;
-	 	ca2_o     : out std_logic;
-	 	ca2_oe    : out std_logic;
-	 	pb_i      : in std_logic_vector(7 downto 0);
-	 	pb_o      : out std_logic_vector(7 downto 0);
-	 	pb_oe     : out std_logic_vector(7 downto 0);
-	 	cb1       : in    std_logic;
-	 	cb2_i     : in std_logic;
-	 	cb2_o     : out std_logic;
-	 	cb2_oe    : out std_logic
-	 );
-end;
-
-architecture pia_arch of pia6821 is
-
-signal porta_ddr   : std_logic_vector(7 downto 0);
-signal porta_data  : std_logic_vector(7 downto 0);
-signal porta_ctrl  : std_logic_vector(5 downto 0);
-signal porta_read  : std_logic;
-
-signal portb_ddr   : std_logic_vector(7 downto 0);
-signal portb_data  : std_logic_vector(7 downto 0);
-signal portb_ctrl  : std_logic_vector(5 downto 0);
-signal portb_read  : std_logic;
-signal portb_write : std_logic;
-
-signal ca1_del     : std_logic;
-signal ca1_rise    : std_logic;
-signal ca1_fall    : std_logic;
-signal ca1_edge    : std_logic;
-signal irqa1       : std_logic;
-
-signal ca2_del     : std_logic;
-signal ca2_rise    : std_logic;
-signal ca2_fall    : std_logic;
-signal ca2_edge    : std_logic;
-signal irqa2       : std_logic;
-signal ca2_out     : std_logic;
-
-signal cb1_del     : std_logic;
-signal cb1_rise    : std_logic;
-signal cb1_fall    : std_logic;
-signal cb1_edge    : std_logic;
-signal irqb1       : std_logic;
-
-signal cb2_del     : std_logic;
-signal cb2_rise    : std_logic;
-signal cb2_fall    : std_logic;
-signal cb2_edge    : std_logic;
-signal irqb2       : std_logic;
-signal cb2_out     : std_logic;
-
-begin
-
--------------------------------
--
-- read I/O port
--
--------------------------------
-
-pia_read : process(	addr,	cs,
-                    irqa1, irqa2, irqb1, irqb2,
-                    porta_ddr,  portb_ddr,
-										porta_data, portb_data,
-										porta_ctrl, portb_ctrl,
-						   			pa_i,       pb_i )
-variable count : integer;
-begin
-      case addr is
-	     when "00" =>
-		    for count in 0 to 7 loop
-			   if porta_ctrl(2) = '0' then
-				  data_out(count) <= porta_ddr(count);
-			     porta_read <= '0';
-            else
-				  if porta_ddr(count) = '1' then
-                data_out(count) <= porta_data(count);
-              else
-                data_out(count) <= pa_i(count);
-              end if;
-			     porta_read <= cs;
-            end if;
-			 end loop;
-			 portb_read <= '0';
-
-	     when "01" =>
-		    data_out <= irqa1 & irqa2 & porta_ctrl;
-			 porta_read <= '0';
-			 portb_read <= '0';
-
-		  when "10" =>
-		    for count in 0 to 7 loop
-			   if portb_ctrl(2) = '0' then
-				  data_out(count) <= portb_ddr(count);
-				  portb_read <= '0';
-            else
-				  if portb_ddr(count) = '1' then
-                data_out(count) <= portb_data(count);
-              else
-                data_out(count) <= pb_i(count);
-				  end if;
-				  portb_read <= cs;
-            end if;
-			 end loop;
-			 porta_read <= '0';
-
-		  when "11" =>
-		    data_out <= irqb1 & irqb2 & portb_ctrl;
-			 porta_read <= '0';
-			 portb_read <= '0';
-
-		  when others =>
-		    data_out <= "00000000";
-			 porta_read <= '0';
-			 portb_read <= '0';
-
-		end case;
-end process;
-
---------------------------------
--
-- Write I/O ports
--
---------------------------------
-
-pia_write : process( clk, rst, addr, cs, rw, data_in,
-                        porta_ctrl, portb_ctrl,
-                        porta_data, portb_data,
-						porta_ddr, portb_ddr )
-begin
-  if rst = '1' then
-      porta_ddr   <= "00000000";
-      porta_data  <= "00000000";
-      porta_ctrl  <= "000000";
-      portb_ddr   <= "00000000";
-      portb_data  <= "00000000";
-		portb_ctrl  <= "000000";
-		portb_write <= '0';
-  elsif clk'event and clk = '1' then
-    if cs = '1' and rw = '0' then
-      case addr is
-	     when "00" =>
-		    if porta_ctrl(2) = '0' then
-		       porta_ddr  <= data_in;
-		       porta_data <= porta_data;
-			 else
-		       porta_ddr  <= porta_ddr;
-		       porta_data <= data_in;
-			 end if;
-			 porta_ctrl  <= porta_ctrl;
-		    portb_ddr   <= portb_ddr;
-		    portb_data  <= portb_data;
-			 portb_ctrl  <= portb_ctrl;
-			 portb_write <= '0';
-		  when "01" =>
-		    porta_ddr   <= porta_ddr;
-		    porta_data  <= porta_data;
-			 porta_ctrl  <= data_in(5 downto 0);
-		    portb_ddr   <= portb_ddr;
-		    portb_data  <= portb_data;
-			 portb_ctrl  <= portb_ctrl;
-			 portb_write <= '0';
-	     when "10" =>
-		    porta_ddr   <= porta_ddr;
-		    porta_data  <= porta_data;
-			 porta_ctrl  <= porta_ctrl;
-		    if portb_ctrl(2) = '0' then
-		       portb_ddr   <= data_in;
-		       portb_data  <= portb_data;
-			    portb_write <= '0';
-			 else
-		       portb_ddr   <= portb_ddr;
-		       portb_data  <= data_in;
-			    portb_write <= '1';
-			 end if;
-			 portb_ctrl  <= portb_ctrl;
-		  when "11" =>
-		    porta_ddr   <= porta_ddr;
-		    porta_data  <= porta_data;
-			 porta_ctrl  <= porta_ctrl;
-		    portb_ddr   <= portb_ddr;
-		    portb_data  <= portb_data;
-			 portb_ctrl  <= data_in(5 downto 0);
-			 portb_write <= '0';
-		  when others =>
-		    porta_ddr   <= porta_ddr;
-		    porta_data  <= porta_data;
-			 porta_ctrl  <= porta_ctrl;
-		    portb_ddr   <= portb_ddr;
-		    portb_data  <= portb_data;
-			 portb_ctrl  <= portb_ctrl;
-			 portb_write <= '0';
-		end case;
-	 else
-		    porta_ddr   <= porta_ddr;
-		    porta_data  <= porta_data;
-			 porta_ctrl  <= porta_ctrl;
-		    portb_data  <= portb_data;
-		    portb_ddr   <= portb_ddr;
-			 portb_ctrl  <= portb_ctrl;
-			 portb_write <= '0';
-	 end if;
-  end if;
-end process;
-
---------------------------------
--
-- direction control port a
--
---------------------------------
-porta_direction : process ( porta_data, porta_ddr )
-variable count : integer;
-begin
-  for count in 0 to 7 loop
-    if porta_ddr(count) = '1' then
-      pa_o(count) <= porta_data(count);
-		pa_oe(count) <= '1';
-    else
-      pa_o(count) <= '0'; 
-      pa_oe(count) <= '0';
-    end if;
-  end loop;
-end process;
-
---------------------------------
--
-- CA1 Edge detect
--
---------------------------------
-ca1_input : process( clk, rst, ca1, ca1_del,
-                     ca1_rise, ca1_fall, ca1_edge,
-							irqa1, porta_ctrl, porta_read )
-begin
-  if rst = '1' then
-    ca1_del  <= '0';
-	 ca1_rise <= '0';
-    ca1_fall <= '0';
-	 ca1_edge <= '0';
-	 irqa1    <= '0';
-  elsif clk'event and clk = '0' then
-    ca1_del  <= ca1;
-    ca1_rise <= (not ca1_del) and ca1;
-    ca1_fall <= ca1_del and (not ca1);
-	 if ca1_edge = '1' then
-	    irqa1 <= '1';
-	 elsif porta_read = '1' then
-	    irqa1 <= '0';
-    else
-	    irqa1 <= irqa1;
-    end if;
-  end if;  
-
-  if porta_ctrl(1) = '0' then
-	 ca1_edge <= ca1_fall;
-  else
-	 ca1_edge <= ca1_rise;
-  end if;
-end process;
-
---------------------------------
--
-- CA2 Edge detect
--
---------------------------------
-ca2_input : process( clk, rst, ca2_i, ca2_del,
-                     ca2_rise, ca2_fall, ca2_edge,
-							irqa2, porta_ctrl, porta_read )
-begin
-  if rst = '1' then
-    ca2_del  <= '0';
-	 ca2_rise <= '0';
-    ca2_fall <= '0';
-	 ca2_edge <= '0';
-	 irqa2    <= '0';
-  elsif clk'event and clk = '0' then
-    ca2_del  <= ca2_i;
-    ca2_rise <= (not ca2_del) and ca2_i;
-    ca2_fall <= ca2_del and (not ca2_i);
-	 if porta_ctrl(5) = '0' and ca2_edge = '1' then
-	    irqa2 <= '1';
-	 elsif porta_read = '1' then
-	    irqa2 <= '0';
-    else
-	    irqa2 <= irqa2;
-    end if;
-  end if;  
-
-  if porta_ctrl(4) = '0' then
-	 ca2_edge <= ca2_fall;
-  else
-	 ca2_edge <= ca2_rise;
-  end if;
-end process;
-
---------------------------------
--
-- CA2 output control
--
---------------------------------
-ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
-begin
-  if rst='1' then
-    ca2_out <= '0';
-  elsif clk'event and clk='0' then
-    case porta_ctrl(5 downto 3) is
-    when "100" => -- read PA clears, CA1 edge sets
-      if porta_read = '1' then
-	     ca2_out <= '0';
-      elsif ca1_edge = '1' then
-	     ca2_out <= '1';
-      else
-	     ca2_out <= ca2_out;
-      end if;
-    when "101" => -- read PA clears, E sets
-      ca2_out <= not porta_read;
-    when "110" =>	-- set low
-	   ca2_out <= '0';
-    when "111" =>	-- set high
-	   ca2_out <= '1';
-    when others => -- no change
-	   ca2_out <= ca2_out;
-    end case;
-  end if;
-end process;
-
---------------------------------
--
-- CA2 direction control
--
---------------------------------
-ca2_direction : process( porta_ctrl, ca2_out )
-begin
-  if porta_ctrl(5) = '0' then
-   ca2_oe <= '0';
-   ca2_o <= '0'; 
-  else
-   ca2_o <= ca2_out;
-	ca2_oe <= '1';
-  end if;
-end process;
-
---------------------------------
--
-- direction control port b
--
---------------------------------
-portb_direction : process ( portb_data, portb_ddr )
-variable count : integer;
-begin
-  for count in 0 to 7 loop
-    if portb_ddr(count) = '1' then
-      pb_o(count) <= portb_data(count);
-		pb_oe(count) <= '1';
-    else
-      pb_o(count) <= '0'; 
-      pb_oe(count) <= '0';
-    end if;
-  end loop;
-end process;
-
---------------------------------
--
-- CB1 Edge detect
--
---------------------------------
-cb1_input : process( clk, rst, cb1, cb1_del,
-                     cb1_rise, cb1_fall, cb1_edge,
-							irqb1, portb_ctrl, portb_read )
-begin
-  if rst = '1' then
-    cb1_del  <= '0';
-	 cb1_rise <= '0';
-    cb1_fall <= '0';
-	 cb1_edge <= '0';
-	 irqb1    <= '0';
-  elsif clk'event and clk = '0' then
-    cb1_del  <= cb1;
-    cb1_rise <= (not cb1_del) and cb1;
-    cb1_fall <= cb1_del and (not cb1);
-	 if cb1_edge = '1' then
-	    irqb1 <= '1';
-	 elsif portb_read = '1' then
-	    irqb1 <= '0';
-    else
-	    irqb1 <= irqb1;
-    end if;
-  end if;
-    
-  if portb_ctrl(1) = '0' then
-	 cb1_edge <= cb1_fall;
-  else
-	 cb1_edge <= cb1_rise;
-  end if;
-end process;
-
---------------------------------
--
-- CB2 Edge detect
--
---------------------------------
-cb2_input : process( clk, rst, cb2_i, cb2_del,
-                     cb2_rise, cb2_fall, cb2_edge,
-							irqb2, portb_ctrl, portb_read )
-begin
-  if rst = '1' then
-    cb2_del  <= '0';
-	 cb2_rise <= '0';
-    cb2_fall <= '0';
-	 cb2_edge <= '0';
-	 irqb2    <= '0';
-  elsif clk'event and clk = '0' then
-    cb2_del  <= cb2_i;
-    cb2_rise <= (not cb2_del) and cb2_i;
-    cb2_fall <= cb2_del and (not cb2_i);
-	 if portb_ctrl(5) = '0' and cb2_edge = '1' then
-	    irqb2 <= '1';
-	 elsif portb_read = '1' then
-	    irqb2 <= '0';
-    else
-	    irqb2 <= irqb2;
-    end if;
-  end if;
-    
-  if portb_ctrl(4) = '0' then
-	 cb2_edge <= cb2_fall;
-  else
-	 cb2_edge <= cb2_rise;
-  end if;
-
-end process;
-
---------------------------------
--
-- CB2 output control
--
---------------------------------
-cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
-begin
-  if rst='1' then
-    cb2_out <= '0';
-  elsif clk'event and clk='0' then
-    case portb_ctrl(5 downto 3) is
-    when "100" => -- write PB clears, CA1 edge sets
-      if portb_write = '1' then
-	     cb2_out <= '0';
-      elsif cb1_edge = '1' then
-	     cb2_out <= '1';
-      else
-	     cb2_out <= cb2_out;
-      end if;
-    when "101" => -- write PB clears, E sets
-      cb2_out <= not portb_write;
-    when "110" =>	-- set low
-	   cb2_out <= '0';
-    when "111" =>	-- set high
-	   cb2_out <= '1';
-    when others => -- no change
-	   cb2_out <= cb2_out;
-    end case;
-  end if;
-end process;
-
---------------------------------
--
-- CB2 direction control
--
---------------------------------
-cb2_direction : process( portb_ctrl, cb2_out )
-begin
-  if portb_ctrl(5) = '0' then
-    cb2_oe <= '0';
-    cb2_o <=  '0'; 
-  else
-    cb2_o <= cb2_out;
-	 cb2_oe <= '1';
-  end if;
-end process;
-
---------------------------------
--
-- IRQ control
--
---------------------------------
-pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
-begin
-  irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
-  irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
-end process;
-
-end pia_arch;
-	
--- a/Hardware/rtl/sdram.sv
+++ b/Hardware/rtl/sdram.sv
@@ -4,21 +4,21 @@
 // sdram controller implementation for the MiST board
 // https://github.com/mist-devel/mist-board
 // 
-// Copyright (c) 2013 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
 // Copyright (c) 2019 Gyorgy Szombathelyi
 //
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
 // This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //

 module sdram (
@@ -46,11 +46,11 @@ module sdram (
 	input      [15:0] port1_d,
 	output reg [15:0] port1_q,

-	input      [16:1] cpu1_addr,
+	input      [19:1] cpu1_addr,
 	output reg [15:0] cpu1_q,
-	input      [16:1] cpu2_addr,
+	input      [19:1] cpu2_addr,
 	output reg [15:0] cpu2_q,
-	input      [16:1] cpu3_addr,
+	input      [19:1] cpu3_addr,
 	output reg [15:0] cpu3_q,

 	input             port2_req,
@@ -60,11 +60,13 @@ module sdram (
 	input       [1:0] port2_ds,
 	input      [15:0] port2_d,
 	output reg [31:0] port2_q,
-	
-	input      [16:2] sp_addr,
+
+	input      [17:2] sp_addr,
 	output reg [31:0] sp_q
 );

+parameter  MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
+
 localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 2 cycles@<100MHz
 localparam BURST_LENGTH   = 3'b001; // 000=1, 001=2, 010=4, 011=8
 localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
@@ -74,8 +76,8 @@ localparam NO_WRITE_BURST = 1'b1;   // 0= write burst enabled, 1=only single acc

 localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 

-// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
-localparam RFRSH_CYCLES = 10'd842;
+// 64ms/8192 rows = 7.8us
+localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;

 // ---------------------------------------------------------------------
 // ------------------------ cycle state machine ------------------------
@@ -144,18 +146,19 @@ localparam CMD_PRECHARGE       = 4'b0010;
 localparam CMD_AUTO_REFRESH    = 4'b0001;
 localparam CMD_LOAD_MODE       = 4'b0000;

-reg [3:0]  sd_cmd;   // current command sent to sd ram
-reg [15:0] sd_din;
+reg  [3:0] sd_cmd;   // current command sent to sd ram
+reg [15:0] sd_din;   // Fast Input register latching incoming SDRAM data
+
 // drive control signals according to current command
 assign SDRAM_nCS  = sd_cmd[3];
 assign SDRAM_nRAS = sd_cmd[2];
 assign SDRAM_nCAS = sd_cmd[1];
 assign SDRAM_nWE  = sd_cmd[0];

-reg [24:1] addr_latch[3];
+reg [24:1] addr_latch[2];
 reg [24:1] addr_latch_next[2];
-reg [16:1] addr_last[4];
-reg [16:2] addr_last2[2];
+reg [19:1] addr_last[3:1];
+reg [17:2] addr_last2[2];
 reg [15:0] din_latch[2];
 reg  [1:0] oe_latch;
 reg  [1:0] we_latch;
@@ -175,26 +178,26 @@ reg  [2:0] next_port[2];
 reg  [2:0] port[2];

 reg        refresh;
-reg [10:0] refresh_cnt;
-wire       need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+reg [11:0] refresh_cnt;
+reg        need_refresh;

 // PORT1: bank 0,1
 always @(*) begin
 	if (refresh) begin
 		next_port[0] = PORT_NONE;
-		addr_latch_next[0] = addr_latch[0];
+		addr_latch_next[0] = addr_latch[1];
 	end else if (port1_req ^ port1_state) begin
 		next_port[0] = PORT_REQ;
 		addr_latch_next[0] = { 1'b0, port1_a };
 	end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
 		next_port[0] = PORT_CPU1;
-		addr_latch_next[0] = { 8'd0, cpu1_addr };
+		addr_latch_next[0] = { 5'd0, cpu1_addr };
 	end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
 		next_port[0] = PORT_CPU2;
-		addr_latch_next[0] = { 8'd0, cpu2_addr };
+		addr_latch_next[0] = { 5'd0, cpu2_addr };
 	end else if (cpu3_addr != addr_last[PORT_CPU3]) begin
 		next_port[0] = PORT_CPU3;
-		addr_latch_next[0] = { 8'd0, cpu3_addr };
+		addr_latch_next[0] = { 5'd0, cpu3_addr };
 	end else begin
 		next_port[0] = PORT_NONE;
 		addr_latch_next[0] = addr_latch[0];
@@ -208,7 +211,7 @@ always @(*) begin
 		addr_latch_next[1] = { 1'b1, port2_a };
 	end else if (sp_addr != addr_last2[PORT_SP]) begin
 		next_port[1] = PORT_SP;
-		addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+		addr_latch_next[1] = { 1'b1, 6'd0, sp_addr, 1'b0 };
 	end else begin
 		next_port[1] = PORT_NONE;
 		addr_latch_next[1] = addr_latch[1];
@@ -223,6 +226,7 @@ always @(posedge clk) begin
 	{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
 	sd_cmd <= CMD_NOP;  // default: idle
 	refresh_cnt <= refresh_cnt + 1'd1;
+	need_refresh <= (refresh_cnt >= RFRSH_CYCLES);

 	if(init) begin
 		// initialization takes place at the end of the reset phase
@@ -255,7 +259,7 @@ always @(posedge clk) begin
 				sd_cmd <= CMD_ACTIVE;
 				SDRAM_A <= addr_latch_next[0][22:10];
 				SDRAM_BA <= addr_latch_next[0][24:23];
-				addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+				addr_last[next_port[0]] <= addr_latch_next[0][19:1];
 				if (next_port[0] == PORT_REQ) begin
 					{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
 					ds[0] <= port1_ds;
@@ -270,7 +274,7 @@ always @(posedge clk) begin

 		// bank 2,3
 		if(t == STATE_RAS1) begin
-			refresh <= 1'b0;
+			refresh <= 0;
 			addr_latch[1] <= addr_latch_next[1];
 			{ oe_latch[1], we_latch[1] } <= 2'b00;
 			port[1] <= next_port[1];
@@ -289,10 +293,8 @@ always @(posedge clk) begin
 					{ oe_latch[1], we_latch[1] } <= 2'b10;
 					ds[1] <= 2'b11;
 				end
-			end
-
-			if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
-				refresh <= 1'b1;
+			end else if (need_refresh && !oe_latch[0] & !we_latch[0]) begin
+				refresh <= 1;
 				refresh_cnt <= 0;
 				sd_cmd <= CMD_AUTO_REFRESH;
 			end
@@ -340,6 +342,7 @@ always @(posedge clk) begin
 			endcase;
 		end

+		//set DQM two cycles before the 2nd word in the burst
 		if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];

 		if(t == STATE_READ1b && oe_latch[1]) begin
--- a/Hardware/rtl/tshoot_cmos_ram.vhd
+++ b/Hardware/rtl/tshoot_cmos_ram.vhd
@@ -1,182 +0,0 @@
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support",x"iles.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr) 
-- http://darfpga.blogspot.fr
--   Remove address register when writing
--
-- Modifies March 2022 by Dar 
--   Add init data with tshoot cmos value
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd init with tshoot cmos value
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
-- tshoot cmos settings --
--
--@00-03:Extra fowl every (XXYY XX=value*1000 YY=index default 320A)
-- 0000/0501/0A02/0F03/1404/1905/1E06/2307
-- 2808/2D09/320A/370B/3C0C/410D/460E/4B0F
-- 5010/5511/5A12/5F13
--
--@04-07: Missions for 1 credit (XXYY XX=value YY=index default 0301)
-- 0200/0301/0402/0503
--
--@08-0B: attract mode no/yes (XXYY XX=value YY=index default 0101)	
-- 0000/0101
--
--@0C-0F: pricing selection (XXYY XX=value YY=index [0000 custom, 0909 free play] default 0303)
-- 0000/0101/.../0909
--
--@10-13 -> CC1C-CC1F: coin slot units (XXYY XX=value YY=index, index is used only when custom)
-- 0000/0101/.../6262
--
--@20-23 -> CC24-CC27: unit for credit/bonus credit (XXYY XX=value YY=index)
-- 0000/0101/.../6262
--
--@28-2B: difficulty (XXYY XX=value YY=index default 0505)
-- 0000/0101/../0909
--
--@2C-2F: ?
-- 0300
--
--@30-33: gun recoil no/yes (XXYY XX=value YY=index default 0101)
-- 0000/0101
--
--@34-35: control sum : sum of nibbles from @00 to @33 + 3
-- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
-entity t_shoot_cmos_ram is
-	generic (
-		dWidth : integer := 8;  -- must be  4",x"or tshoot_cmos_ram
-		aWidth : integer := 10  -- must be 10",x"or tshoot_cmos_ram
-	);
-	port (
-		clk : in std_logic;
-		we : in std_logic;
-		addr : in std_logic_vector((aWidth-1) downto 0);
-		d : in std_logic_vector((dWidth-1) downto 0);
-		q : out std_logic_vector((dWidth-1) downto 0)
-	);
-end entity;
-- -----------------------------------------------------------------------
-- tshoot cmos data
-- (ram is 128x4 => only 4 bits/address, that is only 1 hex digit/address)
-
-architecture rtl of t_shoot_cmos_ram is
-subtype addressRange is integer range 0 to ((2**aWidth)-1);
-type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
-	
-signal ram: ramDef := (		
- x"3",x"2",x"0",x"A",x"0",x"3",x"0",x"1",x"0",x"1",x"0",x"1",x"0",x"3",x"0",x"3",
- x"0",x"1",x"0",x"0",x"0",x"4",x"0",x"0",x"0",x"1",x"0",x"0",x"0",x"1",x"0",x"0",  
- x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"5",x"0",x"5",x"0",x"3",x"0",x"0",
- x"0",x"1",x"0",x"1",x"5",x"F",x"A",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- x"0",x"7",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",
- x"0",x"0",x"0",x"7",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"6",
- x"0",x"0",x"0",x"0",x"1",x"5",x"0",x"0",x"0",x"0",x"0",x"5",x"0",x"0",x"0",x"0",
- x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"5",x"0",x"0",x"0",x"0",x"1",x"7",x"0",x"1",
- x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"1",x"8",x"1",x"0",x"0",x"0",x"0",x"0",x"5",
- x"0",x"2",x"D",x"5",x"5",x"7",x"4",x"9",x"4",x"C",x"0",x"0",x"4",x"0",x"3",x"5",
- x"4",x"D",x"5",x"2",x"5",x"3",x"0",x"0",x"4",x"0",x"2",x"0",x"5",x"2",x"4",x"F",
- x"4",x"E",x"0",x"0",x"3",x"9",x"1",x"5",x"4",x"A",x"5",x"2",x"4",x"E",x"0",x"0",
- x"3",x"8",x"3",x"4",x"5",x"4",x"4",x"E",x"4",x"4",x"0",x"0",x"3",x"7",x"2",x"5",
- x"5",x"7",x"5",x"0",x"4",x"2",x"0",x"0",x"3",x"6",x"1",x"0",x"4",x"3",x"4",x"C",
- x"5",x"3",x"0",x"0",x"3",x"5",x"0",x"3",x"4",x"C",x"4",x"5",x"4",x"F",x"0",x"0",
- x"3",x"4",x"7",x"8",x"4",x"4",x"5",x"2",x"5",x"9",x"0",x"0",x"3",x"3",x"2",x"1",
- x"4",x"A",x"5",x"3",x"4",x"3",x"0",x"0",x"3",x"2",x"5",x"0",x"4",x"A",x"4",x"5",
- x"4",x"8",x"0",x"0",x"3",x"1",x"3",x"6",x"5",x"2",x"4",x"D",x"4",x"9",x"0",x"0",
- x"3",x"0",x"1",x"8",x"4",x"B",x"4",x"5",x"4",x"E",x"0",x"0",x"2",x"9",x"1",x"0",
- x"5",x"0",x"4",x"7",x"4",x"4",x"0",x"0",x"2",x"8",x"0",x"0",x"5",x"0",x"4",x"1",
- x"4",x"8",x"0",x"0",x"2",x"7",x"9",x"8",x"4",x"E",x"5",x"6",x"4",x"2",x"0",x"0",
- x"2",x"6",x"7",x"2",x"4",x"1",x"4",x"7",x"5",x"2",x"0",x"0",x"2",x"5",x"2",x"9",
- x"5",x"6",x"4",x"C",x"4",x"7",x"0",x"0",x"2",x"4",x"7",x"3",x"4",x"4",x"4",x"F",
- x"4",x"E",x"0",x"0",x"2",x"3",x"9",x"0",x"5",x"7",x"4",x"5",x"5",x"3",x"0",x"0",
- x"2",x"2",x"6",x"2",x"4",x"A",x"5",x"0",x"4",x"4",x"0",x"0",x"2",x"1",x"8",x"3",
- x"5",x"0",x"4",x"6",x"5",x"A",x"0",x"0",x"2",x"0",x"2",x"1",x"4",x"B",x"4",x"7",
- x"4",x"D",x"0",x"0",x"1",x"9",x"1",x"8",x"4",x"B",x"5",x"2",x"4",x"4",x"0",x"0",
- x"1",x"8",x"9",x"9",x"5",x"3",x"4",x"3",x"4",x"C",x"0",x"0",x"1",x"7",x"2",x"1",
- x"5",x"2",x"4",x"1",x"5",x"7",x"0",x"0",x"1",x"6",x"7",x"8",x"4",x"2",x"4",x"1",
- x"4",x"E",x"0",x"0",x"1",x"5",x"2",x"1",x"5",x"0",x"5",x"6",x"4",x"1",x"0",x"0",
- x"1",x"4",x"5",x"2",x"4",x"A",x"4",x"3",x"2",x"0",x"0",x"0",x"1",x"3",x"7",x"8",
- x"2",x"0",x"4",x"5",x"5",x"3",x"0",x"0",x"1",x"2",x"6",x"4",x"4",x"8",x"4",x"5",
- x"4",x"3",x"0",x"0",x"1",x"1",x"3",x"7",x"4",x"D",x"4",x"2",x"5",x"3",x"0",x"0",
- x"1",x"0",x"6",x"2",x"5",x"2",x"4",x"3",x"4",x"2",x"0",x"0",x"0",x"9",x"3",x"5",
- x"5",x"0",x"4",x"A",x"4",x"5",x"0",x"0",x"0",x"8",x"2",x"8",x"4",x"2",x"4",x"6",
- x"4",x"4",x"0",x"0",x"0",x"7",x"9",x"0",x"4",x"4",x"4",x"1",x"5",x"2",x"0",x"0",
- x"0",x"7",x"5",x"0",x"5",x"3",x"4",x"4",x"5",x"7",x"0",x"0",x"0",x"6",x"7",x"8",
- x"A",x"D",x"0",x"0",x"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
- X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0");
-	
-signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
-signal qReg : std_logic_vector((dWidth-1) downto 0);
-
-begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
--	q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if we = '1' then
-				ram(to_integer(unsigned(addr))) <= d;
-			end if;
-		end if;
-	end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
-process(clk)
-	begin
-		if rising_edge(clk) then
--			qReg <= ram(to_integer(unsigned(rAddrReg)));
--			rAddrReg <= addr;
--			qReg <= ram(to_integer(unsigned(addr)));
-			q <= ram(to_integer(unsigned(addr)));
-		end if;
-	end process;
--q <= ram(to_integer(unsigned(addr)));
-end architecture;
-
--- a/Hardware/rtl/tshoot_sound_board.vhd
+++ b/Hardware/rtl/tshoot_sound_board.vhd
@@ -38,11 +38,9 @@ port(
 sound_trig   : in std_logic;
 sound_ack    : out std_logic;
 audio_out    : out std_logic_vector( 7 downto 0);
- 
- snd_rom_addr : out std_logic_vector(12 downto 0);
- snd_rom_do : in std_logic_vector(7 downto 0);
- 
- dbg_cpu_addr : out std_logic_vector(15 downto 0)
+
+ snd_rom_addr : buffer std_logic_vector(12 downto 0);
+ snd_rom_do   : in  std_logic_vector( 7 downto 0)
 );
 end tshoot_sound_board;

@@ -65,6 +63,8 @@ architecture struct of tshoot_sound_board is
 signal rom_cs    : std_logic;
 signal rom_do    : std_logic_vector( 7 downto 0);

+ signal snd_rom_addr_r : std_logic_vector(12 downto 0);
+
 -- pia port a
 --      bit 0-7 audio output

@@ -86,8 +86,6 @@ architecture struct of tshoot_sound_board is

 begin

-dbg_cpu_addr <= cpu_addr;
-
 -- clock divider
 process (reset, clock_12)
 begin
@@ -116,7 +114,16 @@ end process;
 wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0';
 pia_cs  <= '1' when cpu_addr(15 downto 13) = "001" else '0';
 rom_cs  <= '1' when cpu_addr(15 downto 13) = "111" else '0';
-	
+
+snd_rom_addr <= cpu_addr(12 downto 0) when rom_cs = '1' else snd_rom_addr_r;
+
+process (reset, clock_12)
+begin
+	if rising_edge(clock_12) then
+		snd_rom_addr_r <= snd_rom_addr;
+	end if;
+end process;
+
 -- write enables
 wram_we <=    '1' when cpu_rw_n = '0' and cpu_clock = '1' and wram_cs = '1' else '0';
 pia_rw_n <=   '0' when cpu_rw_n = '0' and pia_cs = '1' else '1'; 
@@ -155,8 +162,6 @@ port map(
 -- addr => cpu_addr(12 downto 0),
 -- data => rom_do
 --);
-
-snd_rom_addr <= cpu_addr(12 downto 0);
 rom_do <= snd_rom_do;

 -- cpu wram 
--- a/Hardware/rtl/williams2.vhd
+++ b/Hardware/rtl/williams2.vhd
@@ -9,9 +9,9 @@
 -- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
 -- http://www.syntiac.com/fpga64.html
 ---------------------------------------------------------------------------------
-- cpu09l - Version : 0128
-- Synthesizable 6809 instruction compatible VHDL CPU core
-- Copyright (C) 2003 - 2010 John Kent
+-- mc6809 
+-- Cycle-Accurate 6809 Core 
+-- Copyright (c) 2016, Greg Miller
 ---------------------------------------------------------------------------------
 -- cpu68 - Version 9th Jan 2004 0.8
 -- 6800/01 compatible CPU core 
@@ -46,64 +46,83 @@ use ieee.numeric_std.all;

 entity williams2 is
 port(
- clock_12     : in std_logic;
- reset        : in std_logic;
--prg low
- prg_rom_addr : out std_logic_vector(13 downto 0);
- prg_rom_do   : in std_logic_vector(7 downto 0);
--banks 
- rom_addr     : out std_logic_vector(16 downto 0);
- rom_do       : in  std_logic_vector( 7 downto 0);
- rom_rd       : out std_logic;
--snd 
- snd_rom_addr : out std_logic_vector(12 downto 0);
- snd_rom_do   : in std_logic_vector(7 downto 0);
--gfx
- gfx_rom_addr : out std_logic_vector(12 downto 0);
- gfx_rom_do   : in std_logic_vector(23 downto 0);
--dec
- dec_rom_addr : out std_logic_vector(8 downto 0);
- dec_rom_do   : in std_logic_vector(7 downto 0);
-- tv15Khz_mode : in std_logic;
- video_r        : out std_logic_vector(3 downto 0);
- video_g        : out std_logic_vector(3 downto 0);
- video_b        : out std_logic_vector(3 downto 0);
- video_i        : out std_logic_vector(3 downto 0);
- video_csync    : out std_logic;
- video_blankn   : out std_logic;
- video_hs       : out std_logic;
- video_vs       : out std_logic;
- 
- audio_out      : out std_logic_vector(7 downto 0);
- 
+ clock_12      : in std_logic;
+ reset         : in std_logic;
+ hwsel         : in std_logic_vector(1 downto 0);
+
+ rom_addr      : buffer std_logic_vector(17 downto 0);
+ rom_do        : in  std_logic_vector( 7 downto 0);
+ rom_rd        : out std_logic;
+ gfx_rom_addr  : out std_logic_vector(13 downto 0);
+ gfx_rom_do    : in  std_logic_vector(31 downto 0);
+ snd_rom_addr  : out std_logic_vector(12 downto 0);
+ snd_rom_do    : in  std_logic_vector( 7 downto 0);
+ snd2_rom_addr : out std_logic_vector(16 downto 0);
+ snd2_rom_do   : in  std_logic_vector( 7 downto 0);
+
+ video_r       : out std_logic_vector(3 downto 0);
+ video_g       : out std_logic_vector(3 downto 0);
+ video_b       : out std_logic_vector(3 downto 0);
+ video_i       : out std_logic_vector(3 downto 0);
+ video_csync   : out std_logic;
+ video_blankn  : out std_logic;
+ video_hs      : out std_logic;
+ video_vs      : out std_logic;
+
+ audio_left    : out unsigned(16 downto 0);
+ audio_right   : out unsigned(16 downto 0);
+
+ input1        : in  std_logic_vector(7 downto 0);
+ input2        : in  std_logic_vector(7 downto 0);
+ input_sel     : out std_logic;
+
 btn_auto_up          : in std_logic;
 btn_advance          : in std_logic; 
 btn_high_score_reset : in std_logic;
+ btn_coin      : in std_logic;
+
+ cnt_4ms_o     : out std_logic;

- btn_gobble   : in std_logic;
- btn_grenade  : in std_logic;
- btn_coin     : in std_logic;
- btn_start_2  : in std_logic;
- btn_start_1  : in std_logic;
- btn_trigger  : in std_logic;
- 
-- gun_h        : in std_logic_vector(5 downto 0);
-- gun_v        : in std_logic_vector(5 downto 0);
- 
-- cnt_4ms_o    : out std_logic;
- btn_left  		: in std_logic;
- btn_right  	: in std_logic;
- btn_up  		: in std_logic;
- btn_down  		: in std_logic;
- 
 sw_coktail_table : in std_logic;
 seven_seg : out std_logic_vector( 7 downto 0);
- 
- dbg_out : out std_logic_vector(31 downto 0)
+
+ dl_clock       : in  std_logic;
+ dl_addr        : in  std_logic_vector(15 downto 0);
+ dl_data        : in  std_logic_vector( 7 downto 0);
+ dl_wr          : in  std_logic;
+ up_data        : out std_logic_vector(7 downto 0);
+ cmos_wr        : in std_logic
 );
 end williams2;

 architecture struct of williams2 is
+	component mc6809is is
+	port (
+		CLK      : in  std_logic;
+		fallE_en : in  std_logic;
+		fallQ_en : in  std_logic;
+		D        : in  std_logic_vector( 7 downto 0);
+		Dout     : out std_logic_vector( 7 downto 0);
+		ADDR     : out std_logic_vector(15 downto 0);
+		RnW      : out std_logic;
+		BS       : out std_logic;
+		BA       : out std_logic;
+		nIRQ     : in  std_logic := '1';
+		nFIRQ    : in  std_logic := '1';
+		nNMI     : in  std_logic := '1';
+		AVMA     : out std_logic;
+		BUSY     : out std_logic;
+		LIC      : out std_logic;
+		nHALT    : in  std_logic := '1';
+		nRESET   : in  std_logic := '1';
+		nDMABREQ : in  std_logic := '1'
+	);
+	end component mc6809is;
+ 
+ constant HW_TSHOOT : std_logic_vector(1 downto 0) := "00";
+ constant HW_JOUST2 : std_logic_vector(1 downto 0) := "01";
+ constant HW_INFERNO : std_logic_vector(1 downto 0) := "10";
+ constant HW_MYSTICM : std_logic_vector(1 downto 0) := "11";

 signal en_pixel     : std_logic := '0'; 
 signal video_access : std_logic;
@@ -118,6 +137,7 @@ architecture struct of williams2 is
 signal cpu_do     : std_logic_vector( 7 downto 0);
 signal cpu_rw_n   : std_logic;
 signal cpu_irq    : std_logic;
+ signal cpu_firq   : std_logic;

 signal addr_bus      : std_logic_vector(15 downto 0);
 signal data_bus_high : std_logic_vector( 7 downto 0);
@@ -127,7 +147,7 @@ architecture struct of williams2 is

 signal decod_addr : std_logic_vector( 8 downto 0);
 signal decod_do   : std_logic_vector( 7 downto 0);
- 
+
 signal vram_addr    : std_logic_vector(13 downto 0);
 signal vram_cs      : std_logic;
 signal vram_we      : std_logic;
@@ -143,7 +163,8 @@ architecture struct of williams2 is
 signal vram_l2_we   : std_logic;
 signal vram_h2_do   : std_logic_vector( 3 downto 0);
 signal vram_h2_we   : std_logic;
- 
+
+ signal rom_addr_r   : std_logic_vector(17 downto 0);
 signal rom_bank_a_do   : std_logic_vector( 7 downto 0);
 signal rom_bank_b_do   : std_logic_vector( 7 downto 0);
 signal rom_bank_c_do   : std_logic_vector( 7 downto 0);
@@ -152,8 +173,9 @@ architecture struct of williams2 is
 signal rom_prog1_do    : std_logic_vector( 7 downto 0);
 signal rom_prog2_do    : std_logic_vector( 7 downto 0);

-- signal sram0_we        : std_logic;
-- signal sram0_do        : std_logic_vector( 7 downto 0);
+ signal sram_cs        : std_logic;
+ signal sram_we        : std_logic;
+ signal sram_do        : std_logic_vector( 7 downto 0);

 signal page    : std_logic_vector( 2 downto 0);
 signal page_cs : std_logic;
@@ -189,8 +211,9 @@ architecture struct of williams2 is
 signal xscroll_high_cs : std_logic;
 signal xscroll_low_cs  : std_logic;
 signal xscroll         : std_logic_vector(11 downto 0);
- 
- signal graph_addr : std_logic_vector(12 downto 0);
+ signal xscroll_adj     : std_logic_vector( 2 downto 0);
+
+ signal graph_addr : std_logic_vector(13 downto 0);
 signal graph1_do  : std_logic_vector( 7 downto 0);
 signal graph2_do  : std_logic_vector( 7 downto 0);
 signal graph3_do  : std_logic_vector( 7 downto 0);
@@ -229,7 +252,6 @@ architecture struct of williams2 is
 signal bg_pixels_5 : std_logic_vector( 3 downto 0);
 signal bg_pixels_6 : std_logic_vector( 3 downto 0);
 signal bg_pixels_7 : std_logic_vector( 3 downto 0);
- signal bg_pixels_8 : std_logic_vector( 3 downto 0);
 signal bg_pixels_shifted : std_logic_vector(3 downto 0);
 
 signal hsync0,hsync1,hsync2,csync,hblank,vblank : std_logic;
@@ -264,35 +286,22 @@ architecture struct of williams2 is
 signal cpu_ba      : std_logic;
 signal cpu_bs      : std_logic;
 
- signal gun_bin_code  : std_logic_vector(5 downto 0);
- signal gun_gray_code : std_logic_vector(5 downto 0);
-
 signal sound_select : std_logic_vector(7 downto 0);
 signal sound_trig   : std_logic;
+ signal sound_trig2  : std_logic;
 signal sound_ack    : std_logic;
- 
- signal left_r  : std_logic;
- signal right_r : std_logic;
- signal up_r    : std_logic;
- signal down_r  : std_logic;

- signal gun_update_r  : std_logic; 
- signal div_h ,div_v  : std_logic_vector(4 downto 0);
- signal gun_h, gun_v  : std_logic_vector(5 downto 0);
- 
- signal sound_cpu_addr : std_logic_vector(15 downto 0);
+ signal audio        : std_logic_vector( 7 downto 0);
+ signal pia_audio    : std_logic_vector( 7 downto 0);
+ signal speech_out   : std_logic_vector(15 downto 0);
+ signal fm_left      : unsigned(15 downto 0);
+ signal fm_right     : unsigned(15 downto 0);

+ signal ic79_a   : std_logic_vector(3 downto 0);
+ signal ic79_b   : std_logic_vector(3 downto 0);
+ signal ic79_out : std_logic;
 begin

-- for debug
-process (clock_12) 
-begin
-	if rising_edge(clock_12) then 
--		dbg_out(15 downto 0) <= cpu_addr;
-		dbg_out(15 downto 0) <= sound_cpu_addr;		
-	end if;
-end process;
-		
 -- make pixels counters and cpu clock
 -- in original hardware cpu clock = 1us = 6pixels
 -- here one make 2 cpu clock within 1us
@@ -305,21 +314,21 @@ begin
 		video_access <= '0';
 		graph_access <= '0';
 		rom_rd <= '0';
-			
+
 		if pixel_cnt = "000" then en_cpu <= '1';       end if;
 		if pixel_cnt = "001" then rom_rd <= '1';       end if;
 		if pixel_cnt = "011" then video_access <= '1'; end if;			
 		if pixel_cnt = "100" then graph_access <= '1'; end if;
-	
+
 		if en_pixel = '1' then 		
 			if pixel_cnt = "101" then
 				pixel_cnt <= "000";
 			else
 				pixel_cnt <= pixel_cnt + '1';
 			end if;
-					
+
 		end if;						
-			
+
 	end if;
 end process;

@@ -341,7 +350,7 @@ begin
 		
 			if (pixel_cnt = "101") and (en_pixel = '1' ) then
 				hcnt <= hcnt + '1';
-				if hcnt = "111111" then
+				if hcnt = "111101" then
 					if vcnt = '1'&X"FF" then
 						vcnt <= '0'&X"FC";
 					else
@@ -389,7 +398,6 @@ begin
 			bg_pixels_5 <= bg_pixels_4;
 			bg_pixels_6 <= bg_pixels_5;
 			bg_pixels_7 <= bg_pixels_6;
-			bg_pixels_8 <= bg_pixels_7;
 			
 			if flip = '0' then 
 				fg_pixels_0 <= fg_pixels(23 downto 20);
@@ -401,7 +409,8 @@ begin
 	end if;
 end process;

-with xscroll(2 downto 0) select
+xscroll_adj <= xscroll(2 downto 0) when hwsel = HW_TSHOOT else xscroll(2 downto 0) xor "111";
+with xscroll_adj(2 downto 0) select
 bg_pixels_shifted <= 
 	bg_pixels_0 when "000",
 	bg_pixels_1 when "001",
@@ -411,13 +420,20 @@ bg_pixels_shifted <=
 	bg_pixels_5 when "101",
 	bg_pixels_6 when "110",
 	bg_pixels_7 when others;
-	
+
+-- ic79 74LS85 controls low background color bank bit w.r.t ligne number (vcnt)
+ic79_a   <= bg_color_bank(0) & bg_color_bank(0) & "01";
+ic79_b   <= "00"&vcnt(7)&vcnt(6);
+ic79_out <= '1' when (ic79_a > ic79_b) or ((ic79_a = ic79_b) and (vcnt(5)='0')) else '0';
+
 --	mux bus addr and pixels data to palette addr
 palette_addr <=
 	addr_bus(10 downto 1) when color_cs = '1' else 
 	fg_color_bank & fg_pixels_0 when fg_pixels_0 /= x"0" else
+	bg_color_bank(5 downto 0) & bg_pixels_shifted when hwsel = HW_JOUST2 else
+	bg_color_bank(5 downto 3) & bg_color_bank(1) & bg_color_bank(2) & ic79_out & bg_pixels_shifted when hwsel = HW_MYSTICM else
 	bg_color_bank(5 downto 3) & vcnt(7 downto 5) & bg_pixels_shifted;
-	
+
 -- palette output to colors bits
 video_r <= palette_lo_do(3 downto 0);
 video_g <= palette_lo_do(7 downto 4);
@@ -440,20 +456,23 @@ begin
 			if video_access = '1' then
 				fg_pixels <= vram_h0_do & vram_l0_do & vram_h1_do & vram_l1_do & vram_h2_do & vram_l2_do;
 				-- map graphics address
-				flip_bg_a <= map_do(7);
-				if map_do(7) = '0' then
-					graph_addr <= map_do(6 downto 0) & vcnt(3 downto 0) & map_x(1) & map_x(0);
+				if hwsel = HW_JOUST2 then
+					graph_addr <= map_do(7 downto 0) & vcnt(3 downto 0) & map_x(1) & map_x(0);         -- /!\ bit supplementaire
 				else
-					graph_addr <= map_do(6 downto 0) & vcnt(3 downto 0) & not map_x(1) & not map_x(0);
+					flip_bg_a <= map_do(7);
+					if map_do(7) = '0' then
+						graph_addr <= '0' & map_do(6 downto 0) & vcnt(3 downto 0) & map_x(1) & map_x(0);
+					else
+						graph_addr <= '0' & map_do(6 downto 0) & vcnt(3 downto 0) & not map_x(1) & not map_x(0);
+					end if;
 				end if;
 			else
 				fg_pixels <= fg_pixels(19 downto 0) & X"0" ;		
 			end if;
-			
+
 			if graph_access = '1' then
 				flip_bg <= flip_bg_a;
--				bg_pixels <= graph1_do & graph2_do & graph3_do;
-				bg_pixels <= gfx_rom_do;
+				bg_pixels <= graph1_do & graph2_do & graph3_do;
 			else
 				if flip_bg = '0' then 
 					bg_pixels <= bg_pixels(19 downto 0) & X"0";
@@ -461,34 +480,35 @@ begin
 					bg_pixels <= X"0" & bg_pixels(23 downto 4);		
 				end if;
 			end if;
--		else
--		end if;
+		else
+		--end if;
 		end if;
 	end if;
 end process;
-				
-
-gun_bin_code <= gun_v when pia_io1_ca2_o = '0' else gun_h;

 pias_clock <= not clock_12;
-pia_io1_pa_i <= not btn_trigger & '0'& gun_gray_code;
-pia_io1_pb_i <= btn_start_2 & btn_start_1 & "1111" & btn_gobble & btn_grenade; 
-pia_io2_pa_i <= sw_coktail_table & "000" & btn_coin & btn_high_score_reset & btn_advance & btn_auto_up; 
+pia_io1_pa_i <= input1;
+pia_io1_pb_i <= input2; 
+pia_io2_pa_i <= sw_coktail_table & "000" & btn_coin & btn_high_score_reset & btn_advance & btn_auto_up;
+input_sel <= pia_io1_ca2_o;

 -- video syncs to pia
-vcnt_240  <= '0' when vcnt = '1'&X"F0" else '1';
+vcnt_240  <= '1' when vcnt = '1'&X"F0" else '0';
 cnt_4ms   <= vcnt(5);
--cnt_4ms_o <= vcnt(5);
+cnt_4ms_o <= vcnt(5);

 -- pia rom irqs to cpu
-cpu_irq  <= pia_io1_irqa or pia_io1_irqb or pia_io2_irqa or pia_io2_irqb;
+cpu_irq  <= pia_io1_irqa or pia_io1_irqb or pia_io2_irqa or pia_io2_irqb when hwsel = HW_TSHOOT else
+            pia_io1_irqb or pia_io2_irqa or pia_io2_irqb when hwsel = HW_MYSTICM else
+            pia_io2_irqa or pia_io2_irqb;
+cpu_firq <= pia_io1_irqa when hwsel = HW_MYSTICM else '0';

 -- chip select/we
 we_bus  <= '1' when (cpu_rw_n = '0' or blit_rw_n = '0') and en_pixel = '1' and en_cpu = '1' else '0';

 vram_cs <= '1' when color_cs = '0' and 
-						( (blit_has_bus = '0' and  addr_bus < x"C000") or
-						  (blit_has_bus = '1' and (addr_bus < x"9000" or addr_bus >= x"C000" or dma_inh_n = '0'))) else '0';
+                    ( (blit_has_bus = '0' and (addr_bus < x"C000" or hwsel = HW_JOUST2)) or
+                      (blit_has_bus = '1' and (addr_bus < x"9000" or (addr_bus >= x"C000" and hwsel = HW_TSHOOT) or dma_inh_n = '0'))) else '0';

 color_cs         <= '1' when addr_bus(15 downto 12) = X"8" and page(1 downto 0) = "11" else '0'; -- 8000-8FFF & page 3
 rom_bank_cs      <= '1' when addr_bus(15) = '0' and (page /= "000" and page /= "111")  else '0'; -- 0000-7000
@@ -504,12 +524,14 @@ flip_cs          <= '1' when cpu_addr(15 downto  5) = X"CB"&"100" else '0'; -- C
 dma_inh_cs       <= '1' when cpu_addr(15 downto  5) = X"CB"&"101" else '0'; -- CBA0-CBBF
 pia_io2_cs       <= '1' when addr_bus(15 downto  7) = X"C9"&"1" and addr_bus(3 downto 2) = "00" else '0'; -- C980-C983
 pia_io1_cs       <= '1' when addr_bus(15 downto  7) = X"C9"&"1" and addr_bus(3 downto 2) = "01" else '0'; -- C984-C987
+sram_cs          <= '1' when addr_bus(15 downto 12) = X"D" and (hwsel = HW_INFERNO or hwsel = HW_MYSTICM) else '0'; -- D000-DFFF

 palette_lo_we <= '1' when we_bus = '1' and color_cs = '1' and addr_bus(0) = '0' else '0';
 palette_hi_we <= '1' when we_bus = '1' and color_cs = '1' and addr_bus(0) = '1' else '0';
 map_we        <= '1' when we_bus = '1' and addr_bus(15 downto 11) = X"C"&'0'    else '0'; -- C000-C7FF
 cmos_we       <= '1' when we_bus = '1' and addr_bus(15 downto 10) = x"C"&"11"   else '0'; -- CC00-CFFF
 vram_we       <= '1' when we_bus = '1' and vram_cs = '1' else '0';
+sram_we       <= '1' when we_bus = '1' and sram_cs = '1' else '0';

 -- dispatch we to devices with respect to decoder bits 7-6 and blitter inhibit
 vram_l0_we  <= '1' when vram_we = '1' and blit_wr_inh_l = '0' and decod_do(7 downto 6)  = "00" else '0';
@@ -520,17 +542,28 @@ vram_h1_we  <= '1' when vram_we = '1' and blit_wr_inh_h = '0' and decod_do(7 dow
 vram_h2_we  <= '1' when vram_we = '1' and blit_wr_inh_h = '0' and decod_do(7 downto 6)  = "10" else '0';

 -- mux banked rom address to external (d)ram
-rom_addr <= "00"&addr_bus(14 downto 0) when (page = "010"                ) else
-				"01"&addr_bus(14 downto 0) when (page = "110"                ) else
-				"10"&addr_bus(14 downto 0) when (page = "001" or page = "011") else
-				"11"&addr_bus(14 downto 0) when (page = "100" or page = "101") else
-				"00"&addr_bus(14 downto 0);
+rom_addr <= rom_addr_r when (cpu_rw_n = '0' or blit_rw_n = '0') else
+            "10000"&addr_bus(12 downto 0) when addr_bus(15 downto 13) = "111" else -- 8K
+            "100010"&addr_bus(11 downto 0) when addr_bus(15 downto 12) = X"D" else -- 4K
+            "000"&addr_bus(14 downto 0) when (page = "010"                ) else
+            "001"&addr_bus(14 downto 0) when (page = "110"                ) else
+            "010"&addr_bus(14 downto 0) when (page = "001" or page = "011") else
+            "011"&addr_bus(14 downto 0) when (page = "100" or page = "101") else
+            rom_addr_r;
+
+process (clock_12)
+begin
+	if rising_edge(clock_12) then 
+		rom_addr_r <= rom_addr;
+	end if;
+end process;

 -- mux data bus between cpu/blitter/roms/io/vram
 data_bus_high <=
--	rom_prog2_do            when addr_bus(15 downto 12) >= X"E" else -- 8K
--	rom_prog1_do            when addr_bus(15 downto 12) >= X"D" else -- 4K	
-	prg_rom_do            	when addr_bus(15 downto 12) >= X"D" else -- 12K	
+	sram_do                 when sram_cs = '1' else -- 4K- D000-DFFF
+	rom_do                  when addr_bus(15 downto 12) >= X"D" else
+	--rom_prog2_do            when addr_bus(15 downto 12) >= X"E" else -- 8K
+	--rom_prog1_do            when addr_bus(15 downto 12) >= X"D" else -- 4K	
 	vcnt(7 downto 0)        when addr_bus(15 downto  4)  = X"CBE" else
 	map_do                  when addr_bus(15 downto 11)  = X"C"&'0' else
 	x"0"&cmos_do            when addr_bus(15 downto 10)  = X"C"&"11" else
@@ -651,13 +684,13 @@ if reset='1' then
 	blit_wr_inh_h <= '0';
 	blit_wr_inh_l <= '0';
 else 
-	if rising_edge(clock_12) then 
+	if rising_edge(clock_12) then

 		-- sync cpu_halt in the middle of cpu cycle
 		if video_access = '1' then
 			cpu_halt <= blit_halt;
 		end if;
-		
+
 		--	intialize blit
 		if blit_start = '1' and blit_halt = '0' and video_access = '1' then
 			blit_halt <= '1';
@@ -673,67 +706,67 @@ else
 			blit_addr <= blit_src;
 			blit_rw_n <= '1';
 		end if;
-		
+
 		-- do blit
 		if blit_has_bus = '1' then
-		
-			-- read step (use graph access)			
-			if graph_access = '1' and en_pixel = '0' and blit_go = '1' then 
-			
+
+			-- read step (use graph access)
+			if graph_access = '1' and en_pixel = '0' and blit_go = '1' then
+
 				-- next step will be write
 				blit_addr <= blit_cur_dst;
 				blit_rw_n <= '0';
-				
+
 				-- also prepare next source address w.r.t source stride
 				if blit_cmd(0) = '0' then
-					blit_cur_src <= blit_cur_src + 1;							
-				else 
+					blit_cur_src <= blit_cur_src + 1;
+				else
 					if blit_cur_width = 0  then
-						blit_cur_src <= blit_src_ori + 1;							
-						blit_src_ori <= blit_src_ori + 1;							
-					else 
-						blit_cur_src <= blit_cur_src + 256;							
+						blit_cur_src <= blit_src_ori + 1;
+						blit_src_ori <= blit_src_ori + 1;
+					else
+						blit_cur_src <= blit_cur_src + 256;
 					end if;
 				end if;

 				-- get data from source and prepare data to be written
 				blit_h := not blit_cmd(7);
 				blit_l := not blit_cmd(6);
-				
+
 				-- right shift mode
 				if blit_cmd(5) = '0' then
 					data := data_bus;
 				else
-					data :=  right_nibble & data_bus(7 downto 4); 
-					right_nibble <= data_bus(3 downto 0); 
+					data :=  right_nibble & data_bus(7 downto 4);
+					right_nibble <= data_bus(3 downto 0);
 				end if;
-				
+
 				-- transparent mode : don't write pixel if src = 0
-				if blit_cmd(3) = '1' then 
+				if blit_cmd(3) = '1' then
 					if data(7 downto 4) = x"0" then blit_h := '0'; end if;
-					if data(3 downto 0) = x"0" then blit_l := '0'; end if;					
-				end if; 
-					
+					if data(3 downto 0) = x"0" then blit_l := '0'; end if;
+				end if;
+
 				-- solid mode : write color instead of src data
 				if blit_cmd(4) = '1' then
 					data := blit_color;
-				else 
+				else
 					data := data;
 				end if;
-				
+
 				-- put data to written on bus with write inhibits
 				blit_data <= data;
-				blit_wr_inh_h <= not blit_h; 
+				blit_wr_inh_h <= not blit_h;
 				blit_wr_inh_l <= not blit_l;
-					
+
 			end if;
-			
+
 			-- write step (use cpu access)
 			if en_cpu = '1' and en_pixel = '0' and blit_go = '1' then
 				-- next step will be read
 				blit_addr <= blit_cur_src;
 				blit_rw_n <= '1';
-				
+
 				-- also prepare next destination address w.r.t destination stride
 				-- or stop blit
 				if blit_cur_width = 0 then
@@ -745,56 +778,57 @@ else
 					else
 						blit_cur_width <= blit_width;
 						blit_cur_height <= blit_cur_height - 1;
-						
+
 						if blit_cmd(1) = '0' then
 							blit_cur_dst <= blit_cur_dst + 1;
-						else							
+						else
 							blit_cur_dst <= blit_dst_ori + 1;
-							blit_dst_ori <= blit_dst_ori + 1; 
+							blit_dst_ori <= blit_dst_ori + 1;
 						end if;
-						
+
 					end if;
 				else
 					blit_cur_width <= blit_cur_width - 1;
-					
+
 					if blit_cmd(1) = '0' then
 						blit_cur_dst <= blit_cur_dst + 1;
 					else
 						blit_cur_dst <= blit_cur_dst + 256;
-					end if;					
-				end if;					
+					end if;
+				end if;
 			end if;
-					
+
 			-- slow mode
 			if en_cpu = '1' and en_pixel = '0' and blit_cmd(2) = '1' then
 				blit_go <= not blit_go;
 			end if;
-												
-		end if; -- cpu halted	
+
+		end if; -- cpu halted
 	end if;
 end if;
 end process;

 -- microprocessor 6809 -IC28
-main_cpu : entity work.cpu09
-port map(	
-	clk      => en_cpu,   -- E clock input (falling edge)
-	rst      => reset,    -- reset input (active high)
-	vma      => open,     -- valid memory address (active high)
-   lic_out  => open,     -- last instruction cycle (active high)
-   ifetch   => open,     -- instruction fetch cycle (active high)
-   opfetch  => open,     -- opcode fetch (active high)
-   ba       => cpu_ba,   -- bus available (high on sync wait or DMA grant)
-   bs       => cpu_bs,   -- bus status (high on interrupt or reset vector fetch or DMA grant)
-	addr     => cpu_addr, -- address bus output
-	rw       => cpu_rw_n, -- read not write output
-	data_out => cpu_do,   -- data bus output
-	data_in  => cpu_di,   -- data bus input
-	irq      => cpu_irq,  -- interrupt request input (active high)
-	firq     => '0',      -- fast interrupt request input (active high)
-	nmi      => '0',      -- non maskable interrupt request input (active high)
-	halt     => cpu_halt, -- halt input (active high) grants DMA
-	hold     => '0'       -- hold input (active high) extend bus cycle
+main_cpu : mc6809is
+port map(
+	CLK      => clock_12,
+	fallE_en => en_cpu and not en_pixel,
+	fallQ_en => en_cpu and en_pixel,
+	D        => cpu_di,
+	Dout     => cpu_do,
+	ADDR     => cpu_addr,
+	RnW      => cpu_rw_n,
+	BS       => cpu_bs,
+	BA       => cpu_ba,
+	nIRQ     => not cpu_irq,
+	nFIRQ    => not cpu_firq,
+	nNMI     => '1',
+	AVMA     => open,
+	BUSY     => open,
+	LIC      => open,
+	nHALT    => not cpu_halt,
+	nRESET   => not reset,
+	nDMABREQ => '1'
 );

 -- cpu program roms - IC9-10-54
@@ -804,7 +838,7 @@ port map(
 -- addr => addr_bus(11 downto 0),
 -- data => rom_prog1_do
 --);
-
+--
 --prog2_rom : entity work.turkey_shoot_prog2
 --port map(
 -- clk  => clock_12,
@@ -812,7 +846,6 @@ port map(
 -- data => rom_prog2_do
 --);

-prg_rom_addr <= addr_bus(13 downto 0);

 -- rom17.ic26 + rom15.ic24 
 --bank_a_rom : entity work.turkey_shoot_bank_a
@@ -821,8 +854,8 @@ prg_rom_addr <= addr_bus(13 downto 0);
 -- addr => addr_bus(13 downto 0),
 -- data => rom_bank_a_do
 --);
-
-- rom16.ic25 + rom14.ic23 + rom13.ic21 + rom12.ic19 
+--
+---- rom16.ic25 + rom14.ic23 + rom13.ic21 + rom12.ic19 
 --bank_b_rom : entity work.turkey_shoot_bank_b
 --port map(
 -- clk  => clock_12,
@@ -846,6 +879,11 @@ prg_rom_addr <= addr_bus(13 downto 0);
 -- data => rom_bank_d_do
 --);

+gfx_rom_addr <= graph_addr(13 downto 0);
+graph1_do <= gfx_rom_do(7 downto 0);
+graph2_do <= gfx_rom_do(15 downto 8);
+graph3_do <= gfx_rom_do(23 downto 16);
+
 -- rom20.ic57
 --graph1_rom : entity work.turkey_shoot_graph1
 --port map(
@@ -854,15 +892,15 @@ prg_rom_addr <= addr_bus(13 downto 0);
 -- data => graph1_do
 --);

-- rom20.ic58
+---- rom20.ic58
 --graph2_rom : entity work.turkey_shoot_graph2
 --port map(
 -- clk  => clock_12,
 -- addr => graph_addr(12 downto 0),
 -- data => graph2_do
 --);
-
-- rom20.ic41
+--
+------ rom20.ic41
 --graph3_rom : entity work.turkey_shoot_graph3
 --port map(
 -- clk  => clock_12,
@@ -870,15 +908,13 @@ prg_rom_addr <= addr_bus(13 downto 0);
 -- data => graph3_do
 --);

-gfx_rom_addr <= graph_addr(12 downto 0);
-
 -- cpu/video wram low 0 - IC102-105
 cpu_video_ram_l0 : entity work.gen_ram
 generic map( dWidth => 4, aWidth => 14)
 port map(
 clk  => clock_12,
 we   => vram_l0_we,
- addr => vram_addr(13 downto 0),
+ addr => vram_addr,
 d    => data_bus(3 downto 0),
 q    => vram_l0_do
 );
@@ -889,7 +925,7 @@ generic map( dWidth => 4, aWidth => 14)
 port map(
 clk  => clock_12,
 we   => vram_h0_we,
- addr => vram_addr(13 downto 0),
+ addr => vram_addr,
 d    => data_bus(7 downto 4),
 q    => vram_h0_do
 );
@@ -900,7 +936,7 @@ generic map( dWidth => 4, aWidth => 14)
 port map(
 clk  => clock_12,
 we   => vram_l1_we,
- addr => vram_addr(13 downto 0),
+ addr => vram_addr,
 d    => data_bus(3 downto 0),
 q    => vram_l1_do
 );
@@ -911,7 +947,7 @@ generic map( dWidth => 4, aWidth => 14)
 port map(
 clk  => clock_12,
 we   => vram_h1_we,
- addr => vram_addr(13 downto 0),
+ addr => vram_addr,
 d    => data_bus(7 downto 4),
 q    => vram_h1_do
 );
@@ -922,7 +958,7 @@ generic map( dWidth => 4, aWidth => 14)
 port map(
 clk  => clock_12,
 we   => vram_l2_we,
- addr => vram_addr(13 downto 0),
+ addr => vram_addr,
 d    => data_bus(3 downto 0),
 q    => vram_l2_do
 );
@@ -933,12 +969,11 @@ generic map( dWidth => 4, aWidth => 14)
 port map(
 clk  => clock_12,
 we   => vram_h2_we,
- addr => vram_addr(13 downto 0),
+ addr => vram_addr,
 d    => data_bus(7 downto 4),
 q    => vram_h2_do
 );

-
 -- palette rams - IC78-77
 palette_ram_lo : entity work.gen_ram
 generic map( dWidth => 8, aWidth => 10)
@@ -961,7 +996,6 @@ port map(
 q    => palette_hi_do
 );

-
 -- map ram - IC40
 map_ram : entity work.gen_ram
 generic map( dWidth => 8, aWidth => 11)
@@ -973,51 +1007,45 @@ port map(
 q    => map_do
 );

--sram0 : entity work.gen_ram
--generic map( dWidth => 8, aWidth => 11)
--port map(
-- clk  => clock_12,
-- we   => sram0_we,
-- addr => addr_bus(10 downto 0),
-- d    => data_bus,
-- q    => sram0_do
--);
-
-- cmos ram - IC59
-cmos_ram : entity work.t_shoot_cmos_ram
-generic map( dWidth => 4, aWidth => 10)
+-- sram 0 & 1
+sram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 12)
 port map(
 clk  => clock_12,
- we   => cmos_we,
- addr => cpu_addr(9 downto 0),
- d    => data_bus(3 downto 0),
- q    => cmos_do
+ we   => sram_we,
+ addr => addr_bus(11 downto 0),
+ d    => data_bus,
+ q    => sram_do
+);
+
+-- cmos ram - IC59
+cmos_ram : entity work.dpram
+generic map( dWidth => 4, aWidth => 10)
+port map(
+ clk_a  => clock_12,
+ we_a   => cmos_we,
+ addr_a => addr_bus(9 downto 0),
+ d_a    => data_bus(3 downto 0),
+ q_a    => cmos_do,
+ clk_b  => dl_clock,
+ we_b   => cmos_wr,
+ addr_b => dl_addr(9 downto 0),
+ d_b    => dl_data(3 downto 0),
+ q_b    => up_data(3 downto 0)
 );

 -- addr bus to video addr decoder - IC60
-video_addr_decoder : entity work.turkey_shoot_decoder
+video_addr_decoder : entity work.williams2_decoder
 port map(
 clk  => clock_12,
 addr => decod_addr,
 data => decod_do
 );

--dec_rom_addr <= decod_addr;
--decod_do <= dec_rom_do;
-
-- gun gray code encoder
-gun_gray_encoder : entity work.gray_code
-port map(
- clk  => clock_12,
- addr => gun_bin_code,
- data => gun_gray_code
-);
-
-
 -- pia iO1 : ic6 (5C)
 pia_io1 : entity work.pia6821
 port map
-(	
+(
 	clk       	=> pias_clock,            -- rising edge
 	rst       	=> reset,                 -- active high
 	cs        	=> pia_io1_cs,
@@ -1046,7 +1074,7 @@ port map
 -- pia iO2 : ic5 (2C)
 pia_rom : entity work.pia6821
 port map
-(	
+(
 	clk       	=> pias_clock,
 	rst       	=> reset,
 	cs        	=> pia_io2_cs,
@@ -1059,9 +1087,9 @@ port map
 	pa_i      	=> pia_io2_pa_i,
 	pa_o        => open,
 	pa_oe       => open,
-	ca1       	=> '0',
+	ca1       	=> cnt_4ms, --'0',
 	ca2_i      	=> '0',
-	ca2_o       => open,
+	ca2_o       => sound_trig2,
 	ca2_oe      => open,
 	pb_i      	=> (others => '0'),
 	pb_o        => sound_select,
@@ -1097,7 +1125,7 @@ if rising_edge(clock_12) then
  elsif hcnt = hcnt_base+32-64    then hsync2 <= '0';
  elsif hcnt = hcnt_base+64-3-128 then hsync2 <= '1';
  end if;
-  
+
  if hcnt = 63 and pixel_cnt = 5 then
 	 if vcnt = 502 then
 	   vsync_cnt := X"0";
@@ -1130,7 +1158,7 @@ if rising_edge(clock_12) then
  video_blankn <= not (hblank or vblank);

  video_hs <= hsync0;
-  
+
  if    vsync_cnt = 0 then video_vs <= '0';
  elsif vsync_cnt = 8 then video_vs <= '1';
  end if;
@@ -1143,62 +1171,34 @@ tshoot_sound_board : entity work.tshoot_sound_board
 port map(
 clock_12   => clock_12,
 reset      => reset,
+
 sound_select  => sound_select,
 sound_trig    => sound_trig, 
 sound_ack     => sound_ack,
- audio_out     => audio_out,
+ audio_out     => audio,
+
 snd_rom_addr  => snd_rom_addr,
- snd_rom_do    => snd_rom_do,
- dbg_cpu_addr  => sound_cpu_addr
+ snd_rom_do    => snd_rom_do
 );

-process (reset, clock_12)
-begin
-if reset='1' then
-else 
-	if rising_edge(clock_12) then 
-	
-		gun_update_r <= cnt_4ms;
-	
-		if gun_update_r = '0' and cnt_4ms = '1' then 
-	
-			left_r <= btn_left;
-			right_r <= btn_right;
-			up_r <= btn_up;
-			down_r <= btn_down;
-		
+williams_cvsd_board : entity work.williams_cvsd_board
+port map(
+ clock_12   => clock_12,
+ reset      => reset,

-			if ((btn_left = '1' and left_r = '1') or (btn_right = '1' and right_r = '1')) and div_h < 3 then
-				div_h <= div_h + '1';
-			else
-				div_h <= (others => '0');
-			end if;
-				
-			if btn_left = '1' and div_h = 1 and gun_h > 0 then
-				gun_h <= gun_h - '1';
-			end if;
-			if btn_right = '1' and div_h = 1 and gun_h < 63 then
-				gun_h <= gun_h + '1';
-			end if;
+ sound_select  => sound_select,
+ sound_trig    => sound_trig2,

-			if ((btn_up = '1' and up_r = '1') or (btn_down = '1' and down_r = '1')) and div_v < 3 then
-				div_v <= div_v + '1';
-			else
-				div_v <= (others => '0');
-			end if;
-				
-			if btn_up = '1' and div_v = 1 and gun_v > 0 then
-				gun_v <= gun_v - '1';
-			end if;
-			if btn_down = '1' and div_v = 1 and gun_v < 63 then
-				gun_v <= gun_v + '1';
-			end if;
-			
-		end if;
+ pia_audio     => pia_audio,
+ speech_out    => speech_out,
+ ym2151_left   => fm_left,
+ ym2151_right  => fm_right,

-	end if;
-	
-end if;
-end process;
+ snd_rom_addr  => snd2_rom_addr,
+ snd_rom_do    => snd2_rom_do
+);
+
+audio_left  <= "00000000000000000" + unsigned(audio&"00000") + unsigned(pia_audio&"00000") + unsigned(speech_out(15 downto 1)) + fm_left;
+audio_right <= "00000000000000000" + unsigned(audio&"00000") + unsigned(pia_audio&"00000") + unsigned(speech_out(15 downto 1)) + fm_right;

 end struct;
--- a/Hardware/rtl/williams2_colormix.vhd
+++ b/Hardware/rtl/williams2_colormix.vhd
@@ -0,0 +1,91 @@
+ -------------------------------------
+-- Color palette Mame Informations --
+-------------------------------------
+--
+-- Normal values (turkey shoot, inferno, joust2)
+
+--          red    green  blue  
+-- gain(  { 0.25f, 0.25f, 0.25f }),
+-- offset({ 0.00f, 0.00f, 0.00f })
+
+-- Modified value (mystic marathon)
+
+-- gain =   {   0.8f, 0.73f,  0.81f };
+-- offset = { -0.27f, 0.00f, -0.22f };
+
+-- Computation (video/williams.cpp)
+-- color_1 = max(color_in + offset   , 0)
+-- color_2 = min(color_1  * gain/0.25, 1)
+-- with color_in max value = 1
+
+-- because of gain/0.25 is ~3 output value may be much higher than 1
+-- applying  min(x, 1) will strangely saturate/limit result
+
+-- Here by, color_in max value = 15 (before intensity)
+-- => red   offset = -0.27*15 = 4.050 let's assume value 5
+-- => green offset = -0.00*15 = 0.000 let's assume value 0
+-- => blue  offset = -0.22*15 = 3.300 let's assume value 3
+
+-- red   gain = 3.20 rescaled to 127/3.24 => 125.4 let's assume value 125
+-- green gain = 2.92 rescaled to 127/3.24 => 114.5 let's assume value 114
+-- blue  gain = 3.24 rescaled to 127/3.24 => 127.0 let's assume value 127
+
+-- After intensity and gain, limit should be 256*128/3.24 = 10922
+-- limiting to this value gives wrong results so I choose not to
+-- apply limitation (limit to 256*128 = 32768).
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity williams2_colormix is
+port(
+ mysticm   : in  std_logic;
+ r         : in  std_logic_vector(3 downto 0);
+ g         : in  std_logic_vector(3 downto 0);
+ b         : in  std_logic_vector(3 downto 0);
+ intensity : in  std_logic_vector(3 downto 0);
+ vga_r     : out std_logic_vector(7 downto 0);
+ vga_g     : out std_logic_vector(7 downto 0);
+ vga_b     : out std_logic_vector(7 downto 0)
+);
+end williams2_colormix;
+
+architecture struct of williams2_colormix is
+
+ signal ri        : std_logic_vector( 7 downto 0);
+ signal gi        : std_logic_vector( 7 downto 0);
+ signal bi        : std_logic_vector( 7 downto 0);
+ signal ro        : std_logic_vector( 7 downto 0);
+ signal go        : std_logic_vector( 7 downto 0);
+ signal bo        : std_logic_vector( 7 downto 0);
+ signal rg        : std_logic_vector(15 downto 0);
+ signal gg        : std_logic_vector(15 downto 0);
+ signal bg        : std_logic_vector(15 downto 0);
+
+begin
+
+-- apply intensity
+ri <= r*intensity;
+gi <= g*intensity;
+bi <= b*intensity;
+
+-- apply offset and max(x, 0)
+ro <= ri-x"50" when ri > x"50" else x"00";
+go <= gi-x"00" when gi > x"00" else x"00";
+bo <= bi-x"30" when bi > x"30" else x"00";
+
+-- apply gain and limit
+-- in fact limit cannot be reached, anyway I keep the limiting function
+-- here for whos who want to try it
+rg <= ro*x"7D" when ro*x"7D" < x"7FFF" else x"7FFF";
+gg <= go*x"72" when go*x"72" < x"7FFF" else x"7FFF";
+bg <= bo*x"7F" when bo*x"7F" < x"7FFF" else x"7FFF";
+
+-- allow selection to real_time compare results with/without modification
+vga_r <= rg(14 downto 7) when mysticm = '1' else ri;
+vga_g <= gg(14 downto 7) when mysticm = '1' else gi;
+vga_b <= bg(14 downto 7) when mysticm = '1' else bi;
+
+end struct;
--- a/Hardware/rtl/williams_cvsd_board.vhd
+++ b/Hardware/rtl/williams_cvsd_board.vhd
@@ -0,0 +1,495 @@
+---------------------------------------------------------------------------------
+-- Williams cvsd board by Dar (darfpga@aol.fr)
+--
+-- Background sound and speech (D-11298) model
+--
+-- http://darfpga.blogspot.fr
+-- https://sourceforge.net/projects/darfpga/files
+-- github.com/darfpga
+---------------------------------------------------------------------------------
+-- gen_ram.vhd
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- MC6809
+-- Copyright (c) 2016, Greg Miller
+---------------------------------------------------------------------------------
+-- HC55516/HC55564 Continuously Variable Slope Delta decoder
+-- (c)2015 vlait
+---------------------------------------------------------------------------------
+-- JT51 (YM2151). <http://www.gnu.org/licenses/>.
+-- Author: Jose Tejada Gomez. Twitter: @topapate
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Version 0.0 -- 25/03/2022 -- 
+--		    initial version
+---------------------------------------------------------------------------------
+--  Features :
+-- 
+--  Use with MAME roms from joust2.zip
+--
+--  Connexions :
+--
+--     main board                        cvsd board 
+--     pia_io2 pb_o   (IC5/2C - port B)  => sound_select
+--     pia_io2 ca2_o  (IC5/2C - ca2)     => sound_trig
+--
+---------------------------------------------------------------------------------
+--  Use make_joust2_proms.bat to build vhd file and bin from binaries
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity williams_cvsd_board is
+port(
+ clock_12     : in std_logic;
+ reset        : in std_logic;
+ 
+ sound_select : in std_logic_vector(7 downto 0);
+ sound_trig   : in std_logic;
+ 
+ pia_audio    : out std_logic_vector( 7 downto 0);
+ speech_out   : out std_logic_vector(15 downto 0);
+ ym2151_left  : out unsigned (15 downto 0);
+ ym2151_right : out unsigned (15 downto 0);
+
+ snd_rom_addr : buffer std_logic_vector(16 downto 0);
+ snd_rom_do   : in  std_logic_vector( 7 downto 0);
+
+ dbg_out : out std_logic_vector(31 downto 0)
+
+);
+end williams_cvsd_board;
+
+architecture struct of williams_cvsd_board is
+
+component jt51 is
+port (
+
+ rst   : in std_logic;    -- reset
+ clk   : in std_logic;    -- main clock
+ cen   : in std_logic;    -- clock enable (* direct_enable *)
+ cen_p1: in std_logic;    -- clock enable at half the speed (* direct_enable *)
+ cs_n  : in std_logic;    -- chip select
+ wr_n  : in std_logic;    -- write
+ a0    : in std_logic;   
+ din   : in  std_logic_vector(7 downto 0); -- data in
+ dout  : out std_logic_vector(7 downto 0); -- data out
+ -- peripheral control
+ ct1   : out std_logic;
+ ct2   : out std_logic;
+ irq_n : out std_logic;    -- I do not synchronize this signal
+ 
+ -- Low resolution output (same as real chip)
+ sample: out std_logic;     -- marks new output sample
+ left  : out signed (15 downto 0);
+ right : out signed (15 downto 0);
+ -- Full resolution output
+ xleft  : out signed (15 downto 0);
+ xright : out signed (15 downto 0);
+ -- unsigned outputs for sigma delta converters, full resolution
+ dacleft  : out unsigned (15 downto 0);
+ dacright : out unsigned (15 downto 0)
+); end component jt51;
+
+
+component mc6809is is
+port (
+ CLK      : in  std_logic;
+ fallE_en : in  std_logic;
+ fallQ_en : in  std_logic;
+
+ D      : in  std_logic_vector(7 downto 0);
+ DOut   : out std_logic_vector(7 downto 0);
+ ADDR   : out std_logic_vector(15 downto 0);
+ RnW    : out std_logic;
+ BS     : out std_logic;
+ BA     : out std_logic;
+
+ nIRQ   : in  std_logic := '1';
+ nFIRQ  : in  std_logic := '1';
+ nNMI   : in  std_logic := '1';
+	
+ AVMA   : out std_logic;
+ BUSY   : out std_logic;
+ LIC    : out std_logic;
+	
+ nHALT  : in  std_logic := '1';
+ nRESET : in  std_logic := '1';
+	
+ nDMABREQ: in std_logic := '1';
+ RegData : out std_logic_vector(111 downto 0)
+);
+end component mc6809is;
+
+ signal en_cnt  : std_logic := '0'; 
+ signal div_cnt : std_logic_vector(1 downto 0) := "00";
+
+ signal rom_bank_cs  : std_logic;
+ 
+ signal cpu_addr   : std_logic_vector(15 downto 0);
+ signal cpu_di     : std_logic_vector( 7 downto 0);
+ signal cpu_do     : std_logic_vector( 7 downto 0);
+ signal cpu_rw_n   : std_logic;
+ signal write_n    : std_logic;
+
+ signal reset_n    : std_logic;
+ signal cpu_firq_n : std_logic;
+ signal cpu_nmi_n  : std_logic;
+ signal cpu_e_en   : std_logic;
+ signal cpu_q_en   : std_logic;
+  
+ signal page_cs         : std_logic;
+ signal page            : std_logic_vector( 2 downto 0);
+ signal rom_cs          : std_logic;
+ signal rom_bank_a_do   : std_logic_vector( 7 downto 0);
+ signal rom_bank_b_do   : std_logic_vector( 7 downto 0);
+ signal rom_bank_c_do   : std_logic_vector( 7 downto 0);
+
+ signal sram_cs        : std_logic;
+ signal sram_we        : std_logic;
+ signal sram_do        : std_logic_vector( 7 downto 0);
+ 
+ signal cvsd1_cs   : std_logic;
+ signal cvsd2_cs   : std_logic;
+ signal cvsd_data  : std_logic;
+ signal cvsd_clk   : std_logic;
+ signal cvsd_cnt   : std_logic_vector(15 downto 0);
+
+ signal pia_clock  : std_logic;
+
+ signal pia_cs     : std_logic;
+ signal pia_we_n   : std_logic;
+ signal pia_do     : std_logic_vector( 7 downto 0);
+-- signal pia_pa_o   : std_logic_vector( 7 downto 0);
+ signal pia_irqa   : std_logic;
+ signal pia_irqb   : std_logic;
+ 
+ signal ym2151_irq_n  : std_logic := '0';
+ signal ym2151_cs_n   : std_logic;
+ signal ym2151_do     : std_logic_vector( 7 downto 0);
+ signal ym2151_we_n   : std_logic;
+
+ signal lim       : unsigned(9 downto 0);
+ signal cnt_max   : unsigned(9 downto 0);
+ signal next_cnt  : unsigned(9 downto 0);
+ signal next_cnt2 : unsigned(9 downto 0);
+ signal cen_cnt   : unsigned(9 downto 0) := "0000000000";
+ signal alt       : std_logic := '0';
+ signal cen_1p78  : std_logic := '0';
+ signal cen_3p57  : std_logic := '0';
+
+ signal snd_rom_addr_r : std_logic_vector(16 downto 0);
+
+begin
+
+-- for debug
+process (clock_12) 
+begin
+	if rising_edge(clock_12) then 
+		dbg_out(15 downto 0) <= cpu_addr;
+		dbg_out(23 downto 16) <= cpu_di;
+	end if;
+end process;
+
+-- 
+reset_n    <= not reset;
+		
+-- make cpu clocks 2MHz (12MHz/6)
+-- in original hardware 2MHz from 8MHz/4
+--             _   _   _   _   _
+-- en_cnt   |_| |_| |_| |_| |_| | ...  (6MHz)
+--
+-- div_cnt  | 0 | 1 | 2 | 0 | 1 | ...
+--               _           _
+-- cpu_e_en  ___| |_________| |__ ...
+--           _           _        
+-- cpu_q_en | |_________| |______ ...
+--          ______ ___________ __
+-- cpu_do   ______|___________|__ ...
+--          __________     ______
+-- write_n            |___|       ...
+
+process (reset, clock_12)
+begin
+	if rising_edge(clock_12) then
+	
+		en_cnt   <= not en_cnt;
+		write_n  <= '1';
+		cpu_e_en <= '0';
+		cpu_q_en <= '0';
+	
+		if en_cnt = '1' then 		
+			if div_cnt = "10" then
+				div_cnt <= "00";
+			else
+				div_cnt <= div_cnt + '1';
+			end if;
+
+			-- place E and Q falling edge for MC6809
+			if  div_cnt = "00" then cpu_e_en <= '1'; end if;
+			if  div_cnt = "10" then cpu_q_en <= '1'; end if;
+			
+		end if;						
+
+		-- center cpu write pulse 
+		if div_cnt = "10" then write_n <= cpu_rw_n; end if;
+
+		-- synchronize interruptions
+		if  div_cnt = "01" then
+			cpu_nmi_n  <= not pia_irqb;
+			cpu_firq_n <= not pia_irqa;
+		end if;
+		
+	end if;
+end process;
+
+pia_clock <= not clock_12;
+
+-- chip select/we
+sram_cs      <= '1' when cpu_addr(15 downto 13) = "000"   else '0'; -- 0000-1FFF
+ym2151_cs_n  <= '0' when cpu_addr(15 downto 13) = "001"   else '1'; -- 2000-3FFF
+pia_cs       <= '1' when cpu_addr(15 downto 13) = "010"   else '0'; -- 4000-5FFF
+cvsd1_cs     <= '1' when cpu_addr(15 downto 11) = "01100" else '0'; -- 6000-67FF
+cvsd2_cs     <= '1' when cpu_addr(15 downto 11) = "01101" else '0'; -- 6800-6FFF
+page_cs      <= '1' when cpu_addr(15 downto 11) = "01111" else '0'; -- 7800-7FFF
+rom_cs       <= '1' when cpu_addr(15)           = '1';              -- 8000-FFFF
+
+sram_we       <= '1' when write_n = '0' and sram_cs     = '1' else '0';
+pia_we_n      <= '0' when write_n = '0' and pia_cs      = '1' else '1';
+ym2151_we_n   <= '0' when write_n = '0' and ym2151_cs_n = '0' else '1';
+
+-- mux data to cpu di
+cpu_di <=
+	cpu_do        when cpu_rw_n = '0' else 
+	sram_do		  when sram_cs = '1' else
+	ym2151_do	  when ym2151_cs_n = '0' else
+	pia_do        when pia_cs = '1' else
+	snd_rom_do    when rom_cs = '1' else
+	--rom_bank_a_do when rom_cs = '1' and page(1 downto 0) = "00" else
+	--rom_bank_b_do when rom_cs = '1' and page(1 downto 0) = "01" else
+	--rom_bank_c_do when rom_cs = '1' and page(1 downto 0) = "10" else
+	X"00";
+	
+-- page register, cvsd clock and data
+process (reset, clock_12)
+begin
+	if reset='1' then
+		page <= "000";
+		cvsd_data <= '0';
+		cvsd_clk  <= '0';
+	else 
+		if rising_edge(clock_12) then 
+			if page_cs = '1' and write_n = '0' then page <= cpu_do(2 downto 0); end if;
+			if cvsd1_cs = '1' then cvsd_data <= cpu_do(0); end if;
+			if cvsd1_cs = '1' then cvsd_clk <= '0';        end if;
+			if cvsd2_cs = '1' then cvsd_clk <= '1';        end if;			
+		end if;
+	end if;
+end process;
+
+-- microprocessor 6809 -IC28
+--main_cpu : entity work.cpu09
+--port map(	
+--	clk      => en_cpu,   -- E clock input (falling edge)
+--	rst      => reset,    -- reset input (active high)
+--	vma      => open,     -- valid memory address (active high)
+-- lic_out  => open,     -- last instruction cycle (active high)
+-- ifetch   => open,     -- instruction fetch cycle (active high)
+-- opfetch  => open,     -- opcode fetch (active high)
+-- ba       => open,     -- bus available (high on sync wait or DMA grant)
+-- bs       => open,     -- bus status (high on interrupt or reset vector fetch or DMA grant)
+--	addr     => cpu_addr, -- address bus output
+--	rw       => cpu_rw_n, -- read not write output
+--	data_out => cpu_do,   -- data bus output
+--	data_in  => cpu_di,   -- data bus input
+--	irq      => '0',      -- interrupt request input (active high)
+--	firq     => cpu_firq, -- fast interrupt request input (active high)
+--	nmi      => cpu_nmi,  -- non maskable interrupt request input (active high)
+--	halt     => '0',      -- halt input (active high) grants DMA
+--	hold     => '0'       -- hold input (active high) extend bus cycle
+--);
+
+-- microprocessor 6809 - IC28
+main_cpu : mc6809is
+port map (
+ CLK      => clock_12, -- : in  std_logic;
+ fallE_en => cpu_e_en, -- : in  std_logic;
+ fallQ_en => cpu_q_en, -- : in  std_logic;
+
+ D        => cpu_di,   -- : in  std_logic_vector(7 downto 0);
+ DOut     => cpu_do,   -- : out std_logic_vector(7 downto 0);
+ ADDR     => cpu_addr, -- : out std_logic_vector(15 downto 0); 
+ RnW      => cpu_rw_n, -- : out std_logic;
+ BS       => open,     -- : out std_logic;
+ BA       => open,     -- : out std_logic;
+
+ nIRQ     => '1',        -- : in  std_logic := '1';
+ nFIRQ    => cpu_firq_n, -- : in  std_logic := '1';
+ nNMI     => cpu_nmi_n,  -- : in  std_logic := '1';
+	
+ AVMA     => open,   -- : out std_logic;
+ BUSY     => open,   -- : out std_logic;
+ LIC      => open,   -- : out std_logic;
+	
+ nHALT    => '1',    -- : in  std_logic := '1'
+ nRESET   => reset_n,-- : in  std_logic := '1';
+	
+ nDMABREQ => '1',    -- : in std_logic := '1';
+ RegData  => open    -- : out std_logic_vector(111 downto 0);
+);
+
+snd_rom_addr <= page(1 downto 0)&cpu_addr(14 downto 0) when rom_cs = '1' else snd_rom_addr_r;
+
+process (reset, clock_12)
+begin
+	if rising_edge(clock_12) then
+		snd_rom_addr_r <= snd_rom_addr;
+	end if;
+end process;
+
+-- rom0 IC_U4
+--bank_a_rom : entity work.joust2_bg_sound_bank_a
+--port map(
+-- clk  => clock_12,
+-- addr => cpu_addr(14 downto 0),
+-- data => rom_bank_a_do
+--);
+--
+---- rom1 IC_U19
+--bank_b_rom : entity work.joust2_bg_sound_bank_b
+--port map(
+-- clk  => clock_12,
+-- addr => cpu_addr(14 downto 0),
+-- data => rom_bank_b_do
+--);
+--
+---- rom2 IC_U20
+--bank_c_rom : entity work.joust2_bg_sound_bank_c
+--port map(
+-- clk  => clock_12,
+-- addr => cpu_addr(14 downto 0),
+-- data => rom_bank_c_do
+--);
+
+-- sram IC U3
+sram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 11)
+port map(
+ clk  => clock_12,
+ we   => sram_we,
+ addr => cpu_addr(10 downto 0),
+ d    => cpu_do,
+ q    => sram_do
+);
+
+-- pia IC_U2
+pia : entity work.pia6821
+port map
+(	
+	clk       	=> pia_clock,           -- rising edge
+	rst       	=> reset,               -- active high
+	cs        	=> pia_cs,
+	rw        	=> pia_we_n,            -- write low
+	addr      	=> cpu_addr(1 downto 0),
+	data_in   	=> cpu_do,
+	data_out  	=> pia_do,
+	irqa      	=> pia_irqa,            -- active high
+	irqb      	=> pia_irqb,            -- active high
+	pa_i      	=> x"00",
+	pa_o        => pia_audio,
+	pa_oe       => open,
+	ca1       	=> ym2151_irq_n,
+	ca2_i      	=> '0',
+	ca2_o       => open,
+	ca2_oe      => open,
+	pb_i      	=> sound_select,
+	pb_o        => open,
+	pb_oe       => open,
+	cb1       	=> sound_trig,
+	cb2_i      	=> '0',
+	cb2_o       => open,
+	cb2_oe      => open
+);
+
+-- CVSD speech decoder	
+cvsd : entity work.HC55564	
+port map(	
+	clk => clock_12,
+	cen => cvsd_clk,
+	rst => '0', -- Reset is not currently implemented
+	bit_in => cvsd_data,
+	sample_out(15 downto 0) => speech_out
+);
+
+-- YM2151 : FM Clocks
+-- make 3.57 and 1.78MHz from 12MHz
+lim       <= to_unsigned(512,10);
+cnt_max   <= to_unsigned(512+152,10);
+
+next_cnt  <= cen_cnt + to_unsigned(152,10);
+next_cnt2 <= cen_cnt + to_unsigned(152,10) - to_unsigned(512,10);
+
+process (clock_12)
+begin
+	if rising_edge(clock_12) then
+		cen_3p57 <= '0';
+		cen_1p78 <= '0';
+
+		if cen_cnt >= cnt_max then 
+			cen_cnt <= (others => '0');
+			alt <= '0';
+		else		
+			if next_cnt >= lim then
+				cen_cnt <= next_cnt2;
+				cen_3p57 <= '1';
+				alt <= not alt;
+				cen_1p78 <= alt;
+			else
+				cen_cnt <= next_cnt;
+			end if;
+		end if;
+			
+	end if;
+end process;
+
+
+-- YM2151
+jt51_if : jt51
+port map (
+
+ rst    => reset,         -- reset
+ clk    => clock_12,      -- main clock
+ cen    => cen_3p57,      -- clock enable (* direct_enable *)
+ cen_p1 => cen_1p78,      -- clock enable at half the speed (* direct_enable *)
+ cs_n   => ym2151_cs_n,   -- chip select
+ wr_n   => ym2151_we_n,   -- write
+ a0     => cpu_addr(0),  
+ din    => cpu_do,        -- data in
+ dout   => ym2151_do,     -- data out
+ -- peripheral control
+ ct1   => open,
+ ct2   => open,
+ irq_n => ym2151_irq_n,   -- I do not synchronize this signal
+
+ -- Low resolution output (same as real chip)
+ sample => open,          -- marks new output sample
+ left   => open,
+ right  => open,
+ -- Full resolution output
+ xleft  => open,
+ xright => open,
+ -- unsigned outputs for sigma delta converters, full resolution
+ dacleft  => ym2151_left,
+ dacright => ym2151_right
+);
+
+end struct;