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Code Issues Releases Wiki Activity

New Core TripleDrawPoker, move Birdy back to Beta

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This commit is contained in:
Marcel
2019-03-11 18:22:22 +01:00
parent 7c6ae51d93
commit b767fd4979
72 changed files with 6192 additions and 4455 deletions
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20
Arcade_MiST/Pacman Hardware/Birdiy_MiST/README.txt → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt
View File

@@ -1,11 +1,11 @@
---------------------------------------------------------------------------------
--
-- Arcade: Birdiy port to MiST by Gehstock
-- 02 March 2019
-- Arcade: TripleDrawPoker port to MiST by Gehstock
-- 11 Mar 2019
--
---------------------------------------------------------------------------------
-- A simulation model of Pacman hardware
-- Copyright (c) MikeJ - January 2006
-- A simulation model of Galaxian hardware
-- Copyright(c) 2004 Katsumi Degawa
---------------------------------------------------------------------------------
--
-- Only controls and OSD are rotated on Video output.
@@ -13,15 +13,11 @@
--
-- Keyboard inputs :
--
-- ESC : Coin
-- F2 : Start 2 players
-- F1 : Start 1 player
-- UP,DOWN,LEFT,RIGHT arrows : Movements
-- F2 : Coin + Start 2 players
-- F1 : Coin + Start 1 player
-- SPACE : Select
-- ARROW KEYS : Movements
--
-- Joystick support.
--
---------------------------------------------------------------------------------
WIP

BIN
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/Release/TripleDrawPoker.rbf Normal file
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Binary file not shown.

11
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qpf → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf
View File

@@ -1,6 +1,6 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
@@ -17,15 +17,14 @@
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 22:14:32 March 02, 2019
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 21:51:58 January 08, 2018
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "22:14:32 March 02, 2019"
DATE = "21:51:58 January 08, 2018"
# Revisions
PROJECT_REVISION = "Birdiy"
PROJECT_REVISION = "Pacman"
PROJECT_REVISION = "TripleDrawPoker"

75
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qsf → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf
View File

@@ -1,6 +1,6 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
@@ -17,15 +17,15 @@
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 17:05:52 November 20, 2017
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 18:15:04 March 11, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Birdiy_assignment_defaults.qdf
# TripleDrawPoker_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -46,6 +46,38 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TripleDrawPoker_MiST.sv
set_global_assignment -name VHDL_FILE rtl/tripledrawpoker.vhd
set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/dac.vhd
# Pin & Location Assignments
# ==========================
@@ -83,15 +115,18 @@ set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY Birdiy
set_global_assignment -name TOP_LEVEL_ENTITY TripleDrawPoker_MiST
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
# Fitter Assignments
# ==================
@@ -129,8 +164,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------
# start ENTITY(Pacman)
# ----------------------------------
# start ENTITY(TripleDrawPoker_MiST)
# start DESIGN_PARTITION(Top)
# ---------------------------
@@ -144,28 +179,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Pacman)
# ------------------
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Birdiy.sv
set_global_assignment -name VHDL_FILE rtl/pacman.vhd
set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd
set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd
set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80sed.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
# end ENTITY(TripleDrawPoker_MiST)
# --------------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

105
Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.srf → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf
View File

@@ -1,51 +1,54 @@
{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}

0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/clean.bat → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat
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193
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/Pisces.sv Normal file
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//============================================================================
// Arcade: Catacomb
//
// Port to MiSTer
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module Pisces
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Pisces;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clk_24, clk_18, clk_12, clk_6;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_24),
.c1(clk_18),
.c2(clk_12),
.c3(clk_6)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
wire [7:0] audio_a, audio_b;
wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r,g,b;
galaxian catacomb(
.W_CLK_18M(clk_18),
.W_CLK_12M(clk_12),
.W_CLK_6M(clk_6),
.I_RESET(status[0] | status[6] | buttons[1]),
.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
.P2_CSJUDLR({1'b0, btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
.W_R(r),
.W_G(g),
.W_B(b),
.W_H_SYNC(hs),
.W_V_SYNC(vs),
.HBLANK(hb),
.VBLANK(vb),
.W_SDAT_A(audio_a),
.W_SDAT_B(audio_b)
);
video_mixer video_mixer(
.clk_sys(clk_24),
.ce_pix(clk_6),
.ce_pix_actual(clk_6),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : "000"),
.G(blankn ? g : "000"),
.B(blankn ? b : "000"),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.rotate({1'b1,status[2]}),
.scandoublerD(scandoublerD),
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
.ypbpr(ypbpr),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(
.STRLEN(($size(CONF_STR)>>3)))
mist_io(
.clk_sys (clk_24 ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoublerD (scandoublerD ),
.ypbpr (ypbpr ),
.ps2_key (ps2_key ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.msbi_g(15))
dac(
.clk_i(clk_24),
.res_n_i(1),
.dac_i({audio,5'd0}),
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire pressed = ps2_key[9];
wire [7:0] code = ps2_key[7:0];
always @(posedge clk_24) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
case(code)
'h75: btn_up <= pressed; // up
'h72: btn_down <= pressed; // down
'h6B: btn_left <= pressed; // left
'h74: btn_right <= pressed; // right
'h76: btn_coin <= pressed; // ESC
'h05: btn_one_player <= pressed; // F1
'h06: btn_two_players <= pressed; // F2
'h14: btn_fire3 <= pressed; // ctrl
'h11: btn_fire2 <= pressed; // alt
'h29: btn_fire1 <= pressed; // Space
endcase
end
end
endmodule

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BIN
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.bin Normal file
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Binary file not shown.

769
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.hex Normal file
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BIN
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/swap.exe Normal file
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Binary file not shown.

192
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv Normal file
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@@ -0,0 +1,192 @@
//============================================================================
// Arcade: Catacomb
//
// Port to MiSTer
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module TripleDrawPoker_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"TriDraPo;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clk_24, clk_18, clk_12, clk_6;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_24),
.c1(clk_18),
.c2(clk_12),
.c3(clk_6)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
wire [7:0] audio_a, audio_b;
wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r,g,b;
tripledrawpoker tripledrawpoker(
.W_CLK_18M(clk_18),
.W_CLK_12M(clk_12),
.W_CLK_6M(clk_6),
.I_RESET(status[0] | status[6] | buttons[1]),
.P1_CSJUDLR({btn_coin,1'b0,m_left,m_right,m_fire,m_down,1'b0,m_up}),
.P2_CSJUDLR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,btn_two_players,btn_one_player}),
.W_R(r),
.W_G(g),
.W_B(b),
.W_H_SYNC(hs),
.W_V_SYNC(vs),
.HBLANK(hb),
.VBLANK(vb),
.W_SDAT_A(audio_a),
.W_SDAT_B(audio_b)
);
video_mixer video_mixer(
.clk_sys(clk_24),
.ce_pix(clk_6),
.ce_pix_actual(clk_6),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : "000"),
.G(blankn ? g : "000"),
.B(blankn ? b : "000"),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.rotate({1'b1,status[2]}),
.scandoublerD(scandoublerD),
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
.ypbpr(ypbpr),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(
.STRLEN(($size(CONF_STR)>>3)))
mist_io(
.clk_sys (clk_24 ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoublerD (scandoublerD ),
.ypbpr (ypbpr ),
.ps2_key (ps2_key ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.msbi_g(15))
dac(
.clk_i(clk_24),
.res_n_i(1),
.dac_i({audio,5'd0}),
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire pressed = ps2_key[9];
wire [7:0] code = ps2_key[7:0];
always @(posedge clk_24) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
case(code)
'h75: btn_up <= pressed; // up
'h72: btn_down <= pressed; // down
'h6B: btn_left <= pressed; // left
'h74: btn_right <= pressed; // right
'h76: btn_coin <= pressed; // ESC
'h05: btn_one_player <= pressed; // F1
'h06: btn_two_players <= pressed; // F2
'h14: btn_fire3 <= pressed; // ctrl
'h11: btn_fire2 <= pressed; // alt
'h29: btn_fire1 <= pressed; // Space
endcase
end
end
endmodule

0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.tcl → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl
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2
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.v Normal file
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@@ -0,0 +1,2 @@
`define BUILD_DATE "190311"
`define BUILD_TIME "181510"

263
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/T80/T80.vhd → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd
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@@ -2,6 +2,9 @@
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
@@ -84,52 +87,52 @@ use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
@@ -249,6 +252,7 @@ architecture rtl of T80 is
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
@@ -264,81 +268,83 @@ begin
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write);
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
@@ -700,6 +706,9 @@ begin
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
@@ -829,21 +838,21 @@ begin
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
@@ -903,6 +912,10 @@ begin
when others =>
BusB <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;

36
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/T80/T80_ALU.vhd → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd
View File

@@ -82,30 +82,30 @@ entity T80_ALU is
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);

234
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/T80/T80_MCode.vhd → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd
View File

@@ -2,6 +2,8 @@
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
@@ -90,71 +92,73 @@ entity T80_MCode is
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
@@ -188,7 +192,7 @@ architecture rtl of T80_MCode is
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle)
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
@@ -249,6 +253,7 @@ begin
Halt <= '0';
NoRead <= '0';
Write <= '0';
XYbit_undoc <= '0';
case ISet is
when "00" =>
@@ -1162,7 +1167,6 @@ begin
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
@@ -1294,6 +1298,7 @@ begin
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
@@ -1309,6 +1314,7 @@ begin
when 3 =>
Write <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
@@ -1364,10 +1370,29 @@ begin
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
@@ -1401,9 +1426,23 @@ begin
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
@@ -1425,10 +1464,29 @@ begin
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
@@ -1455,11 +1513,31 @@ begin
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
@@ -1801,6 +1879,7 @@ begin
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
@@ -1821,6 +1900,7 @@ begin
Set_BusB_To(3) <= '1';
end if;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
Write <= '1';
IORQ <= '1';
when others =>
@@ -1838,6 +1918,7 @@ begin
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
@@ -1880,6 +1961,7 @@ begin
else
IncDec_16 <= "1110"; -- mikej
end if;
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Write <= '1';
I_BTR <= '1';

220
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd Normal file
View File

@@ -0,0 +1,220 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/T80/T80_Reg.vhd → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd
View File

283
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd Normal file
View File

@@ -0,0 +1,283 @@
------------------------------------------------------------------------------
-- t80as.vhd : The non-tristate signal edition of t80a.vhd
--
-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
--
-- 1.separate 'D' to 'DO' and 'DI'.
-- 2.added 'DOE' to 'DO' enable signal.(data direction)
-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'.
--
-- There is a mark of "--AS" in all the change points.
--
------------------------------------------------------------------------------
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80as is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
--AS-- D : inout std_logic_vector(7 downto 0)
--AS>>
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
DOE : out std_logic
--<<AS
);
end T80as;
architecture RTL of T80as is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
--AS-- signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
--AS-- MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
--AS>>
MREQ_n <= MREQ_n_i;
IORQ_n <= IORQ_n_i;
RD_n <= RD_n_i;
WR_n <= WR_n_i;
RFSH_n <= RFSH_n_i;
A <= A_i;
DOE <= Write when BUSAK_n_i = '1' else '0';
--<<AS
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
-- DInst => D,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
--AS-- DI_Reg <= to_x01(D);
--AS>>
DI_Reg <= to_x01(DI);
--<<AS
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

96
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/T80/T80sed.vhd → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80sed.vhd
View File

@@ -74,65 +74,65 @@ use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin

71
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd Normal file
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@@ -0,0 +1,71 @@
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 11
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;

75
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd Normal file
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@@ -0,0 +1,75 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
numwords_b => 2**addr_width_g,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
widthad_b => addr_width_g,
width_a => data_width_g,
width_b => data_width_g,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock_a,
clock1 => clock_b,
clocken0 => enable_a,
clocken1 => enable_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => q_a,
q_b => q_b
);
END SYN;

442
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/galaxian.vhd Normal file
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@@ -0,0 +1,442 @@
------------------------------------------------------------------------------
-- FPGA GALAXIAN
--
-- Version downto 2.50
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important not
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- 2004- 4-30 galaxian modify by K.DEGAWA
-- 2004- 5- 6 first release.
-- 2004- 8-23 Improvement with T80-IP.
-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use work.pkg_galaxian.all;
entity galaxian is
port(
W_CLK_18M : in std_logic;
W_CLK_12M : in std_logic;
W_CLK_6M : in std_logic;
P1_CSJUDLR : in std_logic_vector(6 downto 0);
P2_CSJUDLR : in std_logic_vector(6 downto 0);
I_RESET : in std_logic;
W_R : out std_logic_vector(2 downto 0);
W_G : out std_logic_vector(2 downto 0);
W_B : out std_logic_vector(2 downto 0);
HBLANK : out std_logic;
VBLANK : out std_logic;
W_H_SYNC : out std_logic;
W_V_SYNC : out std_logic;
W_SDAT_A : out std_logic_vector( 7 downto 0);
W_SDAT_B : out std_logic_vector( 7 downto 0);
O_CMPBL : out std_logic
);
end;
architecture RTL of galaxian is
-- CPU ADDRESS BUS
signal W_A : std_logic_vector(15 downto 0) := (others => '0');
-- CPU IF
signal W_CPU_CLK : std_logic := '0';
signal W_CPU_MREQn : std_logic := '0';
signal W_CPU_NMIn : std_logic := '0';
signal W_CPU_RDn : std_logic := '0';
signal W_CPU_RFSHn : std_logic := '0';
signal W_CPU_WAITn : std_logic := '0';
signal W_CPU_WRn : std_logic := '0';
signal W_CPU_WR : std_logic := '0';
signal W_RESETn : std_logic := '0';
-------- H and V COUNTER -------------------------
signal W_C_BLn : std_logic := '0';
signal W_C_BLnX : std_logic := '0';
signal W_C_BLXn : std_logic := '0';
signal W_H_BL : std_logic := '0';
signal W_H_SYNC_int : std_logic := '0';
signal W_V_BLn : std_logic := '0';
signal W_V_BL2n : std_logic := '0';
signal W_V_SYNC_int : std_logic := '0';
signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0');
signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0');
-------- CPU RAM ----------------------------
signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0');
-------- ADDRESS DECDER ----------------------
signal W_BD_G : std_logic := '0';
signal W_CPU_RAM_CS : std_logic := '0';
signal W_CPU_RAM_RD : std_logic := '0';
-- signal W_CPU_RAM_WR : std_logic := '0';
signal W_CPU_ROM_CS : std_logic := '0';
signal W_DIP_OE : std_logic := '0';
signal W_H_FLIP : std_logic := '0';
signal W_DRIVER_WE : std_logic := '0';
signal W_OBJ_RAM_RD : std_logic := '0';
signal W_OBJ_RAM_RQ : std_logic := '0';
signal W_OBJ_RAM_WR : std_logic := '0';
signal W_PITCH : std_logic := '0';
signal W_SOUND_WE : std_logic := '0';
signal W_STARS_ON : std_logic := '0';
signal W_STARS_OFFn : std_logic := '0';
signal W_SW0_OE : std_logic := '0';
signal W_SW1_OE : std_logic := '0';
signal W_V_FLIP : std_logic := '0';
signal W_VID_RAM_RD : std_logic := '0';
signal W_VID_RAM_WR : std_logic := '0';
signal W_WDR_OE : std_logic := '0';
--------- INPORT -----------------------------
signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0');
--------- VIDEO -----------------------------
signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0');
----- DATA I/F -------------------------------------
signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0');
signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0');
signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0');
signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0');
signal W_CPU_RAM_CLK : std_logic := '0';
signal W_VOL1 : std_logic := '0';
signal W_VOL2 : std_logic := '0';
signal W_FIRE : std_logic := '0';
signal W_HIT : std_logic := '0';
signal W_FS : std_logic_vector( 2 downto 0) := (others => '0');
signal blx_comb : std_logic := '0';
signal W_1VF : std_logic := '0';
signal W_256HnX : std_logic := '0';
signal W_8HF : std_logic := '0';
signal W_DAC_A : std_logic := '0';
signal W_DAC_B : std_logic := '0';
signal W_MISSILEn : std_logic := '0';
signal W_SHELLn : std_logic := '0';
signal W_MS_D : std_logic := '0';
signal W_MS_R : std_logic := '0';
signal W_MS_G : std_logic := '0';
signal W_MS_B : std_logic := '0';
signal new_sw : std_logic_vector( 2 downto 0) := (others => '0');
signal in_game : std_logic_vector( 1 downto 0) := (others => '0');
signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0');
signal rst_count : std_logic_vector( 3 downto 0) := (others => '0');
signal W_COL : std_logic_vector( 2 downto 0) := (others => '0');
signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0');
signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0');
signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0');
signal W_VID : std_logic_vector( 1 downto 0) := (others => '0');
signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0');
signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0');
signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0');
signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0');
signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0');
signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0');
signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0');
signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0');
signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0');
signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0');
signal gfx_bank : std_logic;
begin
mc_vid : entity work.MC_VIDEO
port map(
I_CLK_18M => W_CLK_18M,
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_H_CNT => W_H_CNT,
I_V_CNT => W_V_CNT,
I_H_FLIP => W_H_FLIP,
I_V_FLIP => W_V_FLIP,
I_V_BLn => W_V_BLn,
I_C_BLn => W_C_BLn,
I_A => W_A(9 downto 0),
I_OBJ_SUB_A => "000",
I_BD => W_BDI,
I_OBJ_RAM_RQ => W_OBJ_RAM_RQ,
I_OBJ_RAM_RD => W_OBJ_RAM_RD,
I_OBJ_RAM_WR => W_OBJ_RAM_WR,
I_VID_RAM_RD => W_VID_RAM_RD,
I_VID_RAM_WR => W_VID_RAM_WR,
I_DRIVER_WR => W_DRIVER_WE,
I_BANK => gfx_bank,
O_C_BLnX => W_C_BLnX,
O_8HF => W_8HF,
O_256HnX => W_256HnX,
O_1VF => W_1VF,
O_MISSILEn => W_MISSILEn,
O_SHELLn => W_SHELLn,
O_BD => W_VID_DO,
O_VID => W_VID,
O_COL => W_COL
);
cpu : entity work.T80as
port map (
RESET_n => W_RESETn,
CLK_n => W_CPU_CLK,
WAIT_n => W_CPU_WAITn,
INT_n => '1',
NMI_n => W_CPU_NMIn,
BUSRQ_n => '1',
MREQ_n => W_CPU_MREQn,
RD_n => W_CPU_RDn,
WR_n => W_CPU_WRn,
RFSH_n => W_CPU_RFSHn,
A => W_A,
DI => W_BDO,
DO => W_BDI,
M1_n => open,
IORQ_n => open,
HALT_n => open,
BUSAK_n => open,
DOE => open
);
mc_cpu_ram : entity work.MC_CPU_RAM
port map (
I_CLK => W_CPU_RAM_CLK,
I_ADDR => W_A(9 downto 0),
I_D => W_BDI,
I_WE => W_CPU_WR,
I_OE => W_CPU_RAM_RD,
O_D => W_CPU_RAM_DO
);
mc_adec : entity work.MC_ADEC
port map(
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_CPU_CLK => W_CPU_CLK,
I_RSTn => W_RESETn,
I_CPU_A => W_A,
I_CPU_D => W_BDI(0),
I_MREQn => W_CPU_MREQn,
I_RFSHn => W_CPU_RFSHn,
I_RDn => W_CPU_RDn,
I_WRn => W_CPU_WRn,
I_H_BL => W_H_BL,
I_V_BLn => W_V_BLn,
O_WAITn => W_CPU_WAITn,
O_NMIn => W_CPU_NMIn,
O_CPU_ROM_CS => W_CPU_ROM_CS,
O_CPU_RAM_RD => W_CPU_RAM_RD,
-- O_CPU_RAM_WR => W_CPU_RAM_WR,
O_CPU_RAM_CS => W_CPU_RAM_CS,
O_OBJ_RAM_RD => W_OBJ_RAM_RD,
O_OBJ_RAM_WR => W_OBJ_RAM_WR,
O_OBJ_RAM_RQ => W_OBJ_RAM_RQ,
O_VID_RAM_RD => W_VID_RAM_RD,
O_VID_RAM_WR => W_VID_RAM_WR,
O_SW0_OE => W_SW0_OE,
O_SW1_OE => W_SW1_OE,
O_DIP_OE => W_DIP_OE,
O_WDR_OE => W_WDR_OE,
O_DRIVER_WE => W_DRIVER_WE,
O_SOUND_WE => W_SOUND_WE,
O_PITCH => W_PITCH,
O_H_FLIP => W_H_FLIP,
O_V_FLIP => W_V_FLIP,
O_BD_G => W_BD_G,
O_STARS_ON => W_STARS_ON
);
-- active high buttons
mc_inport : entity work.MC_INPORT
port map (
I_COIN1 => P1_CSJUDLR(6),
I_COIN2 => P2_CSJUDLR(6),
I_1P_START => P1_CSJUDLR(5),
I_2P_START => P2_CSJUDLR(5),
I_1P_SH => P1_CSJUDLR(4),
I_2P_SH => P2_CSJUDLR(4),
I_1P_LE => P1_CSJUDLR(1),
I_2P_LE => P2_CSJUDLR(1),
I_1P_RI => P1_CSJUDLR(0),
I_2P_RI => P2_CSJUDLR(0),
I_SW0_OE => W_SW0_OE,
I_SW1_OE => W_SW1_OE,
I_DIP_OE => W_DIP_OE,
O_D => W_SW_DO
);
mc_hv : entity work.MC_HV_COUNT
port map(
I_CLK => W_CLK_6M,
I_RSTn => W_RESETn,
O_H_CNT => W_H_CNT,
O_H_SYNC => W_H_SYNC_int,
O_H_BL => W_H_BL,
O_V_CNT => W_V_CNT,
O_V_SYNC => W_V_SYNC_int,
O_V_BL2n => W_V_BL2n,
O_V_BLn => W_V_BLn,
O_C_BLn => W_C_BLn
);
mc_col_pal : entity work.MC_COL_PAL
port map(
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_VID => W_VID,
I_COL => W_COL,
I_C_BLnX => W_C_BLnX,
O_C_BLXn => W_C_BLXn,
O_STARS_OFFn => W_STARS_OFFn,
O_R => W_VIDEO_R,
O_G => W_VIDEO_G,
O_B => W_VIDEO_B
);
mc_stars : entity work.MC_STARS
port map (
I_CLK_18M => W_CLK_18M,
I_CLK_6M => W_CLK_6M,
I_H_FLIP => W_H_FLIP,
I_V_SYNC => W_V_SYNC_int,
I_8HF => W_8HF,
I_256HnX => W_256HnX,
I_1VF => W_1VF,
I_2V => W_V_CNT(1),
I_STARS_ON => W_STARS_ON,
I_STARS_OFFn => W_STARS_OFFn,
O_R => W_STARS_R,
O_G => W_STARS_G,
O_B => W_STARS_B,
O_NOISE => open
);
mc_sound_a : entity work.MC_SOUND_A
port map(
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_H_CNT1 => W_H_CNT(1),
I_BD => W_BDI,
I_PITCH => W_PITCH,
I_VOL1 => W_VOL1,
I_VOL2 => W_VOL2,
O_SDAT => W_SDAT_A,
O_DO => open
);
--------- ROM -------------------------------------------------------
mc_roms : entity work.sprom
generic map (
init_file => "./ROM/prog.hex",
widthad_a => 14,
width_a => 8)
port map (
address => W_A(13 downto 0),
clock => W_CLK_12M,
q => W_CPU_ROM_DO
);
-------- VIDEO -----------------------------
blx_comb <= not ( W_C_BLXn and W_V_BL2n );
W_V_SYNC <= not W_V_SYNC_int;
W_H_SYNC <= not W_H_SYNC_int;
O_CMPBL <= W_C_BLnX;
-- MISSILE => Yellow ;
-- SHELL => White ;
W_MS_D <= not (W_MISSILEn and W_SHELLn);
W_MS_R <= not blx_comb and W_MS_D;
W_MS_G <= not blx_comb and W_MS_D;
W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ;
W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
process(W_CLK_6M)
begin
if rising_edge(W_CLK_6M) then
HBLANK <= not W_C_BLXn;
VBLANK <= not W_V_BL2n;
end if;
end process;
----- CPU I/F -------------------------------------
W_CPU_CLK <= W_H_CNT(0);
W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
W_RESETn <= not I_RESET;
W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
W_CPU_WR <= not W_CPU_WRn;
new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
process(W_CPU_CLK, I_RESET)
begin
if (I_RESET = '1') then
rst_count <= (others => '0');
elsif rising_edge( W_CPU_CLK) then
if ( rst_count /= x"f") then
rst_count <= rst_count + 1;
end if;
end if;
end process;
----- Parts 9L ---------
process(W_CLK_12M, I_RESET)
begin
if (I_RESET = '1') then
W_FS <= (others=>'0');
W_HIT <= '0';
W_FIRE <= '0';
W_VOL1 <= '0';
W_VOL2 <= '0';
elsif rising_edge(W_CLK_12M) then
if (W_SOUND_WE = '1') then
case(W_A(2 downto 0)) is
when "000" => W_FS(0) <= W_BDI(0);
when "001" => W_FS(1) <= W_BDI(0);
when "010" => W_FS(2) <= W_BDI(0);
when "011" => W_HIT <= W_BDI(0);
-- when "100" => UNUSED <= W_BDI(0);
when "101" => W_FIRE <= W_BDI(0);
when "110" => W_VOL1 <= W_BDI(0);
when "111" => W_VOL2 <= W_BDI(0);
when others => null;
end case;
end if;
end if;
end process;
----- Parts 9M ---------
process(W_CLK_12M, I_RESET)
begin
if (I_RESET = '1') then
W_DAC <= (others=>'0');
elsif rising_edge(W_CLK_12M) then
if (W_DRIVER_WE = '1') then
case(W_A(2 downto 0)) is
-- next 4 outputs go off board via ULN2075 buffer
-- when "000" => 1P START <= W_BDI(0);
-- when "001" => 2P START <= W_BDI(0);
when "010" => gfx_bank <= W_BDI(0);
-- when "011" => COIN CTR <= W_BDI(0);
when "100" => W_DAC(0) <= W_BDI(0); -- 1M
when "101" => W_DAC(1) <= W_BDI(0); -- 470K
when "110" => W_DAC(2) <= W_BDI(0); -- 220K
when "111" => W_DAC(3) <= W_BDI(0); -- 100K
when others => null;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------
end RTL;

0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/hq2x.sv → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv
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251
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd Normal file
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---------------------------------------------------------------------
-- FPGA GALAXIAN ADDRESS DECDER
--
-- Version : 2.01
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- 2004- 4-30 galaxian modify by K.DEGAWA
-- 2004- 5- 6 first release.
-- 2004- 8-23 Improvement with T80-IP.
---------------------------------------------------------------------
--
--GALAXIAN Address Map
--
-- Address Item(R..read-mode W..wight-mode) Parts
--0000 - 1FFF CPU-ROM..R ( 7H or 7K )
--2000 - 3FFF CPU-ROM..R ( 7L )
--4000 - 47FF CPU-RAM..RW ( 7N & 7P )
--5000 - 57FF VID-RAM..RW
--5800 - 5FFF OBJ-RAM..RW
--6000 - SW0..R LAMP......W
--6800 - SW1..R SOUND.....W
--7000 - DIP..R
--7001 NMI_ON....W
--7004 STARS_ON..W
--7006 H_FLIP....W
--7007 V-FLIP....W
--7800 WDR..R PITCH.....W
--
--W MODE
--6000 1P START
--6001 2P START
--6002 COIN LOCKOUT
--6003 COIN COUNTER
--6004 - 6007 SOUND CONTROL(OSC)
--
--6800 SOUND CONTROL(FS1)
--6801 SOUND CONTROL(FS2)
--6802 SOUND CONTROL(FS3)
--6803 SOUND CONTROL(HIT)
--6805 SOUND CONTROL(SHOT)
--6806 SOUND CONTROL(VOL1)
--6807 SOUND CONTROL(VOL2)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC_ADEC is
port (
I_CLK_12M : in std_logic;
I_CLK_6M : in std_logic;
I_CPU_CLK : in std_logic;
I_RSTn : in std_logic;
I_CPU_A : in std_logic_vector(15 downto 0);
I_CPU_D : in std_logic;
I_MREQn : in std_logic;
I_RFSHn : in std_logic;
I_RDn : in std_logic;
I_WRn : in std_logic;
I_H_BL : in std_logic;
I_V_BLn : in std_logic;
O_WAITn : out std_logic;
O_NMIn : out std_logic;
O_CPU_ROM_CS : out std_logic;
O_CPU_RAM_RD : out std_logic;
O_CPU_RAM_WR : out std_logic;
O_CPU_RAM_CS : out std_logic;
O_OBJ_RAM_RD : out std_logic;
O_OBJ_RAM_WR : out std_logic;
O_OBJ_RAM_RQ : out std_logic;
O_VID_RAM_RD : out std_logic;
O_VID_RAM_WR : out std_logic;
O_SW0_OE : out std_logic;
O_SW1_OE : out std_logic;
O_DIP_OE : out std_logic;
O_WDR_OE : out std_logic;
O_DRIVER_WE : out std_logic;
O_SOUND_WE : out std_logic;
O_PITCH : out std_logic;
O_H_FLIP : out std_logic;
O_V_FLIP : out std_logic;
O_BD_G : out std_logic;
O_STARS_ON : out std_logic
);
end;
architecture RTL of MC_ADEC is
signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0');
signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0');
signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0');
signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0');
signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0');
signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0');
signal W_NMI_ONn : std_logic := '0';
-------- CPU WAITn ----------------------------------------------
-- signal W_6S1_Q : std_logic := '0';
signal W_6S1_Qn : std_logic := '0';
-- signal W_6S2_Qn : std_logic := '0';
signal W_V_BL : std_logic := '0';
begin
W_NMI_ONn <= W_9N_Q(1); -- galaxian
-- O_WAITn <= '1' ; -- No Wait
O_WAITn <= W_6S1_Qn;
process(I_CPU_CLK, I_V_BLn)
begin
if (I_V_BLn = '0') then
-- W_6S1_Q <= '0';
W_6S1_Qn <= '1';
elsif rising_edge(I_CPU_CLK) then
-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2));
W_6S1_Qn <= I_H_BL or W_8P_Q(2);
end if;
end process;
-- process(I_CPU_CLK)
-- begin
-- if falling_edge(I_CPU_CLK) then
-- W_6S2_Qn <= not W_6S1_Q;
-- end if;
-- end process;
-------- CPU NMIn -----------------------------------------------
W_V_BL <= not I_V_BLn;
process(W_V_BL, W_NMI_ONn)
begin
if (W_NMI_ONn = '0') then
O_NMIn <= '1';
elsif rising_edge(W_V_BL) then
O_NMIn <= '0';
end if;
end process;
-------------------------------------------------------------------
u_8e1 : entity work.LOGIC_74XX139
port map (
I_G => I_MREQn,
I_Sel(1) => I_CPU_A(15),
I_Sel(0) => I_CPU_A(14),
O_Q => W_8E1_Q
);
---------- CPU_ROM CS 0000 - 3FFF ---------------------------
u_8e2 : entity work.LOGIC_74XX139
port map (
I_G => I_RDn,
I_Sel(1) => W_8E1_Q(0),
I_Sel(0) => I_CPU_A(13),
O_Q => W_8E2_Q
);
O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF
-------------------------------------------------------------------
-- ADDRESS
-- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE
-- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1
-- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE
-- W_8E1_Q[3] = C000 - FFFF
u_8p : entity work.LOGIC_74XX138
port map (
I_G1 => I_RFSHn,
I_G2a => W_8E1_Q(1), -- <= *1
I_G2b => W_8E1_Q(1), -- <= *1
I_Sel => I_CPU_A(13 downto 11),
O_Q => W_8P_Q
);
u_8n : entity work.LOGIC_74XX138
port map (
I_G1 => '1',
I_G2a => I_RDn,
I_G2b => W_8E1_Q(1), -- <= *1
I_Sel => I_CPU_A(13 downto 11),
O_Q => W_8N_Q
);
u_8m : entity work.LOGIC_74XX138
port map (
-- I_G1 => W_6S2_Qn,
I_G1 => '1', -- No Wait
I_G2a => I_WRn,
I_G2b => W_8E1_Q(1), -- <= *1
I_Sel => I_CPU_A(13 downto 11),
O_Q => W_8M_Q
);
O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0));
O_OBJ_RAM_RQ <= not W_8P_Q(3);
O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0));
O_WDR_OE <= not W_8N_Q(7);
O_DIP_OE <= not W_8N_Q(6);
O_SW1_OE <= not W_8N_Q(5);
O_SW0_OE <= not W_8N_Q(4);
O_OBJ_RAM_RD <= not W_8N_Q(3);
O_VID_RAM_RD <= not W_8N_Q(2);
-- UNUSED <= not W_8N_Q(1);
O_CPU_RAM_RD <= not W_8N_Q(0);
O_PITCH <= not W_8M_Q(7);
-- STARS_ON_ENA <= not W_8M_Q(6);
O_SOUND_WE <= not W_8M_Q(5);
O_DRIVER_WE <= not W_8M_Q(4);
O_OBJ_RAM_WR <= not W_8M_Q(3);
O_VID_RAM_WR <= not W_8M_Q(2);
-- UNUSED <= not W_8M_Q(1);
O_CPU_RAM_WR <= not W_8M_Q(0);
----- Parts 9N ---------
process(I_CLK_12M, I_RSTn)
begin
if (I_RSTn = '0') then
W_9N_Q <= (others => '0');
elsif rising_edge(I_CLK_12M) then
if (W_8M_Q(6) = '0') then
case I_CPU_A(2 downto 0) is
when "000" => W_9N_Q(0) <= I_CPU_D;
when "001" => W_9N_Q(1) <= I_CPU_D;
when "010" => W_9N_Q(2) <= I_CPU_D;
when "011" => W_9N_Q(3) <= I_CPU_D;
when "100" => W_9N_Q(4) <= I_CPU_D;
when "101" => W_9N_Q(5) <= I_CPU_D;
when "110" => W_9N_Q(6) <= I_CPU_D;
when "111" => W_9N_Q(7) <= I_CPU_D;
when others => null;
end case;
end if;
end if;
end process;
O_STARS_ON <= W_9N_Q(4);
O_H_FLIP <= W_9N_Q(6);
O_V_FLIP <= W_9N_Q(7);
end RTL;

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------------------------------------------------------------------------------
-- FPGA MOONCRESTA & GALAXIAN
-- FPGA BLOCK RAM I/F (XILINX SPARTAN)
--
-- Version : 2.50
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- mc_col_rom(6L) added by k.Degawa
--
-- 2004- 5- 6 first release.
-- 2004- 8-23 Improvement with T80-IP. K.Degawa
-- 2004- 9-18 added Xilinx Device K.Degawa
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- mc_top.v use
entity MC_CPU_RAM is
port (
I_CLK : in std_logic;
I_ADDR : in std_logic_vector(9 downto 0);
I_D : in std_logic_vector(7 downto 0);
I_WE : in std_logic;
I_OE : in std_logic;
O_D : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of MC_CPU_RAM is
signal W_D : std_logic_vector(7 downto 0) := (others => '0');
begin
O_D <= W_D when I_OE ='1' else (others=>'0');
ram_inst : work.spram generic map(10,8)
port map
(
address => I_ADDR,
clock => I_CLK,
data => I_D,
wren => I_WE,
q => W_D
);
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- mc_video.v use
entity MC_OBJ_RAM is
port(
I_CLKA : in std_logic := '0';
I_WEA : in std_logic := '0';
I_CEA : in std_logic := '0';
I_ADDRA : in std_logic_vector(7 downto 0);
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
I_CLKB : in std_logic := '0';
I_WEB : in std_logic := '0';
I_CEB : in std_logic := '0';
I_ADDRB : in std_logic_vector(7 downto 0);
I_DB : in std_logic_vector(7 downto 0);
O_DB : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of MC_OBJ_RAM is
begin
ram_inst : work.dpram generic map(8,8)
port map
(
clock_a => I_CLKA,
address_a => I_ADDRA,
data_a => I_DA,
q_a => O_DA,
enable_a => I_CEA,
wren_a => I_WEA,
clock_b => I_CLKB,
address_b => I_ADDRB,
data_b => I_DB,
q_b => O_DB,
enable_b => I_CEB,
wren_b => I_WEB
);
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- mc_video.v use
entity MC_VID_RAM is
port (
I_CLKA : in std_logic := '0';
I_WEA : in std_logic := '0';
I_CEA : in std_logic := '0';
I_ADDRA : in std_logic_vector(9 downto 0);
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
I_CLKB : in std_logic := '0';
I_WEB : in std_logic := '0';
I_CEB : in std_logic := '0';
I_ADDRB : in std_logic_vector(9 downto 0);
I_DB : in std_logic_vector(7 downto 0);
O_DB : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of MC_VID_RAM is
begin
ram_inst : work.dpram generic map(10,8)
port map
(
clock_a => I_CLKA,
address_a => I_ADDRA,
data_a => I_DA,
q_a => O_DA,
enable_a => I_CEA,
wren_a => I_WEA,
clock_b => I_CLKB,
address_b => I_ADDRB,
data_b => I_DB,
q_b => O_DB,
enable_b => I_CEB,
wren_b => I_WEB
);
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- mc_video.v use
entity MC_LRAM is
port (
I_CLK : in std_logic;
I_ADDR : in std_logic_vector(7 downto 0);
I_D : in std_logic_vector(4 downto 0);
I_WE : in std_logic;
O_Dn : out std_logic_vector(4 downto 0)
);
end;
architecture RTL of MC_LRAM is
signal W_D : std_logic_vector(4 downto 0) := (others => '0');
begin
O_Dn <= not W_D;
ram_inst : work.dpram generic map(8,5)
port map
(
clock_a => I_CLK,
address_a => I_ADDR,
data_a => I_D,
wren_a => not I_WE,
clock_b => not I_CLK,
address_b => I_ADDR,
data_b => (others => '0'),
q_b => W_D,
enable_b => '1',
wren_b => '0'
);
end RTL;

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-----------------------------------------------------------------------
-- FPGA MOONCRESTA CLOCK GEN
--
-- Version : 1.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity CLOCKGEN is
port (
CLKIN_IN : in std_logic;
RST_IN : in std_logic;
--
O_CLK_24M : out std_logic;
O_CLK_18M : out std_logic;
O_CLK_12M : out std_logic;
O_CLK_06M : out std_logic
);
end;
architecture RTL of CLOCKGEN is
signal state : std_logic_vector(1 downto 0) := (others => '0');
signal ctr1 : std_logic_vector(1 downto 0) := (others => '0');
signal ctr2 : std_logic_vector(2 downto 0) := (others => '0');
signal CLKFB_IN : std_logic := '0';
signal CLK0_BUF : std_logic := '0';
signal CLKFX_BUF : std_logic := '0';
signal CLK_72M : std_logic := '0';
signal I_DCM_LOCKED : std_logic := '0';
begin
dcm_inst : DCM_SP
generic map (
CLKFX_MULTIPLY => 9,
CLKFX_DIVIDE => 4,
CLKIN_PERIOD => 31.25
)
port map (
CLKIN => CLKIN_IN,
CLKFB => CLKFB_IN,
RST => RST_IN,
CLK0 => CLK0_BUF,
CLKFX => CLKFX_BUF,
LOCKED => I_DCM_LOCKED
);
BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN);
BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M);
O_CLK_06M <= ctr2(2);
O_CLK_12M <= ctr2(1);
O_CLK_24M <= ctr2(0);
O_CLK_18M <= ctr1(1);
-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
process(CLK_72M)
begin
if rising_edge(CLK_72M) then
if (I_DCM_LOCKED = '0') then
state <= "00";
ctr1 <= (others=>'0');
ctr2 <= (others=>'0');
else
ctr1 <= ctr1 + 1;
case state is
when "00" => state <= "01"; ctr2 <= ctr2 + 1;
when "01" => state <= "10"; ctr2 <= ctr2 + 1;
when "10" => state <= "00";
when "11" => state <= "00";
when others => null;
end case;
end if;
end if;
end process;
end RTL;

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-------------------------------------------------------------------------------
-- FPGA MOONCRESTA COLOR-PALETTE
--
-- Version : 2.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- 2004- 9-18 added Xilinx Device. K.Degawa
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- use ieee.numeric_std.all;
--library UNISIM;
-- use UNISIM.Vcomponents.all;
entity MC_COL_PAL is
port (
I_CLK_12M : in std_logic;
I_CLK_6M : in std_logic;
I_VID : in std_logic_vector(1 downto 0);
I_COL : in std_logic_vector(2 downto 0);
I_C_BLnX : in std_logic;
O_C_BLXn : out std_logic;
O_STARS_OFFn : out std_logic;
O_R : out std_logic_vector(2 downto 0);
O_G : out std_logic_vector(2 downto 0);
O_B : out std_logic_vector(2 downto 0)
);
end;
architecture RTL of MC_COL_PAL is
--- Parts 6M --------------------------------------------------------
signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0');
signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0');
signal W_6M_CLR : std_logic := '0';
begin
W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0);
O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0);
O_STARS_OFFn <= W_6M_DO(1);
--always@(posedge I_CLK_6M or negedge W_6M_CLR)
process(I_CLK_6M, W_6M_CLR)
begin
if (W_6M_CLR = '0') then
W_6M_DO <= (others => '0');
elsif rising_edge(I_CLK_6M) then
W_6M_DO <= W_6M_DI;
end if;
end process;
--- COL ROM --------------------------------------------------------
--wire W_COL_ROM_OEn = W_6M_DO[1];
crom : entity work.sprom
generic map (
init_file => "./ROM/col.hex",
widthad_a => 5,
width_a => 8)
port map (
address => W_6M_DO(6 downto 2),
clock => I_CLK_12M,
q => W_COL_ROM_DO
);
--- VID OUT --------------------------------------------------------
O_R <= W_COL_ROM_DO(2 downto 0);
O_G <= W_COL_ROM_DO(5 downto 3);
O_B <= W_COL_ROM_DO(7 downto 6) & "0";
end;

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-----------------------------------------------------------------------
-- FPGA MOONCRESTA H & V COUNTER
--
-- Version : 2.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- 2004- 9-22
-----------------------------------------------------------------------
-- MoonCrest hv_count
-- H_CNT 0 - 255 , 384 - 511 Total 384 count
-- V_CNT 0 - 255 , 504 - 511 Total 264 count
-------------------------------------------------------------------------------------------
-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],
-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H
-------------------------------------------------------------------------------------------
-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]
-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V
-------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC_HV_COUNT is
port(
I_CLK : in std_logic;
I_RSTn : in std_logic;
O_H_CNT : out std_logic_vector(8 downto 0);
O_H_SYNC : out std_logic;
O_H_BL : out std_logic;
O_V_BL2n : out std_logic;
O_V_CNT : out std_logic_vector(7 downto 0);
O_V_SYNC : out std_logic;
O_V_BLn : out std_logic;
O_C_BLn : out std_logic
);
end;
architecture RTL of MC_HV_COUNT is
signal H_CNT : std_logic_vector(8 downto 0) := (others => '0');
signal V_CNT : std_logic_vector(8 downto 0) := (others => '0');
signal H_SYNC : std_logic := '0';
signal H_CLK : std_logic := '0';
signal H_BL : std_logic := '0';
signal V_BLn : std_logic := '0';
signal V_BL2n : std_logic := '0';
begin
--------- H_COUNT ----------------------------------------
process(I_CLK)
begin
if rising_edge(I_CLK) then
if (H_CNT = 255) then
H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
else
H_CNT <= H_CNT + 1 ;
end if;
end if;
end process;
O_H_CNT <= H_CNT;
--------- H_SYNC ----------------------------------------
H_CLK <= H_CNT(4);
process(H_CLK, H_CNT(8))
begin
if (H_CNT(8) = '0') then
H_SYNC <= '0';
elsif rising_edge(H_CLK) then
H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
end if;
end process;
O_H_SYNC <= H_SYNC;
--------- H_BL ------------------------------------------
process(I_CLK)
begin
if rising_edge(I_CLK) then
if H_CNT = 387 then
H_BL <= '1';
elsif H_CNT = 503 then
H_BL <= '0';
end if;
end if;
end process;
O_H_BL <= H_BL;
--------- V_COUNT ----------------------------------------
process(H_SYNC, I_RSTn)
begin
if (I_RSTn = '0') then
V_CNT <= (others => '0');
elsif rising_edge(H_SYNC) then
if (V_CNT = 255) then
V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
else
V_CNT <= V_CNT + 1 ;
end if;
end if;
end process;
O_V_CNT <= V_CNT(7 downto 0);
O_V_SYNC <= V_CNT(8);
--------- V_BLn ------------------------------------------
process(H_SYNC)
begin
if rising_edge(H_SYNC) then
if V_CNT(7 downto 0) = 239 then
V_BLn <= '0';
elsif V_CNT(7 downto 0) = 15 then
V_BLn <= '1';
end if;
end if;
end process;
process(H_SYNC)
begin
if rising_edge(H_SYNC) then
if V_CNT(7 downto 0) = 239 then
V_BL2n <= '0';
elsif V_CNT(7 downto 0) = 16 then
V_BL2n <= '1';
end if;
end if;
end process;
O_V_BLn <= V_BLn;
O_V_BL2n <= V_BL2n;
------- C_BLn ------------------------------------------
O_C_BLn <= V_BLn and (not H_CNT(8));
end;

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-----------------------------------------------------------------------
-- FPGA MOONCRESTA INPORT
--
-- Version : 1.01
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- 2004-4-30 galaxian modify by K.DEGAWA
-----------------------------------------------------------------------
-- DIP SW 0 1 2 3 4 5
-----------------------------------------------------------------
-- COIN CHUTE
-- 1 COIN/1 PLAY 1'b0 1'b0
-- 2 COIN/1 PLAY 1'b1 1'b0
-- 1 COIN/2 PLAY 1'b0 1'b1
-- FREE PLAY 1'b1 1'b1
-- BOUNS
-- 1'b0 1'b0
-- 1'b1 1'b0
-- 1'b0 1'b1
-- 1'b1 1'b1
-- LIVES
-- 2 1'b0
-- 3 1'b1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC_INPORT is
port (
I_COIN1 : in std_logic; -- active high
I_COIN2 : in std_logic; -- active high
I_1P_SH : in std_logic; -- active high
I_1P_LE : in std_logic; -- active high
I_1P_RI : in std_logic; -- active high
I_1P_UP : in std_logic; -- active high
I_1P_DW : in std_logic; -- active high
I_1P_START : in std_logic; -- active high
I_2P_START : in std_logic; -- active high
I_SW0_OE : in std_logic;
I_SW1_OE : in std_logic;
I_DIP_OE : in std_logic;
O_D : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of MC_INPORT is
constant W_TABLE : std_logic := '0'; -- UP = 0;
constant W_TEST : std_logic := '0';
constant W_SERVICE : std_logic := '0';
signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
begin
W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & "0" & I_1P_DW & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1;
W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010000" & I_2P_START & I_1P_START;
W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-- W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1;
-- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & "0" & "0" & "0" & "0" & I_2P_START & I_1P_START;
-- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
-- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-- W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1;
-- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
-- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
end RTL;

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-------------------------------------------------------------------------------
-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
--
-- Version : 2.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC_LD_PLS is
port (
I_CLK_6M : in std_logic;
I_H_CNT : in std_logic_vector(8 downto 0);
I_3D_DI : in std_logic;
O_LDn : out std_logic;
O_CNTRLDn : out std_logic;
O_CNTRCLRn : out std_logic;
O_COLLn : out std_logic;
O_VPLn : out std_logic;
O_OBJDATALn : out std_logic;
O_MLDn : out std_logic;
O_SLDn : out std_logic
);
end;
architecture RTL of MC_LD_PLS is
signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0');
signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0');
signal W_4C1_Q3 : std_logic := '0';
signal W_4C2_B : std_logic := '0';
signal W_4D1_G : std_logic := '0';
signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0');
signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0');
signal W_5C_Q : std_logic := '0';
signal W_HCNT : std_logic := '0';
begin
O_LDn <= W_4D1_G;
O_CNTRLDn <= W_4D1_Q(2);
O_CNTRCLRn <= W_4D1_Q(0);
O_COLLn <= W_4D2_Q(2);
O_VPLn <= W_4D2_Q(0);
O_OBJDATALn <= W_4C1_Q(2);
O_MLDn <= W_4C2_Q(0);
O_SLDn <= W_4C2_Q(1);
W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-- Parts 4D
u_4d1 : entity work.LOGIC_74XX139
port map(
I_G => W_4D1_G,
I_Sel(1) => I_H_CNT(8),
I_Sel(0) => I_H_CNT(3),
O_Q =>W_4D1_Q
);
u_4d2 : entity work.LOGIC_74XX139
port map(
I_G => W_5C_Q,
I_Sel(1) => I_H_CNT(2),
I_Sel(0) => I_H_CNT(1),
O_Q => W_4D2_Q
);
-- Parts 4C
u_4c1 : entity work.LOGIC_74XX139
port map(
I_G => W_4D2_Q(1),
I_Sel(1) => I_H_CNT(8),
I_Sel(0) => I_H_CNT(3),
O_Q => W_4C1_Q
);
u_4c2 : entity work.LOGIC_74XX139
port map(
I_G => W_4D1_Q(3),
I_Sel(1) => W_4C2_B,
I_Sel(0) => W_HCNT,
O_Q => W_4C2_Q
);
process(I_CLK_6M)
begin
if falling_edge(I_CLK_6M) then
W_5C_Q <= I_H_CNT(0);
end if;
end process;
-- 2004-9-22 added
process(I_CLK_6M)
begin
if rising_edge(I_CLK_6M) then
W_4C1_Q3 <= W_4C1_Q(3);
end if;
end process;
process(W_4C1_Q3)
begin
if rising_edge(W_4C1_Q3) then
W_4C2_B <= I_3D_DI;
end if;
end process;
end RTL;

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-------------------------------------------------------------------------------
-- FPGA MOONCRESTA LOGIC IP MODULE
--
-- Version : 1.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- 74xx138
-- 3-to-8 line decoder
-------------------------------------------------------------------------------
entity LOGIC_74XX138 is
port (
I_G1 : in std_logic;
I_G2a : in std_logic;
I_G2b : in std_logic;
I_Sel : in std_logic_vector(2 downto 0);
O_Q : out std_logic_vector(7 downto 0)
);
end logic_74xx138;
architecture RTL of LOGIC_74XX138 is
signal I_G : std_logic_vector(2 downto 0) := (others => '0');
begin
I_G <= I_G1 & I_G2a & I_G2b;
xx138 : process(I_G, I_Sel)
begin
if(I_G = "100" ) then
case I_Sel is
when "000" => O_Q <= "11111110";
when "001" => O_Q <= "11111101";
when "010" => O_Q <= "11111011";
when "011" => O_Q <= "11110111";
when "100" => O_Q <= "11101111";
when "101" => O_Q <= "11011111";
when "110" => O_Q <= "10111111";
when "111" => O_Q <= "01111111";
when others => null;
end case;
else
O_Q <= (others => '1');
end if;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- 74xx139
-- 2-to-4 line decoder
-------------------------------------------------------------------------------
entity LOGIC_74XX139 is
port (
I_G : in std_logic;
I_Sel : in std_logic_vector(1 downto 0);
O_Q : out std_logic_vector(3 downto 0)
);
end;
architecture RTL of LOGIC_74XX139 is
begin
xx139 : process (I_G, I_Sel)
begin
if I_G = '0' then
case I_Sel is
when "00" => O_Q <= "1110";
when "01" => O_Q <= "1101";
when "10" => O_Q <= "1011";
when "11" => O_Q <= "0111";
when others => null;
end case;
else
O_Q <= "1111";
end if;
end process;
end RTL;

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--------------------------------------------------------------------------------
---- FPGA MOONCRESTA VIDEO-MISSILE
----
---- Version : 2.00
----
---- Copyright(c) 2004 Katsumi Degawa , All rights reserved
----
---- Important !
----
---- This program is freeware for non-commercial use.
---- The author does not guarantee this program.
---- You can use this at your own risk.
----
---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC_MISSILE is
port(
I_CLK_6M : in std_logic;
I_CLK_18M : in std_logic;
I_C_BLn_X : in std_logic;
I_MLDn : in std_logic;
I_SLDn : in std_logic;
I_HPOS : in std_logic_vector (7 downto 0);
O_MISSILEn : out std_logic;
O_SHELLn : out std_logic
);
end;
architecture RTL of MC_MISSILE is
signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0');
signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0');
signal W_5P1_Q : std_logic := '0';
signal W_5P2_Q : std_logic := '0';
signal W_5P1_CLK : std_logic := '0';
signal W_5P2_CLK : std_logic := '0';
begin
O_MISSILEn <= W_5P1_CLK;
O_SHELLn <= W_5P2_CLK;
-- missile counter
process(I_CLK_6M)
begin
if falling_edge(I_CLK_6M) then
if (I_MLDn = '0') then
W_45R_Q <= I_HPOS;
else
if (I_C_BLn_X = '1') then
W_45R_Q <= W_45R_Q + 1;
if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
W_5P1_CLK <= '0';
else
W_5P1_CLK <= '1';
end if;
end if;
end if;
end if;
end process;
-- shell counter
process(I_CLK_6M)
begin
if falling_edge(I_CLK_6M) then
if(I_SLDn = '0') then
W_45S_Q <= I_HPOS;
else
if(I_C_BLn_X = '1') then
W_45S_Q <= W_45S_Q + 1;
if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
W_5P2_CLK <= '0';
else
W_5P2_CLK <= '1';
end if;
end if;
end if;
end if;
end process;
-- Standard D-type flip-flop with D input tied low, async active
-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
process(W_5P1_CLK, I_MLDn)
begin
if (I_MLDn = '0') then
W_5P1_Q <= '1';
elsif rising_edge(W_5P1_CLK) then
W_5P1_Q <= '0';
end if;
end process;
-- Standard D-type flip-flop with D input tied low, async active
-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
process(W_5P2_CLK, I_SLDn)
begin
if (I_SLDn = '0') then
W_5P2_Q <= '1';
elsif rising_edge(W_5P2_CLK) then
W_5P2_Q <= '0';
end if;
end process;
end RTL;

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------------------------------------------------------------------------------
-- FPGA MOONCRESTA SOUND I/F
--
-- Version : 1.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
entity MC_SOUND_A is
port (
I_CLK_12M : in std_logic;
I_CLK_6M : in std_logic;
I_H_CNT1 : in std_logic;
I_BD : in std_logic_vector(7 downto 0);
I_PITCH : in std_logic;
I_VOL1 : in std_logic;
I_VOL2 : in std_logic;
O_SDAT : out std_logic_vector(7 downto 0);
O_DO : out std_logic_vector(3 downto 0)
);
end;
architecture RTL of MC_SOUND_A is
signal W_PITCH : std_logic := '0';
signal W_89K_LDn : std_logic := '0';
signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0');
signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0');
signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0');
signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0');
signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0');
begin
O_DO <= W_6T_Q;
process (I_CLK_12M)
begin
if rising_edge(I_CLK_12M) then
W_PITCH <= I_PITCH;
if (W_89K_Q = x"ff") then
W_89K_LDn <= '0' ;
else
W_89K_LDn <= '1' ;
end if;
end if;
end process;
-- Parts 9J
process (W_PITCH)
begin
if falling_edge(W_PITCH) then
W_89K_LDATA <= I_BD;
end if;
end process;
process (I_H_CNT1)
begin
if rising_edge(I_H_CNT1) then
if (W_89K_LDn = '0') then
W_89K_Q <= W_89K_LDATA;
else
W_89K_Q <= W_89K_Q + 1;
end if;
end if;
end process;
process (W_89K_LDn)
begin
if falling_edge(W_89K_LDn) then
W_6T_Q <= W_6T_Q + 1;
end if;
end process;
process (I_CLK_6M)
begin
if rising_edge(I_CLK_6M) then
O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
if W_6T_Q(0)='1' then
W_SDAT0 <= x"2a";
else
W_SDAT0 <= (others => '0');
end if;
if W_6T_Q(2)='1' then
if I_VOL1 = '1' then
W_SDAT2 <= x"69";
else
W_SDAT2 <= x"39";
end if;
else
W_SDAT2 <= (others => '0');
end if;
if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
W_SDAT3 <= x"48" ;
else
W_SDAT3 <= (others => '0');
end if;
end if;
end process;
end;

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--------------------------------------------------------------------------------
---- FPGA MOONCRESTA WAVE SOUND
----
---- Version : 1.00
----
---- Copyright(c) 2004 Katsumi Degawa , All rights reserved
----
---- Important !
----
---- This program is freeware for non-commercial use.
---- The author does no guarantee this program.
---- You can use this at your own risk.
----
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--pragma translate_off
-- use ieee.std_logic_textio.all;
-- use std.textio.all;
--pragma translate_on
entity MC_SOUND_B is
port(
I_CLK1 : in std_logic; -- 6MHz
I_RSTn : in std_logic;
I_SW : in std_logic_vector( 2 downto 0);
I_DAC : in std_logic_vector( 3 downto 0);
I_FS : in std_logic_vector( 2 downto 0);
O_SDAT : out std_logic_vector( 7 downto 0)
);
end;
architecture RTL of MC_SOUND_B is
constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
constant fire_cnt : std_logic_vector(15 downto 0) := x"2000";
constant hit_cnt : std_logic_vector(15 downto 0) := x"2000";
signal sample : std_logic_vector(10 downto 0) := (others => '0');
signal sample_pls : std_logic := '0';
signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0');
signal s0_trg : std_logic := '0';
signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0');
signal s1_trg : std_logic := '0';
signal fire_addr : std_logic_vector(15 downto 0) := (others => '0');
signal hit_addr : std_logic_vector(15 downto 0) := (others => '0');
signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0');
signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0');
signal SDAT : std_logic_vector(10 downto 0) := (others => '0');
begin
-- ideally we should divide by 5 because this is the sum of 5 channels
-- but in practice we divide by 4 and just clip sounds that are too loud.
O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
process(I_CLK1)
begin
if rising_edge(I_CLK1) then
SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
end if;
end process;
process(I_CLK1, I_RSTn)
begin
if (I_RSTn = '0') then
sample <= (others => '0');
sample_pls <= '0';
elsif rising_edge(I_CLK1) then
if (sample = sample_time - 1) then
sample <= (others => '0');
sample_pls <= '1';
else
sample <= sample + 1;
sample_pls <= '0';
end if;
end if;
end process;
------------- FIRE SOUND ------------------------------------------
mc_roms_fire : entity work.GAL_FIR
port map (
CLK => I_CLK1,
ADDR => fire_addr(12 downto 0),
DATA => WAV_D0
);
process(I_CLK1, I_RSTn)
begin
if (I_RSTn = '0') then
s0_trg_ff <= (others => '0');
s0_trg <= '0';
elsif rising_edge(I_CLK1) then
s0_trg_ff(0) <= I_SW(0);
s0_trg_ff(1) <= s0_trg_ff(0);
s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0);
end if;
end process;
process(I_CLK1, I_RSTn)
begin
if (I_RSTn = '0') then
fire_addr <= fire_cnt;
elsif rising_edge(I_CLK1) then
if (s0_trg = '1') then
fire_addr <= (others => '0');
else
if(sample_pls = '1') then
if(fire_addr <= fire_cnt) then
fire_addr <= fire_addr + 1;
else
fire_addr <= fire_addr ;
end if;
end if;
end if;
end if;
end process;
------------- HIT SOUND ------------------------------------------
mc_roms_hit : entity work.GAL_HIT
port map (
CLK => I_CLK1,
ADDR => hit_addr(12 downto 0),
DATA => WAV_D1
);
process(I_CLK1, I_RSTn)
begin
if (I_RSTn = '0') then
s1_trg_ff <= (others => '0');
s1_trg <= '0';
elsif rising_edge(I_CLK1) then
s1_trg_ff(0) <= I_SW(1);
s1_trg_ff(1) <= s1_trg_ff(0);
s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0);
end if;
end process;
process(I_CLK1, I_RSTn)
begin
if (I_RSTn = '0') then
hit_addr <= hit_cnt;
elsif rising_edge(I_CLK1) then
if (s1_trg = '1') then
hit_addr <= (others => '0');
else
if (sample_pls = '1') then
if (hit_addr <= hit_cnt) then
hit_addr <= hit_addr + 1 ;
else
hit_addr <= hit_addr ;
end if;
end if;
end if;
end if;
end process;
--------------- EFFECT SOUND ---------------------------------------
-- 9R modulator voltage generator based on DAC value
process(I_CLK1, I_RSTn)
begin
if (I_RSTn = '0') then
VCO_CTR <= (others=>'0');
elsif rising_edge(I_CLK1) then
VCO_CTR <= VCO_CTR + (not I_DAC);
end if;
end process;
-- modulator frequency lookup tables for the three VCOs
process(I_CLK1, I_RSTn)
begin
if (I_RSTn = '0') then
elsif rising_edge(I_CLK1) then
case VCO_CTR(23 downto 19) is
when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53";
when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40";
when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
when others => null;
end case;
end if;
end process;
-- 8R VCO 240Hz - 140Hz (8)
mc_vco1 : entity work.MC_SOUND_VCO
port map (
I_CLK => I_CLK1,
I_RSTn => I_RSTn,
I_FS => I_FS(0),
I_STEP => W_VCO1_STEP,
O_WAV => W_VCO1_OUT
);
-- 8S VCO 330Hz - 190Hz (11)
mc_vco2 : entity work.MC_SOUND_VCO
port map (
I_CLK => I_CLK1,
I_RSTn => I_RSTn,
I_FS => I_FS(1),
I_STEP => W_VCO2_STEP,
O_WAV => W_VCO2_OUT
);
-- 8T VCO 480Hz - 270Hz (16)
mc_vco3 : entity work.MC_SOUND_VCO
port map (
I_CLK => I_CLK1,
I_RSTn => I_RSTn,
I_FS => I_FS(2),
I_STEP => W_VCO3_STEP,
O_WAV => W_VCO3_OUT
);
end RTL;

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--------------------------------------------------------------------------------
---- FPGA VCO
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.sine_package.all;
-- O_CLK = (I_CLK / 2^20) * I_STEP
entity MC_SOUND_VCO is
port(
I_CLK : in std_logic;
I_RSTn : in std_logic;
I_FS : in std_logic;
I_STEP : in std_logic_vector( 7 downto 0);
O_WAV : out std_logic_vector( 7 downto 0)
);
end;
architecture RTL of MC_SOUND_VCO is
signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0');
signal sine : std_logic_vector(14 downto 0) := (others => '0');
begin
O_WAV <= sine(14 downto 7);
process(I_CLK, I_RSTn)
begin
if (I_RSTn = '0') then
VCO1_CTR <= (others=>'0');
elsif rising_edge(I_CLK) then
if I_FS = '1' then
VCO1_CTR <= VCO1_CTR + I_STEP;
case VCO1_CTR(19 downto 18) is
when "00" =>
sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15));
when "01" =>
sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
when "10" =>
sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15));
when "11" =>
sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
when others => null;
end case;
end if;
end if;
end process;
end RTL;

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------------------------------------------------------------------------------
-- FPGA MOONCRESTA STARS
--
-- Version : 2.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MC_STARS is
port (
I_CLK_18M : in std_logic;
I_CLK_6M : in std_logic;
I_H_FLIP : in std_logic;
I_V_SYNC : in std_logic;
I_8HF : in std_logic;
I_256HnX : in std_logic;
I_1VF : in std_logic;
I_2V : in std_logic;
I_STARS_ON : in std_logic;
I_STARS_OFFn : in std_logic;
O_R : out std_logic_vector(1 downto 0);
O_G : out std_logic_vector(1 downto 0);
O_B : out std_logic_vector(1 downto 0);
O_NOISE : out std_logic
);
end;
architecture RTL of MC_STARS is
signal CLK_1C : std_logic := '0';
signal W_2D_Qn : std_logic := '0';
signal W_3B : std_logic := '0';
signal noise : std_logic := '0';
signal W_2A : std_logic := '0';
signal W_4P : std_logic := '0';
signal CLK_1AB : std_logic := '0';
signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0');
signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0');
begin
O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
W_3B <= W_2D_Qn xor W_1AB_Q(4);
W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
O_NOISE <= noise ;
process(I_2V)
begin
if rising_edge(I_2V) then
noise <= W_2D_Qn;
end if;
end process;
process(CLK_1C, I_V_SYNC)
begin
if(I_V_SYNC = '1') then
W_1C_Q <= (others => '0');
elsif rising_edge(CLK_1C) then
W_1C_Q <= W_1C_Q(0) & '1';
end if;
end process;
process(CLK_1AB, I_STARS_ON)
begin
if(I_STARS_ON = '0') then
W_1AB_Q <= (others => '0');
W_2D_Qn <= '1';
elsif rising_edge(CLK_1AB) then
W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
W_2D_Qn <= not W_1AB_Q(15);
end if;
end process;
end RTL;

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--------------------------------------------------------------------------------
---- FPGA GALAXIAN VIDEO
----
---- Version : 2.50
----
---- Copyright(c) 2004 Katsumi Degawa , All rights reserved
----
---- Important !
----
---- This program is freeware for non-commercial use.
---- The author does not guarantee this program.
---- You can use this at your own risk.
----
---- 2004- 4-30 galaxian modify by K.DEGAWA
---- 2004- 5- 6 first release.
---- 2004- 8-23 Improvement with T80-IP.
---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),
-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H
-------------------------------------------------------------------------------------------
-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)
-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V
-------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC_VIDEO is
port(
I_CLK_18M : in std_logic;
I_CLK_12M : in std_logic;
I_CLK_6M : in std_logic;
I_H_CNT : in std_logic_vector(8 downto 0);
I_V_CNT : in std_logic_vector(7 downto 0);
I_H_FLIP : in std_logic;
I_V_FLIP : in std_logic;
I_V_BLn : in std_logic;
I_C_BLn : in std_logic;
I_A : in std_logic_vector(9 downto 0);
I_BD : in std_logic_vector(7 downto 0);
I_OBJ_SUB_A : in std_logic_vector(2 downto 0);
I_OBJ_RAM_RQ : in std_logic;
I_OBJ_RAM_RD : in std_logic;
I_OBJ_RAM_WR : in std_logic;
I_VID_RAM_RD : in std_logic;
I_VID_RAM_WR : in std_logic;
I_DRIVER_WR : in std_logic;
I_BANK : in std_logic;
O_C_BLnX : out std_logic;
O_8HF : out std_logic;
O_256HnX : out std_logic;
O_1VF : out std_logic;
O_MISSILEn : out std_logic;
O_SHELLn : out std_logic;
O_BD : out std_logic_vector(7 downto 0);
O_VID : out std_logic_vector(1 downto 0);
O_COL : out std_logic_vector(2 downto 0)
);
end;
architecture RTL of MC_VIDEO is
signal WB_LDn : std_logic := '0';
signal WB_CNTRLDn : std_logic := '0';
signal WB_CNTRCLRn : std_logic := '0';
signal WB_COLLn : std_logic := '0';
signal WB_VPLn : std_logic := '0';
signal WB_OBJDATALn : std_logic := '0';
signal WB_MLDn : std_logic := '0';
signal WB_SLDn : std_logic := '0';
signal W_3D : std_logic := '0';
signal W_LDn : std_logic := '0';
signal W_CNTRLDn : std_logic := '0';
signal W_CNTRCLRn : std_logic := '0';
signal W_COLLn : std_logic := '0';
signal W_VPLn : std_logic := '0';
signal W_OBJDATALn : std_logic := '0';
signal W_MLDn : std_logic := '0';
signal W_SLDn : std_logic := '0';
signal W_VID : std_logic_vector( 1 downto 0) := (others => '0');
signal W_COL : std_logic_vector( 2 downto 0) := (others => '0');
signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0');
signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0');
signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0');
signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0');
signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0');
signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0');
signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0');
signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0');
signal W_RV : std_logic_vector( 1 downto 0) := (others => '0');
signal W_RC : std_logic_vector( 2 downto 0) := (others => '0');
signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0');
signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0');
signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0');
signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0');
signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0');
signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0');
signal W_CD : std_logic_vector( 2 downto 0) := (others => '0');
signal W_1M : std_logic_vector( 3 downto 0) := (others => '0');
signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0');
signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0');
signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0');
signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0');
signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0');
signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0');
signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0');
signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0');
-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0');
signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0');
signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0');
signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0');
signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0');
signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0');
signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0');
signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0');
signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0');
signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0');
signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0');
signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0');
signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0');
signal W_256HnX : std_logic := '0';
signal W_2N : std_logic := '0';
signal W_45T_CLR : std_logic := '0';
signal W_C_BLnX : std_logic := '0';
signal W_H_FLIP1 : std_logic := '0';
signal W_H_FLIP2 : std_logic := '0';
signal W_H_FLIP1X : std_logic := '0';
signal W_H_FLIP2X : std_logic := '0';
signal W_LRAM_AND : std_logic := '0';
signal W_RAW0 : std_logic := '0';
signal W_RAW1 : std_logic := '0';
signal W_RAW_OR : std_logic := '0';
signal W_SRCLK : std_logic := '0';
signal W_SRLD : std_logic := '0';
signal W_VID_RAM_CS : std_logic := '0';
signal W_CLK_6Mn : std_logic := '0';
begin
ld_pls : entity work.MC_LD_PLS
port map(
I_CLK_6M => I_CLK_6M,
I_H_CNT => I_H_CNT,
I_3D_DI => W_3D,
O_LDn => WB_LDn,
O_CNTRLDn => WB_CNTRLDn,
O_CNTRCLRn => WB_CNTRCLRn,
O_COLLn => WB_COLLn,
O_VPLn => WB_VPLn,
O_OBJDATALn => WB_OBJDATALn,
O_MLDn => WB_MLDn,
O_SLDn => WB_SLDn
);
obj_ram : entity work.MC_OBJ_RAM
port map(
I_CLKA => I_CLK_12M,
I_ADDRA => I_A(7 downto 0),
I_WEA => I_OBJ_RAM_WR,
I_CEA => I_OBJ_RAM_RQ,
I_DA => I_BD,
O_DA => W_OBJ_RAM_DOA,
I_CLKB => I_CLK_12M,
I_ADDRB => W_OBJ_RAM_AB,
I_WEB => '0',
I_CEB => '1',
I_DB => x"00",
O_DB => W_OBJ_RAM_DOB
);
lram : entity work.MC_LRAM
port map(
I_CLK => I_CLK_18M,
I_ADDR => W_LRAM_A,
I_WE => W_CLK_6Mn,
I_D => W_LRAM_DI,
O_Dn => W_LRAM_DO
);
missile : entity work.MC_MISSILE
port map(
I_CLK_18M => I_CLK_18M,
I_CLK_6M => I_CLK_6M,
I_C_BLn_X => W_C_BLnX,
I_MLDn => W_MLDn,
I_SLDn => W_SLDn,
I_HPOS => W_H_POSI,
O_MISSILEn => O_MISSILEn,
O_SHELLn => O_SHELLn
);
vid_ram : entity work.MC_VID_RAM
port map (
I_CLKA => I_CLK_12M,
I_ADDRA => I_A(9 downto 0),
I_DA => W_VID_RAM_DI,
I_WEA => I_VID_RAM_WR,
I_CEA => W_VID_RAM_CS,
O_DA => W_VID_RAM_DOA,
I_CLKB => I_CLK_12M,
I_ADDRB => W_VID_RAM_A(9 downto 0),
I_DB => x"00",
I_WEB => '0',
I_CEB => '1',
O_DB => W_VID_RAM_DOB
);
k_rom : entity work.sprom
generic map (
init_file => "./ROM/h.hex",
widthad_a => 11,
width_a => 8)
port map (
address => W_O_OBJ_ROM_A,
clock => I_CLK_12M,
q => W_1K_D
);
h_rom : entity work.sprom
generic map (
init_file => "./ROM/k.hex",
widthad_a => 11,
width_a => 8)
port map (
address => W_O_OBJ_ROM_A,
clock => I_CLK_12M,
q => W_1H_D
);
-----------------------------------------------------------------------------------
process(I_CLK_12M)
begin
if falling_edge(I_CLK_12M) then
W_LDn <= WB_LDn;
W_CNTRLDn <= WB_CNTRLDn;
W_CNTRCLRn <= WB_CNTRCLRn;
W_COLLn <= WB_COLLn;
W_VPLn <= WB_VPLn;
W_OBJDATALn <= WB_OBJDATALn;
W_MLDn <= WB_MLDn;
W_SLDn <= WB_SLDn;
end if;
end process;
W_CLK_6Mn <= not I_CLK_6M;
W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT;
O_8HF <= W_HF_CNT(3);
O_1VF <= W_VF_CNT(0);
W_H_FLIP2 <= W_6J_Q(3);
-- Parts 4F,5F
W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
process(I_CLK_12M)
begin
if rising_edge(I_CLK_12M) then
W_H_POSI <= W_OBJ_RAM_DOB;
end if;
end process;
W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-- Parts 4L
process(W_OBJDATALn)
begin
if rising_edge(W_OBJDATALn) then
W_OBJ_D <= W_H_POSI;
end if;
end process;
-- Parts 4,5N
W_45N_Q <= W_VF_CNT + W_H_POSI;
W_3D <= '0' when W_45N_Q = x"FF" else '1';
process(W_VPLn, I_V_BLn)
begin
if (I_V_BLn = '0') then
W_2M_Q <= (others => '0');
elsif rising_edge(W_VPLn) then
W_2M_Q <= W_45N_Q;
end if;
end process;
W_2N <= I_H_CNT(8) and W_OBJ_D(7);
W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR;
W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
---- VIDEO DATA OUTPUT --------------
O_BD <= W_OBJ_RAM_D or W_VID_RAM_D;
W_SRLD <= not (W_LDn or W_VID_RAM_A(11));
W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-----------------------------------------------------------------------------------
W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD;
W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0
C_2HJ <= W_3L_Y(1 downto 0);
C_2KL <= W_3L_Y(1 downto 0);
W_RAW0 <= W_3L_Y(2);
W_RAW1 <= W_3L_Y(3);
W_SRCLK <= I_CLK_6M;
-------- PARTS 2KL ----------------------------------------------
process(W_SRCLK)
begin
if rising_edge(W_SRCLK) then
case(C_2KL) is
when "00" => reg_2KL <= reg_2KL;
when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
when "11" => reg_2KL <= W_1K_D;
when others => null;
end case;
end if;
end process;
-------- PARTS 2HJ ----------------------------------------------
process(W_SRCLK)
begin
if rising_edge(W_SRCLK) then
case(C_2HJ) is
when "00" => reg_2HJ <= reg_2HJ;
when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
when "11" => reg_2HJ <= W_1H_D;
when others => null;
end case;
end if;
end process;
------- SHT2 -----------------------------------------------------
-- Parts 6K
process(W_COLLn)
begin
if rising_edge(W_COLLn) then
W_6K_Q <= W_H_POSI(2 downto 0);
end if;
end process;
-- Parts 6P
process(I_CLK_6M)
begin
if rising_edge(I_CLK_6M) then
if (W_LDn = '0') then
W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
else
W_6P_Q <= W_6P_Q;
end if;
end if;
end process;
W_H_FLIP2X <= W_6P_Q(6);
W_H_FLIP1X <= W_6P_Q(5);
W_C_BLnX <= W_6P_Q(4);
W_256HnX <= W_6P_Q(3);
W_CD <= W_6P_Q(2 downto 0);
O_256HnX <= W_256HnX;
O_C_BLnX <= W_C_BLnX;
W_45T_CLR <= W_CNTRCLRn or W_256HnX ;
process(I_CLK_6M, W_45T_CLR)
begin
if (W_45T_CLR = '0') then
W_45T_Q <= (others => '0');
elsif rising_edge(I_CLK_6M) then
if (W_CNTRLDn = '0') then
W_45T_Q <= W_H_POSI;
else
W_45T_Q <= W_45T_Q + 1;
end if;
end if;
end process;
W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
process(I_CLK_6M)
begin
if falling_edge(I_CLK_6M) then
W_RV <= W_LRAM_DO(1 downto 0);
W_RC <= W_LRAM_DO(4 downto 2);
end if;
end process;
W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
W_RAW_OR <= W_RAW0 or W_RAW1 ;
W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0));
W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1));
W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0));
W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1));
W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2));
O_VID <= W_VID;
O_COL <= W_COL;
W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1);
W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
end RTL;

0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/mist_io.v → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v
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0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/osd.v → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v
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451
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd Normal file
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@@ -0,0 +1,451 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 9,
clk0_duty_cycle => 50,
clk0_multiply_by => 8,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 9,
clk2_duty_cycle => 50,
clk2_multiply_by => 4,
clk2_phase_shift => "0",
clk3_divide_by => 9,
clk3_duty_cycle => 50,
clk3_multiply_by => 2,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

11
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/scandoubler.v → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v
View File

@@ -46,6 +46,17 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
output [DWIDTH:0] b_out
);
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
localparam DWIDTH = HALF_DEPTH ? 2 : 5;

152
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd Normal file
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@@ -0,0 +1,152 @@
library ieee;
use ieee.std_logic_1164.all;
package sine_package is
subtype table_value_type is integer range 0 to 16383;
subtype table_index_type is std_logic_vector( 6 downto 0 );
function get_table_value (table_index: table_index_type) return table_value_type;
end;
package body sine_package is
function get_table_value (table_index: table_index_type) return table_value_type is
variable table_value: table_value_type;
begin
case table_index is
when "0000000" => table_value := 101;
when "0000001" => table_value := 302;
when "0000010" => table_value := 503;
when "0000011" => table_value := 703;
when "0000100" => table_value := 904;
when "0000101" => table_value := 1105;
when "0000110" => table_value := 1305;
when "0000111" => table_value := 1506;
when "0001000" => table_value := 1706;
when "0001001" => table_value := 1906;
when "0001010" => table_value := 2105;
when "0001011" => table_value := 2304;
when "0001100" => table_value := 2503;
when "0001101" => table_value := 2702;
when "0001110" => table_value := 2900;
when "0001111" => table_value := 3098;
when "0010000" => table_value := 3295;
when "0010001" => table_value := 3491;
when "0010010" => table_value := 3688;
when "0010011" => table_value := 3883;
when "0010100" => table_value := 4078;
when "0010101" => table_value := 4273;
when "0010110" => table_value := 4466;
when "0010111" => table_value := 4659;
when "0011000" => table_value := 4852;
when "0011001" => table_value := 5044;
when "0011010" => table_value := 5234;
when "0011011" => table_value := 5425;
when "0011100" => table_value := 5614;
when "0011101" => table_value := 5802;
when "0011110" => table_value := 5990;
when "0011111" => table_value := 6177;
when "0100000" => table_value := 6362;
when "0100001" => table_value := 6547;
when "0100010" => table_value := 6731;
when "0100011" => table_value := 6914;
when "0100100" => table_value := 7095;
when "0100101" => table_value := 7276;
when "0100110" => table_value := 7456;
when "0100111" => table_value := 7634;
when "0101000" => table_value := 7811;
when "0101001" => table_value := 7988;
when "0101010" => table_value := 8162;
when "0101011" => table_value := 8336;
when "0101100" => table_value := 8509;
when "0101101" => table_value := 8680;
when "0101110" => table_value := 8850;
when "0101111" => table_value := 9018;
when "0110000" => table_value := 9185;
when "0110001" => table_value := 9351;
when "0110010" => table_value := 9515;
when "0110011" => table_value := 9678;
when "0110100" => table_value := 9840;
when "0110101" => table_value := 10000;
when "0110110" => table_value := 10158;
when "0110111" => table_value := 10315;
when "0111000" => table_value := 10471;
when "0111001" => table_value := 10625;
when "0111010" => table_value := 10777;
when "0111011" => table_value := 10927;
when "0111100" => table_value := 11076;
when "0111101" => table_value := 11224;
when "0111110" => table_value := 11369;
when "0111111" => table_value := 11513;
when "1000000" => table_value := 11655;
when "1000001" => table_value := 11796;
when "1000010" => table_value := 11934;
when "1000011" => table_value := 12071;
when "1000100" => table_value := 12206;
when "1000101" => table_value := 12339;
when "1000110" => table_value := 12471;
when "1000111" => table_value := 12600;
when "1001000" => table_value := 12728;
when "1001001" => table_value := 12853;
when "1001010" => table_value := 12977;
when "1001011" => table_value := 13099;
when "1001100" => table_value := 13219;
when "1001101" => table_value := 13336;
when "1001110" => table_value := 13452;
when "1001111" => table_value := 13566;
when "1010000" => table_value := 13678;
when "1010001" => table_value := 13787;
when "1010010" => table_value := 13895;
when "1010011" => table_value := 14000;
when "1010100" => table_value := 14104;
when "1010101" => table_value := 14205;
when "1010110" => table_value := 14304;
when "1010111" => table_value := 14401;
when "1011000" => table_value := 14496;
when "1011001" => table_value := 14588;
when "1011010" => table_value := 14679;
when "1011011" => table_value := 14767;
when "1011100" => table_value := 14853;
when "1011101" => table_value := 14936;
when "1011110" => table_value := 15018;
when "1011111" => table_value := 15097;
when "1100000" => table_value := 15174;
when "1100001" => table_value := 15249;
when "1100010" => table_value := 15321;
when "1100011" => table_value := 15391;
when "1100100" => table_value := 15459;
when "1100101" => table_value := 15524;
when "1100110" => table_value := 15587;
when "1100111" => table_value := 15648;
when "1101000" => table_value := 15706;
when "1101001" => table_value := 15762;
when "1101010" => table_value := 15816;
when "1101011" => table_value := 15867;
when "1101100" => table_value := 15916;
when "1101101" => table_value := 15963;
when "1101110" => table_value := 16007;
when "1101111" => table_value := 16048;
when "1110000" => table_value := 16088;
when "1110001" => table_value := 16124;
when "1110010" => table_value := 16159;
when "1110011" => table_value := 16191;
when "1110100" => table_value := 16220;
when "1110101" => table_value := 16247;
when "1110110" => table_value := 16272;
when "1110111" => table_value := 16294;
when "1111000" => table_value := 16314;
when "1111001" => table_value := 16331;
when "1111010" => table_value := 16346;
when "1111011" => table_value := 16358;
when "1111100" => table_value := 16368;
when "1111101" => table_value := 16375;
when "1111110" => table_value := 16380;
when "1111111" => table_value := 16383;
when others => null;
end case;
return table_value;
end;
end;

55
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd Normal file
View File

@@ -0,0 +1,55 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
width_a => data_width_g,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => q
);
END SYN;

0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/sprom.vhd → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd
View File

447
Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd Normal file
View File

@@ -0,0 +1,447 @@
------------------------------------------------------------------------------
-- FPGA TripleDrawPoker
--
-- Version downto 2.50
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important not
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
-- 2004- 4-30 galaxian modify by K.DEGAWA
-- 2004- 5- 6 first release.
-- 2004- 8-23 Improvement with T80-IP.
-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use work.pkg_galaxian.all;
entity tripledrawpoker is
port(
W_CLK_18M : in std_logic;
W_CLK_12M : in std_logic;
W_CLK_6M : in std_logic;
P1_CSJUDLR : in std_logic_vector(7 downto 0);
P2_CSJUDLR : in std_logic_vector(7 downto 0);
I_RESET : in std_logic;
W_R : out std_logic_vector(2 downto 0);
W_G : out std_logic_vector(2 downto 0);
W_B : out std_logic_vector(2 downto 0);
HBLANK : out std_logic;
VBLANK : out std_logic;
W_H_SYNC : out std_logic;
W_V_SYNC : out std_logic;
W_SDAT_A : out std_logic_vector( 7 downto 0);
W_SDAT_B : out std_logic_vector( 7 downto 0);
O_CMPBL : out std_logic
);
end;
architecture RTL of tripledrawpoker is
-- CPU ADDRESS BUS
signal W_A : std_logic_vector(15 downto 0) := (others => '0');
-- CPU IF
signal W_CPU_CLK : std_logic := '0';
signal W_CPU_MREQn : std_logic := '0';
signal W_CPU_NMIn : std_logic := '0';
signal W_CPU_RDn : std_logic := '0';
signal W_CPU_RFSHn : std_logic := '0';
signal W_CPU_WAITn : std_logic := '0';
signal W_CPU_WRn : std_logic := '0';
signal W_CPU_WR : std_logic := '0';
signal W_RESETn : std_logic := '0';
-------- H and V COUNTER -------------------------
signal W_C_BLn : std_logic := '0';
signal W_C_BLnX : std_logic := '0';
signal W_C_BLXn : std_logic := '0';
signal W_H_BL : std_logic := '0';
signal W_H_SYNC_int : std_logic := '0';
signal W_V_BLn : std_logic := '0';
signal W_V_BL2n : std_logic := '0';
signal W_V_SYNC_int : std_logic := '0';
signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0');
signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0');
-------- CPU RAM ----------------------------
signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0');
-------- ADDRESS DECDER ----------------------
signal W_BD_G : std_logic := '0';
signal W_CPU_RAM_CS : std_logic := '0';
signal W_CPU_RAM_RD : std_logic := '0';
-- signal W_CPU_RAM_WR : std_logic := '0';
signal W_CPU_ROM_CS : std_logic := '0';
signal W_DIP_OE : std_logic := '0';
signal W_H_FLIP : std_logic := '0';
signal W_DRIVER_WE : std_logic := '0';
signal W_OBJ_RAM_RD : std_logic := '0';
signal W_OBJ_RAM_RQ : std_logic := '0';
signal W_OBJ_RAM_WR : std_logic := '0';
signal W_PITCH : std_logic := '0';
signal W_SOUND_WE : std_logic := '0';
signal W_STARS_ON : std_logic := '0';
signal W_STARS_OFFn : std_logic := '0';
signal W_SW0_OE : std_logic := '0';
signal W_SW1_OE : std_logic := '0';
signal W_V_FLIP : std_logic := '0';
signal W_VID_RAM_RD : std_logic := '0';
signal W_VID_RAM_WR : std_logic := '0';
signal W_WDR_OE : std_logic := '0';
--------- INPORT -----------------------------
signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0');
--------- VIDEO -----------------------------
signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0');
----- DATA I/F -------------------------------------
signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0');
signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0');
signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0');
signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0');
signal W_CPU_RAM_CLK : std_logic := '0';
signal W_VOL1 : std_logic := '0';
signal W_VOL2 : std_logic := '0';
signal W_FIRE : std_logic := '0';
signal W_HIT : std_logic := '0';
signal W_FS : std_logic_vector( 2 downto 0) := (others => '0');
signal blx_comb : std_logic := '0';
signal W_1VF : std_logic := '0';
signal W_256HnX : std_logic := '0';
signal W_8HF : std_logic := '0';
signal W_DAC_A : std_logic := '0';
signal W_DAC_B : std_logic := '0';
signal W_MISSILEn : std_logic := '0';
signal W_SHELLn : std_logic := '0';
signal W_MS_D : std_logic := '0';
signal W_MS_R : std_logic := '0';
signal W_MS_G : std_logic := '0';
signal W_MS_B : std_logic := '0';
signal new_sw : std_logic_vector( 2 downto 0) := (others => '0');
signal in_game : std_logic_vector( 1 downto 0) := (others => '0');
signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0');
signal rst_count : std_logic_vector( 3 downto 0) := (others => '0');
signal W_COL : std_logic_vector( 2 downto 0) := (others => '0');
signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0');
signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0');
signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0');
signal W_VID : std_logic_vector( 1 downto 0) := (others => '0');
signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0');
signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0');
signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0');
signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0');
signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0');
signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0');
signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0');
signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0');
signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0');
signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0');
signal gfx_bank : std_logic;
begin
mc_vid : entity work.MC_VIDEO
port map(
I_CLK_18M => W_CLK_18M,
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_H_CNT => W_H_CNT,
I_V_CNT => W_V_CNT,
I_H_FLIP => W_H_FLIP,
I_V_FLIP => W_V_FLIP,
I_V_BLn => W_V_BLn,
I_C_BLn => W_C_BLn,
I_A => W_A(9 downto 0),
I_OBJ_SUB_A => "000",
I_BD => W_BDI,
I_OBJ_RAM_RQ => W_OBJ_RAM_RQ,
I_OBJ_RAM_RD => W_OBJ_RAM_RD,
I_OBJ_RAM_WR => W_OBJ_RAM_WR,
I_VID_RAM_RD => W_VID_RAM_RD,
I_VID_RAM_WR => W_VID_RAM_WR,
I_DRIVER_WR => W_DRIVER_WE,
I_BANK => gfx_bank,
O_C_BLnX => W_C_BLnX,
O_8HF => W_8HF,
O_256HnX => W_256HnX,
O_1VF => W_1VF,
O_MISSILEn => W_MISSILEn,
O_SHELLn => W_SHELLn,
O_BD => W_VID_DO,
O_VID => W_VID,
O_COL => W_COL
);
cpu : entity work.T80as
port map (
RESET_n => W_RESETn,
CLK_n => W_CPU_CLK,
WAIT_n => W_CPU_WAITn,
INT_n => '1',
NMI_n => W_CPU_NMIn,
BUSRQ_n => '1',
MREQ_n => W_CPU_MREQn,
RD_n => W_CPU_RDn,
WR_n => W_CPU_WRn,
RFSH_n => W_CPU_RFSHn,
A => W_A,
DI => W_BDO,
DO => W_BDI,
M1_n => open,
IORQ_n => open,
HALT_n => open,
BUSAK_n => open,
DOE => open
);
mc_cpu_ram : entity work.MC_CPU_RAM
port map (
I_CLK => W_CPU_RAM_CLK,
I_ADDR => W_A(9 downto 0),
I_D => W_BDI,
I_WE => W_CPU_WR,
I_OE => W_CPU_RAM_RD,
O_D => W_CPU_RAM_DO
);
mc_adec : entity work.MC_ADEC
port map(
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_CPU_CLK => W_CPU_CLK,
I_RSTn => W_RESETn,
I_CPU_A => W_A,
I_CPU_D => W_BDI(0),
I_MREQn => W_CPU_MREQn,
I_RFSHn => W_CPU_RFSHn,
I_RDn => W_CPU_RDn,
I_WRn => W_CPU_WRn,
I_H_BL => W_H_BL,
I_V_BLn => W_V_BLn,
O_WAITn => W_CPU_WAITn,
O_NMIn => W_CPU_NMIn,
O_CPU_ROM_CS => W_CPU_ROM_CS,
O_CPU_RAM_RD => W_CPU_RAM_RD,
-- O_CPU_RAM_WR => W_CPU_RAM_WR,
O_CPU_RAM_CS => W_CPU_RAM_CS,
O_OBJ_RAM_RD => W_OBJ_RAM_RD,
O_OBJ_RAM_WR => W_OBJ_RAM_WR,
O_OBJ_RAM_RQ => W_OBJ_RAM_RQ,
O_VID_RAM_RD => W_VID_RAM_RD,
O_VID_RAM_WR => W_VID_RAM_WR,
O_SW0_OE => W_SW0_OE,
O_SW1_OE => W_SW1_OE,
O_DIP_OE => W_DIP_OE,
O_WDR_OE => W_WDR_OE,
O_DRIVER_WE => W_DRIVER_WE,
O_SOUND_WE => W_SOUND_WE,
O_PITCH => W_PITCH,
O_H_FLIP => W_H_FLIP,
O_V_FLIP => W_V_FLIP,
O_BD_G => W_BD_G,
O_STARS_ON => W_STARS_ON
);
-- active high buttons
mc_inport : entity work.MC_INPORT
port map (
I_COIN1 => P1_CSJUDLR(7),
I_COIN2 => P1_CSJUDLR(6),
I_1P_START => P2_CSJUDLR(0),
I_2P_START => P2_CSJUDLR(1),
I_1P_SH => P1_CSJUDLR(3),
-- I_2P_SH => P2_CSJUDLR(4),
I_1P_UP => P1_CSJUDLR(0),
-- I_2P_UP => P2_CSJUDLR(3),
I_1P_DW => P1_CSJUDLR(2),
-- I_2P_DW => P2_CSJUDLR(2),
I_1P_LE => P1_CSJUDLR(5),
-- I_2P_LE => P2_CSJUDLR(1),
I_1P_RI => P1_CSJUDLR(4),
-- I_2P_RI => P2_CSJUDLR(0),
I_SW0_OE => W_SW0_OE,
I_SW1_OE => W_SW1_OE,
I_DIP_OE => W_DIP_OE,
O_D => W_SW_DO
);
mc_hv : entity work.MC_HV_COUNT
port map(
I_CLK => W_CLK_6M,
I_RSTn => W_RESETn,
O_H_CNT => W_H_CNT,
O_H_SYNC => W_H_SYNC_int,
O_H_BL => W_H_BL,
O_V_CNT => W_V_CNT,
O_V_SYNC => W_V_SYNC_int,
O_V_BL2n => W_V_BL2n,
O_V_BLn => W_V_BLn,
O_C_BLn => W_C_BLn
);
mc_col_pal : entity work.MC_COL_PAL
port map(
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_VID => W_VID,
I_COL => W_COL,
I_C_BLnX => W_C_BLnX,
O_C_BLXn => W_C_BLXn,
O_STARS_OFFn => W_STARS_OFFn,
O_R => W_VIDEO_R,
O_G => W_VIDEO_G,
O_B => W_VIDEO_B
);
mc_stars : entity work.MC_STARS
port map (
I_CLK_18M => W_CLK_18M,
I_CLK_6M => W_CLK_6M,
I_H_FLIP => W_H_FLIP,
I_V_SYNC => W_V_SYNC_int,
I_8HF => W_8HF,
I_256HnX => W_256HnX,
I_1VF => W_1VF,
I_2V => W_V_CNT(1),
I_STARS_ON => W_STARS_ON,
I_STARS_OFFn => W_STARS_OFFn,
O_R => W_STARS_R,
O_G => W_STARS_G,
O_B => W_STARS_B,
O_NOISE => open
);
mc_sound_a : entity work.MC_SOUND_A
port map(
I_CLK_12M => W_CLK_12M,
I_CLK_6M => W_CLK_6M,
I_H_CNT1 => W_H_CNT(1),
I_BD => W_BDI,
I_PITCH => W_PITCH,
I_VOL1 => W_VOL1,
I_VOL2 => W_VOL2,
O_SDAT => W_SDAT_A,
O_DO => open
);
--------- ROM -------------------------------------------------------
mc_roms : entity work.sprom
generic map (
init_file => "./ROM/prog.hex",
widthad_a => 14,
width_a => 8)
port map (
address => W_A(13 downto 0),
clock => W_CLK_12M,
q => W_CPU_ROM_DO
);
-------- VIDEO -----------------------------
blx_comb <= not ( W_C_BLXn and W_V_BL2n );
W_V_SYNC <= not W_V_SYNC_int;
W_H_SYNC <= not W_H_SYNC_int;
O_CMPBL <= W_C_BLnX;
-- MISSILE => Yellow ;
-- SHELL => White ;
W_MS_D <= not (W_MISSILEn and W_SHELLn);
W_MS_R <= not blx_comb and W_MS_D;
W_MS_G <= not blx_comb and W_MS_D;
W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ;
W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
process(W_CLK_6M)
begin
if rising_edge(W_CLK_6M) then
HBLANK <= not W_C_BLXn;
VBLANK <= not W_V_BL2n;
end if;
end process;
----- CPU I/F -------------------------------------
W_CPU_CLK <= W_H_CNT(0);
W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
W_RESETn <= not I_RESET;
W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
W_CPU_WR <= not W_CPU_WRn;
new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
process(W_CPU_CLK, I_RESET)
begin
if (I_RESET = '1') then
rst_count <= (others => '0');
elsif rising_edge( W_CPU_CLK) then
if ( rst_count /= x"f") then
rst_count <= rst_count + 1;
end if;
end if;
end process;
----- Parts 9L ---------
process(W_CLK_12M, I_RESET)
begin
if (I_RESET = '1') then
W_FS <= (others=>'0');
W_HIT <= '0';
W_FIRE <= '0';
W_VOL1 <= '0';
W_VOL2 <= '0';
elsif rising_edge(W_CLK_12M) then
if (W_SOUND_WE = '1') then
case(W_A(2 downto 0)) is
when "000" => W_FS(0) <= W_BDI(0);
when "001" => W_FS(1) <= W_BDI(0);
when "010" => W_FS(2) <= W_BDI(0);
when "011" => W_HIT <= W_BDI(0);
-- when "100" => UNUSED <= W_BDI(0);
when "101" => W_FIRE <= W_BDI(0);
when "110" => W_VOL1 <= W_BDI(0);
when "111" => W_VOL2 <= W_BDI(0);
when others => null;
end case;
end if;
end if;
end process;
----- Parts 9M ---------
process(W_CLK_12M, I_RESET)
begin
if (I_RESET = '1') then
W_DAC <= (others=>'0');
elsif rising_edge(W_CLK_12M) then
if (W_DRIVER_WE = '1') then
case(W_A(2 downto 0)) is
-- next 4 outputs go off board via ULN2075 buffer
-- when "000" => 1P START <= W_BDI(0);
-- when "001" => 2P START <= W_BDI(0);
when "010" => gfx_bank <= W_BDI(0);
-- when "011" => COIN CTR <= W_BDI(0);
when "100" => W_DAC(0) <= W_BDI(0); -- 1M
when "101" => W_DAC(1) <= W_BDI(0); -- 470K
when "110" => W_DAC(2) <= W_BDI(0); -- 220K
when "111" => W_DAC(3) <= W_BDI(0); -- 100K
when others => null;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------
end RTL;

0
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/video_mixer.sv → Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv
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//============================================================================
// Arcade: Birdiy
//
// Version for MiSTer
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module Birdiy(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Birdiy;;",
"O1,Rack Test,off,on;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v0.00.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clk_sys, clk_snd;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys),
.locked(pll_locked)
);
reg ce_6m;
always @(posedge clk_sys) begin
reg [1:0] div;
div <= div + 1'd1;
ce_6m <= !div;
end
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
wire [7:0] audio;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r,g;
wire [1:0] b;
pacmant pacmant(
.O_VIDEO_R(r),
.O_VIDEO_G(g),
.O_VIDEO_B(b),
.O_HSYNC(hs),
.O_VSYNC(vs),
.O_HBLANK(hb),
.O_VBLANK(vb),
.O_AUDIO(audio),
.I_JOYSTICK_A(~{m_fire,m_right,m_left,m_down,m_up}),
.I_JOYSTICK_B(~{m_fire,m_right,m_left,m_down,m_up}),
.I_SW({status[1], btn_two_players, btn_coin, status[1], btn_one_player}),
.RESET(status[0] | status[6] | buttons[1]),
.CLK(clk_sys),
.ENA_6(ce_6m)
);
video_mixer video_mixer(
.clk_sys(clk_sys),
.ce_pix(ce_6m),
.ce_pix_actual(ce_6m),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? {r} : "000"),
.G(blankn ? {g} : "000"),
.B(blankn ? {b,b[1]} : "000"),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.rotate({1'b1,status[2]}),
.scandoublerD(scandoublerD),
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
.ypbpr(ypbpr),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(
.STRLEN(($size(CONF_STR)>>3)))
mist_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoublerD (scandoublerD ),
.ypbpr (ypbpr ),
.ps2_key (ps2_key ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(15))
dac(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i({audio,audio}),
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire pressed = ps2_key[9];
wire [7:0] code = ps2_key[7:0];
always @(posedge clk_sys) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
case(code)
'h75: btn_up <= pressed; // up
'h72: btn_down <= pressed; // down
'h6B: btn_left <= pressed; // left
'h74: btn_right <= pressed; // right
'h76: btn_coin <= pressed; // ESC
'h05: btn_one_player <= pressed; // F1
'h06: btn_two_players <= pressed; // F2
'h14: btn_fire3 <= pressed; // ctrl
'h11: btn_fire2 <= pressed; // alt
'h29: btn_fire1 <= pressed; // Space
endcase
end
end
endmodule
//wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
//wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2];
//wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1];
//wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0];
//TODO
/*
VIDEO_START_MEMBER(pacman_state,birdiy)
{
VIDEO_START_CALL_MEMBER( pacman );
m_xoffsethack = 0;
m_inv_spr = 1; // sprites are mirrored in X-axis compared to normal behaviour
}
void pacman_state::pacman_map(address_map &map)
{
//A lot of games don't have an a15 at the cpu. Generally only games with a cpu daughter board can access the full 32k of romspace.
map(0x0000, 0x3fff).mirror(0x8000).rom();
map(0x4000, 0x43ff).mirror(0xa000).ram().w(FUNC(pacman_state::pacman_videoram_w)).share("videoram");
map(0x4400, 0x47ff).mirror(0xa000).ram().w(FUNC(pacman_state::pacman_colorram_w)).share("colorram");
map(0x4800, 0x4bff).mirror(0xa000).r(FUNC(pacman_state::pacman_read_nop)).nopw();
map(0x4c00, 0x4fef).mirror(0xa000).ram();
map(0x4ff0, 0x4fff).mirror(0xa000).ram().share("spriteram");
map(0x5000, 0x5007).mirror(0xaf38).w(m_mainlatch, FUNC(addressable_latch_device::write_d0));
map(0x5040, 0x505f).mirror(0xaf00).w(m_namco_sound, FUNC(namco_device::pacman_sound_w));
map(0x5060, 0x506f).mirror(0xaf00).writeonly().share("spriteram2");
map(0x5070, 0x507f).mirror(0xaf00).nopw();
map(0x5080, 0x5080).mirror(0xaf3f).nopw();
map(0x50c0, 0x50c0).mirror(0xaf3f).w(m_watchdog, FUNC(watchdog_timer_device::reset_w));
map(0x5000, 0x5000).mirror(0xaf3f).portr("IN0");
map(0x5040, 0x5040).mirror(0xaf3f).portr("IN1");
map(0x5080, 0x5080).mirror(0xaf3f).portr("DSW1");
map(0x50c0, 0x50c0).mirror(0xaf3f).portr("DSW2");
}
void pacman_state::birdiy_map(address_map &map)
{
map(0x0000, 0x3fff).mirror(0x8000).rom();
map(0x4000, 0x43ff).mirror(0xa000).ram().w(FUNC(pacman_state::pacman_videoram_w)).share("videoram");
map(0x4400, 0x47ff).mirror(0xa000).ram().w(FUNC(pacman_state::pacman_colorram_w)).share("colorram");
// AM_RANGE(0x4800, 0x4bff) AM_MIRROR(0xa000) AM_READ(pacman_read_nop) AM_WRITENOP
map(0x4c00, 0x4fef).mirror(0xa000).ram();
map(0x4ff0, 0x4fff).mirror(0xa000).ram().share("spriteram");
map(0x5000, 0x5007).mirror(0xaf38).w(m_mainlatch, FUNC(ls259_device::write_d0));
map(0x5080, 0x509f).mirror(0xaf00).w(m_namco_sound, FUNC(namco_device::pacman_sound_w));
map(0x50a0, 0x50af).mirror(0xaf00).writeonly().share("spriteram2");
// AM_RANGE(0x5070, 0x507f) AM_MIRROR(0xaf00) AM_WRITENOP
// AM_RANGE(0x5080, 0x5080) AM_MIRROR(0xaf3f) AM_WRITENOP
map(0x50c0, 0x50c0).mirror(0xaf3f).w(m_watchdog, FUNC(watchdog_timer_device::reset_w));
map(0x5000, 0x5000).mirror(0xaf3f).portr("IN0");
map(0x5040, 0x5040).mirror(0xaf3f).portr("IN1");
map(0x5080, 0x5080).mirror(0xaf3f).portr("DSW1");
map(0x50c0, 0x50c0).mirror(0xaf3f).portr("DSW2");
}*/

217
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/T80/T80_Pack.vhd
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@@ -1,217 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

2
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.v
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@@ -1,2 +0,0 @@
`define BUILD_DATE "190310"
`define BUILD_TIME "105929"

48
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/dac.vhd
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-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 10
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

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-------------------------------------------------------------------------------
-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dpram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
port (
clk_a_i : in std_logic;
en_a_i : in std_logic;
we_i : in std_logic;
addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
data_a_i : in std_logic_vector(data_width_g-1 downto 0);
data_a_o : out std_logic_vector(data_width_g-1 downto 0);
clk_b_i : in std_logic;
addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
data_b_o : out std_logic_vector(data_width_g-1 downto 0)
);
end dpram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dpram is
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
signal ram_q : ram_t;
begin
mem_a: process (clk_a_i)
begin
if rising_edge(clk_a_i) then
if we_i = '1' and en_a_i = '1' then
ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
data_a_o <= data_a_i;
else
data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
end if;
end if;
end process mem_a;
mem_b: process (clk_b_i)
begin
if rising_edge(clk_b_i) then
data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
end if;
end process mem_b;
end rtl;

672
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd
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--
-- A simulation model of Pacman hardware
-- Copyright (c) MikeJ - January 2006
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email pacman@fpgaarcade.com
--
-- Revision list
--
-- version 005 Papilio release by Jack Gassett
-- version 004 spartan3e release
-- version 003 Jan 2006 release, general tidy up
-- version 002 optional vga scan doubler
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pacmant is
port (
O_VIDEO_R : out std_logic_vector(2 downto 0);
O_VIDEO_G : out std_logic_vector(2 downto 0);
O_VIDEO_B : out std_logic_vector(1 downto 0);
O_HSYNC : out std_logic;
O_VSYNC : out std_logic;
O_HBLANK : out std_logic;
O_VBLANK : out std_logic;
--
O_AUDIO : out std_logic_vector(7 downto 0);
--
I_JOYSTICK_A : in std_logic_vector(4 downto 0);
I_JOYSTICK_B : in std_logic_vector(4 downto 0);
I_SW : in std_logic_vector(4 downto 0); -- active high
--
RESET : in std_logic;
CLK : in std_logic;
ENA_6 : in std_logic
);
end;
architecture RTL of pacmant is
-- timing
signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80
signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8
signal do_hsync : boolean;
signal hsync : std_logic;
signal vsync : std_logic;
signal hblank : std_logic;
signal vblank : std_logic := '1';
-- cpu
signal cpu_ena : std_logic;
signal cpu_m1_l : std_logic;
signal cpu_mreq_l : std_logic;
signal cpu_iorq_l : std_logic;
signal cpu_rd_l : std_logic;
signal cpu_rfsh_l : std_logic;
signal cpu_wait_l : std_logic;
signal cpu_int_l : std_logic;
signal cpu_nmi_l : std_logic;
signal cpu_busrq_l : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal rom_data : std_logic_vector(7 downto 0);
signal sync_bus_cs_l : std_logic;
signal control_reg : std_logic_vector(7 downto 0);
--
signal vram_addr_ab : std_logic_vector(11 downto 0);
signal ab : std_logic_vector(11 downto 0);
signal sync_bus_db : std_logic_vector(7 downto 0);
signal sync_bus_r_w_l : std_logic;
signal sync_bus_wreq_l : std_logic;
signal sync_bus_stb : std_logic;
signal cpu_vec_reg : std_logic_vector(7 downto 0);
signal sync_bus_reg : std_logic_vector(7 downto 0);
signal vram_l : std_logic;
signal rams_data_out : std_logic_vector(7 downto 0);
-- more decode
signal wr0_l : std_logic;
signal wr1_l : std_logic;
signal wr2_l : std_logic;
signal iodec_out_l : std_logic;
signal iodec_wdr_l : std_logic;
signal iodec_in0_l : std_logic;
signal iodec_in1_l : std_logic;
signal iodec_dipsw_l : std_logic;
-- watchdog
signal watchdog_cnt : std_logic_vector(3 downto 0);
signal watchdog_reset_l : std_logic;
signal freeze : std_logic;
-- ip registers
signal button_in : std_logic_vector(14 downto 0);
signal button_debounced : std_logic_vector(14 downto 0);
signal in0_reg : std_logic_vector(7 downto 0);
signal in1_reg : std_logic_vector(7 downto 0);
signal dipsw_reg : std_logic_vector(7 downto 0);
signal joystick_reg : std_logic_vector(4 downto 0);
signal joystick_reg2 : std_logic_vector(4 downto 0);
begin
joystick_reg <= I_JOYSTICK_A;
joystick_reg2 <= I_JOYSTICK_B;
--
-- video timing
--
p_hvcnt : process
variable hcarry,vcarry : boolean;
begin
wait until rising_edge(clk);
if (ena_6 = '1') then
hcarry := (hcnt = "111111111");
if hcarry then
hcnt <= "010000000"; -- 080
else
hcnt <= hcnt +"1";
end if;
-- hcnt 8 on circuit is 256H_L
vcarry := (vcnt = "111111111");
if do_hsync then
if vcarry then
vcnt <= "011111000"; -- 0F8
else
vcnt <= vcnt +"1";
end if;
end if;
end if;
end process;
p_sync_comb : process(hcnt, vcnt)
begin
vsync <= not vcnt(8);
do_hsync <= (hcnt = "010101111"); -- 0AF
end process;
p_sync : process
begin
wait until rising_edge(clk);
if (ena_6 = '1') then
-- Timing hardware is coded differently to the real hw
-- to avoid the use of multiple clocks. Result is identical.
if (hcnt = "010010111") then -- 097
O_HBLANK <= '1';
elsif (hcnt = "010001111") then -- 08F
hblank <= '1';
elsif (hcnt = "011101111") then
hblank <= '0'; -- 0EF
O_HBLANK <= '0';
end if;
if do_hsync then
hsync <= '1';
elsif (hcnt = "011001111") then -- 0CF
hsync <= '0';
end if;
if do_hsync then
if (vcnt = "111101111") then -- 1EF
vblank <= '1';
elsif (vcnt = "100001111") then -- 10F
vblank <= '0';
end if;
end if;
end if;
end process;
--
-- cpu
--
p_cpu_wait_comb : process(freeze, sync_bus_wreq_l)
begin
cpu_wait_l <= '1';
if (freeze = '1') or (sync_bus_wreq_l = '0') then
cpu_wait_l <= '0';
end if;
end process;
p_irq_req_watchdog : process
variable rising_vblank : boolean;
begin
wait until rising_edge(clk);
if (ena_6 = '1') then
rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF
--rising_vblank := do_hsync; -- debug
-- interrupt 8c
if (control_reg(0) = '0') then
cpu_int_l <= '1';
elsif rising_vblank then -- 1EF
cpu_int_l <= '0';
end if;
-- watchdog 8c
-- note sync reset
if (reset = '1') then
watchdog_cnt <= "1111";
elsif (iodec_wdr_l = '0') then
watchdog_cnt <= "0000";
elsif rising_vblank and (freeze = '0') then
watchdog_cnt <= watchdog_cnt + "1";
end if;
watchdog_reset_l <= '1';
if (watchdog_cnt = "1111") then
watchdog_reset_l <= '0';
end if;
-- simulation
-- pragma translate_off
-- synopsys translate_off
watchdog_reset_l <= not reset; -- watchdog disable
-- synopsys translate_on
-- pragma translate_on
end if;
end process;
-- other cpu signals
cpu_busrq_l <= '1';
cpu_nmi_l <= '1';
p_cpu_ena : process(hcnt, ena_6)
begin
cpu_ena <= '0';
if (ena_6 = '1') then
cpu_ena <= hcnt(0);
end if;
end process;
u_cpu : entity work.T80sed
port map (
RESET_n => watchdog_reset_l,
CLK_n => clk,
CLKEN => cpu_ena,
WAIT_n => cpu_wait_l,
INT_n => cpu_int_l,
NMI_n => cpu_nmi_l,
BUSRQ_n => cpu_busrq_l,
M1_n => cpu_m1_l,
MREQ_n => cpu_mreq_l,
IORQ_n => cpu_iorq_l,
RD_n => cpu_rd_l,
WR_n => open,
RFSH_n => cpu_rfsh_l,
HALT_n => open,
BUSAK_n => open,
A => cpu_addr,
DI => cpu_data_in,
DO => cpu_data_out
);
--
-- primary addr decode
--
p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr)
begin
-- rom 0x0000 - 0x3FFF
-- syncbus 0x4000 - 0x7FFF
-- 7M
-- 7N
sync_bus_cs_l <= '1';
-- program_rom_cs_l <= '1';
if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then
-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then
-- program_rom_cs_l <= '0';
-- end if;
if (cpu_addr(14) = '1') then
sync_bus_cs_l <= '0';
end if;
end if;
end process;
--
-- sync bus custom ic
--
p_sync_bus_reg : process
begin
wait until rising_edge(clk);
if (ena_6 = '1') then
-- register on sync bus module that is used to store interrupt vector
if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then
cpu_vec_reg <= cpu_data_out;
end if;
-- read holding reg
if (hcnt(1 downto 0) = "01") then
sync_bus_reg <= cpu_data_in;
end if;
end if;
end process;
p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt)
begin
-- sync_bus_stb is now an active low clock enable signal
sync_bus_stb <= '1';
sync_bus_r_w_l <= '1';
if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then
if (cpu_rd_l = '1') then
sync_bus_r_w_l <= '0';
end if;
sync_bus_stb <= '0';
end if;
sync_bus_wreq_l <= '1';
if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then
sync_bus_wreq_l <= '0';
end if;
end process;
--
-- vram addr custom ic
--
u_vram_addr : entity work.PACMAN_VRAM_ADDR
port map (
AB => vram_addr_ab,
H256_L => hcnt(8),
H128 => hcnt(7),
H64 => hcnt(6),
H32 => hcnt(5),
H16 => hcnt(4),
H8 => hcnt(3),
H4 => hcnt(2),
H2 => hcnt(1),
H1 => hcnt(0),
V128 => vcnt(7),
V64 => vcnt(6),
V32 => vcnt(5),
V16 => vcnt(4),
V8 => vcnt(3),
V4 => vcnt(2),
V2 => vcnt(1),
V1 => vcnt(0),
FLIP => control_reg(3)
);
p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab)
begin
--When 2H is low, the CPU controls the bus.
if (hcnt(1) = '0') then
ab <= cpu_addr(11 downto 0);
else
ab <= vram_addr_ab;
end if;
end process;
p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb)
variable a,b : std_logic;
begin
a := not (cpu_addr(12) or sync_bus_stb);
b := hcnt(1) and hcnt(0);
vram_l <= not (a or b);
end process;
p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr)
variable sel : std_logic_vector(2 downto 0);
variable dec : std_logic_vector(7 downto 0);
variable selb : std_logic_vector(1 downto 0);
variable decb : std_logic_vector(3 downto 0);
begin
-- WRITE
-- out_l 0x5000 - 0x503F control space
-- wr0_l 0x5040 - 0x504F sound
-- wr1_l 0x5050 - 0x505F sound
-- wr2_l 0x5060 - 0x506F sprite
-- 0x5080 - 0x50BF unused
-- wdr_l 0x50C0 - 0x50FF watchdog reset
-- READ
-- in0_l 0x5000 - 0x503F in port 0
-- in1_l 0x5040 - 0x507F in port 1
-- dipsw_l 0x5080 - 0x50BF dip switches
-- 7J
dec := "11111111";
sel := sync_bus_r_w_l & ab(7) & ab(6);
if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then
case sel is
when "000" => dec := "11111110";
when "001" => dec := "11111101";
when "010" => dec := "11111011";
when "011" => dec := "11110111";
when "100" => dec := "11101111";
when "101" => dec := "11011111";
when "110" => dec := "10111111";
when "111" => dec := "01111111";
when others => null;
end case;
end if;
iodec_out_l <= dec(0);
iodec_wdr_l <= dec(3);
iodec_in0_l <= dec(4);
iodec_in1_l <= dec(5);
iodec_dipsw_l <= dec(6);
-- 7M
decb := "1111";
selb := ab(5) & ab(4);
if (dec(1) = '0') then
case selb is
when "00" => decb := "1110";
when "01" => decb := "1101";
when "10" => decb := "1011";
when "11" => decb := "0111";
when others => null;
end case;
end if;
wr0_l <= decb(0);
wr1_l <= decb(1);
wr2_l <= decb(2);
end process;
p_control_reg : process
variable ena : std_logic_vector(7 downto 0);
begin
-- 8 bit addressable latch 7K
-- (made into register)
-- 0 interrupt ena
-- 1 sound ena
-- 2 not used
-- 3 flip
-- 4 1 player start lamp
-- 5 2 player start lamp
-- 6 coin lockout
-- 7 coin counter
wait until rising_edge(clk);
if (ena_6 = '1') then
ena := "00000000";
if (iodec_out_l = '0') then
case ab(2 downto 0) is
when "000" => ena := "00000001";
when "001" => ena := "00000010";
when "010" => ena := "00000100";
when "011" => ena := "00001000";
when "100" => ena := "00010000";
when "101" => ena := "00100000";
when "110" => ena := "01000000";
when "111" => ena := "10000000";
when others => null;
end case;
end if;
if (watchdog_reset_l = '0') then
control_reg <= (others => '0');
else
for i in 0 to 7 loop
if (ena(i) = '1') then
control_reg(i) <= cpu_data_out(0);
end if;
end loop;
end if;
end if;
end process;
p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out)
begin
-- simplified data source for video subsystem
-- only cpu or ram are sources of interest
if (hcnt(1) = '0') then
sync_bus_db <= cpu_data_out;
else
sync_bus_db <= rams_data_out;
end if;
end process;
p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l,
iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data,
rams_data_out, in0_reg, in1_reg, dipsw_reg)
begin
-- simplifed again
if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then
cpu_data_in <= cpu_vec_reg;
elsif (sync_bus_wreq_l = '0') then
cpu_data_in <= sync_bus_reg;
else
if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff
cpu_data_in <= rom_data;
elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff
cpu_data_in <= rom_data;
else
cpu_data_in <= rams_data_out;
if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if;
if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if;
if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if;
end if;
end if;
end process;
u_rams : work.dpram generic map (12,8)
port map
(
clk_a_i => clk,
en_a_i => ena_6,
we_i => not sync_bus_r_w_l and not vram_l,
addr_a_i => ab(11 downto 0),
data_a_i => cpu_data_out, -- cpu only source of ram data
clk_b_i => clk,
addr_b_i => ab(11 downto 0),
data_b_o => rams_data_out
);
u_program_rom0 : entity work.sprom
generic map (
init_file => "./roms/prog.hex",
widthad_a => 14,
width_a => 8)
port map (
address => cpu_addr(13 downto 0),
clock => clk,
q => rom_data
);
-- video subsystem
--
u_video : entity work.PACMAN_VIDEO
port map (
I_HCNT => hcnt,
I_VCNT => vcnt,
--
I_AB => ab,
I_DB => sync_bus_db,
--
I_HBLANK => hblank,
I_VBLANK => vblank,
I_FLIP => control_reg(3),
I_WR2_L => wr2_l,
--
O_RED => O_VIDEO_R,
O_GREEN => O_VIDEO_G,
O_BLUE => O_VIDEO_B,
--
ENA_6 => ena_6,
CLK => clk
);
O_HSYNC <= hSync;
O_VSYNC <= vSync;
--O_HBLANK <= hblank;
O_VBLANK <= vblank;
--
--
-- audio subsystem
--
u_audio : entity work.PACMAN_AUDIO
port map (
I_HCNT => hcnt,
--
I_AB => ab,
I_DB => sync_bus_db,
--
I_WR1_L => wr1_l,
I_WR0_L => wr0_l,
I_SOUND_ON => control_reg(1),
--
O_AUDIO => O_AUDIO,
ENA_6 => ena_6,
CLK => clk
);
button_in(9 downto 5) <= I_SW(4 downto 0);
button_in(4 downto 0) <= joystick_reg(4 downto 0);
button_in(14 downto 10) <= joystick_reg2(4 downto 0);
button_debounced <= button_in;
--button_debounced Arcade MegaWing Location
-- 8 RIGHT PushButton
-- 7 DOWN PushButton
-- 6 UP PushButton
-- 5 LEFT PushButton
-- 4 Fire Joystick
-- 3 RIGHT Joystick
-- 2 LEFT Joystick
-- 1 DOWN Joystick
-- 0 UP Joystick
p_input_registers : process
begin
wait until rising_edge(clk);
if (ena_6 = '1') then
-- on is low
in0_reg(7) <= '0'; -- IPT_SERVICE1
in0_reg(6) <= not button_debounced(7); -- coin2
in0_reg(5) <= not button_debounced(7); -- coin1
in0_reg(4) <= not button_debounced(9); -- "Rack Test (Cheat)"
in0_reg(3) <= button_debounced(1); -- p1 down
in0_reg(2) <= button_debounced(3); -- p1 right
in0_reg(1) <= button_debounced(2); -- p1 left
in0_reg(0) <= button_debounced(0); -- p1 up
in1_reg(7) <= '1'; -- unused
in1_reg(6) <= not button_debounced(8); -- start2 RIGHT PushButton
in1_reg(5) <= not button_debounced(5); -- start1 LEFT PushButton
in1_reg(4) <= not button_debounced(6); -- Service Mode
in1_reg(3) <= button_debounced(11); -- p2 down
in1_reg(2) <= button_debounced(13); -- p2 right
in1_reg(1) <= button_debounced(12); -- p2 left
in1_reg(0) <= button_debounced(10); -- p2 up
-- on is low
freeze <= '0';
dipsw_reg(7) <= '1'; -- Stop Screen
dipsw_reg(5) <= '1'; -- Unused
dipsw_reg(5) <= '1'; -- Skip Screen
dipsw_reg(4) <= '0'; -- Cabinet
dipsw_reg(3 downto 2) <= "10"; -- Lives (3)
dipsw_reg(1 downto 0) <= "01"; -- cost (1 coin, 1 play)
end if;
end process;
end RTL;

213
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@@ -1,213 +0,0 @@
--
-- A simulation model of Pacman hardware
-- Copyright (c) MikeJ - January 2006
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email pacman@fpgaarcade.com
--
-- Revision list
--
-- version 003 Jan 2006 release, general tidy up
-- version 002 added volume multiplier
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
entity PACMAN_AUDIO is
port (
I_HCNT : in std_logic_vector(8 downto 0);
--
I_AB : in std_logic_vector(11 downto 0);
I_DB : in std_logic_vector( 7 downto 0);
--
I_WR1_L : in std_logic;
I_WR0_L : in std_logic;
I_SOUND_ON : in std_logic;
--
O_AUDIO : out std_logic_vector(7 downto 0);
ENA_6 : in std_logic;
CLK : in std_logic
);
end;
architecture RTL of PACMAN_AUDIO is
signal addr : std_logic_vector(3 downto 0);
signal data : std_logic_vector(3 downto 0);
signal vol_ram_dout : std_logic_vector(3 downto 0);
signal frq_ram_dout : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(5 downto 0);
signal accum_reg : std_logic_vector(5 downto 0);
signal rom3m_n : std_logic_vector(15 downto 0);
signal rom3m_w : std_logic_vector(3 downto 0);
signal rom3m : std_logic_vector(3 downto 0);
signal rom1m_addr : std_logic_vector(7 downto 0);
signal rom1m_data : std_logic_vector(7 downto 0);
begin
p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg)
begin
if (I_HCNT(1) = '0') then -- 2h,
addr <= I_AB(3 downto 0);
data <= I_DB(3 downto 0); -- removed invert
else
addr <= I_HCNT(5 downto 2);
data <= accum_reg(4 downto 1);
end if;
end process;
vol_ram : work.dpram generic map (4,4)
port map
(
clk_a_i => CLK,
en_a_i => ENA_6,
we_i => not I_WR1_L,
addr_a_i => addr(3 downto 0),
data_a_i => data,
clk_b_i => CLK,
addr_b_i => addr(3 downto 0),
data_b_o => vol_ram_dout
);
frq_ram : work.dpram generic map (4,4)
port map
(
clk_a_i => CLK,
en_a_i => ENA_6,
we_i => rom3m(1),
addr_a_i => addr(3 downto 0),
data_a_i => data,
clk_b_i => CLK,
addr_b_i => addr(3 downto 0),
data_b_o => frq_ram_dout
);
p_control_rom_comb : process(I_HCNT)
begin
rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign
case I_HCNT(3 downto 0) is
when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0";
when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2";
when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0";
when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0";
when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0";
when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2";
when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0";
when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0";
when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0";
when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2";
when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0";
when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0";
when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0";
when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2";
when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0";
when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0";
when others => null;
end case;
end process;
p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w)
begin
rom3m <= rom3m_w;
if (I_WR0_L = '1') then
case I_HCNT(5 downto 4) is
when "00" => rom3m <= rom3m_n( 3 downto 0);
when "01" => rom3m <= rom3m_n( 7 downto 4);
when "10" => rom3m <= rom3m_n(11 downto 8);
when "11" => rom3m <= rom3m_n(15 downto 12);
when others => null;
end case;
end if;
end process;
p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg)
begin
-- 1K 4 bit adder
sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5));
end process;
p_accum_reg : process
begin
-- 1L
wait until rising_edge(CLK);
if (ENA_6 = '1') then
if (rom3m(3) = '1') then -- clear
accum_reg <= "000000";
elsif (rom3m(0) = '1') then -- rising edge clk
accum_reg <= sum(5 downto 1) & accum_reg(4);
end if;
end if;
end process;
p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout)
begin
rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0);
rom1m_addr(4 downto 0) <= accum_reg(4 downto 0);
end process;
audio_rom_1m : entity work.sprom
generic map (
init_file => "./roms/prom1.hex",
widthad_a => 8,
width_a => 8)
port map (
address => rom1m_addr,
clock => CLK,
q => rom1m_data
);
p_original_output_reg : process
begin
-- 2m used to use async clear
wait until rising_edge(CLK);
if (ENA_6 = '1') then
if (I_SOUND_ON = '0') then
O_AUDIO <= "00000000";
elsif (rom3m(2) = '1') then
O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0);
end if;
end if;
end process;
end architecture RTL;

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--
-- A simulation model of Pacman hardware
-- Copyright (c) MikeJ - January 2006
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email pacman@fpgaarcade.com
--
-- Revision list
--
-- version 003 Jan 2006 release, general tidy up
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
entity PACMAN_VIDEO is
port (
I_HCNT : in std_logic_vector(8 downto 0);
I_VCNT : in std_logic_vector(8 downto 0);
--
I_AB : in std_logic_vector(11 downto 0);
I_DB : in std_logic_vector( 7 downto 0);
--
I_HBLANK : in std_logic;
I_VBLANK : in std_logic;
I_FLIP : in std_logic;
I_WR2_L : in std_logic;
--
O_RED : out std_logic_vector(2 downto 0);
O_GREEN : out std_logic_vector(2 downto 0);
O_BLUE : out std_logic_vector(1 downto 0);
ENA_6 : in std_logic;
CLK : in std_logic
);
end;
architecture RTL of PACMAN_VIDEO is
signal sprite_xy_ram_temp : std_logic_vector(7 downto 0);
signal dr : std_logic_vector(7 downto 0);
signal char_reg : std_logic_vector(7 downto 0);
signal char_sum_reg : std_logic_vector(3 downto 0);
signal char_match_reg : std_logic;
signal char_hblank_reg : std_logic;
signal char_hblank_reg_t1 : std_logic;
signal db_reg : std_logic_vector(7 downto 0);
signal xflip : std_logic;
signal yflip : std_logic;
signal obj_on : std_logic;
signal ca : std_logic_vector(12 downto 0);
signal char_rom_5ef_dout : std_logic_vector(7 downto 0);
signal shift_regl : std_logic_vector(3 downto 0);
signal shift_regu : std_logic_vector(3 downto 0);
signal shift_op : std_logic_vector(1 downto 0);
signal shift_sel : std_logic_vector(1 downto 0);
signal vout_obj_on : std_logic;
signal vout_yflip : std_logic;
signal vout_hblank : std_logic;
signal vout_db : std_logic_vector(4 downto 0);
signal cntr_ld : std_logic;
signal ra : std_logic_vector(7 downto 0);
signal sprite_ram_ip : std_logic_vector(3 downto 0);
signal sprite_ram_op : std_logic_vector(3 downto 0);
signal sprite_ram_addr : std_logic_vector(7 downto 0);
signal sprite_ram_addr_t1 : std_logic_vector(7 downto 0);
signal vout_obj_on_t1 : std_logic;
signal col_rom_addr : std_logic_vector(7 downto 0);
signal lut_4a : std_logic_vector(7 downto 0);
signal lut_4a_t1 : std_logic_vector(7 downto 0);
signal vout_hblank_t1 : std_logic;
signal sprite_ram_reg : std_logic_vector(3 downto 0);
signal video_out : std_logic_vector(7 downto 0);
signal video_op_sel : std_logic;
signal final_col : std_logic_vector(3 downto 0);
begin
-- ram enable is low when HBLANK_L is 0 (for sprite access) or
-- 2H is low (for cpu writes)
-- we can simplify this
dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board
sprite_xy_ram : work.dpram generic map (4,8)
port map
(
clk_a_i => CLK,
en_a_i => ENA_6,
we_i => not I_WR2_L,
addr_a_i => I_AB(3 downto 0),
data_a_i => I_DB,
clk_b_i => CLK,
addr_b_i => I_AB(3 downto 0),
data_b_o => sprite_xy_ram_temp
);
p_char_regs : process
variable inc : std_logic;
variable sum : std_logic_vector(8 downto 0);
variable match : std_logic;
begin
wait until rising_edge (CLK);
if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h
inc := (not I_HBLANK);
-- 1f, 2f
sum := (I_VCNT(7 downto 0) & '1') + (dr & inc);
-- 3e
match := '0';
if (sum(8 downto 5) = "1111") then
match := '1';
end if;
-- 1h
char_sum_reg <= sum(4 downto 1);
char_match_reg <= match;
char_hblank_reg <= I_HBLANK;
-- 4d
db_reg <= I_DB; -- character reg
end if;
end process;
p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg)
begin
if (char_hblank_reg = '0') then
xflip <= I_FLIP;
yflip <= I_FLIP;
else
xflip <= db_reg(1);
yflip <= db_reg(0);
end if;
end process;
p_char_addr_comb : process(db_reg, I_HCNT,
char_match_reg, char_sum_reg, char_hblank_reg,
xflip, yflip)
begin
-- 2h, 4e
obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l
ca(12) <= char_hblank_reg;
ca(11 downto 6) <= db_reg(7 downto 2);
if (char_hblank_reg = '0') then
ca(5) <= db_reg(1);
ca(4) <= db_reg(0);
else
ca(5) <= char_sum_reg(3) xor xflip;
ca(4) <= I_HCNT(3);
end if;
ca(3) <= I_HCNT(2) xor yflip;
ca(2) <= char_sum_reg(2) xor xflip;
ca(1) <= char_sum_reg(1) xor xflip;
ca(0) <= char_sum_reg(0) xor xflip;
end process;
-- char roms
char_rom_5ef : entity work.sprom
generic map (
init_file => "./roms/gfx.hex",
widthad_a => 13,
width_a => 8)
port map (
address => ca,
clock => CLK,
q => char_rom_5ef_dout
);
p_char_shift : process
begin
-- 4 bit shift req
wait until rising_edge (CLK);
if (ENA_6 = '1') then
case shift_sel is
when "00" => null;
when "01" => shift_regu <= '0' & shift_regu(3 downto 1);
shift_regl <= '0' & shift_regl(3 downto 1);
when "10" => shift_regu <= shift_regu(2 downto 0) & '0';
shift_regl <= shift_regl(2 downto 0) & '0';
when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load
shift_regl <= char_rom_5ef_dout(3 downto 0);
when others => null;
end case;
end if;
end process;
p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl)
variable ip : std_logic;
begin
ip := I_HCNT(0) and I_HCNT(1);
if (vout_yflip = '0') then
shift_sel(0) <= ip;
shift_sel(1) <= '1';
shift_op(0) <= shift_regl(3);
shift_op(1) <= shift_regu(3);
else
shift_sel(0) <= '1';
shift_sel(1) <= ip;
shift_op(0) <= shift_regl(0);
shift_op(1) <= shift_regu(0);
end if;
end process;
p_video_out_reg : process
begin
wait until rising_edge (CLK);
if (ENA_6 = '1') then
if (I_HCNT(2 downto 0) = "111") then
vout_obj_on <= obj_on;
vout_yflip <= yflip;
vout_hblank <= I_HBLANK;
vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg
end if;
end if;
end process;
p_lut_4a_comb : process(vout_db, shift_op)
begin
col_rom_addr <= '0' & vout_db(4 downto 0) & shift_op(1 downto 0);
end process;
col_rom_4a : entity work.sprom
generic map (
init_file => "./roms/prom4.hex",
widthad_a => 8,
width_a => 8)
port map (
address => col_rom_addr,
clock => CLK,
q => lut_4a
);
cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0';
p_ra_cnt : process
begin
wait until rising_edge (CLK);
if (ENA_6 = '1') then
if (cntr_ld = '1') then
ra <= dr;
else
ra <= ra + "1";
end if;
end if;
end process;
sprite_ram_addr <= ra;
u_sprite_ram : work.dpram generic map (8,4)
port map
(
clk_a_i => CLK,
en_a_i => ENA_6,
we_i => vout_obj_on,
addr_a_i => sprite_ram_addr,
data_a_i => sprite_ram_ip,
clk_b_i => CLK,
addr_b_i => sprite_ram_addr,
data_b_o => sprite_ram_op
);
sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000";
video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0';
p_sprite_ram_ip_reg : process
begin
wait until rising_edge (CLK);
if (ENA_6 = '1') then
vout_obj_on_t1 <= vout_obj_on;
vout_hblank_t1 <= vout_hblank;
lut_4a_t1 <= lut_4a;
end if;
end process;
p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1)
begin
-- 3a
if (vout_hblank_t1 = '0') then
sprite_ram_ip <= (others => '0');
else
if (video_op_sel = '1') then
sprite_ram_ip <= sprite_ram_reg;
else
sprite_ram_ip <= lut_4a_t1(3 downto 0);
end if;
end if;
end process;
p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a)
begin
-- 3b
if (vout_hblank = '1') or (I_VBLANK = '1') then
final_col <= (others => '0');
else
if (video_op_sel = '1') then
final_col <= sprite_ram_reg; -- sprite
else
final_col <= lut_4a(3 downto 0);
end if;
end if;
end process;
col : entity work.sprom
generic map (
init_file => "./roms/col.hex",
widthad_a => 4,
width_a => 8)
port map (
address => final_col,
clock => CLK,
q => video_out
);
-- assign outputs
O_BLUE (1 downto 0) <= video_out(7 downto 6);
O_GREEN(2 downto 0) <= video_out(5 downto 3);
O_RED (2 downto 0) <= video_out(2 downto 0);
end architecture;

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@@ -1,273 +0,0 @@
--
-- A simulation model of Pacman hardware
-- Copyright (c) MikeJ & CarlW - January 2006
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email pacman@fpgaarcade.com
--
-- Revision list
--
-- version 003 Jan 2006 release, general tidy up
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity X74_157 is
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
G : in std_logic;
S : in std_logic
);
end;
architecture RTL of X74_157 is
begin
p_y_comb : process(S,G,A,B)
begin
for i in 0 to 3 loop
-- quad 2 line to 1 line mux (true logic)
if (G = '1') then
Y(i) <= '0';
else
if (S = '0') then
Y(i) <= A(i);
else
Y(i) <= B(i);
end if;
end if;
end loop;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity X74_257 is
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
S : in std_logic
);
end;
architecture RTL of X74_257 is
signal ab : std_logic_vector (3 downto 0);
begin
Y <= ab; -- no tristate
p_ab : process(S,A,B)
begin
for i in 0 to 3 loop
if (S = '0') then
AB(i) <= A(i);
else
AB(i) <= B(i);
end if;
end loop;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity PACMAN_VRAM_ADDR is
port (
AB : out std_logic_vector (11 downto 0);
H256_L : in std_logic;
H128 : in std_logic;
H64 : in std_logic;
H32 : in std_logic;
H16 : in std_logic;
H8 : in std_logic;
H4 : in std_logic;
H2 : in std_logic;
H1 : in std_logic;
V128 : in std_logic;
V64 : in std_logic;
V32 : in std_logic;
V16 : in std_logic;
V8 : in std_logic;
V4 : in std_logic;
V2 : in std_logic;
V1 : in std_logic;
FLIP : in std_logic
);
end;
architecture RTL of PACMAN_VRAM_ADDR is
signal v128p : std_logic;
signal v64p : std_logic;
signal v32p : std_logic;
signal v16p : std_logic;
signal v8p : std_logic;
signal h128p : std_logic;
signal h64p : std_logic;
signal h32p : std_logic;
signal h16p : std_logic;
signal h8p : std_logic;
signal sel : std_logic;
signal y157 : std_logic_vector (11 downto 0);
component X74_157
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
G : in std_logic;
S : in std_logic
);
end component;
component X74_257
port (
Y : out std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
A : in std_logic_vector (3 downto 0);
S : in std_logic
);
end component;
begin
p_vp_comb : process(FLIP, V8, V16, V32, V64, V128)
begin
v128p <= FLIP xor V128;
v64p <= FLIP xor V64;
v32p <= FLIP xor V32;
v16p <= FLIP xor V16;
v8p <= FLIP xor V8;
end process;
p_hp_comb : process(FLIP, H8, H16, H32, H64, H128)
begin
H128P <= FLIP xor H128;
H64P <= FLIP xor H64;
H32P <= FLIP xor H32;
H16P <= FLIP xor H16;
H8P <= FLIP xor H8;
end process;
p_sel : process(H16, H32, H64)
begin
sel <= not((H32 xor H16) or (H32 xor H64));
end process;
--p_oe257 : process(H2)
--begin
-- oe <= not(H2);
--end process;
U6 : X74_157
port map(
Y => y157(11 downto 8),
B(3) => '0',
B(2) => H4,
B(1) => h64p,
B(0) => h64p,
A => "1111",
G => '0',
S => sel
);
U5 : X74_157
port map(
Y => y157(7 downto 4),
B(3) => h64p,
B(2) => h64p,
B(1) => h8p,
B(0) => v128p,
A => "1111",
G => '0',
S => sel
);
U4 : X74_157
port map(
Y => y157(3 downto 0),
B(3) => v64p,
B(2) => v32p,
B(1) => v16p,
B(0) => v8p,
A(3) => H64,
A(2) => H32,
A(1) => H16,
A(0) => H4,
G => '0',
S => sel
);
U3 : X74_257
port map(
Y => AB(11 downto 8),
B(3) => '0',
B(2) => H4,
B(1) => v128p,
B(0) => v64p,
A => y157(11 downto 8),
S => H256_L
);
U2 : X74_257
port map(
Y => AB(7 downto 4),
B(3) => v32p,
B(2) => v16p,
B(1) => v8p,
B(0) => h128p,
A => y157(7 downto 4),
S => H256_L
);
U1 : X74_257
port map(
Y => AB(3 downto 0),
B(3) => h64p,
B(2) => h32p,
B(1) => h16p,
B(0) => h8p,
A => y157(3 downto 0),
S => H256_L
);
end RTL;

4
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.qip
View File

@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

320
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.v
View File

@@ -1,320 +0,0 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

2
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/roms/col.hex
View File

@@ -1,2 +0,0 @@
:10000000000766EF00F8EA6F003F00C938AAAFF6B4
:00000001FF

513
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/roms/gfx.hex
View File

@@ -1,513 +0,0 @@
:100000000000000000CCFFFF00000000EEFFFFFF3B
:10001000CCEEEEEEFFFFFFFFFFFFFFFFFFFFFFFF56
:10002000FFFFFFFF772288CCFFFF7711CCFFFFFF98
:1000300088CCEEEEEEEECC883377DFBFBFFF7733B0
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:1000C000CCEEFFFFFFFFFF77BFBFFF777733110055
:1000D000FFFFFFEEEECC88003377FFFFFFFFFFEE60
:1000E000FFFFFFFFFFFFCCCCFFFFFFFF7777DFDFD6
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:10010000FFFFFFFFEEEECC00FFFFFFFF777733002E
:10011000FFFFFFFFFFFFFFFF234757579FBFBFFFB3
:100120000000000033FF9FBF0000000000001133FB
:10013000EEFFFFFFFFFFFF77FFFFFFFFFFFF330033
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:10015000000000000088FFFF00008888CCDDCCEEA6
:10016000000000000000000000000000000000EEA1
:100170001133777777333300000000000000000070
:10018000000000000000000000000000000088FFE8
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:1002000000000000000000000000000000000000EE
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:10022000FFFFFF77FFFFFFFFFFFF33CCFFFFFFFF65
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:1002500099555533884422118855331100FF880081
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:1002B000FFFFFFFFFFFFFFFFFFFFFFFFFF11FFFF3C
:1002C0000000EEDDDD000000000000000000000086
:1002D000050A050A050A050A8D8A8D8A8D8A8D8A86
:1002E0000000006666000000000000000000000042
:1002F00000000000000000000000EEDDDD00000056
:1003000088CC222266CC88003377CC88887733006B
:100310002222EEEE222200000000FFFF4400000037
:100320002222AAAAEEEE660066FFBB9999CC440091
:10033000CCEE22222266440088DDFFBB99880000B3
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:1003F000C0C8D5FFFFD9C0803071F0F3F4F0713080
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1025
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/roms/prog.hex
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File diff suppressed because it is too large Load Diff

17
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/roms/prom1.hex
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@@ -1,17 +0,0 @@
:1000000007090A0B0C0D0D0E0E0E0D0D0C0B0A0937
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17
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/roms/prom4.hex
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@@ -1,17 +0,0 @@
:1000000000000000000F0B01000F0B03000F0B0F8F
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:00000001FF

82
Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/keyboard.v
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module keyboard
(
input clk,
input reset,
input ps2_kbd_clk,
input ps2_kbd_data,
output reg[9:0] joystick
);
reg [11:0] shift_reg = 12'hFFF;
wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
wire [7:0] kcode = kdata[9:2];
reg release_btn = 0;
reg [7:0] code;
reg input_strobe = 0;
always @(negedge clk) begin
reg old_reset = 0;
old_reset <= reset;
if(~old_reset & reset)begin
joystick <= 0;
end
if(input_strobe) begin
case(code)
'h16: joystick[1] <= ~release_btn; // 1
'h1E: joystick[2] <= ~release_btn; // 2
'h75: joystick[4] <= ~release_btn; // arrow up
'h72: joystick[5] <= ~release_btn; // arrow down
'h6B: joystick[6] <= ~release_btn; // arrow left
'h74: joystick[7] <= ~release_btn; // arrow right
'h29: joystick[0] <= ~release_btn; // Space
'h11: joystick[8] <= ~release_btn; // Left Alt
'h0d: joystick[9] <= ~release_btn; // Tab
'h76: joystick[3] <= ~release_btn; // Escape
endcase
end
end
always @(posedge clk) begin
reg [3:0] prev_clk = 0;
reg old_reset = 0;
reg action = 0;
old_reset <= reset;
input_strobe <= 0;
if(~old_reset & reset)begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
end else begin
prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
if(prev_clk == 1) begin
if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
shift_reg <= 12'hFFF;
if (kcode == 8'he0) ;
// Extended key code follows
else if (kcode == 8'hf0)
// Release code follows
action <= 1;
else begin
// Cancel extended/release flags for next time
action <= 0;
release_btn <= action;
code <= kcode;
input_strobe <= 1;
end
end else begin
shift_reg <= kdata;
end
end
end
end
endmodule