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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-16 08:14:53 +00:00

Move jt5205 to common

This commit is contained in:
Gyorgy Szombathelyi 2020-03-16 15:42:56 +01:00
parent 9a02517201
commit bbf7522211
8 changed files with 6 additions and 6 deletions

View File

@ -235,6 +235,7 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end ENTITY(IremM62_MiST)
# ---------------------------
set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/IremM62_MiST.sv
set_global_assignment -name VHDL_FILE rtl/target_top.vhd
set_global_assignment -name VHDL_FILE rtl/platform_variant_pkg.vhd
@ -263,8 +264,8 @@ set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name QIP_FILE rtl/jt5205/jt5205.qip
set_global_assignment -name VHDL_FILE rtl/Sound_Board.vhd
set_global_assignment -name QIP_FILE ../../common/Sound/jt5205/jt5205.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name VHDL_FILE ../../common/CPU/T80/Z80.vhd
@ -273,5 +274,4 @@ set_global_assignment -name SIGNALTAP_FILE output_files/sp.stp
set_global_assignment -name SIGNALTAP_FILE output_files/tilemap.stp
set_global_assignment -name SIGNALTAP_FILE output_files/sprite.stp
set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
set_global_assignment -name SIGNALTAP_FILE output_files/snd.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SIGNALTAP_FILE output_files/snd.stp

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@ -41,12 +41,12 @@ end
always @(posedge clk) begin
if (lim == 1) begin
cnt <= 1'b0;
if (sel == 2'd3) begin
cnt <= 7'd0;
vclk_o <= 1'b0;
end
if(cen) begin
if (lim != 1) cnt <= cnt + 7'd1;
if (sel != 2'd3) cnt <= cnt + 7'd1;
pre <= 1'b0;
preb <= 1'b0;