mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-19 09:18:02 +00:00
Some Changes
This commit is contained in:
Marcel
parent
5c870a0838
commit
c23fc0a76c
@ -1,6 +1,6 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Copyright (C) 1991-2014 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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@ -17,15 +17,15 @@
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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# Date created = 18:40:37 November 24, 2017
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# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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# Date created = 19:37:13 March 20, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# ace_assignment_defaults.qdf
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# Berzerk_MiST_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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@ -41,9 +41,31 @@
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/berzerk_mist.sv
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set_global_assignment -name VHDL_FILE rtl/berzerk.vhd
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set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_speech.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_speech_rom.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_sound_fx.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_program2.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_program1.vhd
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set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
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set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name VERILOG_FILE rtl/osd.v
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set_global_assignment -name VERILOG_FILE rtl/mist_io.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
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set_global_assignment -name VHDL_FILE rtl/dac.vhd
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# Pin & Location Assignments
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# ==========================
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@ -129,15 +151,17 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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# ================================
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name TOP_LEVEL_ENTITY berzerk_mist
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set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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# Fitter Assignments
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# ==================
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set_global_assignment -name DEVICE EP3C25E144C8
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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# set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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# set_global_assignment -name ENABLE_NCE_PIN OFF
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# set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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@ -173,55 +197,26 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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# EDA Netlist Writer Assignments
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# ==============================
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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# end EDA_TOOL_SETTINGS(eda_simulation)
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# -------------------------------------
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# ----------------------
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# start ENTITY(ace_mist)
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# --------------------------
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# start ENTITY(berzerk_mist)
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# start DESIGN_PARTITION(Top)
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# ---------------------------
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# Incremental Compilation Assignments
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# ===================================
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(ace_mist)
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# --------------------
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set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/berzerk_mist.sv
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set_global_assignment -name VHDL_FILE rtl/berzerk.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_speech.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_sound_fx.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_program2.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_program1.vhd
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set_global_assignment -name VHDL_FILE rtl/line_doubler.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
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set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
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set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name VERILOG_FILE rtl/osd.v
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set_global_assignment -name VERILOG_FILE rtl/mist_io.v
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set_global_assignment -name VERILOG_FILE rtl/keyboard.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
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set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/dac.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
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set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
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set_global_assignment -name VHDL_FILE rtl/berzerk_speech_rom.vhd
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# end ENTITY(berzerk_mist)
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# ------------------------
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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Binary file not shown.
@ -73,7 +73,6 @@ entity berzerk is
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port(
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clock_10 : in std_logic;
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reset : in std_logic;
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tv15Khz_mode : in std_logic;
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video_r : out std_logic;
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video_g : out std_logic;
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@ -83,6 +82,8 @@ port(
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video_csync : out std_logic;
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video_hs : out std_logic;
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video_vs : out std_logic;
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video_hb : out std_logic;
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video_vb : out std_logic;
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audio_out : out std_logic_vector(15 downto 0);
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start2 : in std_logic;
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@ -252,19 +253,6 @@ color <= colors(7 downto 4) when hcnt(2) = '0' else colors(3 downto 0);
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-- serialize video byte
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video <= color when graphx(to_integer(unsigned(not hcnt(2 downto 0)))) = '1' else "0000";
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-- apply blanking
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process(clock_10)
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begin
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if rising_edge(clock_10) then
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if ena_pixel = '1' then
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if blank = '0' then
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video_i <= video;
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else
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video_i <= (others => '0');
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end if;
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end if;
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end if;
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end process;
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@ -315,7 +303,7 @@ begin
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end if;
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end process;
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process (clock_10, cpu_iorq_n, cpu_addr)
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process (clock_10, cpu_iorq_n, cpu_addr, reset)
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begin
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if reset = '1' then
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cpu_int_n <= '1';
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@ -501,39 +489,22 @@ port map (
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hsync => hsync,
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vsync => vsync,
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csync => csync,
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blank => blank,
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hblank => video_hb,
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vblank => video_vb,
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hcnt_o => hcnt,
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vcnt_o => vcnt
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);
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-- line doubler
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line_doubler : entity work.line_doubler
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port map(
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clock => clock_10,
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video_i => video_i,
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hsync_i => hsync,
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vsync_i => vsync,
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video_o => video_o,
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hsync_o => hsync_o,
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vsync_o => vsync_o
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);
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--video_s <= video_i;
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--video_hs <= hsync;
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--video_vs <= vsync;
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video_s <= video;
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video_hs <= hsync;
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video_vs <= vsync;
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video_r <= video_s(0);
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video_g <= video_s(1);
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video_b <= video_s(2);
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video_hi <= video_s(3);
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-- output
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video_s <= video_o when tv15Khz_mode = '0' else video_i;
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video_clk <= clock_10;
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video_csync <= csync;
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video_hs <= hsync_o when tv15Khz_mode = '0' else hsync;
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video_vs <= vsync_o when tv15Khz_mode = '0' else vsync;
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-- Z80
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Z80 : entity work.T80se
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generic map(Mode => 0, T2Write => 1, IOWait => 1)
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@ -1,5 +1,4 @@
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module berzerk_mist
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(
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module berzerk_mist(
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output LED,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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@ -21,28 +20,16 @@ module berzerk_mist
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localparam CONF_STR = {
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"Berzerk;;",
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// "O2,Joystick Control,Upright,Normal;",
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"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"T6,Reset;",
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"V,v1.00.",`BUILD_DATE
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"V,v1.20.",`BUILD_DATE
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};
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire [9:0] kbjoy;
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wire [7:0] joystick_0;
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wire [7:0] joystick_1;
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wire scandoubler_disable;
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wire ypbpr;
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wire ps2_kbd_clk, ps2_kbd_data;
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assign LED = 1;
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assign AUDIO_R = AUDIO_L;
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wire clk_20, clk_10, clk_5;
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pll pll
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(
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pll pll(
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.inclk0(CLOCK_27),
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.areset(0),
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.c0(clk_20),
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@ -50,20 +37,24 @@ pll pll
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.c2(clk_5)
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);
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wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
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wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2];
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wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1];
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wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0];
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wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4];
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wire m_start1 = kbjoy[1];
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wire m_start2 = kbjoy[2];
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wire m_coin = kbjoy[3];
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire [9:0] kbjoy;
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wire [7:0] joystick_0;
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wire [7:0] joystick_1;
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wire scandoublerD;
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wire ypbpr;
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wire [10:0] ps2_key;
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wire hs, vs;
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wire hb, vb;
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wire blankn = ~(hb | vb);
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wire r, g, b;
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wire [15:0] audio;
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berzerk berzerk(
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.clock_10(clk_10),
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.reset(status[0] | status[6] | buttons[1]),
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.tv15Khz_mode(1'b1),
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.video_r(r),
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.video_g(g),
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.video_b(b),
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@ -72,10 +63,12 @@ berzerk berzerk(
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.video_csync(),
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.video_hs(hs),
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.video_vs(vs),
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.video_hb(hb),
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.video_vb(vb),
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.audio_out(audio),
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.start2(m_start2),
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.start1(m_start1),
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.coin1(m_coin),
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.start2(btn_two_players),
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.start1(btn_one_player),
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.coin1(btn_coin),
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.cocktail(1'b0),
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.right1(m_right),
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.left1(m_left),
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@ -93,31 +86,16 @@ berzerk berzerk(
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.dbg_cpu_addr_latch()
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);
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wire [15:0] audio;
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dac dac (
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.clk_i(clk_20),
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.res_n_i(1),
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.dac_i(audio[15:4]),
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.dac_o(AUDIO_L)
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);
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||||
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assign AUDIO_R = AUDIO_L;
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wire hs, vs;
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wire r, g, b;
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||||
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||||
video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer
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(
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video_mixer video_mixer(
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.clk_sys(clk_20),
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.ce_pix(clk_5),
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||||
.ce_pix_actual(clk_5),
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||||
.SPI_SCK(SPI_SCK),
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||||
.SPI_SS3(SPI_SS3),
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.SPI_DI(SPI_DI),
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||||
.R({r,r,r,r,r,r}),
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.G({g,g,g,g,g,g}),
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.B({b,b,b,b,b,b}),
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.R(blankn ? {r,r,r} : "000"),
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.G(blankn ? {g,g,g} : "000"),
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.B(blankn ? {b,b,b} : "000"),
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.HSync(hs),
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.VSync(vs),
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||||
.VGA_R(VGA_R),
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@ -125,17 +103,18 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer
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||||
.VGA_B(VGA_B),
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.VGA_VS(VGA_VS),
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.VGA_HS(VGA_HS),
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.scandoubler_disable(scandoubler_disable),//scandoubler_disable),
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||||
.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
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||||
.hq2x(status[4:3]==1),
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||||
.scandoublerD(scandoublerD),
|
||||
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
|
||||
.ypbpr(ypbpr),
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||||
.ypbpr_full(1),
|
||||
.line_start(0),
|
||||
.mono(0)
|
||||
);
|
||||
|
||||
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
|
||||
(
|
||||
.clk_sys (clk_20 ),
|
||||
mist_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
mist_io(
|
||||
.clk_sys (clk_20 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_SCK (SPI_SCK ),
|
||||
.CONF_DATA0 (CONF_DATA0 ),
|
||||
@ -144,26 +123,60 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
|
||||
.SPI_DI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable(scandoubler_disable),
|
||||
.scandoublerD (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.ps2_kbd_clk (ps2_kbd_clk ),
|
||||
.ps2_kbd_data (ps2_kbd_data ),
|
||||
.ps2_key (ps2_key ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
keyboard keyboard(
|
||||
.clk(clk_20),
|
||||
.reset(),
|
||||
.ps2_kbd_clk(ps2_kbd_clk),
|
||||
.ps2_kbd_data(ps2_kbd_data),
|
||||
.joystick(kbjoy)
|
||||
);
|
||||
dac #(
|
||||
.msbi_g(15))
|
||||
dac(
|
||||
.clk_i(clk_20),
|
||||
.res_n_i(1),
|
||||
.dac_i(audio),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
wire m_up = btn_up | joystick_0[3] | joystick_1[3];
|
||||
wire m_down = btn_down | joystick_0[2] | joystick_1[2];
|
||||
wire m_left = btn_left | joystick_0[1] | joystick_1[1];
|
||||
wire m_right = btn_right | joystick_0[0] | joystick_1[0];
|
||||
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
|
||||
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
|
||||
|
||||
reg btn_one_player = 0;
|
||||
reg btn_two_players = 0;
|
||||
reg btn_left = 0;
|
||||
reg btn_right = 0;
|
||||
reg btn_down = 0;
|
||||
reg btn_up = 0;
|
||||
reg btn_fire1 = 0;
|
||||
reg btn_fire2 = 0;
|
||||
reg btn_fire3 = 0;
|
||||
reg btn_coin = 0;
|
||||
wire pressed = ps2_key[9];
|
||||
wire [7:0] code = ps2_key[7:0];
|
||||
|
||||
always @(posedge clk_20) begin
|
||||
reg old_state;
|
||||
old_state <= ps2_key[10];
|
||||
if(old_state != ps2_key[10]) begin
|
||||
case(code)
|
||||
'h75: btn_up <= pressed; // up
|
||||
'h72: btn_down <= pressed; // down
|
||||
'h6B: btn_left <= pressed; // left
|
||||
'h74: btn_right <= pressed; // right
|
||||
'h76: btn_coin <= pressed; // ESC
|
||||
'h05: btn_one_player <= pressed; // F1
|
||||
'h06: btn_two_players <= pressed; // F2
|
||||
'h14: btn_fire3 <= pressed; // ctrl
|
||||
'h11: btn_fire2 <= pressed; // alt
|
||||
'h29: btn_fire1 <= pressed; // Space
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
`define BUILD_DATE "180925"
|
||||
`define BUILD_TIME "181542"
|
||||
`define BUILD_DATE "190320"
|
||||
`define BUILD_TIME "193746"
|
||||
|
||||
@ -1,82 +0,0 @@
|
||||
|
||||
|
||||
module keyboard
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
input ps2_kbd_clk,
|
||||
input ps2_kbd_data,
|
||||
|
||||
output reg[7:0] joystick
|
||||
);
|
||||
|
||||
reg [11:0] shift_reg = 12'hFFF;
|
||||
wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
|
||||
wire [7:0] kcode = kdata[9:2];
|
||||
reg release_btn = 0;
|
||||
|
||||
reg [7:0] code;
|
||||
reg input_strobe = 0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
reg old_reset = 0;
|
||||
|
||||
old_reset <= reset;
|
||||
|
||||
if(~old_reset & reset)begin
|
||||
joystick <= 0;
|
||||
end
|
||||
|
||||
if(input_strobe) begin
|
||||
case(code)
|
||||
'h16: joystick[1] <= ~release_btn; // 1
|
||||
'h1E: joystick[2] <= ~release_btn; // 2
|
||||
|
||||
'h75: joystick[4] <= ~release_btn; // arrow up
|
||||
'h72: joystick[5] <= ~release_btn; // arrow down
|
||||
'h6B: joystick[6] <= ~release_btn; // arrow left
|
||||
'h74: joystick[7] <= ~release_btn; // arrow right
|
||||
|
||||
'h29: joystick[0] <= ~release_btn; // Space
|
||||
'h11: joystick[1] <= ~release_btn; // Left Alt
|
||||
'h0d: joystick[2] <= ~release_btn; // Tab
|
||||
'h76: joystick[3] <= ~release_btn; // Escape
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [3:0] prev_clk = 0;
|
||||
reg old_reset = 0;
|
||||
reg action = 0;
|
||||
|
||||
old_reset <= reset;
|
||||
input_strobe <= 0;
|
||||
|
||||
if(~old_reset & reset)begin
|
||||
prev_clk <= 0;
|
||||
shift_reg <= 12'hFFF;
|
||||
end else begin
|
||||
prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
|
||||
if(prev_clk == 1) begin
|
||||
if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
|
||||
shift_reg <= 12'hFFF;
|
||||
if (kcode == 8'he0) ;
|
||||
// Extended key code follows
|
||||
else if (kcode == 8'hf0)
|
||||
// Release code follows
|
||||
action <= 1;
|
||||
else begin
|
||||
// Cancel extended/release flags for next time
|
||||
action <= 0;
|
||||
release_btn <= action;
|
||||
code <= kcode;
|
||||
input_strobe <= 1;
|
||||
end
|
||||
end else begin
|
||||
shift_reg <= kdata;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@ -1,104 +0,0 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Line doubler - Dar - Feb 2014
|
||||
---------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity line_doubler is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
video_i : in std_logic_vector(3 downto 0);
|
||||
hsync_i : in std_logic;
|
||||
vsync_i : in std_logic;
|
||||
video_o : out std_logic_vector(3 downto 0);
|
||||
hsync_o : out std_logic;
|
||||
vsync_o : out std_logic
|
||||
);
|
||||
end line_doubler;
|
||||
|
||||
architecture struct of line_doubler is
|
||||
|
||||
signal hsync_i_reg : std_logic;
|
||||
signal vsync_i_reg : std_logic;
|
||||
signal hcnt_i : integer range 0 to 1023;
|
||||
signal vcnt_i : integer range 0 to 511;
|
||||
signal hcnt_o : integer range 0 to 511;
|
||||
|
||||
signal flip_flop : std_logic;
|
||||
signal blank : std_logic;
|
||||
|
||||
type ram_1024x8 is array(0 to 1023) of std_logic_vector(3 downto 0);
|
||||
signal ram1 : ram_1024x8;
|
||||
signal ram2 : ram_1024x8;
|
||||
signal video : std_logic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
|
||||
hsync_i_reg <= hsync_i;
|
||||
vsync_i_reg <= vsync_i;
|
||||
|
||||
if (vsync_i = '0' and vsync_i_reg = '1') then
|
||||
vcnt_i <= 0;
|
||||
else
|
||||
if (hsync_i = '0' and hsync_i_reg = '1') then
|
||||
vcnt_i <= vcnt_i + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if (hsync_i = '0' and hsync_i_reg = '1') then
|
||||
flip_flop <= not flip_flop;
|
||||
hcnt_i <= 0;
|
||||
else
|
||||
hcnt_i <= hcnt_i + 1;
|
||||
end if;
|
||||
|
||||
if (hsync_i = '0' and hsync_i_reg = '1') or hcnt_o = 319 then
|
||||
hcnt_o <= 0;
|
||||
else
|
||||
hcnt_o <= hcnt_o + 1;
|
||||
end if;
|
||||
|
||||
-- if hcnt_o = 0 then hsync_o <= '0';
|
||||
-- elsif hcnt_o = 4 then hsync_o <= '1';
|
||||
-- end if;
|
||||
|
||||
if hcnt_o = 319-2-4 then hsync_o <= '0';
|
||||
elsif hcnt_o = 319-2 then hsync_o <= '1';
|
||||
end if;
|
||||
|
||||
if hcnt_o = 54 then blank <= '0';
|
||||
elsif hcnt_o = 308 then blank <= '1';
|
||||
end if;
|
||||
|
||||
if vcnt_i = 0 then vsync_o <= '0';
|
||||
elsif vcnt_i = 4 then vsync_o <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if flip_flop = '0' then
|
||||
ram1(hcnt_i/2) <= video_i;
|
||||
video <= ram2(hcnt_o);
|
||||
else
|
||||
ram2(hcnt_i/2) <= video_i;
|
||||
video <= ram1(hcnt_o);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if blank = '0' then
|
||||
video_o <= video;
|
||||
else
|
||||
video_o <= (others => '0');
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@ -5,6 +5,7 @@
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2015-2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
@ -47,13 +48,16 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
// output reg [31:0] joystick_2,
|
||||
// output reg [31:0] joystick_3,
|
||||
// output reg [31:0] joystick_4,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
output scandoubler_disable,
|
||||
output scandoublerD,
|
||||
output ypbpr,
|
||||
|
||||
output reg [31:0] status,
|
||||
@ -61,13 +65,13 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
// SD config
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output img_mounted, // signaling that new image has been mounted
|
||||
output [1:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg [31:0] img_size, // size of image in bytes
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba,
|
||||
input sd_rd,
|
||||
input sd_wr,
|
||||
input [1:0] sd_rd,
|
||||
input [1:0] sd_wr,
|
||||
output reg sd_ack,
|
||||
output reg sd_ack_conf,
|
||||
|
||||
@ -83,186 +87,221 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
|
||||
// ARM -> FPGA download
|
||||
input ioctl_force_erase,
|
||||
input ioctl_ce,
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg ioctl_erasing = 0, // signal indicating an active erase
|
||||
output reg [7:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr = 0,
|
||||
output reg [24:0] ioctl_addr,
|
||||
output reg [7:0] ioctl_dout
|
||||
);
|
||||
|
||||
reg [7:0] b_data;
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [7:0] byte_cnt; // counts bytes
|
||||
reg [7:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
reg mount_strobe = 0;
|
||||
reg [1:0] mount_strobe = 0;
|
||||
assign img_mounted = mount_strobe;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoubler_disable = but_sw[4];
|
||||
assign scandoublerD = but_sw[4];
|
||||
assign ypbpr = but_sw[5];
|
||||
|
||||
wire [7:0] spi_dout = { sbuf, SPI_DI};
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
|
||||
wire drive_sel = sd_rd[1] | sd_wr[1];
|
||||
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
|
||||
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
|
||||
reg spi_do;
|
||||
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
|
||||
|
||||
// drive MISO only when transmitting core id
|
||||
always@(negedge SPI_SCK) begin
|
||||
if(!CONF_DATA0) begin
|
||||
// first byte returned is always core type, further bytes are
|
||||
// command dependent
|
||||
if(byte_cnt == 0) begin
|
||||
spi_do <= core_type[~bit_cnt];
|
||||
reg [7:0] spi_data_out;
|
||||
|
||||
end else begin
|
||||
case(cmd)
|
||||
// reading config string
|
||||
8'h14: begin
|
||||
// returning a byte from string
|
||||
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
|
||||
else spi_do <= 0;
|
||||
end
|
||||
// SPI transmitter
|
||||
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
|
||||
|
||||
// reading sd card status
|
||||
8'h16: begin
|
||||
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
|
||||
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
|
||||
else spi_do <= 0;
|
||||
end
|
||||
|
||||
// reading sd card write data
|
||||
8'h18:
|
||||
spi_do <= b_data[~bit_cnt];
|
||||
|
||||
default:
|
||||
spi_do <= 0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg b_wr2,b_wr3;
|
||||
always @(negedge clk_sys) begin
|
||||
b_wr3 <= b_wr2;
|
||||
sd_buff_wr <= b_wr3;
|
||||
end
|
||||
reg [7:0] spi_data_in;
|
||||
reg spi_data_ready = 0;
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [31:0] sd_lba_r;
|
||||
reg drive_sel_r;
|
||||
|
||||
if(CONF_DATA0) begin
|
||||
b_wr2 <= 0;
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
end else begin
|
||||
b_wr2 <= 0;
|
||||
|
||||
sbuf <= spi_dout[6:0];
|
||||
spi_data_out <= core_type;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
if(bit_cnt == 5) begin
|
||||
if (byte_cnt == 0) sd_buff_addr <= 0;
|
||||
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
|
||||
end
|
||||
sbuf <= {sbuf[5:0], SPI_DI};
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
spi_data_in <= {sbuf, SPI_DI};
|
||||
spi_data_ready <= ~spi_data_ready;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
|
||||
if(byte_cnt == 0) begin
|
||||
cmd <= spi_dout;
|
||||
|
||||
if(spi_dout == 8'h19) begin
|
||||
sd_ack_conf <= 1;
|
||||
sd_buff_addr <= 0;
|
||||
end
|
||||
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
|
||||
sd_ack <= 1;
|
||||
sd_buff_addr <= 0;
|
||||
end
|
||||
if(spi_dout == 8'h18) b_data <= sd_buff_din;
|
||||
|
||||
mount_strobe <= 0;
|
||||
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_dout;
|
||||
8'h02: joystick_0 <= spi_dout;
|
||||
8'h03: joystick_1 <= spi_dout;
|
||||
spi_data_out <= 0;
|
||||
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
|
||||
// reading config string
|
||||
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
|
||||
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
// reading sd card status
|
||||
8'h16: if(byte_cnt == 0) begin
|
||||
spi_data_out <= sd_cmd;
|
||||
sd_lba_r <= sd_lba;
|
||||
drive_sel_r <= drive_sel;
|
||||
end else if (byte_cnt == 1) begin
|
||||
spi_data_out <= drive_sel_r;
|
||||
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_dout;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_dout;
|
||||
b_wr2 <= 1;
|
||||
end
|
||||
// reading sd card write data
|
||||
8'h18: spi_data_out <= sd_buff_din;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
8'h18: b_data <= sd_buff_din;
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
|
||||
else if(byte_cnt == 2) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
|
||||
end else if(byte_cnt == 3) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
|
||||
end
|
||||
end
|
||||
// transfer to clk_sys domain
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_ss1, old_ss2;
|
||||
reg old_ready1, old_ready2;
|
||||
reg [2:0] b_wr;
|
||||
reg got_ps2 = 0;
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe <= 1;
|
||||
old_ss1 <= CONF_DATA0;
|
||||
old_ss2 <= old_ss1;
|
||||
old_ready1 <= spi_data_ready;
|
||||
old_ready2 <= old_ready1;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
|
||||
default: ;
|
||||
endcase
|
||||
if(old_ss2) begin
|
||||
got_ps2 <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
sd_buff_addr <= 0;
|
||||
if(got_ps2) begin
|
||||
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
if(old_ready2 ^ old_ready1) begin
|
||||
|
||||
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
|
||||
if(byte_cnt < 2) begin
|
||||
|
||||
if (cmd == 8'h19) sd_ack_conf <= 1;
|
||||
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
|
||||
mount_strobe <= 0;
|
||||
|
||||
if(cmd == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_data_in;
|
||||
8'h02: joystick_0 <= spi_data_in;
|
||||
8'h03: joystick_1 <= spi_data_in;
|
||||
// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
got_ps2 <= 1;
|
||||
case(byte_cnt)
|
||||
2: ps2_mouse[7:0] <= spi_data_in;
|
||||
3: ps2_mouse[15:8] <= spi_data_in;
|
||||
4: ps2_mouse[23:16] <= spi_data_in;
|
||||
endcase
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
got_ps2 <= 1;
|
||||
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_data_in;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_data_in;
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
|
||||
else if(byte_cnt == 3) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
|
||||
end else if(byte_cnt == 4) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
|
||||
end
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@ -417,6 +456,8 @@ localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
reg rdownload = 0;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
reg [6:0] sbuf;
|
||||
@ -426,15 +467,10 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
|
||||
if(SPI_SS2) cnt <= 0;
|
||||
else begin
|
||||
rclk <= 0;
|
||||
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
|
||||
|
||||
// increase target address after write
|
||||
if(rclk) addr <= addr + 1'd1;
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
@ -446,18 +482,15 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(SPI_DI) begin
|
||||
case(ioctl_index)
|
||||
0: addr <= 'h080000; // BOOT ROM
|
||||
'h01: addr <= 'h000100; // ROM file
|
||||
'h41: addr <= 'h000100; // COM file
|
||||
'h81: addr <= 'h000000; // C00 file
|
||||
'hC1: addr <= 'h010000; // EDD file
|
||||
default: addr <= 'h100000; // FDD file
|
||||
case(ioctl_index[4:0])
|
||||
1: addr <= 25'h200000; // TRD buffer at 2MB
|
||||
2: addr <= 25'h400000; // tape buffer at 4MB
|
||||
default: addr <= 25'h150000; // boot rom
|
||||
endcase
|
||||
ioctl_download <= 1;
|
||||
rdownload <= 1;
|
||||
end else begin
|
||||
addr_w <= addr;
|
||||
ioctl_download <= 0;
|
||||
rdownload <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
@ -465,7 +498,8 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
addr_w <= addr;
|
||||
data_w <= {sbuf, SPI_DI};
|
||||
rclk <= 1;
|
||||
addr <= addr + 1'd1;
|
||||
rclk <= ~rclk;
|
||||
end
|
||||
|
||||
// expose file (menu) index
|
||||
@ -473,60 +507,24 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
end
|
||||
end
|
||||
|
||||
reg [24:0] erase_mask;
|
||||
wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask;
|
||||
|
||||
// transfer to ioctl_clk domain.
|
||||
// ioctl_index is set before ioctl_download, so it's stable already
|
||||
always@(posedge clk_sys) begin
|
||||
reg rclkD, rclkD2;
|
||||
reg old_force = 0;
|
||||
reg [5:0] erase_clk_div;
|
||||
reg [24:0] end_addr;
|
||||
reg erase_trigger = 0;
|
||||
|
||||
rclkD <= rclk;
|
||||
rclkD2 <= rclkD;
|
||||
ioctl_wr <= 0;
|
||||
if(ioctl_ce) begin
|
||||
ioctl_download <= rdownload;
|
||||
|
||||
if(rclkD & ~rclkD2) begin
|
||||
ioctl_dout <= data_w;
|
||||
ioctl_addr <= addr_w;
|
||||
ioctl_wr <= 1;
|
||||
end
|
||||
rclkD <= rclk;
|
||||
rclkD2 <= rclkD;
|
||||
ioctl_wr <= 0;
|
||||
|
||||
if(ioctl_download) begin
|
||||
old_force <= 0;
|
||||
ioctl_erasing <= 0;
|
||||
erase_trigger <= (ioctl_index == 1);
|
||||
end else begin
|
||||
|
||||
old_force <= ioctl_force_erase;
|
||||
|
||||
// start erasing
|
||||
if(erase_trigger) begin
|
||||
erase_trigger <= 0;
|
||||
erase_mask <= 'hFFFF;
|
||||
end_addr <= 'h0100;
|
||||
erase_clk_div <= 1;
|
||||
ioctl_erasing <= 1;
|
||||
end else if((ioctl_force_erase & ~old_force)) begin
|
||||
erase_trigger <= 0;
|
||||
ioctl_addr <= 'h1FFFFFF;
|
||||
erase_mask <= 'h1FFFFFF;
|
||||
end_addr <= 'h0050000;
|
||||
erase_clk_div <= 1;
|
||||
ioctl_erasing <= 1;
|
||||
end else if(ioctl_erasing) begin
|
||||
erase_clk_div <= erase_clk_div + 1'd1;
|
||||
if(!erase_clk_div) begin
|
||||
if(next_erase == end_addr) ioctl_erasing <= 0;
|
||||
else begin
|
||||
ioctl_addr <= next_erase;
|
||||
ioctl_dout <= 0;
|
||||
ioctl_wr <= 1;
|
||||
end
|
||||
end
|
||||
if(rclkD != rclkD2) begin
|
||||
ioctl_dout <= data_w;
|
||||
ioctl_addr <= addr_w;
|
||||
ioctl_wr <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
@ -11,13 +11,15 @@ module osd (
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] R_in,
|
||||
input [5:0] G_in,
|
||||
input [5:0] B_in,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] R_out,
|
||||
output [5:0] G_out,
|
||||
@ -59,7 +61,7 @@ always@(posedge SPI_SCK, posedge SPI_SS3) begin
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
|
||||
|
||||
@ -91,7 +93,7 @@ reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
|
||||
|
||||
wire doublescan = (dsp_height>350);
|
||||
wire doublescan = (dsp_height>350);
|
||||
|
||||
reg ce_pix;
|
||||
always @(negedge clk_sys) begin
|
||||
@ -124,13 +126,13 @@ always @(posedge clk_sys) begin
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of HSync
|
||||
if(!hsD && hsD2) begin
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of HSync
|
||||
else if(hsD && !hsD2) begin
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_low <= h_cnt;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
@ -142,13 +144,13 @@ always @(posedge clk_sys) begin
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of VSync
|
||||
if(!vsD && vsD2) begin
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of VSync
|
||||
else if(vsD && !vsD2) begin
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
@ -160,17 +162,30 @@ wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
|
||||
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
|
||||
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
|
||||
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
|
||||
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
|
||||
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
|
||||
|
||||
wire osd_de = osd_enable &&
|
||||
wire osd_de = osd_enable &&
|
||||
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
|
||||
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
|
||||
|
||||
reg [7:0] osd_byte;
|
||||
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
|
||||
reg [10:0] osd_buffer_addr;
|
||||
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
|
||||
reg osd_pixel;
|
||||
|
||||
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
always @(posedge clk_sys) begin
|
||||
if(ce_pix) begin
|
||||
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
|
||||
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
|
||||
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
|
||||
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
|
||||
|
||||
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
|
||||
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
end
|
||||
end
|
||||
|
||||
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
|
||||
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
|
||||
|
||||
@ -19,18 +19,6 @@
|
||||
|
||||
// TODO: Delay vsync one line
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
@ -118,6 +106,18 @@ always @(*) begin
|
||||
endcase
|
||||
end
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
(
|
||||
|
||||
@ -14,17 +14,15 @@ port(
|
||||
hsync : out std_logic;
|
||||
vsync : out std_logic;
|
||||
csync : out std_logic;
|
||||
blank : out std_logic;
|
||||
|
||||
hblank : out std_logic;
|
||||
vblank : out std_logic;
|
||||
hcnt_o : out std_logic_vector(8 downto 0);
|
||||
vcnt_o : out std_logic_vector(8 downto 0)
|
||||
);
|
||||
end video_gen;
|
||||
|
||||
architecture struct of video_gen is
|
||||
signal hblank : std_logic;
|
||||
signal vblank : std_logic;
|
||||
signal vblank_r: std_logic;
|
||||
|
||||
signal hcnt : std_logic_vector(8 downto 0);
|
||||
signal vcnt : std_logic_vector(8 downto 0);
|
||||
|
||||
@ -38,7 +36,7 @@ hcnt_o <= hcnt;
|
||||
vcnt_o <= vcnt;
|
||||
|
||||
hsync <= hsync0;
|
||||
blank <= hblank or vblank_r;
|
||||
|
||||
|
||||
-- Compteur horizontal
|
||||
-- 1C0..1FF-000..0FF : 64+256 = 320 pixels
|
||||
@ -86,7 +84,7 @@ begin
|
||||
end if;
|
||||
|
||||
if hcnt = std_logic_vector(to_unsigned(448+16,9)) then
|
||||
vblank_r <= vblank;
|
||||
-- vblank_r <= vblank;
|
||||
end if;
|
||||
|
||||
|
||||
|
||||
@ -20,10 +20,10 @@
|
||||
|
||||
module video_mixer
|
||||
#(
|
||||
parameter LINE_LENGTH = 768,
|
||||
parameter HALF_DEPTH = 0,
|
||||
parameter LINE_LENGTH = 480,
|
||||
parameter HALF_DEPTH = 1,
|
||||
|
||||
parameter OSD_COLOR = 3'd7,
|
||||
parameter OSD_COLOR = 3'd4,
|
||||
parameter OSD_X_OFFSET = 10'd0,
|
||||
parameter OSD_Y_OFFSET = 10'd0
|
||||
)
|
||||
@ -50,7 +50,7 @@ module video_mixer
|
||||
input [1:0] scanlines,
|
||||
|
||||
// 0 = HVSync 31KHz, 1 = CSync 15KHz
|
||||
input scandoubler_disable,
|
||||
input scandoublerD,
|
||||
|
||||
// High quality 2x scaling
|
||||
input hq2x,
|
||||
@ -60,7 +60,7 @@ module video_mixer
|
||||
|
||||
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
|
||||
input ypbpr_full,
|
||||
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
@ -113,9 +113,9 @@ scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
|
||||
wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
|
||||
wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
|
||||
wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd);
|
||||
wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd);
|
||||
wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd);
|
||||
|
||||
generate
|
||||
if(HALF_DEPTH) begin
|
||||
@ -129,8 +129,8 @@ generate
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs = (scandoubler_disable ? HSync : hs_sd);
|
||||
wire vs = (scandoubler_disable ? VSync : vs_sd);
|
||||
wire hs = (scandoublerD ? HSync : hs_sd);
|
||||
wire vs = (scandoublerD ? VSync : vs_sd);
|
||||
|
||||
reg scanline = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
@ -182,6 +182,7 @@ osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
|
||||
.B_in(b_out),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.rotate(rotate),
|
||||
|
||||
.R_out(red),
|
||||
.G_out(green),
|
||||
@ -236,7 +237,7 @@ wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[1
|
||||
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
|
||||
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
|
||||
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
|
||||
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
|
||||
assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
|
||||
assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
|
||||
assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user