Some Work on SG1000

2026-03-30 19:05:00 +00:00 · 2018-11-08 10:26:28 +01:00
parent afc7fdcade
commit c2566132cc
14 changed files with 492 additions and 79 deletions
--- a/SG1000/Snapshot/sg1000.qar
+++ b/SG1000/Snapshot/sg1000.qar
--- a/SG1000/Snapshot/sg1000.rbf
+++ b/SG1000/Snapshot/sg1000.rbf
--- a/SG1000/rtl/RAM2K.qip
+++ b/SG1000/rtl/RAM2K.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "RAM2K.v"]
--- a/SG1000/rtl/RAM2K.v
+++ b/SG1000/rtl/RAM2K.v
@@ -0,0 +1,177 @@
+// megafunction wizard: %RAM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: RAM2K.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module RAM2K (
+	address,
+	clken,
+	clock,
+	data,
+	wren,
+	q);
+
+	input	[10:0]  address;
+	input	  clken;
+	input	  clock;
+	input	[7:0]  data;
+	input	  wren;
+	output	[7:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clken;
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.clocken0 (clken),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.clock_enable_input_a = "NORMAL",
+		altsyncram_component.clock_enable_output_a = "NORMAL",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 2048,
+		altsyncram_component.operation_mode = "SINGLE_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 11,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrData NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+// Retrieval info: PRIVATE: Clken NUMERIC "1"
+// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegData NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
--- a/SG1000/rtl/SG1000_MiST.sv
+++ b/SG1000/rtl/SG1000_MiST.sv
@@ -43,7 +43,7 @@ wire [1:0] r, g, b;
 wire hb, vb, hs, vs;
 wire blankn = ~(hb | vb);
 wire [5:0] audio;
-
+wire  [7:0] joystick_0, joystick_1;
 wire clk_8, clk_16, clk_64;

 pll pll (
@@ -70,6 +70,8 @@ user_io (
 	.switches(switches),
 	.ps2_kbd_clk(ps2_kbd_clk),
 	.ps2_kbd_data(ps2_kbd_data),
+	.joystick_0(joystick_0[5:0]),
+	.joystick_1(joystick_1[5:0]),
 	.ioctl_ce(1'b1),
 	.ioctl_wr(ioctl_wr),
 	.ioctl_index(ioctl_index),
@@ -113,9 +115,11 @@ sg1000_top sg1000_top (
 	.sys_clk(clk_8),
 	.clk_vdp(clk_16),
 	.pause(status[5]),
-	.Cart_In(Cart_In),
-	.Cart_Out(Cart_Out),
-	.Cart_Addr(Cart_Addr),
+	.ps2_kbd_clk(ps2_kbd_clk),
+	.ps2_kbd_data(ps2_kbd_data),
+	//.Cart_In(Cart_In),
+	//.Cart_Out(Cart_Out),
+	//.Cart_Addr(Cart_Addr),
 	.audio(audio),
 	.vblank(vb), 
 	.hblank(hb),
--- a/SG1000/rtl/TTL74_257.v
+++ b/SG1000/rtl/TTL74_257.v
@@ -0,0 +1,90 @@
+
+module TTL74_257(
+	GN,
+	SEL,
+	B4,
+	A4,
+	B3,
+	A3,
+	B2,
+	A2,
+	B1,
+	A1,
+	Y4,
+	Y3,
+	Y2,
+	Y1
+);
+
+
+input wire	GN;
+input wire	SEL;
+input wire	B4;
+input wire	A4;
+input wire	B3;
+input wire	A3;
+input wire	B2;
+input wire	A2;
+input wire	B1;
+input wire	A1;
+output wire	Y4;
+output wire	Y3;
+output wire	Y2;
+output wire	Y1;
+
+wire	SYNTHESIZED_WIRE_0;
+wire	SYNTHESIZED_WIRE_1;
+wire	SYNTHESIZED_WIRE_2;
+wire	SYNTHESIZED_WIRE_20;
+wire	SYNTHESIZED_WIRE_4;
+wire	SYNTHESIZED_WIRE_5;
+wire	SYNTHESIZED_WIRE_6;
+wire	SYNTHESIZED_WIRE_8;
+wire	SYNTHESIZED_WIRE_9;
+wire	SYNTHESIZED_WIRE_10;
+wire	SYNTHESIZED_WIRE_12;
+wire	SYNTHESIZED_WIRE_14;
+wire	SYNTHESIZED_WIRE_15;
+wire	SYNTHESIZED_WIRE_21;
+
+
+
+
+assign	SYNTHESIZED_WIRE_2 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
+
+assign	SYNTHESIZED_WIRE_1 = B1 & SEL;
+
+assign	Y1 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_2 : 1'bz;
+
+assign	SYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5;
+
+assign	Y2 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_6 : 1'bz;
+
+assign	SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9;
+
+assign	Y3 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_10 : 1'bz;
+
+assign	Y4 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_12 : 1'bz;
+
+assign	SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15;
+
+assign	SYNTHESIZED_WIRE_20 =  ~GN;
+
+assign	SYNTHESIZED_WIRE_21 =  ~SEL;
+
+assign	SYNTHESIZED_WIRE_0 = A1 & SYNTHESIZED_WIRE_21;
+
+assign	SYNTHESIZED_WIRE_4 = A2 & SYNTHESIZED_WIRE_21;
+
+assign	SYNTHESIZED_WIRE_8 = A3 & SYNTHESIZED_WIRE_21;
+
+assign	SYNTHESIZED_WIRE_14 = A4 & SYNTHESIZED_WIRE_21;
+
+assign	SYNTHESIZED_WIRE_5 = B2 & SEL;
+
+assign	SYNTHESIZED_WIRE_9 = B3 & SEL;
+
+assign	SYNTHESIZED_WIRE_15 = B4 & SEL;
+
+
+endmodule
--- a/SG1000/rtl/build_id.tcl
+++ b/SG1000/rtl/build_id.tcl
@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
 	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]

 	# Create a Verilog file for output
-	set outputFileName "sys/build_id.v"
+	set outputFileName "rtl/build_id.v"
 	set outputFile [open $outputFileName "w"]

 	# Output the Verilog source
--- a/SG1000/rtl/build_id.v
+++ b/SG1000/rtl/build_id.v
@@ -1,2 +1,2 @@
-`define BUILD_DATE "180816"
-`define BUILD_TIME "200421"
+`define BUILD_DATE "181108"
+`define BUILD_TIME "102032"
--- a/SG1000/rtl/cart.sv
+++ b/SG1000/rtl/cart.sv
@@ -0,0 +1,32 @@
+module cart(
+input					clk_cpu,
+	input 			DSRAM_n,
+	input 			EXM1_n,
+	input 			RD_n,
+	input 			WR_n,
+	input				RFSH_n,
+	input				MREQ_n,
+	output			CON,
+	input 			EXM2_n,
+	input 			M1_n,
+	input   [14:0]	Addr,
+	output	[7:0]	Cart_Out,
+	output	[7:0]	Cart_Ram_Out,
+	input 	[7:0]	Cart_In
+);
+
+wire [5:0]bank0;
+wire [5:0]bank1;
+wire [5:0]bank2;
+
+always @(clk_cpu) begin
+	if (~WR_n & Addr[14:2] == "1111111111111")
+		case (Addr[1:0])
+			2'b01 : bank0 = Cart_In[5:0];
+			2'b10 : bank1 = Cart_In[5:0];
+			2'b11 : bank2 = Cart_In[5:0];
+			default : ;
+		endcase;
+end
+
+endmodule 
--- a/SG1000/rtl/greybox_tmp/cbx_args.txt
+++ b/SG1000/rtl/greybox_tmp/cbx_args.txt
@@ -0,0 +1,17 @@
+CLOCK_ENABLE_INPUT_A=NORMAL
+CLOCK_ENABLE_OUTPUT_A=NORMAL
+INTENDED_DEVICE_FAMILY="Cyclone III"
+NUMWORDS_A=2048
+OPERATION_MODE=SINGLE_PORT
+OUTDATA_ACLR_A=NONE
+OUTDATA_REG_A=CLOCK0
+POWER_UP_UNINITIALIZED=FALSE
+READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
+WIDTHAD_A=11
+WIDTH_A=8
+WIDTH_BYTEENA_A=1
+DEVICE_FAMILY="Cyclone III"
+address_a
+clock0
+clocken0
+q_a
--- a/SG1000/rtl/keyboard.sv
+++ b/SG1000/rtl/keyboard.sv
@@ -0,0 +1,15 @@
+module keyboard(
+	input [2:0]	Addr,
+	input 		JOY_SEL_n,
+	input 		KB_SEL_n,
+	output 		Kb_Out,
+	input 		RD_n,
+	input 		WR_n,
+	input 		CON,//not sure
+	input  		IORQ_n,
+	input  		ps2_kbd_clk,
+	input  		ps2_kbd_data
+);
+
+
+endmodule 
--- a/SG1000/rtl/sg1000_top.sv
+++ b/SG1000/rtl/sg1000_top.sv
@@ -3,9 +3,11 @@ input				RESET_n,
 input				sys_clk,//8
 input				clk_vdp,//16
 input				pause,
-input 	[7:0]	Cart_Out,
-output 	[7:0]	Cart_In,
-output  [14:0]	Cart_Addr,
+input  			ps2_kbd_clk,
+input  			ps2_kbd_data,
+//input 	[7:0]	Cart_Out,
+//output 	[7:0]	Cart_In,
+//output  [14:0]	Cart_Addr,
 output 	[5:0] audio,
 output 			vblank, 
 output 			hblank,
@@ -14,18 +16,25 @@ output 			vga_vs,
 output 	[1:0]	vga_r,
 output 	[1:0]	vga_g,
 output 	[1:0]	vga_b,
-input 	[7:0]	Joy_A,
-input 	[7:0]	Joy_B
+input 	[5:0]	Joy_A,
+input 	[5:0]	Joy_B
 );

-wire WAIT_n, MREQ_n, M1_n, IORQ_n, RFSH_n, INT_n;
-wire NMI_n = pause;
-wire RD_n, WR_n;
-wire [7:0]D_in, D_out, RAM_D_out;
-wire [7:0]Cart_ram_Out = 8'h00000000; 
-wire [7:0]Joy_Out = 8'h00000000; 
-wire [7:0]Kb_Out = 8'h00000000;
+wire DSRAM_n = CS_WRAM_n;
+wire CS_WRAM_n = (~MREQ_n) & (Addr[15:14] == "11") ? 1'b0 : 1'b1;
+wire M1_n;
+wire MREQ_n;
+wire IORQ_n;
+wire RD_n;
+wire WR_n;
+wire RFSH_n;
+wire WAIT_n; 
+wire INT_n;
+wire NMI_n = pause;//todo
 wire [15:0]Addr;
+wire [7:0]D_in; 
+wire [7:0]D_out;
+


 T80se #(
@@ -36,10 +45,9 @@ CPU (
 	.RESET_n(RESET_n),
 	.CLK_n(sys_clk),
 	.CLKEN(1'b1),
-	.WAIT_n(1'b1),
 	.INT_n(INT_n),
 	.NMI_n(NMI_n),
-	.BUSRQ_n(),//?
+	.BUSRQ_n(1'b1),
 	.M1_n(M1_n),
 	.MREQ_n(MREQ_n),
 	.IORQ_n(IORQ_n),
@@ -47,12 +55,13 @@ CPU (
 	.WR_n(WR_n),
 	.RFSH_n(RFSH_n),
 	.HALT_n(WAIT_n),
-	.BUSAK_n(),
 	.A(Addr),
 	.DI(D_in),
 	.DO(D_out)
 	);
 	
+wire	[7:0]RAM_D_out;
+/*
 spram #(
 	.widthad_a(11),//2k
 	.width_a(8))
@@ -62,26 +71,22 @@ MRAM (
 	.data(D_out),
 	.wren(~WR_n),
 	.q(RAM_D_out)
+	);*/
+	
+RAM2K RAM2K(
+	.address(Addr[10:0]),
+	.clock(sys_clk),
+	.clken(~CS_WRAM_n),
+	.data(D_out),
+	.wren(~WR_n),
+	.q(RAM_D_out)
 	);
 	
-assign Cart_Addr = Addr[14:0];	
-/*wire 	[7:0]	Cart_Out, Cart_In;
-wire [14:0] Cart_Addr = Addr[14:0];	
-
-sprom #(
-	.init_file("roms/32.hex"),
-	.widthad_a(15),
-	.width_a(8))
-CART (
-	.address(Cart_Addr),
-	.clock(sys_clk),
-	.q(Cart_Out)
-	);	*/
-
+wire CS_PSG_n = (~IORQ_n) & (Addr[7:6] == "01") ? 1'b0 : 1'b1;
 psg PSG (
 	.clk(sys_clk),
 	.WR_n(WR_n),
-	.D_in((CS_PSG_n == 1'b0) ? D_out : 8'b00000000),
+	.D_in(D_out),
 	.outputs(audio)
 	);
 	
@@ -89,6 +94,8 @@ wire [7:0]vdp_D_out;
 wire [8:0]x;
 wire [7:0]y;
 wire [5:0] color;
+wire VDP_RD_n = (~IORQ_n & Addr[7:6] == "10") | RD_n ? 1'b0 : 1'b1;
+wire VDP_WR_n = (~IORQ_n & Addr[7:6] == "10") | WR_n ? 1'b0 : 1'b1;

 vdp vdp (
 	.cpu_clk(sys_clk),
@@ -119,29 +126,91 @@ vga_video vga_video (
 	.green(vga_g),
 	.blue(vga_b)
 	);
-
-
 	
-wire CS_WRAM_n = (~MREQ_n & Addr[15:14] == "11") ? 1'b0 : 1'b1;
+wire [7:0]Joy_Out;
+wire JOY_SEL_n = (~IORQ_n & Addr[7:6] == "11") | RD_n ? 1'b0 : 1'b1;
+wire CON;
+TTL74_257 IC18(
+	.GN(JOY_SEL_n),
+	.SEL(Addr[0]),
+	.B4(Joy_B[5]),
+	.A4(Joy_A[2]),
+	.B3(Joy_B[4]),
+	.A3(Joy_A[3]),
+	.B2(Joy_B[3]),
+	.A2(Joy_A[5]),
+	.B1(Joy_B[2]),
+	.A1(Joy_A[4]),
+	.Y4(Joy_Out[3]),
+	.Y3(Joy_Out[2]),
+	.Y2(Joy_Out[1]),
+	.Y1(Joy_Out[0])
+);
+	
+TTL74_257 IC21(
+	.GN(JOY_SEL_n),
+	.SEL(Addr[0]),
+	.B4(),
+	.A4(Joy_B[1]),
+	.B3(),
+	.A3(Joy_B[0]),
+	.B2(),
+	.A2(Joy_A[0]),
+	.B1(CON),
+	.A1(Joy_A[1]),
+	.Y4(Joy_Out[7]),
+	.Y3(Joy_Out[6]),
+	.Y2(Joy_Out[5]),
+	.Y1(Joy_Out[4])
+);
+
+wire KB_SEL_n = (~IORQ_n & Addr[7:6] == "11") ? 1'b0 : 1'b1;
+wire [7:0]Kb_Out;
+
+keyboard keyboard(
+	.Addr(Addr[2:0]),
+	.JOY_SEL_n(JOY_SEL_n),
+	.KB_SEL_n(KB_SEL_n),
+	.Kb_Out(Kb_Out),
+	.RD_n(RD_n),
+	.WR_n(WR_n),
+	.CON(CON),
+	.IORQ_n(IORQ_n),
+	.ps2_kbd_clk(ps2_kbd_clk),
+	.ps2_kbd_data(ps2_kbd_data)
+);
+
 wire EXM1_n = (~MREQ_n & Addr[15:14] == "10") ? 1'b0 : 1'b1;
 wire EXM2_n = (~MREQ_n | Addr[15]) ? 1'b0 : 1'b1;
-wire CS_PSG_n = (~IORQ_n & Addr[7:6] == "01") ? 1'b0 : 1'b1;
+wire [7:0]Cart_Out; 

-wire VDP_RD_n = (~IORQ_n & Addr[7:6] == "10") | RD_n ? 1'b0 : 1'b1;
-wire VDP_WR_n = (~IORQ_n & Addr[7:6] == "10") | WR_n ? 1'b0 : 1'b1;
-wire JOY_SEL_n = (~IORQ_n & Addr[7:6] == "11") | RD_n ? 1'b0 : 1'b1;
-wire KB_SEL_n = (~IORQ_n & Addr[7:6] == "11") ? 1'b0 : 1'b1;
+cart cart(
+	.DSRAM_n(DSRAM_n),
+	.EXM1_n(EXM1_n),
+	.RD_n(RD_n),
+	.WR_n(WR_n),
+	.RFSH_n(RFSH_n),
+	.MREQ_n(MREQ_n),
+	.CON(CON),
+	.EXM2_n(EXM2_n),
+	.M1_n,
+	.Addr(Addr[14:0]),
+	.Cart_Out(Cart_Out),
+	.Cart_Ram_Out(Cart_Ram_Out),
+	.Cart_In(D_out)
+);

 always @(sys_clk) begin

-		D_in <= 	(CS_WRAM_n == 1'b0) ? RAM_D_out :
-					(VDP_RD_n == 1'b0) ? vdp_D_out  :
-					(EXM1_n == 1'b0) ? Cart_Out  :
-					(EXM2_n == 1'b0) ? Cart_ram_Out  :
-					(JOY_SEL_n == 1'b0) ? Joy_Out  :
-					(KB_SEL_n == 1'b0) ? Kb_Out  :
-					8'b00000000;	
+		D_in <= 	~CS_WRAM_n ? RAM_D_out :
+					~VDP_RD_n ? vdp_D_out  :
+					~EXM1_n ? Cart_Out  :
+					~EXM2_n ? Cart_Ram_Out  :
+					~JOY_SEL_n ? Joy_Out  :
+					~KB_SEL_n ? Kb_Out  :
+					1'hz;	
 end
+
 endmodule 


--- a/SG1000/sg1000.qsf
+++ b/SG1000/sg1000.qsf
@@ -43,33 +43,8 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:09  SEPTEMBER 21, 2018"
 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprites.vhd
-set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprite_shifter.vhd
-set_global_assignment -name VHDL_FILE rtl/vdp/vdp_main.vhd
-set_global_assignment -name VHDL_FILE rtl/vdp/vdp_cram.vhd
-set_global_assignment -name VHDL_FILE rtl/vdp/vdp_background.vhd
-set_global_assignment -name VHDL_FILE rtl/vdp/vdp.vhd
-set_global_assignment -name VHDL_FILE rtl/psg/psg_tone.vhd
-set_global_assignment -name VHDL_FILE rtl/psg/psg_noise.vhd
-set_global_assignment -name VHDL_FILE rtl/psg/psg.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/sg1000_top.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/SG1000_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/vga_video.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+

 # Classic Timing Assignments
 # ==========================
@@ -160,8 +135,39 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sg1000_top.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SG1000_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/vga_video.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprites.vhd
+set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprite_shifter.vhd
+set_global_assignment -name VHDL_FILE rtl/vdp/vdp_main.vhd
+set_global_assignment -name VHDL_FILE rtl/vdp/vdp_cram.vhd
+set_global_assignment -name VHDL_FILE rtl/vdp/vdp_background.vhd
+set_global_assignment -name VHDL_FILE rtl/vdp/vdp.vhd
+set_global_assignment -name VHDL_FILE rtl/psg/psg_tone.vhd
+set_global_assignment -name VHDL_FILE rtl/psg/psg_noise.vhd
+set_global_assignment -name VHDL_FILE rtl/psg/psg.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80se.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd
+set_global_assignment -name VERILOG_FILE rtl/TTL74_257.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cart.sv
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name QIP_FILE rtl/RAM2K.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/SG1000/sg1000.qws
+++ b/SG1000/sg1000.qws