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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-02-08 09:01:24 +00:00

Donkey Kong: add Donkey Kong 3 (bootleg on DKJr HW)

This commit is contained in:
Gyorgy Szombathelyi
2021-01-01 19:09:46 +01:00
parent 3a1c0af5dd
commit c2807b3323
9 changed files with 120 additions and 40 deletions

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@@ -0,0 +1,45 @@
<misterromdescription>
<name>Donkey Kong 3 (bootleg on DKJr HW)</name>
<mameversion>0217</mameversion>
<setname>dkong3b</setname>
<mratimestamp>201912300000</mratimestamp>
<year>1982</year>
<manufacturer>Nintendo of America</manufacturer>
<category>Maze / Monkeys</category>
<category>Platform</category>
<category>Platform / Mario Bros.</category>
<rbf>dkong</rbf>
<buttons names="Jump,Start 1P,Start 2P,Coin" default="A,Start,Select,R" />
<rom index="1"><part>03</part></rom>
<rom index="0" zip="dkong3.zip" md5="403f810061c5eda8651b5284af4b92ce" type="merged">
<!-- Main CPU 32k-->
<part crc="dea28158" name="dkong3b/5b.bin"/>
<part crc="6fb5faf6" name="dkong3b/5c-2.bin"/>
<part crc="d042b6a8" name="dkong3b/5e-2.bin"/>
<part crc="d042b6a8" name="dkong3b/5c-1.bin"/>
<part crc="d042b6a8" name="dkong3b/5e-1.bin"/>
<!-- GFX1 8k-->
<part crc="4ef64ba5" name="dkong3b/3p.bin"/>
<part crc="8d51aca9" name="dkong3b/3n.bin"/>
<!-- GFX2 16k-->
<part crc="dc7f4164" name="dk3v.7c"/>
<part crc="dc7f4164" name="dk3v.7d"/>
<part crc="dc7f4164" name="dk3v.7e"/>
<part crc="dc7f4164" name="dk3v.7f"/>
<!-- Sound CPU 4k-->
<part crc="715da5f8" name="dkong3b/3h.bin"/>
<!-- LUTs -->
<part crc="47ba0042" name="dkc1-c.1c"/>
<part crc="463dc7ad" name="dkc1-c.1d"/>
<part crc="dbf185bf" name="dkc1-v.2n"/>
<part repeat="2816">00</part>
</rom>
</misterromdescription>

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@@ -20,7 +20,7 @@
</switches>
<rom index="1"><part>01</part></rom>
<rom index="0" zip="dkongjr.zip" md5="bb9b77f52d45312bcf08409c76b1b8db" type="merged|nonmerged">
<rom index="0" zip="dkongjr.zip" md5="8ccadf69374bfc47254dfe8e5d4d8f7e" type="merged|nonmerged">
<!-- Main CPU 32k-->
<part crc="dea28158" name="djr1-c_5b_f-2.5b"/>
<part crc="6fb5faf6" name="djr1-c_5c_f-2.5c"/>
@@ -46,9 +46,11 @@
<!-- LUTs -->
<part crc="463dc7ad" name="djr1-c-2e.2e"/>
<part crc="463dc7ad" name="djr1-c-2e.2e"/>
<part crc="47ba0042" name="djr1-c-2f.2f"/>
<part crc="47ba0042" name="djr1-c-2f.2f"/>
<part crc="dbf185bf" name="djr1-v-2n.2n"/>
<part repeat="3328">00</part>
<part repeat="2816">00</part>
<!-- WAVs -->
<part>

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@@ -12,9 +12,10 @@
<switches default="80" base="8">
<dip bits="0,1" name="Lives" ids="3,4,5,6"/>
<dip bits="2,3" name="Bonus Life" ids="7K,10K,15K,20K"/>
<dip bits="4,6" name="Coins" ids="1C1P,2C1P,1C1P,3C1P,1C1P,4C1P,1C1P,5C1P,1C1P"/>
<dip bits="7" name="Cabinet" ids="Cocktail,Upright"/>
</switches>
<rom index="0" zip="dkong.zip" md5="ac7807bf1c69c3720888212143af10af">
</switches>
<rom index="0" zip="dkong.zip" md5="2b33a8e64b3ac1d361cd6d06cabc4f7c">
<!-- Main CPU 32k -->
<part crc="ba70b88b" name="c_5et_g.bin"/>
<part crc="5ec461ec" name="c_5ct_g.bin"/>
@@ -47,9 +48,11 @@
<!-- LUTs 3x256 -->
<part crc="e273ede5" name="c-2k.bpr"/>
<part crc="e273ede5" name="c-2k.bpr"/>
<part crc="d6412358" name="c-2j.bpr"/>
<part crc="d6412358" name="c-2j.bpr"/>
<part crc="b869b8f5" name="v-5e.bpr"/>
<part repeat="3328">00</part>
<part repeat="2816">00</part>
<!-- WAWs -->
<part>

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@@ -139,9 +139,7 @@ wire [7:0] audio;
wire hs_n, vs_n;
wire hb, vb;
wire blankn = ~vb;//~(hb | vb);
wire [2:0] r, g;
wire [1:0] b;
wire [3:0] r, g, b;
dkong_top dkong(
.I_CLK_24576M(clock_24),
@@ -161,6 +159,7 @@ dkong_top dkong(
.I_C1(~m_coin1),
.I_DIP_SW(status[15:8]),
.I_DKJR(core_mod[0]),
.I_DK3B(core_mod[1]),
.O_SOUND_DAT(audio),
.O_VGA_R(r),
.O_VGA_G(g),
@@ -181,14 +180,14 @@ dkong_top dkong(
.WAV_ROM_DO(wav_rom_a[0] ? wav_rom_do[15:8] : wav_rom_do[7:0])
);
mist_video #(.COLOR_DEPTH(3),.SD_HCNT_WIDTH(10)) mist_video(
mist_video #(.COLOR_DEPTH(4),.SD_HCNT_WIDTH(10)) mist_video(
.clk_sys(clock_24),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : 0),
.G(blankn ? g : 0),
.B(blankn ? {b, 1'b1} : 0),
.B(blankn ? b : 0),
.HSync(hs_n),
.VSync(vs_n),
.VGA_R(VGA_R),

View File

@@ -24,6 +24,7 @@ I_CLK_EN_P,
I_CLK_EN_N,
I_RESET_n,
I_DKJR,
I_DK3B,
I_AB,
I_DB,
I_MREQ_n,
@@ -39,6 +40,7 @@ O_ROM_CS_n,
O_RAM1_CS_n,
O_RAM2_CS_n,
O_RAM3_CS_n,
O_RAMDK3B_CS_n,
O_DMA_CS_n,
O_6A_G_n,
O_OBJ_RQ_n,
@@ -62,6 +64,7 @@ input I_CLK_EN_P; // H_CNT[1] 3.072MHz
input I_CLK_EN_N;
input I_RESET_n;
input I_DKJR;
input I_DK3B;
input [15:0]I_AB;
input [3:0]I_DB;
input I_MREQ_n;
@@ -75,6 +78,7 @@ output O_ROM_CS_n; // 0000 H - 3FFF H (5E,5C,5B,5A)
output O_RAM1_CS_n; // 6000 H - 63FF H (3C,4C)
output O_RAM2_CS_n; // 6400 H - 67FF H (3B,4B)
output O_RAM3_CS_n; // 6800 H - 6BFF H (3A,4A)
output O_RAMDK3B_CS_n; // 6C00 H - 6FFF H (DK3B only)
output O_DMA_CS_n; // 7800 H - 783F H (DMA)
output O_6A_G_n; // 7000 H - 77FF H => Active
output O_OBJ_RQ_n; // 7000 H - 73FF H
@@ -148,7 +152,7 @@ logic_74xx138 U_4D(
);
assign O_ROM_CS_n = I_DKJR ? &W_4D_Q[5:0] : &W_4D_Q[3:0];
assign O_ROM_CS_n = I_DKJR ? (&W_4D_Q[5:0] & (!I_DK3B | !(I_AB[15:12] == 4'h9 | I_AB[15:12] == 4'hD))) : &W_4D_Q[3:0];
// ADDR DEC 7000H - 7FFFH
@@ -217,6 +221,7 @@ logic_74xx138 U_2D(
assign O_RAM1_CS_n = W_2D_Q[0];
assign O_RAM2_CS_n = W_2D_Q[1];
assign O_RAM3_CS_n = W_2D_Q[2];
assign O_RAMDK3B_CS_n = !I_DK3B | W_2D_Q[3];
// ADDR DEC 7C00H - 7FFFH (R)
logic_74xx138 U_1B(

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@@ -17,14 +17,16 @@
module dkong_col_pal(
input CLK_24M,
input CLK_6M_EN,
input I_DK3B,
input I_PALBNK,
input [5:0]I_VRAM_D,
input [5:0]I_OBJ_D,
input I_CMPBLKn,
input I_5H_Q6,
input I_5H_Q7,
output [2:0]O_R,
output [2:0]O_G,
output [1:0]O_B,
output [3:0]O_R,
output [3:0]O_G,
output [3:0]O_B,
input [15:0] DL_ADDR,
input DL_WR,
@@ -47,7 +49,7 @@ begin
end
//------- PARTS 2EF ------------------------------------
wire [3:0]W_2E_DO,W_2F_DO;
wire [7:0]W_2E_DO,W_2F_DO;
/*
col1 rom2j(
.clk(CLK_24M),
@@ -55,15 +57,15 @@ col1 rom2j(
.data(W_2F_DO)
);
*/
dpram #(8,4) col1 (
dpram #(9,8) col1 (
.clock_a(CLK_24M),
.address_a(W_1EF_Q[9:2]),
.q_a(W_2F_DO),
.clock_b(CLK_24M),
.address_b(DL_ADDR[7:0]),
.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF1),
.data_b(DL_DATA[3:0])
.wren_b(DL_WR && DL_ADDR[15:9] == {4'hF, 3'b001}),
.data_b(DL_DATA)
);
/*
col2 rom2k(
@@ -72,17 +74,20 @@ col2 rom2k(
.data(W_2E_DO)
);
*/
dpram #(8,4) col2 (
dpram #(9,8) col2 (
.clock_a(CLK_24M),
.address_a(W_1EF_Q[9:2]),
.q_a(W_2E_DO),
.clock_b(CLK_24M),
.address_b(DL_ADDR[7:0]),
.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF0),
.data_b(DL_DATA[3:0])
.wren_b(DL_WR && DL_ADDR[15:9] == {4'hF, 3'b000}),
.data_b(DL_DATA)
);
assign {O_R, O_G, O_B} = {~W_2F_DO, ~W_2E_DO};
//assign {O_R, O_G, O_B} = I_DK3B ? {W_2F_DO, W_2E_DO} : ~{W_2F_DO[3:1], W_2F_DO[3], ~W_2E_DO};
assign O_R = I_DK3B ? W_2F_DO[7:4] : ~{W_2F_DO[3:1], W_2F_DO[3]};
assign O_G = I_DK3B ? W_2F_DO[3:0] : ~{W_2F_DO[0], W_2E_DO[3:2], W_2F_DO[0]};
assign O_B = I_DK3B ? W_2E_DO[3:0] : ~{W_2E_DO[1:0], W_2E_DO[1:0]};
endmodule

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@@ -310,7 +310,7 @@ begin
end
wire [10:0]W_ROM_OBJ_AB = {W_6H_Q[6:0],W_8H_Q[3:0]^{W_6H_Q[7],W_6H_Q[7],W_6H_Q[7],W_6H_Q[7]}};
wire [11:0]W_ROM_OBJ_AB = {W_6J_Q[6],W_6H_Q[6:0],W_8H_Q[3:0]^{W_6H_Q[7],W_6H_Q[7],W_6H_Q[7],W_6H_Q[7]}};
wire [7:0]W_OBJ_DO_7C,W_OBJ_DO_7D,W_OBJ_DO_7E,W_OBJ_DO_7F;
@@ -321,14 +321,14 @@ obj1 obj1 (
.data(W_OBJ_DO_7C)
);
*/
dpram #(11,8) obj1 (
dpram #(12,8) obj1 (
.clock_a(CLK_24M),
.address_a(W_ROM_OBJ_AB),
.q_a(W_OBJ_DO_7C),
.clock_b(CLK_24M),
.address_b(DL_ADDR[10:0]),
.wren_b(DL_WR && DL_ADDR[15:11] == {4'hA, 1'b0}),
.address_b(DL_ADDR[11:0]),
.wren_b(DL_WR && DL_ADDR[15:12] == 4'hA),
.data_b(DL_DATA)
);
/*
@@ -338,14 +338,14 @@ obj2 obj2 (
.data(W_OBJ_DO_7D)
);
*/
dpram #(11,8) obj2 (
dpram #(12,8) obj2 (
.clock_a(CLK_24M),
.address_a(W_ROM_OBJ_AB),
.q_a(W_OBJ_DO_7D),
.clock_b(CLK_24M),
.address_b(DL_ADDR[10:0]),
.wren_b(DL_WR && DL_ADDR[15:11] == {4'hB, 1'b0}),
.address_b(DL_ADDR[11:0]),
.wren_b(DL_WR && DL_ADDR[15:12] == 4'hB),
.data_b(DL_DATA)
);
/*
@@ -355,14 +355,14 @@ obj3 obj3 (
.data(W_OBJ_DO_7E)
);
*/
dpram #(11,8) obj3 (
dpram #(12,8) obj3 (
.clock_a(CLK_24M),
.address_a(W_ROM_OBJ_AB),
.q_a(W_OBJ_DO_7E),
.clock_b(CLK_24M),
.address_b(DL_ADDR[10:0]),
.wren_b(DL_WR && DL_ADDR[15:11] == {4'hC, 1'b0}),
.address_b(DL_ADDR[11:0]),
.wren_b(DL_WR && DL_ADDR[15:12] == 4'hC),
.data_b(DL_DATA)
);
/*
@@ -372,14 +372,14 @@ obj4 obj4 (
.data(W_OBJ_DO_7F)
);
*/
dpram #(11,8) obj4 (
dpram #(12,8) obj4 (
.clock_a(CLK_24M),
.address_a(W_ROM_OBJ_AB),
.q_a(W_OBJ_DO_7F),
.clock_b(CLK_24M),
.address_b(DL_ADDR[10:0]),
.wren_b(DL_WR && DL_ADDR[15:11] == {4'hD, 1'b0}),
.address_b(DL_ADDR[11:0]),
.wren_b(DL_WR && DL_ADDR[15:12] == 4'hD),
.data_b(DL_DATA)
);

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@@ -36,11 +36,12 @@ module dkong_top
input [7:0] I_DIP_SW,
input I_DKJR,
input I_DK3B,
// VGA (VIDEO) IF
output [2:0]O_VGA_R,
output [2:0]O_VGA_G,
output [1:0]O_VGA_B,
output [3:0]O_VGA_R,
output [3:0]O_VGA_G,
output [3:0]O_VGA_B,
output O_H_BLANK,
output O_V_BLANK,
output O_VGA_H_SYNCn,
@@ -83,6 +84,7 @@ wire W_ROM_CSn;
wire W_RAM1_CSn;
wire W_RAM2_CSn;
wire W_RAM3_CSn;
wire W_RAMDK3B_CSn;
//wire W_6A_Gn;
wire W_OBJ_RQn;
wire W_OBJ_RDn;
@@ -103,6 +105,7 @@ wire [4:0]W_3D_Q;
wire [7:0]W_RAM1_DO;
wire [7:0]W_RAM2_DO;
wire [7:0]W_RAM3_DO;
wire [7:0]W_RAMDK3B_DO;
// ROM DATA
wire [7:0]W_ROM_DO;
@@ -156,7 +159,7 @@ wire W_CPU_CLK_EN_N = W_H_CNT[1:0] == 2'b11;
.DO(ZDI)
);
//========= CPU DATA BUS[7:0] ==============================================
wire [7:0]WO_D = W_SW_DO | W_RAM1_DO |W_RAM2_DO |W_RAM3_DO | W_ROM_DO | W_VRAM_DB ;
wire [7:0]WO_D = W_SW_DO | W_RAM1_DO |W_RAM2_DO |W_RAM3_DO |W_RAMDK3B_DO | W_ROM_DO | W_VRAM_DB ;
assign ZDO = WO_D;
wire [11:0]OBJ_ROM_A;
@@ -184,6 +187,11 @@ always @(*) begin
6'h07: MAIN_CPU_A = {5'h03,W_CPU_A[10:0]}; // 0x3800-0x3FFF -> 0x1800-0x1FFF in ROM file
6'h09: MAIN_CPU_A = {5'h05,W_CPU_A[10:0]}; // 0x4800-0x4FFF -> 0x2800-0x2FFF in ROM file
6'h0B: MAIN_CPU_A = {5'h07,W_CPU_A[10:0]}; // 0x5800-0x5FFF -> 0x3800-0x3FFF in ROM file
// dkong3b
6'h12: MAIN_CPU_A = {5'h0C,W_CPU_A[10:0]}; // 0x9000-0x97FF -> 0x6000-0x6FFF in ROM file
6'h13: MAIN_CPU_A = {5'h0D,W_CPU_A[10:0]}; // 0x9800-0x9FFF -> 0x6000-0x6FFF in ROM file
6'h1A: MAIN_CPU_A = {5'h0E,W_CPU_A[10:0]}; // 0xD000-0xD7FF -> 0x7000-0x7FFF in ROM file
6'h1B: MAIN_CPU_A = {5'h0F,W_CPU_A[10:0]}; // 0xD800-0xDFFF -> 0x7000-0x7FFF in ROM file
default: MAIN_CPU_A = W_CPU_A[15:0];
endcase
end
@@ -211,6 +219,16 @@ ram_1024_8 U_3B4B
.O_D(W_RAM2_DO)
);
ram_1024_8 U_DK3BRAM
(
.I_CLK(I_CLK_24576M),
.I_ADDR(W_CPU_A[9:0]),
.I_D(WI_D),
.I_CE(~W_RAMDK3B_CSn),
.I_WE(~W_CPU_WRn),
.O_D(W_RAMDK3B_DO)
);
//=============== Sprite DMA ======================
wire [9:0]W_OBJ_AB = {W_2PSL, W_H_CNT[8:0]};
@@ -293,6 +311,7 @@ dkong_adec adec
.I_CLK_EN_N(W_CPU_CLK_EN_N),
.I_RESET_n(W_RESETn),
.I_DKJR(I_DKJR),
.I_DK3B(I_DK3B),
.I_AB(W_CPU_A),
.I_DB(WI_D),
.I_MREQ_n(W_CPU_MREQn),
@@ -307,6 +326,7 @@ dkong_adec adec
.O_RAM1_CS_n(W_RAM1_CSn),
.O_RAM2_CS_n(W_RAM2_CSn),
.O_RAM3_CS_n(W_RAM3_CSn),
.O_RAMDK3B_CS_n(W_RAMDK3B_CSn),
.O_DMA_CS_n(/*O_DMA_CSn*/),
.O_6A_G_n(/*W_6A_Gn*/),
.O_OBJ_RQ_n(W_OBJ_RQn),
@@ -422,6 +442,7 @@ dkong_col_pal cpal
// input
.CLK_24M(W_CLK_24576M),
.CLK_6M_EN(W_CLK_12288M & !W_H_CNT[0]),
.I_DK3B(I_DK3B),
.I_VRAM_D({W_VRAM_COL[3:0],W_VRAM_VID[1:0]}),
.I_OBJ_D(W_OBJ_DAT),
.I_CMPBLKn(W_L_CMPBLKn),

View File

@@ -92,7 +92,7 @@ dpram #(8,4) col3 (
.clock_b(CLK_24M),
.address_b(DL_ADDR[7:0]),
.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF2),
.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF4),
.data_b(DL_DATA[3:0])
);