mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-08 09:01:24 +00:00
Donkey Kong: add Donkey Kong 3 (bootleg on DKJr HW)
This commit is contained in:
@@ -0,0 +1,45 @@
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<misterromdescription>
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<name>Donkey Kong 3 (bootleg on DKJr HW)</name>
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<mameversion>0217</mameversion>
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<setname>dkong3b</setname>
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<mratimestamp>201912300000</mratimestamp>
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<year>1982</year>
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<manufacturer>Nintendo of America</manufacturer>
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<category>Maze / Monkeys</category>
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<category>Platform</category>
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<category>Platform / Mario Bros.</category>
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<rbf>dkong</rbf>
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<buttons names="Jump,Start 1P,Start 2P,Coin" default="A,Start,Select,R" />
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<rom index="1"><part>03</part></rom>
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<rom index="0" zip="dkong3.zip" md5="403f810061c5eda8651b5284af4b92ce" type="merged">
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<!-- Main CPU 32k-->
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<part crc="dea28158" name="dkong3b/5b.bin"/>
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<part crc="6fb5faf6" name="dkong3b/5c-2.bin"/>
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<part crc="d042b6a8" name="dkong3b/5e-2.bin"/>
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<part crc="d042b6a8" name="dkong3b/5c-1.bin"/>
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<part crc="d042b6a8" name="dkong3b/5e-1.bin"/>
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<!-- GFX1 8k-->
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<part crc="4ef64ba5" name="dkong3b/3p.bin"/>
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<part crc="8d51aca9" name="dkong3b/3n.bin"/>
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<!-- GFX2 16k-->
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<part crc="dc7f4164" name="dk3v.7c"/>
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<part crc="dc7f4164" name="dk3v.7d"/>
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<part crc="dc7f4164" name="dk3v.7e"/>
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<part crc="dc7f4164" name="dk3v.7f"/>
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<!-- Sound CPU 4k-->
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<part crc="715da5f8" name="dkong3b/3h.bin"/>
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<!-- LUTs -->
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<part crc="47ba0042" name="dkc1-c.1c"/>
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<part crc="463dc7ad" name="dkc1-c.1d"/>
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<part crc="dbf185bf" name="dkc1-v.2n"/>
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<part repeat="2816">00</part>
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</rom>
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</misterromdescription>
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@@ -20,7 +20,7 @@
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</switches>
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<rom index="1"><part>01</part></rom>
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<rom index="0" zip="dkongjr.zip" md5="bb9b77f52d45312bcf08409c76b1b8db" type="merged|nonmerged">
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<rom index="0" zip="dkongjr.zip" md5="8ccadf69374bfc47254dfe8e5d4d8f7e" type="merged|nonmerged">
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<!-- Main CPU 32k-->
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<part crc="dea28158" name="djr1-c_5b_f-2.5b"/>
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<part crc="6fb5faf6" name="djr1-c_5c_f-2.5c"/>
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@@ -46,9 +46,11 @@
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<!-- LUTs -->
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<part crc="463dc7ad" name="djr1-c-2e.2e"/>
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<part crc="463dc7ad" name="djr1-c-2e.2e"/>
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<part crc="47ba0042" name="djr1-c-2f.2f"/>
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<part crc="47ba0042" name="djr1-c-2f.2f"/>
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<part crc="dbf185bf" name="djr1-v-2n.2n"/>
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<part repeat="3328">00</part>
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<part repeat="2816">00</part>
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<!-- WAVs -->
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<part>
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@@ -12,9 +12,10 @@
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<switches default="80" base="8">
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<dip bits="0,1" name="Lives" ids="3,4,5,6"/>
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<dip bits="2,3" name="Bonus Life" ids="7K,10K,15K,20K"/>
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<dip bits="4,6" name="Coins" ids="1C1P,2C1P,1C1P,3C1P,1C1P,4C1P,1C1P,5C1P,1C1P"/>
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<dip bits="7" name="Cabinet" ids="Cocktail,Upright"/>
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</switches>
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<rom index="0" zip="dkong.zip" md5="ac7807bf1c69c3720888212143af10af">
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</switches>
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<rom index="0" zip="dkong.zip" md5="2b33a8e64b3ac1d361cd6d06cabc4f7c">
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<!-- Main CPU 32k -->
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<part crc="ba70b88b" name="c_5et_g.bin"/>
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<part crc="5ec461ec" name="c_5ct_g.bin"/>
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@@ -47,9 +48,11 @@
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<!-- LUTs 3x256 -->
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<part crc="e273ede5" name="c-2k.bpr"/>
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<part crc="e273ede5" name="c-2k.bpr"/>
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<part crc="d6412358" name="c-2j.bpr"/>
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<part crc="d6412358" name="c-2j.bpr"/>
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<part crc="b869b8f5" name="v-5e.bpr"/>
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<part repeat="3328">00</part>
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<part repeat="2816">00</part>
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<!-- WAWs -->
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<part>
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@@ -139,9 +139,7 @@ wire [7:0] audio;
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wire hs_n, vs_n;
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wire hb, vb;
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wire blankn = ~vb;//~(hb | vb);
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wire [2:0] r, g;
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wire [1:0] b;
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wire [3:0] r, g, b;
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dkong_top dkong(
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.I_CLK_24576M(clock_24),
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@@ -161,6 +159,7 @@ dkong_top dkong(
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.I_C1(~m_coin1),
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.I_DIP_SW(status[15:8]),
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.I_DKJR(core_mod[0]),
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.I_DK3B(core_mod[1]),
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.O_SOUND_DAT(audio),
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.O_VGA_R(r),
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.O_VGA_G(g),
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@@ -181,14 +180,14 @@ dkong_top dkong(
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.WAV_ROM_DO(wav_rom_a[0] ? wav_rom_do[15:8] : wav_rom_do[7:0])
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);
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mist_video #(.COLOR_DEPTH(3),.SD_HCNT_WIDTH(10)) mist_video(
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mist_video #(.COLOR_DEPTH(4),.SD_HCNT_WIDTH(10)) mist_video(
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.clk_sys(clock_24),
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.SPI_SCK(SPI_SCK),
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.SPI_SS3(SPI_SS3),
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.SPI_DI(SPI_DI),
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.R(blankn ? r : 0),
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.G(blankn ? g : 0),
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.B(blankn ? {b, 1'b1} : 0),
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.B(blankn ? b : 0),
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.HSync(hs_n),
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.VSync(vs_n),
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.VGA_R(VGA_R),
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@@ -24,6 +24,7 @@ I_CLK_EN_P,
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I_CLK_EN_N,
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I_RESET_n,
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I_DKJR,
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I_DK3B,
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I_AB,
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I_DB,
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I_MREQ_n,
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@@ -39,6 +40,7 @@ O_ROM_CS_n,
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O_RAM1_CS_n,
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O_RAM2_CS_n,
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O_RAM3_CS_n,
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O_RAMDK3B_CS_n,
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O_DMA_CS_n,
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O_6A_G_n,
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O_OBJ_RQ_n,
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@@ -62,6 +64,7 @@ input I_CLK_EN_P; // H_CNT[1] 3.072MHz
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input I_CLK_EN_N;
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input I_RESET_n;
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input I_DKJR;
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input I_DK3B;
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input [15:0]I_AB;
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input [3:0]I_DB;
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input I_MREQ_n;
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@@ -75,6 +78,7 @@ output O_ROM_CS_n; // 0000 H - 3FFF H (5E,5C,5B,5A)
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output O_RAM1_CS_n; // 6000 H - 63FF H (3C,4C)
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output O_RAM2_CS_n; // 6400 H - 67FF H (3B,4B)
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output O_RAM3_CS_n; // 6800 H - 6BFF H (3A,4A)
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output O_RAMDK3B_CS_n; // 6C00 H - 6FFF H (DK3B only)
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output O_DMA_CS_n; // 7800 H - 783F H (DMA)
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output O_6A_G_n; // 7000 H - 77FF H => Active
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output O_OBJ_RQ_n; // 7000 H - 73FF H
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@@ -148,7 +152,7 @@ logic_74xx138 U_4D(
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);
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assign O_ROM_CS_n = I_DKJR ? &W_4D_Q[5:0] : &W_4D_Q[3:0];
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assign O_ROM_CS_n = I_DKJR ? (&W_4D_Q[5:0] & (!I_DK3B | !(I_AB[15:12] == 4'h9 | I_AB[15:12] == 4'hD))) : &W_4D_Q[3:0];
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// ADDR DEC 7000H - 7FFFH
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@@ -217,6 +221,7 @@ logic_74xx138 U_2D(
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assign O_RAM1_CS_n = W_2D_Q[0];
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assign O_RAM2_CS_n = W_2D_Q[1];
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assign O_RAM3_CS_n = W_2D_Q[2];
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assign O_RAMDK3B_CS_n = !I_DK3B | W_2D_Q[3];
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// ADDR DEC 7C00H - 7FFFH (R)
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logic_74xx138 U_1B(
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@@ -17,14 +17,16 @@
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module dkong_col_pal(
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input CLK_24M,
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input CLK_6M_EN,
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input I_DK3B,
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input I_PALBNK,
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input [5:0]I_VRAM_D,
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input [5:0]I_OBJ_D,
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input I_CMPBLKn,
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input I_5H_Q6,
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input I_5H_Q7,
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output [2:0]O_R,
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output [2:0]O_G,
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output [1:0]O_B,
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output [3:0]O_R,
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output [3:0]O_G,
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output [3:0]O_B,
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input [15:0] DL_ADDR,
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input DL_WR,
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@@ -47,7 +49,7 @@ begin
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end
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//------- PARTS 2EF ------------------------------------
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wire [3:0]W_2E_DO,W_2F_DO;
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wire [7:0]W_2E_DO,W_2F_DO;
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/*
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col1 rom2j(
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.clk(CLK_24M),
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@@ -55,15 +57,15 @@ col1 rom2j(
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.data(W_2F_DO)
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);
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*/
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dpram #(8,4) col1 (
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dpram #(9,8) col1 (
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.clock_a(CLK_24M),
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.address_a(W_1EF_Q[9:2]),
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.q_a(W_2F_DO),
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.clock_b(CLK_24M),
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.address_b(DL_ADDR[7:0]),
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.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF1),
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.data_b(DL_DATA[3:0])
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.wren_b(DL_WR && DL_ADDR[15:9] == {4'hF, 3'b001}),
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.data_b(DL_DATA)
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);
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/*
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col2 rom2k(
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@@ -72,17 +74,20 @@ col2 rom2k(
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.data(W_2E_DO)
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);
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*/
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dpram #(8,4) col2 (
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dpram #(9,8) col2 (
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.clock_a(CLK_24M),
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.address_a(W_1EF_Q[9:2]),
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.q_a(W_2E_DO),
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.clock_b(CLK_24M),
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.address_b(DL_ADDR[7:0]),
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.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF0),
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.data_b(DL_DATA[3:0])
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.wren_b(DL_WR && DL_ADDR[15:9] == {4'hF, 3'b000}),
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.data_b(DL_DATA)
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);
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assign {O_R, O_G, O_B} = {~W_2F_DO, ~W_2E_DO};
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//assign {O_R, O_G, O_B} = I_DK3B ? {W_2F_DO, W_2E_DO} : ~{W_2F_DO[3:1], W_2F_DO[3], ~W_2E_DO};
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assign O_R = I_DK3B ? W_2F_DO[7:4] : ~{W_2F_DO[3:1], W_2F_DO[3]};
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assign O_G = I_DK3B ? W_2F_DO[3:0] : ~{W_2F_DO[0], W_2E_DO[3:2], W_2F_DO[0]};
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assign O_B = I_DK3B ? W_2E_DO[3:0] : ~{W_2E_DO[1:0], W_2E_DO[1:0]};
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endmodule
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@@ -310,7 +310,7 @@ begin
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end
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wire [10:0]W_ROM_OBJ_AB = {W_6H_Q[6:0],W_8H_Q[3:0]^{W_6H_Q[7],W_6H_Q[7],W_6H_Q[7],W_6H_Q[7]}};
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wire [11:0]W_ROM_OBJ_AB = {W_6J_Q[6],W_6H_Q[6:0],W_8H_Q[3:0]^{W_6H_Q[7],W_6H_Q[7],W_6H_Q[7],W_6H_Q[7]}};
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wire [7:0]W_OBJ_DO_7C,W_OBJ_DO_7D,W_OBJ_DO_7E,W_OBJ_DO_7F;
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@@ -321,14 +321,14 @@ obj1 obj1 (
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.data(W_OBJ_DO_7C)
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);
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*/
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dpram #(11,8) obj1 (
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dpram #(12,8) obj1 (
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.clock_a(CLK_24M),
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.address_a(W_ROM_OBJ_AB),
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.q_a(W_OBJ_DO_7C),
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.clock_b(CLK_24M),
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.address_b(DL_ADDR[10:0]),
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.wren_b(DL_WR && DL_ADDR[15:11] == {4'hA, 1'b0}),
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.address_b(DL_ADDR[11:0]),
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.wren_b(DL_WR && DL_ADDR[15:12] == 4'hA),
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.data_b(DL_DATA)
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);
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/*
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@@ -338,14 +338,14 @@ obj2 obj2 (
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.data(W_OBJ_DO_7D)
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);
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*/
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dpram #(11,8) obj2 (
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dpram #(12,8) obj2 (
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.clock_a(CLK_24M),
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.address_a(W_ROM_OBJ_AB),
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.q_a(W_OBJ_DO_7D),
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.clock_b(CLK_24M),
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.address_b(DL_ADDR[10:0]),
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.wren_b(DL_WR && DL_ADDR[15:11] == {4'hB, 1'b0}),
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.address_b(DL_ADDR[11:0]),
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.wren_b(DL_WR && DL_ADDR[15:12] == 4'hB),
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.data_b(DL_DATA)
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);
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/*
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@@ -355,14 +355,14 @@ obj3 obj3 (
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.data(W_OBJ_DO_7E)
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);
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*/
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dpram #(11,8) obj3 (
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dpram #(12,8) obj3 (
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.clock_a(CLK_24M),
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.address_a(W_ROM_OBJ_AB),
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.q_a(W_OBJ_DO_7E),
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.clock_b(CLK_24M),
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.address_b(DL_ADDR[10:0]),
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.wren_b(DL_WR && DL_ADDR[15:11] == {4'hC, 1'b0}),
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.address_b(DL_ADDR[11:0]),
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.wren_b(DL_WR && DL_ADDR[15:12] == 4'hC),
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.data_b(DL_DATA)
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);
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/*
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@@ -372,14 +372,14 @@ obj4 obj4 (
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.data(W_OBJ_DO_7F)
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);
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*/
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dpram #(11,8) obj4 (
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dpram #(12,8) obj4 (
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.clock_a(CLK_24M),
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.address_a(W_ROM_OBJ_AB),
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.q_a(W_OBJ_DO_7F),
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.clock_b(CLK_24M),
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.address_b(DL_ADDR[10:0]),
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.wren_b(DL_WR && DL_ADDR[15:11] == {4'hD, 1'b0}),
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.address_b(DL_ADDR[11:0]),
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.wren_b(DL_WR && DL_ADDR[15:12] == 4'hD),
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.data_b(DL_DATA)
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);
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@@ -36,11 +36,12 @@ module dkong_top
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input [7:0] I_DIP_SW,
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input I_DKJR,
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input I_DK3B,
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// VGA (VIDEO) IF
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output [2:0]O_VGA_R,
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output [2:0]O_VGA_G,
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output [1:0]O_VGA_B,
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output [3:0]O_VGA_R,
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output [3:0]O_VGA_G,
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output [3:0]O_VGA_B,
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output O_H_BLANK,
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output O_V_BLANK,
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output O_VGA_H_SYNCn,
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@@ -83,6 +84,7 @@ wire W_ROM_CSn;
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wire W_RAM1_CSn;
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wire W_RAM2_CSn;
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wire W_RAM3_CSn;
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wire W_RAMDK3B_CSn;
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//wire W_6A_Gn;
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wire W_OBJ_RQn;
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wire W_OBJ_RDn;
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@@ -103,6 +105,7 @@ wire [4:0]W_3D_Q;
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wire [7:0]W_RAM1_DO;
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wire [7:0]W_RAM2_DO;
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wire [7:0]W_RAM3_DO;
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wire [7:0]W_RAMDK3B_DO;
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// ROM DATA
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wire [7:0]W_ROM_DO;
|
||||
@@ -156,7 +159,7 @@ wire W_CPU_CLK_EN_N = W_H_CNT[1:0] == 2'b11;
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||||
.DO(ZDI)
|
||||
);
|
||||
//========= CPU DATA BUS[7:0] ==============================================
|
||||
wire [7:0]WO_D = W_SW_DO | W_RAM1_DO |W_RAM2_DO |W_RAM3_DO | W_ROM_DO | W_VRAM_DB ;
|
||||
wire [7:0]WO_D = W_SW_DO | W_RAM1_DO |W_RAM2_DO |W_RAM3_DO |W_RAMDK3B_DO | W_ROM_DO | W_VRAM_DB ;
|
||||
assign ZDO = WO_D;
|
||||
|
||||
wire [11:0]OBJ_ROM_A;
|
||||
@@ -184,6 +187,11 @@ always @(*) begin
|
||||
6'h07: MAIN_CPU_A = {5'h03,W_CPU_A[10:0]}; // 0x3800-0x3FFF -> 0x1800-0x1FFF in ROM file
|
||||
6'h09: MAIN_CPU_A = {5'h05,W_CPU_A[10:0]}; // 0x4800-0x4FFF -> 0x2800-0x2FFF in ROM file
|
||||
6'h0B: MAIN_CPU_A = {5'h07,W_CPU_A[10:0]}; // 0x5800-0x5FFF -> 0x3800-0x3FFF in ROM file
|
||||
// dkong3b
|
||||
6'h12: MAIN_CPU_A = {5'h0C,W_CPU_A[10:0]}; // 0x9000-0x97FF -> 0x6000-0x6FFF in ROM file
|
||||
6'h13: MAIN_CPU_A = {5'h0D,W_CPU_A[10:0]}; // 0x9800-0x9FFF -> 0x6000-0x6FFF in ROM file
|
||||
6'h1A: MAIN_CPU_A = {5'h0E,W_CPU_A[10:0]}; // 0xD000-0xD7FF -> 0x7000-0x7FFF in ROM file
|
||||
6'h1B: MAIN_CPU_A = {5'h0F,W_CPU_A[10:0]}; // 0xD800-0xDFFF -> 0x7000-0x7FFF in ROM file
|
||||
default: MAIN_CPU_A = W_CPU_A[15:0];
|
||||
endcase
|
||||
end
|
||||
@@ -211,6 +219,16 @@ ram_1024_8 U_3B4B
|
||||
.O_D(W_RAM2_DO)
|
||||
);
|
||||
|
||||
ram_1024_8 U_DK3BRAM
|
||||
(
|
||||
.I_CLK(I_CLK_24576M),
|
||||
.I_ADDR(W_CPU_A[9:0]),
|
||||
.I_D(WI_D),
|
||||
.I_CE(~W_RAMDK3B_CSn),
|
||||
.I_WE(~W_CPU_WRn),
|
||||
.O_D(W_RAMDK3B_DO)
|
||||
);
|
||||
|
||||
//=============== Sprite DMA ======================
|
||||
|
||||
wire [9:0]W_OBJ_AB = {W_2PSL, W_H_CNT[8:0]};
|
||||
@@ -293,6 +311,7 @@ dkong_adec adec
|
||||
.I_CLK_EN_N(W_CPU_CLK_EN_N),
|
||||
.I_RESET_n(W_RESETn),
|
||||
.I_DKJR(I_DKJR),
|
||||
.I_DK3B(I_DK3B),
|
||||
.I_AB(W_CPU_A),
|
||||
.I_DB(WI_D),
|
||||
.I_MREQ_n(W_CPU_MREQn),
|
||||
@@ -307,6 +326,7 @@ dkong_adec adec
|
||||
.O_RAM1_CS_n(W_RAM1_CSn),
|
||||
.O_RAM2_CS_n(W_RAM2_CSn),
|
||||
.O_RAM3_CS_n(W_RAM3_CSn),
|
||||
.O_RAMDK3B_CS_n(W_RAMDK3B_CSn),
|
||||
.O_DMA_CS_n(/*O_DMA_CSn*/),
|
||||
.O_6A_G_n(/*W_6A_Gn*/),
|
||||
.O_OBJ_RQ_n(W_OBJ_RQn),
|
||||
@@ -422,6 +442,7 @@ dkong_col_pal cpal
|
||||
// input
|
||||
.CLK_24M(W_CLK_24576M),
|
||||
.CLK_6M_EN(W_CLK_12288M & !W_H_CNT[0]),
|
||||
.I_DK3B(I_DK3B),
|
||||
.I_VRAM_D({W_VRAM_COL[3:0],W_VRAM_VID[1:0]}),
|
||||
.I_OBJ_D(W_OBJ_DAT),
|
||||
.I_CMPBLKn(W_L_CMPBLKn),
|
||||
|
||||
@@ -92,7 +92,7 @@ dpram #(8,4) col3 (
|
||||
|
||||
.clock_b(CLK_24M),
|
||||
.address_b(DL_ADDR[7:0]),
|
||||
.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF2),
|
||||
.wren_b(DL_WR && DL_ADDR[15:8] == 8'hF4),
|
||||
.data_b(DL_DATA[3:0])
|
||||
);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user