mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-13 15:17:55 +00:00
Marcel
GitHub
commit
c32edb285f
@ -31,7 +31,7 @@ module IremM72_MiST(
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output SDRAM_CKE
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);
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`include "rtl/build_id.v"
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`include "build_id.v"
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`define CORE_NAME "RTYPE2"
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//`define CORE_NAME "HHARRYU"
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@ -94,8 +94,8 @@ pll_mist pll(
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire [7:0] joystick_0;
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wire [7:0] joystick_1;
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wire [15:0] joystick_0;
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wire [15:0] joystick_1;
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wire scandoublerD;
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wire ypbpr;
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wire no_csync;
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@ -308,7 +308,6 @@ rom_loader rom_loader(
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wire [15:0] ch_left, ch_right;
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wire [7:0] R, G, B;
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wire HBlank, VBlank, HSync, VSync;
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wire blankn = !(HBlank | VBlank);
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wire ce_pix;
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ddr_debug_data_t ddr_debug_data;
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@ -400,14 +399,16 @@ m72 m72(
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.video_60hz(video_60hz)
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);
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mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
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mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10), .USE_BLANKS(1'b1)) mist_video(
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.clk_sys ( CLK_32M ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS3 ( SPI_SS3 ),
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.SPI_DI ( SPI_DI ),
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.R ( blankn ? R[7:2] : 0 ),
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.G ( blankn ? G[7:2] : 0 ),
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.B ( blankn ? B[7:2] : 0 ),
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.R ( R[7:2] ),
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.G ( G[7:2] ),
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.B ( B[7:2] ),
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.HBlank ( HBlank ),
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.VBlank ( VBlank ),
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.HSync ( HSync ),
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.VSync ( VSync ),
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.VGA_R ( VGA_R ),
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@ -446,7 +447,7 @@ wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE,
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wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
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wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
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arcade_inputs inputs (
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arcade_inputs #(.START1(8), .START2(10), .COIN1(9)) inputs (
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.clk ( CLK_32M ),
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.key_strobe ( key_strobe ),
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.key_pressed ( key_pressed ),
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@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
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set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
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# Create a Verilog file for output
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set outputFileName "rtl/build_id.v"
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set outputFileName "build_id.v"
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set outputFile [open $outputFileName "w"]
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# Output the Verilog source
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30
Arcade_MiST/IremM72 Hardware/sidi/IremM72.qpf
Normal file
30
Arcade_MiST/IremM72 Hardware/sidi/IremM72.qpf
Normal file
@ -0,0 +1,30 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2011 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
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# Date created = 23:49:02 July 13, 2012
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "10.1"
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DATE = "23:49:02 July 13, 2012"
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# Revisions
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PROJECT_REVISION = "IremM72"
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256
Arcade_MiST/IremM72 Hardware/sidi/IremM72.qsf
Normal file
256
Arcade_MiST/IremM72 Hardware/sidi/IremM72.qsf
Normal file
@ -0,0 +1,256 @@
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set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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# Date created = 21:06:00 February 29, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# IremM72_MiST_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:../rtl/build_id.tcl"
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set_global_assignment -name SMART_RECOMPILE ON
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# Pin & Location Assignments
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# ==========================
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set_location_assignment PIN_G1 -to LED
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set_location_assignment PIN_E1 -to CLOCK_27
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set_location_assignment PIN_P16 -to VGA_R[5]
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set_location_assignment PIN_P15 -to VGA_R[4]
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set_location_assignment PIN_R16 -to VGA_R[3]
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set_location_assignment PIN_R14 -to VGA_R[2]
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set_location_assignment PIN_T15 -to VGA_R[1]
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set_location_assignment PIN_T14 -to VGA_R[0]
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set_location_assignment PIN_J16 -to VGA_B[5]
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set_location_assignment PIN_J15 -to VGA_B[4]
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set_location_assignment PIN_J14 -to VGA_B[3]
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set_location_assignment PIN_K16 -to VGA_B[2]
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set_location_assignment PIN_K15 -to VGA_B[1]
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set_location_assignment PIN_J13 -to VGA_B[0]
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set_location_assignment PIN_F16 -to VGA_G[5]
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set_location_assignment PIN_F15 -to VGA_G[4]
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set_location_assignment PIN_L16 -to VGA_G[3]
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set_location_assignment PIN_L15 -to VGA_G[2]
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set_location_assignment PIN_N15 -to VGA_G[1]
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set_location_assignment PIN_N16 -to VGA_G[0]
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set_location_assignment PIN_T10 -to VGA_VS
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set_location_assignment PIN_T11 -to VGA_HS
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set_location_assignment PIN_T12 -to AUDIO_L
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set_location_assignment PIN_T13 -to AUDIO_R
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set_location_assignment PIN_T2 -to SPI_DO
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set_location_assignment PIN_R1 -to SPI_DI
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set_location_assignment PIN_T3 -to SPI_SCK
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set_location_assignment PIN_T4 -to SPI_SS2
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set_location_assignment PIN_G15 -to SPI_SS3
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set_location_assignment PIN_G16 -to SPI_SS4
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set_location_assignment PIN_H2 -to CONF_DATA0
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set_location_assignment PIN_B14 -to SDRAM_A[0]
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set_location_assignment PIN_C14 -to SDRAM_A[1]
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set_location_assignment PIN_C15 -to SDRAM_A[2]
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set_location_assignment PIN_C16 -to SDRAM_A[3]
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set_location_assignment PIN_B16 -to SDRAM_A[4]
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set_location_assignment PIN_A15 -to SDRAM_A[5]
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set_location_assignment PIN_A14 -to SDRAM_A[6]
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set_location_assignment PIN_A13 -to SDRAM_A[7]
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set_location_assignment PIN_A12 -to SDRAM_A[8]
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set_location_assignment PIN_D16 -to SDRAM_A[9]
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set_location_assignment PIN_B13 -to SDRAM_A[10]
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set_location_assignment PIN_D15 -to SDRAM_A[11]
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set_location_assignment PIN_D14 -to SDRAM_A[12]
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set_location_assignment PIN_C3 -to SDRAM_DQ[0]
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set_location_assignment PIN_C2 -to SDRAM_DQ[1]
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set_location_assignment PIN_A4 -to SDRAM_DQ[2]
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set_location_assignment PIN_B4 -to SDRAM_DQ[3]
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set_location_assignment PIN_A6 -to SDRAM_DQ[4]
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set_location_assignment PIN_D6 -to SDRAM_DQ[5]
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set_location_assignment PIN_A7 -to SDRAM_DQ[6]
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set_location_assignment PIN_B7 -to SDRAM_DQ[7]
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set_location_assignment PIN_E6 -to SDRAM_DQ[8]
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set_location_assignment PIN_C6 -to SDRAM_DQ[9]
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set_location_assignment PIN_B6 -to SDRAM_DQ[10]
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set_location_assignment PIN_B5 -to SDRAM_DQ[11]
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set_location_assignment PIN_A5 -to SDRAM_DQ[12]
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set_location_assignment PIN_B3 -to SDRAM_DQ[13]
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set_location_assignment PIN_A3 -to SDRAM_DQ[14]
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set_location_assignment PIN_A2 -to SDRAM_DQ[15]
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set_location_assignment PIN_A11 -to SDRAM_BA[0]
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set_location_assignment PIN_B12 -to SDRAM_BA[1]
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set_location_assignment PIN_C9 -to SDRAM_DQMH
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set_location_assignment PIN_C8 -to SDRAM_DQML
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set_location_assignment PIN_A10 -to SDRAM_nRAS
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set_location_assignment PIN_B10 -to SDRAM_nCAS
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set_location_assignment PIN_D8 -to SDRAM_nWE
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set_location_assignment PIN_B11 -to SDRAM_nCS
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set_location_assignment PIN_C11 -to SDRAM_CKE
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set_location_assignment PIN_R4 -to SDRAM_CLK
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# Classic Timing Assignments
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# ==========================
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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# Analysis & Synthesis Assignments
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# ================================
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set_global_assignment -name TOP_LEVEL_ENTITY IremM72_MiST
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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# Fitter Assignments
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# ==================
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set_global_assignment -name DEVICE EP4CE22F17C8
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_NCE_PIN OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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# Assembler Assignments
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# =====================
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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# SignalTap II Assignments
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# ========================
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu2.stp
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# Power Estimation Assignments
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# ============================
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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# Advanced I/O Timing Assignments
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# ===============================
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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# -----------------------------
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# start ENTITY(IremM72_MiST)
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# Pin & Location Assignments
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# ==========================
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
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# Fitter Assignments
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# ==================
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
|
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
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# start DESIGN_PARTITION(Top)
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# ---------------------------
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# Incremental Compilation Assignments
|
||||
# ===================================
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(IremM72_MiST)
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# ---------------------------
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set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1
|
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set_global_assignment -name DSP_BLOCK_BALANCING "DSP BLOCKS"
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
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set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION AUTO
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING ON
|
||||
set_global_assignment -name SDC_FILE ../IremM72.sdc
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/IremM72_MiST.sv
|
||||
set_global_assignment -name QIP_FILE ../rtl/pll_mist.qip
|
||||
set_global_assignment -name QIP_FILE ../rtl/m72.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/CPU/v30/V30.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/CPU/MC8051/mc8051.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/Sound/jt51/jt51.qip
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/cpu2.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/cpu3.stp
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@ -1,7 +1,8 @@
|
||||
<misterromdescription>
|
||||
<name>Undercover Cops (World)</name>
|
||||
<name>Undercover Cops - Alpha Renewal Version (World)</name>
|
||||
<mameversion>0245</mameversion>
|
||||
<setname>uccops</setname>
|
||||
<setname>uccopsar</setname>
|
||||
<parent>uccops</parent>
|
||||
<year>1992</year>
|
||||
<manufacturer>Irem</manufacturer>
|
||||
<category>Fighter</category>
|
||||
@ -27,44 +28,44 @@
|
||||
<dip bits="12,15" ids="1C/1C,2C/1C,3C/1C,4C/1C,5C/1C,6C/1C,1C/2C,1C/3C,1C/4C,1C/5C,1C/6C,2C/3C,3C/2C,4C/3C,2S/1C,Free Play" name="Coin Mode"></dip>
|
||||
</switches>
|
||||
|
||||
<rom index="0" zip="uccops.zip" md5="None">
|
||||
<rom index="0" zip="uccops.zip|uccopsar.zip" md5="None">
|
||||
<!-- board type -->
|
||||
<part>00</part>
|
||||
|
||||
<!-- maincpu -->
|
||||
<part>00 0c 00 00</part>
|
||||
<interleave output="16">
|
||||
<part name="ucc_e-h0.ic28" crc="240aa5f7" map="10" />
|
||||
<part name="ucc_e-l0.ic39" crc="df9a4826" map="01" />
|
||||
<part name="uc_h0_a.ic28" crc="9e17cada" map="10" />
|
||||
<part name="uc_l0_a.ic39" crc="4a4e3208" map="01" />
|
||||
</interleave>
|
||||
<interleave output="16">
|
||||
<part name="ucc_h1.ic27" crc="8d29bcd6" map="10" />
|
||||
<part name="ucc_l1.ic38" crc="a8a402d8" map="01" />
|
||||
<part name="uc_ar_h1.ic27" crc="79d79742" map="10" />
|
||||
<part name="uc_ar_l1.ic38" crc="37211581" map="01" />
|
||||
</interleave>
|
||||
|
||||
<!-- gfx1 tiles -->
|
||||
<part>01 20 00 00</part>
|
||||
<interleave output="32">
|
||||
<part name="uc_w38m.rom" crc="130a40e5" map="0001" />
|
||||
<part name="uc_w39m.rom" crc="e42ca144" map="0010" />
|
||||
<part name="uc_w40m.rom" crc="c2961648" map="0100" />
|
||||
<part name="uc_w41m.rom" crc="f5334b80" map="1000" />
|
||||
<part name="uc_c0.ic26" crc="6a419a36" map="0001" />
|
||||
<part name="uc_c1.ic25" crc="d703ecc7" map="0010" />
|
||||
<part name="uc_c2.ic24" crc="96397ac6" map="0100" />
|
||||
<part name="uc_c3.ic23" crc="5d07d10d" map="1000" />
|
||||
</interleave>
|
||||
|
||||
<!-- gfx2 sprites -->
|
||||
<part>02 40 00 00</part>
|
||||
<interleave output="32">
|
||||
<part name="uc_k16m.rom" crc="4a225f09" map="0001" />
|
||||
<part name="uc_k17m.rom" crc="e4ed9a54" map="0010" />
|
||||
<part name="uc_k18m.rom" crc="a626eb12" map="0100" />
|
||||
<part name="uc_k19m.rom" crc="5df46549" map="1000" />
|
||||
<part name="uc_030.ic37" crc="97f7775e" map="0001" />
|
||||
<part name="uc_020.ic36" crc="5e0b1d65" map="0010" />
|
||||
<part name="uc_010.ic35" crc="bdc224b3" map="0100" />
|
||||
<part name="uc_000.ic34" crc="7526daec" map="1000" />
|
||||
</interleave>
|
||||
|
||||
<!-- soundcpu -->
|
||||
<part>03 02 00 00</part>
|
||||
<interleave output="16">
|
||||
<part name="ucc_e-sh0.ic30" crc="df90b198" map="10" />
|
||||
<part name="ucc_e-sl0.ic31" crc="96c11aac" map="01" />
|
||||
<part name="uc_sh0.ic30" crc="f0ca1b03" map="10" />
|
||||
<part name="uc_sl0.ic31" crc="d1661723" map="01" />
|
||||
</interleave>
|
||||
|
||||
<!-- soundcpu key -->
|
||||
@ -90,13 +91,13 @@
|
||||
|
||||
<!-- iremg20 -->
|
||||
<part>05 08 00 00</part>
|
||||
<part name="uc_w42.rom" crc="d17d3fd6" />
|
||||
<part name="uc_da.bin" crc="0b2855e9" />
|
||||
</rom>
|
||||
<!--hiscore support. see hiscore.sv for modified header values-->
|
||||
<rom index="3" md5="none">
|
||||
<part>
|
||||
00 00 00 0F 05 FF 00 01 00 0F 00 01 00 01 02 00
|
||||
00 0e 3e 9a 00 49 30 01
|
||||
00 0e 3e 7c 00 49 30 01
|
||||
</part>
|
||||
</rom>
|
||||
<nvram index="4" size="73"></nvram>
|
||||
@ -52,7 +52,9 @@ localparam CONF_STR = {
|
||||
`endif
|
||||
//"OD,Audio Filters,On,Off;",
|
||||
"DIP;",
|
||||
`ifndef NO_EEPROM
|
||||
"R8192,Save EEPROM;",
|
||||
`endif
|
||||
"T0,Reset;",
|
||||
"V,v1.0.",`BUILD_DATE
|
||||
};
|
||||
@ -66,7 +68,7 @@ wire [2:0] dbg_en_layers = ~status[11:9];
|
||||
wire dbg_fm_en = ~status[12];
|
||||
wire dbg_sprite_freeze = 0;
|
||||
wire filters = 0;//~status[13];
|
||||
wire [1:0] orientation = {1'b0, core_mod[0]};
|
||||
wire [1:0] orientation = {flipped, core_mod[0]};
|
||||
reg oneplayer = 0;
|
||||
wire [15:0] dip_sw = status[31:16];
|
||||
|
||||
@ -323,13 +325,13 @@ rom_loader rom_loader(
|
||||
wire [15:0] ch_left, ch_right;
|
||||
wire [7:0] R, G, B;
|
||||
wire HBlank, VBlank, HSync, VSync;
|
||||
wire blankn = !(HBlank | VBlank);
|
||||
wire ce_pix;
|
||||
|
||||
wire flipped;
|
||||
|
||||
m92 m92(
|
||||
.clk_sys(CLK_40M),
|
||||
.ce_pix(ce_pix),
|
||||
.flipped(flipped),
|
||||
.reset_n(~reset),
|
||||
.HBlank(HBlank),
|
||||
.VBlank(VBlank),
|
||||
@ -420,14 +422,16 @@ m92 m92(
|
||||
.en_audio_filters(filters)
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
|
||||
mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10), .USE_BLANKS(1)) mist_video(
|
||||
.clk_sys ( CLK_40M ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( blankn ? R[7:2] : 0 ),
|
||||
.G ( blankn ? G[7:2] : 0 ),
|
||||
.B ( blankn ? B[7:2] : 0 ),
|
||||
.R ( R[7:2] ),
|
||||
.G ( G[7:2] ),
|
||||
.B ( B[7:2] ),
|
||||
.HBlank ( HBlank ),
|
||||
.VBlank ( VBlank ),
|
||||
.HSync ( HSync ),
|
||||
.VSync ( VSync ),
|
||||
.VGA_R ( VGA_R ),
|
||||
@ -469,7 +473,7 @@ wire m_up4, m_down4, m_left4, m_right4, m_up4B, m_down4B, m_left4B, m_right4B;
|
||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||
wire [11:0] m_fire1, m_fire2, m_fire3, m_fire4;
|
||||
|
||||
arcade_inputs inputs (
|
||||
arcade_inputs #(.START1(10), .START2(12), .COIN1(11)) inputs (
|
||||
.clk ( CLK_40M ),
|
||||
.key_strobe ( key_strobe ),
|
||||
.key_pressed ( key_pressed ),
|
||||
|
||||
@ -221,7 +221,7 @@ end
|
||||
assign dout = buf_cs ? (direct_access_obj ? obj_din : (direct_access_pal ? pal_din : buffer_din)) : 16'd0;
|
||||
assign busy = copy_state != IDLE;
|
||||
|
||||
assign buffer_we = ~busy & buf_cs & wr & ~direct_access_obj & ~direct_access_pal;
|
||||
assign buffer_we = ~busy & buf_cs & wr;
|
||||
assign buffer_addr = busy ? buffer_src_addr : addr;
|
||||
|
||||
assign buffer_dout = din;
|
||||
|
||||
@ -53,7 +53,7 @@ reg linebuf_write;
|
||||
reg linebuf_flip;
|
||||
reg scan_toggle = 0;
|
||||
reg [9:0] scan_pos = 0;
|
||||
wire [9:0] scan_pos_nl = scan_pos ^ {10{NL}};
|
||||
wire [9:0] scan_pos_nl = scan_pos ^ {1'b0, {9{NL}}};
|
||||
wire [11:0] scan_out;
|
||||
|
||||
double_linebuf line_buffer(
|
||||
@ -87,11 +87,13 @@ wire obj_flipx = obj_data[40];
|
||||
wire obj_flipy = obj_data[41];
|
||||
wire [9:0] obj_org_x = obj_data[57:48];
|
||||
|
||||
reg [8:0] V;
|
||||
wire [8:0] VE = V ^ {9{NL}};
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
reg visible;
|
||||
reg [3:0] span;
|
||||
reg [3:0] end_span;
|
||||
reg [8:0] V;
|
||||
|
||||
reg [15:0] code;
|
||||
reg [8:0] height_px;
|
||||
@ -144,7 +146,7 @@ always_ff @(posedge clk) begin
|
||||
end_span <= ( 4'd1 << obj_width ) - 1'd1;
|
||||
height_px = 9'd16 << obj_height;
|
||||
width = 4'd1 << obj_width;
|
||||
rel_y = V + obj_org_y + ( 9'd16 << obj_height );
|
||||
rel_y = VE + obj_org_y + ( 9'd16 << obj_height );
|
||||
row_y = obj_flipy ? (height_px - rel_y - 9'd1) : rel_y;
|
||||
|
||||
if (rel_y < height_px) begin
|
||||
|
||||
@ -33,6 +33,8 @@ module GA23(
|
||||
output reg vram_req,
|
||||
input [31:0] vram_din,
|
||||
|
||||
input NL,
|
||||
|
||||
input large_tileset,
|
||||
|
||||
input [31:0] sdr_data_a,
|
||||
@ -77,7 +79,11 @@ assign vblank = vcnt > 10'd113 && vcnt < 10'd136;
|
||||
assign vsync = vcnt > 10'd119 && vcnt < 10'd125;
|
||||
assign hpulse = hcnt == 10'd48;
|
||||
assign vpulse = (vcnt == 10'd124 && hcnt > 10'd260) || (vcnt == 10'd125 && hcnt < 10'd260);
|
||||
assign hint = vcnt == hint_line && hcnt > 10'd422 && ~paused;
|
||||
|
||||
wire [9:0] VE = vcnt ^ {1'b0, {9{NL}}};
|
||||
|
||||
assign hint = VE == hint_line && hcnt > 10'd422 && ~paused;
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (ce) begin
|
||||
@ -149,19 +155,19 @@ always_ff @(posedge clk, posedge reset) begin
|
||||
case(rs_cyc)
|
||||
0: vram_addr <= 'h7800;
|
||||
4: begin
|
||||
rs_y = y_ofs[0] + vcnt;
|
||||
rs_y = y_ofs[0] + VE;
|
||||
vram_addr <= 'h7a00 + rs_y[8:0];
|
||||
vram_req <= ~vram_req;
|
||||
end
|
||||
7: rowscroll[0] <= vram_din[9:0];
|
||||
8: begin
|
||||
rs_y = y_ofs[1] + vcnt;
|
||||
rs_y = y_ofs[1] + VE;
|
||||
vram_addr <= 'h7c00 + rs_y[8:0];
|
||||
vram_req <= ~vram_req;
|
||||
end
|
||||
10: rowscroll[1] <= vram_din[9:0];
|
||||
12: begin
|
||||
rs_y = y_ofs[2] + vcnt;
|
||||
rs_y = y_ofs[2] + VE;
|
||||
vram_addr <= 'h7e00 + rs_y[8:0];
|
||||
vram_req <= ~vram_req;
|
||||
end
|
||||
@ -280,15 +286,15 @@ generate
|
||||
.clk(clk),
|
||||
.ce_pix(ce),
|
||||
|
||||
.NL(0),
|
||||
.NL(NL),
|
||||
.large_tileset(large_tileset),
|
||||
|
||||
.x_ofs(_x_ofs),
|
||||
.y_ofs(_y_ofs),
|
||||
.control(_control),
|
||||
|
||||
.x_base({hcnt[9:3], 3'd0}),
|
||||
.y(_y_ofs + vcnt),
|
||||
.x_base({hcnt[9:3] ^ {7{NL}}, 3'd0}),
|
||||
.y(_y_ofs + VE),
|
||||
.rowscroll(_rowscroll),
|
||||
|
||||
.vram_addr(layer_vram_addr[i]),
|
||||
|
||||
@ -58,10 +58,10 @@ wire wide = control[2];
|
||||
wire enabled = ~control[4] & dbg_enabled;
|
||||
wire en_rowscroll = control[6];
|
||||
wire [9:0] x = x_base + ( en_rowscroll ? rowscroll : x_ofs );
|
||||
wire [6:0] tile_x = x[9:3] + ( wide ? 7'd32 : 7'd0);
|
||||
wire [6:0] tile_x = NL ? ( x[9:3] - ( wide ? 7'd32 : 7'd0) ) : ( x[9:3] + ( wide ? 7'd32 : 7'd0) );
|
||||
wire [5:0] tile_y = y[8:3];
|
||||
|
||||
assign vram_addr = vram_base + (wide ? {1'b0, tile_y, tile_x[6:0], 1'b0} : {2'b00, tile_y, tile_x[5:0], 1'b0});
|
||||
assign vram_addr = wide ? {vram_base[14], tile_y, tile_x[6:0], 1'b0} : {vram_base[14:13], tile_y, tile_x[5:0], 1'b0};
|
||||
|
||||
reg [3:0] cnt;
|
||||
|
||||
@ -81,8 +81,8 @@ always_ff @(posedge clk) begin
|
||||
sdr_req <= ~sdr_req;
|
||||
palette <= attrib[6:0];
|
||||
prio <= attrib[8:7];
|
||||
flip_x <= attrib[9];
|
||||
offset <= x[2:0];
|
||||
flip_x <= attrib[9] ^ NL;
|
||||
offset <= x[2:0] ^ {3{NL}};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
@ -25,10 +25,10 @@ module m92 (
|
||||
|
||||
input reset_n,
|
||||
output reg ce_pix,
|
||||
output flipped,
|
||||
|
||||
input board_cfg_t board_cfg,
|
||||
|
||||
|
||||
output [7:0] R,
|
||||
output [7:0] G,
|
||||
output [7:0] B,
|
||||
@ -128,6 +128,7 @@ module m92 (
|
||||
);
|
||||
|
||||
assign ioctl_upload_index = 8'd1;
|
||||
assign flipped = NL;
|
||||
|
||||
wire [15:0] rgb_color;
|
||||
assign R = { rgb_color[4:0], rgb_color[4:2] };
|
||||
@ -359,7 +360,7 @@ end
|
||||
wire int_req, int_ack;
|
||||
wire [8:0] int_vector;
|
||||
|
||||
v30 v30(
|
||||
v30 #(.INTACK_DELAY(0)) v30(
|
||||
.clk(clk_sys),
|
||||
.ce(ce_cpu),
|
||||
.ce_4x(ce_4x_cpu),
|
||||
@ -593,6 +594,7 @@ GA23 ga23(
|
||||
.vram_din(sdr_vram_data),
|
||||
.vram_req(sdr_vram_req),
|
||||
|
||||
.NL(NL),
|
||||
.large_tileset(board_cfg.large_tileset),
|
||||
|
||||
.sdr_data_a(sdr_bg_data_a),
|
||||
@ -696,6 +698,7 @@ sound sound(
|
||||
assign AUDIO_L = sound_sample;
|
||||
assign AUDIO_R = sound_sample;
|
||||
|
||||
`ifndef NO_EEPROM
|
||||
eeprom_28C64 eeprom(
|
||||
.clk(clk_sys),
|
||||
.reset(~reset_n),
|
||||
@ -720,5 +723,6 @@ eeprom_28C64 eeprom(
|
||||
.ioctl_din(ioctl_din),
|
||||
.ioctl_rd(ioctl_rd)
|
||||
);
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
@ -249,4 +249,5 @@ set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/CPU/v30/V30.qip
|
||||
set_global_assignment -name QIP_FILE ../../../common/Sound/jt51/jt51.qip
|
||||
set_global_assignment -name VERILOG_MACRO "JT51_ONLYTIMERS=1"
|
||||
set_global_assignment -name VERILOG_MACRO "NO_EEPROM=1"
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@ -33,6 +33,10 @@ use work.pReg_savestates.all;
|
||||
use work.whatever.all;
|
||||
|
||||
entity v30 is
|
||||
generic
|
||||
(
|
||||
INTACK_DELAY : integer := 22
|
||||
);
|
||||
port
|
||||
(
|
||||
clk : in std_logic;
|
||||
@ -460,7 +464,7 @@ begin
|
||||
cpu_halt <= halt;
|
||||
cpu_irqrequest <= irqrequest;
|
||||
cpu_prefix <= '1' when PrefixIP > 0 else '0';
|
||||
bus_prefetch <= '0' when (prefetchState = PREFETCH_IDLE or prefetchState = PREFETCH_RECEIVE) else '1';
|
||||
bus_prefetch <= '0' when (prefetchAllow = '0' or prefetchState = PREFETCH_IDLE or prefetchState = PREFETCH_RECEIVE) else '1';
|
||||
|
||||
canSpeedup <= '1';
|
||||
|
||||
@ -698,7 +702,7 @@ begin
|
||||
if (irqrequest = '1') then
|
||||
irqrequest <= '0';
|
||||
repeat <= '0';
|
||||
delay <= 22;
|
||||
delay <= INTACK_DELAY;
|
||||
cpustage <= CPUSTAGE_IRQVECTOR_REQ;
|
||||
pushlist <= REGPOS_f or REGPOS_cs or REGPOS_ip;
|
||||
poplist <= (others => '0');
|
||||
|
||||
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Reference in New Issue
Block a user