Move Midway 8080

Arcade_MiST/.gitignore

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+Test

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "280ZZZAP"

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.qsf

@@ -0,0 +1,172 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 20:51:02  August 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		280ZZZAP_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/D280ZZZAP_memory.sv
+set_global_assignment -name VHDL_FILE rtl/D280ZZZAP_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY D280ZZZAP_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------------
+# start ENTITY(D280ZZZAP_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(D280ZZZAP_mist)
+# --------------------------

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/280ZZZAP.sdc

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+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/README.txt

@@ -0,0 +1,27 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: 280zzzap port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+	
+

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/clean.bat

@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_Overlay.vhd

@@ -0,0 +1,111 @@
+--Datsun 280 ZZZAP Color Overlay Gehstock 2019
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity D280ZZZAP_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end D280ZZZAP_Overlay;
+
+architecture rtl of D280ZZZAP_Overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_B1      : boolean;
+	signal Overlay_B1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal col_data        : std_logic_vector(3 downto 0);
+	signal col_addr        : std_logic_vector(9 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_B1_VCnt <= false;
+	  Overlay_B1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt >= x"C4") then
+		  Overlay_B1_VCnt <= true;
+		else
+		  Overlay_B1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt <= x"0") and Overlay_B1_VCnt then
+		Overlay_B1 <= true;
+	  elsif (HCnt >= x"228") then
+		Overlay_B1 <= false;
+	  end if;
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_B1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_B1 then
+		VideoRGB  <= "001";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+  
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_memory.sv

@@ -0,0 +1,104 @@
+module D280ZZZAP_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [7:0]rom_data_5;
+
+
+sprom #(
+	.init_file("./roms/zzzap_h.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_0)
+	);
+	
+sprom #(
+	.init_file("./roms/zzzap_g.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_1)
+	);	
+
+sprom #(
+	.init_file("./roms/zzzap_f.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_2)
+	);
+	
+sprom #(
+	.init_file("./roms/zzzap_e.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_3)
+	);
+
+sprom #(
+	.init_file("./roms/zzzap_d.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_d (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_4)
+	);
+	
+sprom #(
+	.init_file("./roms/zzzap_c.hex"),
+	.widthad_a(10), 
+	.width_a(8))
+u_rom_c (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_5)
+	);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:10])
+			6'b000000 : Rom_out = rom_data_0; //0
+			6'b000001 : Rom_out = rom_data_1; //0400
+			6'b000010 : Rom_out = rom_data_2; //0800
+			6'b000011 : Rom_out = rom_data_3; //0c00		
+			6'b000100 : Rom_out = rom_data_4; //1000
+			6'b000101 : Rom_out = rom_data_5; //1400
+
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/D280ZZZAP_mist.sv

@@ -0,0 +1,228 @@
+module D280ZZZAP_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"280ZZZAP;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v0.00.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+/*
+Dip Switch:E3
+1		2		3		4		5		6		7		8		Function	Option
+Coinage
+On		On	 	 	 	 	 	 								1 Coin/1 Credit*
+Off	On	 	 	 	 	 	 								1 Coin/2 Credits
+On		Off	 	 	 	 	 	 							2 Coins/1 Credit
+Off	Off	 	 	 	 	 	 							2 Coins/3 Credits
+Game Time
+				Off	On	 	 	 	 						Test Mode
+When Extended Time At not set to None
+				Off	Off	 	 	 	 					60 seconds + 30 extended
+				On		On	 	 	 	 						80 seconds + 40 extended*
+				On		Off	 	 	 	 					99 seconds + 50 extended
+When Extended Time At set to None
+				Off	Off	 	 	 	 					60 seconds
+				On		On	 	 	 	 						80 seconds*
+				On		Off	 	 	 	 					99 seconds
+Extended Time At				
+								Off	On	 	 				2.00
+								On		On	 	 				2.50*
+								Off	Off	 	 			None
+								On		Off	 	 			None
+Language								
+												On		On		English*
+												On		Off	French
+												Off	On		German
+												Off	Off	Spanish
+*/
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP("00000000"),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+D280ZZZAP_memory D280ZZZAP_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+D280ZZZAP_Overlay D280ZZZAP_Overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T8080se.vhd

@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_ALU.vhd

@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Pack.vhd

@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/T80/T80_Reg.vhd

@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/build_id.tcl

@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders.vhd

@@ -0,0 +1,245 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+--IN0
+	GDB0(0) <= '0';	-- PEDAL
+	GDB0(1) <= '0';	-- PEDAL
+	GDB0(2) <= '0';	-- PEDAL
+	GDB0(3) <= '1';	-- PEDAL
+	GDB0(4) <= not Fire;	-- fire
+	GDB0(5) <= '1';	-- UNUSED
+	GDB0(6) <= not Coin;	-- coin
+	GDB0(7) <= not Sel1Player;	-- start
+--IN1
+	GDB1(0) <= '0';	-- steering wheel 
+	GDB1(1) <= '0';	-- steering wheel 
+	GDB1(2) <= '0';	-- steering wheel 
+	GDB1(3) <= '0';	-- steering wheel 
+	GDB1(4) <= '0';	-- steering wheel 
+	GDB1(5) <= '0';	-- steering wheel 
+	GDB1(6) <= '0';	-- steering wheel 
+	GDB1(7) <= '1';	-- steering wheel 
+--IN2
+	GDB2(0) <= '0';--Coinage
+	GDB2(1) <= '0';--Coinage
+	GDB2(2) <= '1';--Game_Time
+	GDB2(3) <= '1';--Game_Time
+	GDB2(4) <= '1';--Extended Time At
+	GDB2(5) <= '1';--Extended Time At
+	GDB2(6) <= '0';--Language
+	GDB2(7) <= '0';--Language
+	
+
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/invaders_audio.vhd

@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/mw8080.vhd

@@ -0,0 +1,335 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/pll.vhd

@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_c.hex

@@ -0,0 +1,65 @@
+:10000000821491141F139B14AA14BE145F13D014EE
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+:1003F00043484140454C40424F544FCEFFFFFFFF22
+:00000001FF

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_d.hex

@@ -0,0 +1,65 @@
+:10000000DB02070707E6065F1600195E2356C93AAA
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+:00000001FF

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_e.hex

@@ -0,0 +1,65 @@
+:10000000B60D3E033223203A4420324220F781CD00
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Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_f.hex

@@ -0,0 +1,65 @@
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Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_g.hex

@@ -0,0 +1,65 @@
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Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/roms/zzzap_h.hex

@@ -0,0 +1,65 @@
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Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/spram.vhd

@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;

Arcade_MiST/Midway-Taito 8080 Hardware/280ZZZAP_MiST/rtl/sprom.vhd

@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "BalloonBomber"

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf

@@ -0,0 +1,177 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 02:57:11  June 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		BalloonBomber_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY BalloonBomber_mist
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ---------------------------
+# start ENTITY(OzmaWars_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(OzmaWars_mist)
+# -------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_memory.sv
+set_global_assignment -name VHDL_FILE rtl/BalloonBomber_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+set_global_assignment -name VHDL_FILE rtl/roms/tn07.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn06.vhd
+set_global_assignment -name VHDL_FILE "rtl/roms/tn05-1.vhd"
+set_global_assignment -name VHDL_FILE rtl/roms/tn04.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn03.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn02.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/tn01.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/clean.bat

@@ -0,0 +1,16 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s build_id.v
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_Overlay.vhd

@@ -0,0 +1,366 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+
+--Not Cleaned, iam to lazy for this
+
+
+entity BalloonBomber_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		CAB               : in    std_logic_vector(9 downto 0);
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end BalloonBomber_Overlay;
+
+architecture rtl of BalloonBomber_Overlay is
+
+	signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_A1      : boolean;
+	signal Overlay_A1_VCnt : boolean;
+	signal Overlay_A2      : boolean;
+	signal Overlay_A3      : boolean;
+	signal Overlay_A3_VCnt : boolean;	
+	signal Overlay_A4      : boolean;
+	signal Overlay_A4_VCnt : boolean;	
+	
+	signal Overlay_R1      : boolean;
+	signal Overlay_R1_VCnt : boolean;
+	signal Overlay_R2      : boolean;
+	signal Overlay_R3      : boolean;
+
+	signal Overlay_Y1      : boolean;
+	signal Overlay_Y1_VCnt : boolean;
+	signal Overlay_Y2      : boolean;
+	signal Overlay_Y3      : boolean;
+	signal Overlay_Y4      : boolean;
+	signal Overlay_Y4_VCnt : boolean;	
+	signal Overlay_Y5      : boolean;	
+	signal Overlay_Y5_VCnt : boolean;
+
+	signal Overlay_G1      : boolean;
+	signal Overlay_G1_VCnt : boolean;	
+	signal Overlay_G2      : boolean;
+   signal Overlay_G3      : boolean;
+	signal Overlay_G4      : boolean;
+	signal Overlay_G4_VCnt : boolean;	
+
+   signal Overlay_P1      : boolean;
+	signal Overlay_P2      : boolean;
+	signal Overlay_P2_VCnt : boolean;	
+	signal Overlay_P3      : boolean;
+	signal Overlay_P3_VCnt : boolean;
+	signal Overlay_P4      : boolean;
+	signal Overlay_P4_VCnt : boolean;
+	
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal COLOR        : std_logic_vector(3 downto 0);
+
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  
+	  Overlay_G1 <= false;
+	  Overlay_G1_VCnt <= false;
+	  Overlay_G2 <= false;
+	  Overlay_G3 <= false;
+	  Overlay_G4 <= false;
+	  Overlay_G4_VCnt <= false;
+	  
+	  Overlay_A1 <= false;
+	  Overlay_A1_VCnt <= false;
+	  Overlay_A2 <= false;
+	  Overlay_A3 <= false;
+	  Overlay_A3_VCnt <= false;
+	  Overlay_A4 <= false;
+	  Overlay_A4_VCnt <= false;
+	  
+	  Overlay_R1 <= false;
+	  Overlay_R1_VCnt <= false;	  
+	  Overlay_R2 <= false;
+	  Overlay_R3 <= false;
+	  
+	  Overlay_Y1 <= false;
+	  Overlay_Y1_VCnt <= false;	  
+	  Overlay_Y2 <= false;
+	  Overlay_Y3 <= false;
+	  Overlay_Y4 <= false;
+	  Overlay_Y4_VCnt <= false;	  
+	  Overlay_Y5 <= false;
+	  Overlay_Y5_VCnt <= false;
+	  
+	  Overlay_P1 <= false;
+	  Overlay_P3 <= false;
+	  Overlay_P3_VCnt <= false;
+	  Overlay_P4 <= false;
+	  Overlay_P4_VCnt <= false;
+	  
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt >= 0) and (Vcnt <= 99) then
+		  Overlay_A1_VCnt <= true;
+		else
+		  Overlay_A1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 100) and (Vcnt <= 149 ) then
+		  Overlay_R1_VCnt <= true;
+		else
+		  Overlay_R1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 150) and (Vcnt <= 240) then
+		  Overlay_Y1_VCnt <= true;
+		else
+		  Overlay_Y1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 236) and (Vcnt <= 16) then
+		  Overlay_G1_VCnt <= true;
+		else
+		  Overlay_G1_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 0) and (Vcnt <= 72) then
+		  Overlay_G4_VCnt <= true;
+		  Overlay_Y5_VCnt <= true;
+		else
+		  Overlay_G4_VCnt <= false;
+		  Overlay_Y5_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 73) and (Vcnt <= 200) then
+		  Overlay_P3_VCnt <= true;
+		else
+		  Overlay_P3_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 224) and (Vcnt <= 230) then
+		  Overlay_P4_VCnt <= true;
+		else
+		  Overlay_P4_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 160) and (Vcnt <= 166 ) then
+		  Overlay_A3_VCnt <= true;
+		else
+		  Overlay_A3_VCnt <= false;
+		end if;
+
+		if (Vcnt >= 24 ) and (Vcnt <= 230 ) then
+		  Overlay_A4_VCnt <= true;
+		else
+		  Overlay_A4_VCnt <= false;
+		end if;
+	  
+	  	if (Vcnt >= 32 ) and (Vcnt <= 222 ) then
+		  Overlay_P2_VCnt <= true;
+		else
+		  Overlay_P2_VCnt <= false;
+		end if;
+	  end if;
+	  
+	  	if (Vcnt >= 42 ) and (Vcnt <= 216 ) then------------------------------------
+		  Overlay_Y4_VCnt <= true;
+		else
+		  Overlay_Y4_VCnt <= false;
+		end if;
+	  
+	  if (HCnt = 518)then--ok
+		if  Overlay_A1_VCnt then Overlay_A1 <= true; end if;
+		if  Overlay_R1_VCnt then Overlay_R1 <= true; end if;
+		if  Overlay_Y1_VCnt then Overlay_Y1 <= true; end if;
+	  elsif (HCnt >= 540) then
+		if  Overlay_A1_VCnt then Overlay_A1 <= false; end if;
+		if  Overlay_R1_VCnt then Overlay_R1 <= false; end if;
+		if  Overlay_Y1_VCnt then Overlay_Y1 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 528)then--check
+		if  Overlay_G1_VCnt then Overlay_G1 <= true; end if;
+	  elsif (HCnt >= 540) then
+		if  Overlay_G1_VCnt then Overlay_G1 <= false; end if;
+	  end if;
+	    
+	  if (HCnt = 486) then--ok
+		Overlay_R2 <= true;
+	  elsif (HCnt = 502) then
+		Overlay_R2 <= false;
+	  end if;
+
+	  if (HCnt = 438) then--ok
+		Overlay_Y2 <= true;
+	  elsif (HCnt = 470) then
+		Overlay_Y2 <= false;	
+	  end if;
+	  
+	  if (HCnt = 373) then--ok
+		Overlay_G2 <= true;
+	  elsif (HCnt = 445) then
+		Overlay_G2 <= false;
+	  end if;
+	  
+	  if (HCnt = 324) then--ok
+		Overlay_P1 <= true;
+	  elsif (HCnt = 380) then
+		Overlay_P1 <= false;
+	  end if;
+	  
+	  if (HCnt = 275) then--ok
+		Overlay_A2 <= true;
+	  elsif (HCnt = 327) then
+		Overlay_A2 <= false;
+	  end if;
+
+	  if (HCnt = 210) then--ok
+		Overlay_Y3 <= true;
+	  elsif (HCnt = 274) then
+		Overlay_Y3 <= false;
+	  end if;
+	  
+	  if (HCnt = 166) then--ok
+		Overlay_R3 <= true;
+	  elsif (HCnt = 214) then
+		Overlay_R3 <= false;
+	  end if;	  
+
+	  if (HCnt = 70) then--ok
+		Overlay_G3 <= true;
+	  elsif (HCnt = 170) then
+		Overlay_G3 <= false;
+	  end if;
+	  
+	  if (HCnt = 70) then--check
+		if  Overlay_P4_VCnt then Overlay_P4 <= true; end if;
+	  elsif (HCnt = 86) then
+		if  Overlay_P4_VCnt then Overlay_P4 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 0) then--ok
+		if  Overlay_Y5_VCnt then Overlay_Y5 <= true; end if;
+		if  Overlay_P3_VCnt then Overlay_P3 <= true; end if;
+	  elsif (HCnt = 70) then
+		if  Overlay_Y5_VCnt then Overlay_Y5 <= false; end if;
+		if  Overlay_P3_VCnt then Overlay_P3 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 164) then--check
+		if  Overlay_A3_VCnt then Overlay_A3 <= true; end if;
+	  elsif (HCnt = 172) then
+		if  Overlay_A3_VCnt then Overlay_A3 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 118) then--check
+		if  Overlay_A4_VCnt then Overlay_A4 <= true; end if;
+	  elsif (HCnt = 134) then
+		if  Overlay_A4_VCnt then Overlay_A4 <= false; end if;
+	  end if;
+	 
+	  if (HCnt = 102) then--check
+		if  Overlay_P2_VCnt then Overlay_P2 <= true; end if;
+	  elsif (HCnt = 118) then
+		if  Overlay_P2_VCnt then Overlay_P2 <= false; end if;
+	  end if;
+	  
+	  if (HCnt = 86) then--check
+		if  Overlay_Y4_VCnt then Overlay_Y4 <= true; end if;
+	  elsif (HCnt = 102) then
+		if  Overlay_Y4_VCnt then Overlay_Y4 <= false; end if;
+	  end if; 
+	  
+	  if (HCnt = 486) then--ok
+		if  Overlay_G4_VCnt then Overlay_G4 <= true; end if;
+	  elsif (HCnt = 470) then
+		if  Overlay_G4_VCnt then Overlay_G4 <= false; end if;
+	  end if;
+
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video)
+  begin
+	if (Video = '0') then
+		VideoRGB  <= "000";
+	elsif Overlay_R1 or Overlay_R2 or (Overlay_R3 and not Overlay_A3) then--Red      
+		VideoRGB  <= "100";
+	elsif Overlay_A1 or Overlay_A2 or Overlay_A3 or Overlay_A4 then--Aqua
+		VideoRGB  <= "011";
+	elsif (Overlay_Y1 and not Overlay_G1) or Overlay_Y2 or Overlay_Y3 or Overlay_Y4 or Overlay_Y5 then--Yellow
+		VideoRGB  <= "110";	
+	elsif Overlay_G1 or Overlay_G2 or (Overlay_G3 and not (Overlay_P4 or Overlay_A4 or Overlay_P2 or Overlay_Y4))-- or Overlay_G4 
+	then
+		VideoRGB  <= "010";	
+	elsif Overlay_P1 or Overlay_P2 or Overlay_P3 or Overlay_P4 then--Purple
+		VideoRGB  <= "101";		
+--	elsif not (Overlay_G4) then--white 
+	else
+		VideoRGB  <= "111";-- end if;
+	end if;
+  end process;
+  
+--colPROM: entity work.col
+--port map(
+--	clk  => Clk,
+--	addr => CAB, --should be Video Counters 
+--	data => COLOR
+--);
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  
+--  O_VIDEO_R <= COLOR(2);
+--  O_VIDEO_G <= COLOR(1);
+--  O_VIDEO_B <= COLOR(0);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_memory.sv

@@ -0,0 +1,72 @@
+
+module BalloonBomber_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+wire [7:0]rom_data_4;
+wire [10:0]rom_addr = {Addr[11:10],~Addr[9],Addr[8:4],~Addr[3],Addr[2:1],~Addr[0]};
+
+tn01 tn01 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_0)
+);
+
+tn02 tn02 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_1)
+);
+
+tn03 tn03 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_2)
+);
+
+tn04 tn04 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_3)
+);
+
+tn05_1 tn05_1 (
+	.clk(Clock),
+	.addr(rom_addr),
+	.data(rom_data_4)
+);
+	
+always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			5'b00011 : Rom_out = rom_data_3;
+			5'b01000 : Rom_out = rom_data_4;//0100 0000 0000 0000
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv

@@ -0,0 +1,208 @@
+module BalloonBomber_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"BallBomb;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_sys, clk_core;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hs, vs;
+wire 			r,g,b;
+
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.MoveUp(~m_up),
+	.MoveDown(~m_down),	
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+BalloonBomber_memory BalloonBomber_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+	
+BalloonBomber_Overlay BalloonBomber_Overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+			
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T8080se.vhd

@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_ALU.vhd

@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Pack.vhd

@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/T80/T80_Reg.vhd

@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/build_id.tcl

@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders.vhd

@@ -0,0 +1,281 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		MoveUp          : in  std_logic;
+		MoveDown        : in  std_logic;
+		DIP             : in  std_logic_vector(8 downto 1);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+	signal GDB_A        : unsigned(1 downto 0);
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => '1',--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+--	with AD_i(9 downto 8) select
+--		GDB <= GDB0 when "00",
+--				GDB1 when "01",
+--				GDB2 when "10",
+--				S when others;
+				
+			GDB_A <= not AD_i(9) & AD_i(8);
+
+	with GDB_A select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+	GDB0(0) <= '0';
+	GDB0(1) <= '0';
+	GDB0(2) <= '0';
+	GDB0(3) <= '0';
+	GDB0(4) <= not Fire;
+	GDB0(5) <= not MoveLeft;
+	GDB0(6) <= not MoveRight;
+	GDB0(7) <= '0';
+	
+	GDB1(0) <= Coin;
+	GDB1(1) <= not Sel2Player;
+	GDB1(2) <= not Sel1Player;
+	GDB1(3) <= '1';
+	GDB1(4) <= not Fire;--controller
+	GDB1(5) <= not MoveLeft;--controller
+	GDB1(6) <= not MoveRight;--controller
+	GDB1(7) <= '1';
+
+	GDB2(0) <= '0';--active high
+	GDB2(1) <= '0';--active high
+	GDB2(2) <= '0';--active high
+	GDB2(3) <= '0';--active high
+	GDB2(4) <= '0';--active high
+	GDB2(5) <= '0';--active high
+	GDB2(6) <= '0';--active high
+	GDB2(7) <= '0';--active high
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/invaders_audio.vhd

@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/mw8080.vhd

@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/pll.vhd

@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn01.vhd

@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn01 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn01 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"00",X"C3",X"18",X"00",X"00",X"00",X"FB",X"C9",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"E5",X"D5",X"C5",X"F5",X"C3",X"D8",X"04",X"FF",X"31",X"00",X"24",X"CD",X"76",X"01",X"06",X"00",
+		X"CD",X"BC",X"04",X"CD",X"C5",X"04",X"CD",X"D0",X"04",X"CD",X"4C",X"00",X"FB",X"AF",X"D3",X"03",
+		X"D3",X"05",X"CD",X"BC",X"00",X"CD",X"BB",X"01",X"CD",X"C1",X"00",X"CD",X"24",X"01",X"CD",X"01",
+		X"01",X"CD",X"BB",X"01",X"CD",X"55",X"00",X"D3",X"06",X"C3",X"2D",X"00",X"21",X"3C",X"09",X"CD",
+		X"7B",X"1A",X"C3",X"35",X"1B",X"CD",X"BA",X"04",X"CD",X"C5",X"04",X"21",X"2F",X"20",X"34",X"21",
+		X"E0",X"20",X"34",X"CD",X"52",X"1A",X"2E",X"06",X"06",X"12",X"70",X"2E",X"0A",X"70",X"2E",X"0E",
+		X"70",X"2E",X"12",X"70",X"2E",X"16",X"70",X"2E",X"1A",X"70",X"21",X"35",X"20",X"AF",X"BE",X"C2",
+		X"A5",X"00",X"CD",X"94",X"00",X"21",X"54",X"20",X"34",X"CD",X"DB",X"16",X"CD",X"18",X"12",X"D3",
+		X"06",X"C3",X"7A",X"00",X"21",X"14",X"20",X"AF",X"BE",X"C0",X"3A",X"01",X"20",X"E6",X"7F",X"C0",
+		X"23",X"23",X"36",X"01",X"C9",X"CD",X"9A",X"18",X"21",X"E0",X"20",X"36",X"00",X"CD",X"BA",X"04",
+		X"CD",X"C5",X"04",X"C3",X"C1",X"00",X"3E",X"FF",X"32",X"DF",X"20",X"C9",X"AF",X"32",X"DF",X"20",
+		X"C9",X"3E",X"50",X"C3",X"D5",X"14",X"21",X"05",X"26",X"11",X"D7",X"00",X"01",X"08",X"01",X"CD",
+		X"D5",X"01",X"06",X"17",X"C3",X"60",X"02",X"3C",X"42",X"99",X"A5",X"A5",X"81",X"42",X"3C",X"1B",
+		X"21",X"29",X"28",X"20",X"1B",X"13",X"00",X"08",X"13",X"0E",X"1B",X"02",X"0E",X"11",X"0F",X"0E",
+		X"11",X"00",X"13",X"08",X"0E",X"0D",X"01",X"0E",X"0C",X"01",X"04",X"11",X"3E",X"20",X"C3",X"D5",
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+		X"77",X"05",X"21",X"05",X"20",X"AF",X"BE",X"C8",X"CD",X"77",X"08",X"22",X"07",X"20",X"2A",X"09",
+		X"20",X"01",X"60",X"00",X"09",X"22",X"09",X"20",X"44",X"21",X"0B",X"20",X"AF",X"BE",X"C2",X"E7",
+		X"07",X"78",X"FE",X"2B",X"D2",X"32",X"08",X"23",X"AF",X"BE",X"C2",X"F3",X"07",X"78",X"FE",X"31",
+		X"D2",X"4D",X"08",X"23",X"AF",X"BE",X"C2",X"FF",X"07",X"78",X"FE",X"37",X"D2",X"5B",X"08",X"23");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn02.vhd

@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn02 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn02 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"AF",X"BE",X"C2",X"0B",X"08",X"78",X"FE",X"3E",X"D2",X"69",X"08",X"78",X"FE",X"3C",X"DA",X"25",
+		X"08",X"2A",X"09",X"20",X"01",X"1E",X"02",X"CD",X"8C",X"08",X"21",X"05",X"20",X"36",X"00",X"21",
+		X"BF",X"20",X"36",X"00",X"C9",X"2A",X"07",X"20",X"EB",X"2A",X"09",X"20",X"01",X"1E",X"02",X"C3",
+		X"D5",X"01",X"36",X"FF",X"21",X"05",X"21",X"CD",X"A0",X"08",X"EB",X"2E",X"06",X"CD",X"52",X"1A",
+		X"E5",X"C1",X"0A",X"6F",X"03",X"0A",X"67",X"CD",X"D2",X"01",X"C3",X"25",X"08",X"36",X"FF",X"21",
+		X"09",X"21",X"CD",X"A0",X"08",X"EB",X"2E",X"0A",X"C3",X"3D",X"08",X"36",X"FF",X"21",X"0D",X"21",
+		X"CD",X"A0",X"08",X"EB",X"2E",X"0E",X"C3",X"3D",X"08",X"36",X"FF",X"21",X"11",X"21",X"CD",X"A0",
+		X"08",X"EB",X"2E",X"12",X"C3",X"3D",X"08",X"21",X"06",X"20",X"34",X"7E",X"E6",X"01",X"C2",X"85",
+		X"08",X"21",X"72",X"40",X"C9",X"21",X"36",X"40",X"C9",X"01",X"20",X"03",X"AF",X"C5",X"E5",X"77",
+		X"23",X"05",X"C2",X"8F",X"08",X"E1",X"01",X"20",X"00",X"09",X"C1",X"0D",X"C2",X"8D",X"08",X"C9",
+		X"7E",X"21",X"1D",X"41",X"3D",X"C8",X"11",X"60",X"00",X"19",X"C3",X"A4",X"08",X"AF",X"7C",X"1F",
+		X"57",X"7D",X"1F",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"5F",X"7A",X"E6",X"0F",X"07",X"07",X"07",
+		X"07",X"B3",X"C9",X"11",X"DD",X"43",X"06",X"02",X"C3",X"AD",X"0E",X"11",X"DD",X"43",X"06",X"02",
+		X"C3",X"9A",X"19",X"CD",X"38",X"14",X"CD",X"53",X"14",X"CD",X"40",X"10",X"CD",X"42",X"09",X"CD",
+		X"F8",X"08",X"CD",X"65",X"09",X"3A",X"E4",X"20",X"A7",X"CA",X"22",X"05",X"CD",X"89",X"1A",X"CD",
+		X"13",X"09",X"CD",X"35",X"1B",X"C3",X"22",X"05",X"21",X"1F",X"20",X"7E",X"A7",X"C8",X"46",X"36",
+		X"00",X"21",X"24",X"20",X"7E",X"0F",X"D0",X"36",X"00",X"2A",X"22",X"20",X"EB",X"21",X"38",X"20",
+		X"C3",X"0D",X"0A",X"CD",X"52",X"1A",X"2E",X"24",X"7E",X"FE",X"03",X"D8",X"21",X"BF",X"20",X"AF",
+		X"BE",X"C0",X"34",X"21",X"35",X"09",X"C3",X"7B",X"1A",X"00",X"00",X"07",X"07",X"01",X"00",X"01",
+		X"00",X"06",X"06",X"01",X"00",X"00",X"00",X"04",X"04",X"01",X"00",X"00",X"02",X"00",X"01",X"01",
+		X"01",X"00",X"3A",X"E4",X"20",X"A7",X"C8",X"21",X"38",X"20",X"7E",X"FE",X"FF",X"CA",X"60",X"09",
+		X"0F",X"D2",X"59",X"09",X"3E",X"10",X"C3",X"0E",X"02",X"23",X"23",X"23",X"23",X"C3",X"4A",X"09",
+		X"3E",X"10",X"C3",X"17",X"02",X"21",X"04",X"20",X"34",X"7E",X"E6",X"03",X"77",X"A7",X"CA",X"28",
+		X"19",X"FE",X"01",X"CA",X"38",X"19",X"FE",X"02",X"CA",X"66",X"19",X"FE",X"03",X"CA",X"85",X"19",
+		X"C9",X"21",X"38",X"20",X"CD",X"21",X"0A",X"21",X"3C",X"20",X"CD",X"21",X"0A",X"11",X"9D",X"20",
+		X"CD",X"DF",X"09",X"CD",X"07",X"13",X"CD",X"6A",X"0A",X"C3",X"D9",X"09",X"21",X"40",X"20",X"CD",
+		X"21",X"0A",X"21",X"44",X"20",X"CD",X"21",X"0A",X"11",X"9E",X"20",X"CD",X"DF",X"09",X"2E",X"0C",
+		X"CD",X"52",X"1A",X"CD",X"6A",X"0A",X"CD",X"D9",X"09",X"C3",X"15",X"15",X"21",X"48",X"20",X"CD",
+		X"21",X"0A",X"21",X"4C",X"20",X"CD",X"21",X"0A",X"11",X"9F",X"20",X"CD",X"DF",X"09",X"2E",X"14",
+		X"CD",X"52",X"1A",X"CD",X"6A",X"0A",X"C3",X"D9",X"09",X"21",X"9C",X"20",X"36",X"00",X"C9",X"21",
+		X"9B",X"20",X"7E",X"A7",X"CA",X"EB",X"09",X"23",X"36",X"00",X"C9",X"EB",X"34",X"7E",X"FE",X"02",
+		X"D2",X"F8",X"09",X"EB",X"23",X"36",X"FF",X"C9",X"36",X"00",X"EB",X"23",X"36",X"00",X"C9",X"57",
+		X"3A",X"9C",X"20",X"A7",X"7A",X"C2",X"0A",X"0A",X"37",X"C9",X"37",X"3F",X"C9",X"78",X"3D",X"CA",
+		X"19",X"0A",X"23",X"23",X"23",X"23",X"C3",X"0E",X"0A",X"36",X"01",X"23",X"23",X"73",X"23",X"72",
+		X"C9",X"7E",X"0F",X"D0",X"23",X"23",X"E5",X"CD",X"6C",X"11",X"CD",X"5B",X"0A",X"E1",X"E5",X"CD",
+		X"6C",X"11",X"7D",X"FE",X"18",X"DA",X"48",X"0A",X"01",X"F9",X"FF",X"09",X"EB",X"E1",X"73",X"23",
+		X"72",X"EB",X"11",X"DA",X"43",X"C3",X"CF",X"0E",X"E1",X"E5",X"CD",X"6C",X"11",X"22",X"B7",X"20",
+		X"E1",X"2B",X"AF",X"77",X"2B",X"77",X"21",X"B5",X"20",X"34",X"C9",X"11",X"DA",X"43",X"C3",X"AB",
+		X"0E",X"7C",X"B5",X"37",X"C8",X"7B",X"95",X"7A",X"9C",X"C9",X"E5",X"7E",X"47",X"07",X"D2",X"8A",
+		X"0A",X"23",X"23",X"CD",X"15",X"0B",X"78",X"0F",X"0F",X"7A",X"D2",X"DA",X"0A",X"FE",X"4B",X"DA",
+		X"A1",X"0A",X"36",X"25",X"E1",X"E5",X"3E",X"DF",X"A6",X"77",X"21",X"37",X"20",X"34",X"E1",X"23",
+		X"23",X"23",X"23",X"3A",X"37",X"20",X"FE",X"02",X"DA",X"6A",X"0A",X"21",X"37",X"20",X"36",X"00",
+		X"C9",X"FE",X"3C",X"D2",X"CC",X"0A",X"78",X"0F",X"E1",X"E5",X"23",X"7E",X"23",X"4E",X"23",X"46",
+		X"2B",X"2B",X"DA",X"2F",X"0B",X"CD",X"FF",X"09",X"D2",X"BF",X"0A",X"3D",X"CA",X"23",X"0B",X"77",
+		X"CD",X"A1",X"08",X"EB",X"60",X"69",X"CD",X"D2",X"01",X"C3",X"8A",X"0A",X"E1",X"E5",X"CD",X"03",
+		X"0B",X"E1",X"E5",X"7E",X"0F",X"0F",X"0F",X"C3",X"8A",X"0A",X"2B",X"2B",X"2B",X"FE",X"25",X"DA",
+		X"EE",X"0A",X"FE",X"3C",X"DA",X"FB",X"0A",X"7E",X"0F",X"0F",X"0F",X"C3",X"8A",X"0A",X"CD",X"08",
+		X"0B",X"E1",X"E5",X"23",X"23",X"23",X"36",X"48",X"C3",X"8A",X"0A",X"46",X"3E",X"DF",X"A6",X"77",
+		X"C3",X"A6",X"0A",X"7E",X"07",X"07",X"07",X"D8",X"3E",X"20",X"B6",X"77",X"23",X"23",X"5E",X"23",
+		X"56",X"EB",X"C3",X"89",X"08",X"E5",X"5E",X"23",X"56",X"2A",X"28",X"21",X"19",X"EB",X"E1",X"73",
+		X"23",X"72",X"C9",X"36",X"01",X"2B",X"3E",X"01",X"B6",X"77",X"3E",X"01",X"C3",X"C0",X"0A",X"CD",
+		X"FF",X"09",X"D2",X"BF",X"0A",X"3C",X"FE",X"08",X"DA",X"BF",X"0A",X"36",X"07",X"2B",X"3E",X"FE",
+		X"A6",X"77",X"3E",X"07",X"C3",X"C0",X"0A",X"CD",X"56",X"0B",X"CD",X"AB",X"0B",X"CD",X"D6",X"0B",
+		X"CD",X"40",X"15",X"C3",X"27",X"16",X"AF",X"21",X"B5",X"20",X"BE",X"C8",X"23",X"34",X"7E",X"FE",
+		X"01",X"CA",X"01",X"0C",X"FE",X"04",X"CA",X"07",X"0C",X"FE",X"07",X"D8",X"11",X"3C",X"44",X"CD",
+		X"0A",X"0C",X"CD",X"E0",X"15",X"21",X"B8",X"20",X"D2",X"81",X"0B",X"CD",X"9B",X"0B",X"C3",X"84",
+		X"0B",X"CD",X"8B",X"0B",X"21",X"00",X"00",X"22",X"B5",X"20",X"C9",X"AF",X"3A",X"34",X"20",X"BE",
+		X"D8",X"7E",X"21",X"7D",X"20",X"BE",X"D8",X"77",X"C3",X"0D",X"16",X"AF",X"3A",X"34",X"20",X"BE",
+		X"D0",X"7E",X"21",X"7F",X"20",X"BE",X"D0",X"77",X"C3",X"ED",X"15",X"AF",X"21",X"1D",X"20",X"BE",
+		X"C8",X"23",X"34",X"7E",X"FE",X"01",X"CA",X"16",X"0C",X"FE",X"04",X"CA",X"1C",X"0C",X"FE",X"07",
+		X"D8",X"2A",X"22",X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00",
+		X"22",X"1D",X"20",X"C3",X"7D",X"15",X"AF",X"21",X"27",X"20",X"BE",X"C8",X"23",X"34",X"7E",X"FE",
+		X"01",X"CA",X"2B",X"0C",X"FE",X"04",X"CA",X"47",X"0C",X"FE",X"07",X"D8",X"2A",X"2D",X"20",X"01",
+		X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00",X"22",X"27",X"20",X"CD",X"6F",X"1A",X"C3",X"7D",
+		X"15",X"11",X"0C",X"44",X"C3",X"0A",X"0C",X"11",X"24",X"44",X"2A",X"B7",X"20",X"CD",X"76",X"03",
+		X"01",X"0C",X"02",X"C3",X"D5",X"01",X"11",X"54",X"44",X"C3",X"1F",X"0C",X"11",X"74",X"44",X"2A",
+		X"22",X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"C3",X"D5",X"01",X"2A",X"29",X"20",X"11",X"DA",
+		X"43",X"CD",X"AD",X"0E",X"2A",X"29",X"20",X"CD",X"76",X"03",X"22",X"2D",X"20",X"11",X"94",X"44",
+		X"01",X"10",X"02",X"CD",X"D5",X"01",X"C9",X"2A",X"2D",X"20",X"11",X"B4",X"44",X"C3",X"40",X"0C",
+		X"3A",X"E4",X"20",X"A7",X"C8",X"3A",X"DB",X"20",X"0F",X"DB",X"01",X"D0",X"DB",X"02",X"C9",X"21",
+		X"2F",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"6E",X"0C",X"34",X"CD",X"E4",X"0C",X"3A",X"E4",
+		X"20",X"A7",X"C2",X"9D",X"0C",X"2A",X"E2",X"20",X"3A",X"E1",X"20",X"3C",X"32",X"E1",X"20",X"E6",
+		X"0F",X"C2",X"8B",X"0C",X"7D",X"FE",X"13",X"CC",X"9A",X"0C",X"23",X"22",X"E2",X"20",X"7E",X"0F",
+		X"DA",X"06",X"0D",X"0F",X"DA",X"23",X"0D",X"C3",X"A9",X"0C",X"2E",X"00",X"C9",X"CD",X"50",X"0C",
+		X"07",X"07",X"DA",X"06",X"0D",X"07",X"DA",X"23",X"0D",X"06",X"00",X"21",X"32",X"20",X"70",X"CD",
+		X"E4",X"0C",X"21",X"31",X"20",X"CD",X"A1",X"0D",X"2A",X"33",X"20",X"11",X"BE",X"43",X"01",X"02",
+		X"0E",X"CD",X"71",X"03",X"C5",X"E5",X"1A",X"A6",X"CA",X"D0",X"0C",X"3E",X"01",X"32",X"35",X"20",
+		X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"C6",X"0C",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",
+		X"C2",X"C4",X"0C",X"C9",X"2A",X"33",X"20",X"11",X"BE",X"43",X"01",X"02",X"0E",X"CD",X"71",X"03",
+		X"C5",X"E5",X"1A",X"AE",X"77",X"23",X"13",X"0D",X"C2",X"F2",X"0C",X"E1",X"01",X"20",X"00",X"09",
+		X"C1",X"05",X"C2",X"F0",X"0C",X"C9",X"3A",X"34",X"20",X"FE",X"DA",X"D2",X"A9",X"0C",X"2A",X"33",
+		X"20",X"01",X"F8",X"0F",X"09",X"CD",X"76",X"03",X"7E",X"FE",X"7F",X"C2",X"A9",X"0C",X"06",X"02",
+		X"C3",X"AB",X"0C",X"3A",X"34",X"20",X"FE",X"38",X"DA",X"A9",X"0C",X"2A",X"33",X"20",X"01",X"F8",
+		X"FC",X"09",X"CD",X"76",X"03",X"7E",X"FE",X"7F",X"C2",X"A9",X"0C",X"06",X"FE",X"C3",X"AB",X"0C",
+		X"23",X"23",X"5E",X"23",X"7E",X"C6",X"02",X"57",X"EB",X"CD",X"AD",X"08",X"57",X"7D",X"E6",X"1F",
+		X"07",X"07",X"07",X"5F",X"EB",X"C9",X"21",X"54",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"73",
+		X"0D",X"34",X"23",X"BE",X"21",X"00",X"FD",X"22",X"58",X"20",X"21",X"C8",X"D0",X"C4",X"1A",X"0E",
+		X"22",X"5A",X"20",X"3A",X"56",X"20",X"A7",X"21",X"5B",X"20",X"7E",X"C2",X"AD",X"0D",X"FE",X"28",
+		X"DA",X"C9",X"0D",X"21",X"57",X"20",X"34",X"E6",X"01",X"21",X"AE",X"40",X"CC",X"C1",X"0D",X"22",
+		X"5C",X"20",X"21",X"5A",X"20",X"CD",X"F0",X"0D",X"CD",X"02",X"0E",X"CD",X"24",X"0E",X"21",X"58",
+		X"20",X"4E",X"23",X"46",X"23",X"79",X"86",X"77",X"23",X"78",X"86",X"77",X"C9",X"FE",X"D0",X"D2",
+		X"C9",X"0D",X"21",X"57",X"20",X"34",X"E6",X"01",X"21",X"36",X"40",X"CC",X"C5",X"0D",X"C3",X"8F",
+		X"0D",X"21",X"E5",X"40",X"C9",X"21",X"72",X"40",X"C9",X"2A",X"5A",X"20",X"01",X"1B",X"02",X"CD",
+		X"76",X"03",X"CD",X"8C",X"08",X"06",X"0C",X"21",X"54",X"46",X"11",X"54",X"20",X"CD",X"8B",X"03",
+		X"21",X"13",X"20",X"34",X"7E",X"E6",X"01",X"21",X"56",X"20",X"36",X"01",X"C0",X"36",X"00",X"C9",
+		X"E5",X"23",X"23",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"E1",X"D5",X"5E",X"23",X"56",X"EB",
+		X"D1",X"C9",X"CD",X"76",X"03",X"C5",X"E5",X"1A",X"77",X"23",X"13",X"0D",X"C2",X"07",X"0E",X"E1",
+		X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"05",X"0E",X"C9",X"21",X"00",X"03",X"22",X"58",X"20",
+		X"21",X"C8",X"28",X"C9",X"3A",X"56",X"20",X"A7",X"C2",X"A1",X"0E",X"CD",X"35",X"0E",X"D6",X"0A",
+		X"B8",X"DA",X"3D",X"0E",X"C9",X"2A",X"34",X"20",X"44",X"3A",X"0A",X"20",X"C9",X"21",X"B0",X"20",
+		X"AF",X"BE",X"CA",X"47",X"0E",X"35",X"C9",X"E5",X"CD",X"4B",X"1A",X"23",X"7E",X"FE",X"04",X"06",
+		X"50",X"D2",X"56",X"0E",X"06",X"60",X"E1",X"70",X"FE",X"0B",X"D2",X"7A",X"0E",X"FE",X"09",X"CD",
+		X"52",X"1A",X"2E",X"24",X"7E",X"FE",X"04",X"D2",X"8F",X"0E",X"21",X"60",X"20",X"34",X"2E",X"67",
+		X"34",X"2E",X"6E",X"34",X"21",X"95",X"20",X"36",X"00",X"C9",X"21",X"FB",X"03",X"22",X"63",X"20",
+		X"21",X"FA",X"02",X"22",X"6A",X"20",X"21",X"FB",X"FA",X"22",X"71",X"20",X"C3",X"6A",X"0E",X"21",
+		X"FC",X"02",X"22",X"63",X"20",X"21",X"FB",X"01",X"22",X"6A",X"20",X"21",X"FB",X"FD",X"C3",X"89",
+		X"0E",X"CD",X"35",X"0E",X"C6",X"08",X"B8",X"D2",X"3D",X"0E",X"C9",X"06",X"03",X"CD",X"71",X"03",
+		X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"2F",X"A6",X"77",X"23",X"13",X"AF",X"D3",X"04",X"DB",
+		X"03",X"2F",X"A6",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"B0",X"0E",X"C9",X"06",
+		X"03",X"CD",X"71",X"03",X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"AE",X"77",X"23",X"13",X"AF",
+		X"D3",X"04",X"DB",X"03",X"AE",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"D4",X"0E",
+		X"C9",X"21",X"60",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"FE",X"0E",X"35",X"C9",X"23",X"BE",
+		X"C2",X"0A",X"0F",X"34",X"CD",X"33",X"0F",X"22",X"65",X"20",X"CD",X"3B",X"0F",X"21",X"66",X"20",
+		X"7E",X"FE",X"30",X"DC",X"46",X"0F",X"FE",X"E8",X"D4",X"53",X"0F",X"2B",X"7E",X"FE",X"18",X"DA",
+		X"5E",X"0F",X"21",X"63",X"20",X"CD",X"A1",X"0D",X"2A",X"65",X"20",X"11",X"DA",X"0F",X"06",X"08",
+		X"C3",X"D1",X"0E",X"2A",X"5A",X"20",X"01",X"00",X"08",X"09",X"C9",X"2A",X"65",X"20",X"11",X"DA",
+		X"0F",X"06",X"08",X"C3",X"AD",X"0E",X"F5",X"E5",X"2A",X"65",X"20",X"CD",X"3E",X"0F",X"E1",X"36",
+		X"E0",X"F1",X"C9",X"E5",X"2A",X"65",X"20",X"CD",X"3E",X"0F",X"E1",X"36",X"34",X"C9",X"CD",X"3B",
+		X"0F",X"21",X"60",X"46",X"11",X"60",X"20",X"06",X"07",X"C3",X"8B",X"03",X"21",X"67",X"20",X"AF",
+		X"BE",X"C8",X"23",X"BE",X"CA",X"79",X"0F",X"35",X"C9",X"23",X"BE",X"C2",X"85",X"0F",X"34",X"CD",
+		X"33",X"0F",X"22",X"6C",X"20",X"2A",X"6C",X"20",X"CD",X"3E",X"0F",X"21",X"6D",X"20",X"7E",X"FE",
+		X"30",X"DC",X"BC",X"0F",X"FE",X"E8",X"D4",X"C4",X"0F",X"2B",X"7E",X"47",X"CD",X"52",X"1A",X"2E",
+		X"24",X"7E",X"FE",X"05",X"0E",X"13",X"D2",X"AB",X"0F",X"0E",X"18",X"78",X"B9",X"DA",X"CB",X"0F",
+		X"21",X"6A",X"20",X"CD",X"A1",X"0D",X"2A",X"6C",X"20",X"C3",X"2B",X"0F",X"F5",X"E5",X"2A",X"6C",
+		X"20",X"C3",X"57",X"0F",X"E5",X"2A",X"6C",X"20",X"C3",X"4B",X"0F",X"2A",X"6C",X"20",X"CD",X"3E",
+		X"0F",X"21",X"67",X"46",X"11",X"67",X"20",X"C3",X"67",X"0F",X"60",X"F0",X"F0",X"F0",X"F0",X"60",
+		X"90",X"90",X"21",X"6E",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"CA",X"EF",X"0F",X"35",X"C9",X"23",
+		X"BE",X"C2",X"FB",X"0F",X"34",X"CD",X"33",X"0F",X"22",X"73",X"20",X"2A",X"73",X"20",X"CD",X"3E");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn03.vhd

@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn03 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn03 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"21",X"74",X"20",X"7E",X"FE",X"30",X"DC",X"22",X"10",X"FE",X"E8",X"D4",X"2A",X"10",X"2B",
+		X"7E",X"FE",X"18",X"DA",X"31",X"10",X"21",X"71",X"20",X"CD",X"A1",X"0D",X"2A",X"73",X"20",X"C3",
+		X"2B",X"0F",X"F5",X"E5",X"2A",X"73",X"20",X"C3",X"4B",X"0F",X"E5",X"2A",X"73",X"20",X"C3",X"57",
+		X"0F",X"2A",X"73",X"20",X"CD",X"3E",X"0F",X"21",X"6E",X"46",X"11",X"6E",X"20",X"C3",X"67",X"0F",
+		X"21",X"11",X"20",X"AF",X"BE",X"C8",X"36",X"00",X"21",X"14",X"20",X"34",X"21",X"00",X"00",X"22",
+		X"16",X"20",X"2A",X"1A",X"20",X"CD",X"C3",X"08",X"21",X"60",X"20",X"AF",X"BE",X"CA",X"B0",X"10",
+		X"21",X"65",X"20",X"CD",X"8F",X"10",X"D4",X"6C",X"10",X"C3",X"B0",X"10",X"CD",X"96",X"10",X"DA",
+		X"73",X"10",X"C9",X"CD",X"9D",X"10",X"D2",X"7A",X"10",X"C9",X"CD",X"A9",X"10",X"DA",X"81",X"10",
+		X"C9",X"E1",X"2A",X"65",X"20",X"22",X"93",X"20",X"21",X"91",X"20",X"34",X"C3",X"5E",X"0F",X"3A",
+		X"1A",X"20",X"C6",X"08",X"BE",X"C9",X"F5",X"3E",X"10",X"86",X"C3",X"A5",X"10",X"3A",X"1B",X"20",
+		X"23",X"F5",X"7E",X"D6",X"08",X"47",X"F1",X"B8",X"C9",X"F5",X"3E",X"10",X"86",X"C3",X"A5",X"10",
+		X"21",X"67",X"20",X"AF",X"BE",X"CA",X"E7",X"10",X"21",X"6C",X"20",X"CD",X"8F",X"10",X"D4",X"C4",
+		X"10",X"C3",X"E7",X"10",X"CD",X"96",X"10",X"DA",X"CB",X"10",X"C9",X"CD",X"9D",X"10",X"D2",X"D2",
+		X"10",X"C9",X"CD",X"A9",X"10",X"DA",X"D9",X"10",X"C9",X"E1",X"2A",X"6C",X"20",X"22",X"93",X"20",
+		X"21",X"91",X"20",X"34",X"C3",X"CB",X"0F",X"21",X"6E",X"20",X"AF",X"BE",X"CA",X"1E",X"11",X"21",
+		X"73",X"20",X"CD",X"8F",X"10",X"D4",X"FB",X"10",X"C3",X"1E",X"11",X"CD",X"96",X"10",X"DA",X"02",
+		X"11",X"C9",X"CD",X"9D",X"10",X"D2",X"09",X"11",X"C9",X"CD",X"A9",X"10",X"DA",X"10",X"11",X"C9",
+		X"E1",X"2A",X"73",X"20",X"22",X"93",X"20",X"21",X"91",X"20",X"34",X"C3",X"31",X"10",X"21",X"38",
+		X"20",X"22",X"75",X"20",X"0E",X"06",X"7E",X"A7",X"CA",X"33",X"11",X"23",X"23",X"CD",X"8F",X"10",
+		X"D4",X"44",X"11",X"2A",X"75",X"20",X"11",X"04",X"00",X"19",X"22",X"75",X"20",X"0D",X"C2",X"26",
+		X"11",X"C3",X"71",X"11",X"CD",X"96",X"10",X"DA",X"4B",X"11",X"C9",X"CD",X"9D",X"10",X"D2",X"52",
+		X"11",X"C9",X"CD",X"A9",X"10",X"DA",X"59",X"11",X"C9",X"F1",X"2B",X"2B",X"2B",X"36",X"00",X"CD",
+		X"6A",X"11",X"22",X"29",X"20",X"21",X"27",X"20",X"34",X"C9",X"23",X"23",X"5E",X"23",X"56",X"EB",
+		X"C9",X"CD",X"07",X"13",X"22",X"77",X"20",X"0E",X"06",X"E5",X"21",X"1F",X"20",X"34",X"E1",X"7E",
+		X"07",X"DC",X"9D",X"11",X"2A",X"77",X"20",X"11",X"04",X"00",X"19",X"22",X"77",X"20",X"0D",X"C2",
+		X"79",X"11",X"21",X"1F",X"20",X"36",X"00",X"CD",X"E2",X"14",X"C3",X"7D",X"15",X"CD",X"6A",X"11",
+		X"7C",X"FE",X"3C",X"D0",X"C5",X"CD",X"49",X"0D",X"22",X"79",X"20",X"C1",X"21",X"79",X"20",X"3A",
+		X"1A",X"20",X"C6",X"0A",X"BE",X"D2",X"B9",X"11",X"C9",X"F5",X"3E",X"20",X"86",X"47",X"F1",X"B8",
+		X"DA",X"C4",X"11",X"C9",X"3A",X"1B",X"20",X"23",X"F5",X"7E",X"D6",X"08",X"47",X"F1",X"B8",X"D2",
+		X"D3",X"11",X"C9",X"F5",X"3E",X"23",X"86",X"47",X"F1",X"B8",X"DA",X"DE",X"11",X"C9",X"F1",X"E5",
+		X"21",X"1D",X"20",X"34",X"2A",X"1A",X"20",X"01",X"00",X"F6",X"09",X"22",X"22",X"20",X"2A",X"77",
+		X"20",X"7E",X"E6",X"0F",X"77",X"CD",X"6A",X"11",X"CD",X"89",X"08",X"E1",X"2B",X"3E",X"05",X"86",
+		X"47",X"3A",X"1A",X"20",X"B8",X"D2",X"0E",X"12",X"CD",X"67",X"1A",X"C3",X"0C",X"13",X"21",X"24",
+		X"20",X"34",X"CD",X"5F",X"1A",X"C3",X"0C",X"13",X"2E",X"24",X"CD",X"52",X"1A",X"7E",X"FE",X"06",
+		X"D2",X"24",X"12",X"C9",X"E5",X"3A",X"1D",X"20",X"A7",X"D3",X"06",X"C2",X"25",X"12",X"E1",X"36",
+		X"00",X"CD",X"0D",X"19",X"CD",X"4C",X"00",X"21",X"7B",X"20",X"34",X"21",X"00",X"46",X"11",X"00",
+		X"20",X"06",X"31",X"CD",X"8B",X"03",X"21",X"35",X"46",X"11",X"35",X"20",X"06",X"46",X"CD",X"8B",
+		X"03",X"21",X"81",X"46",X"11",X"81",X"20",X"06",X"3F",X"CD",X"8B",X"03",X"21",X"14",X"20",X"34",
+		X"CD",X"1E",X"14",X"CD",X"52",X"1A",X"2E",X"26",X"34",X"7E",X"47",X"0F",X"DA",X"71",X"12",X"2B",
+		X"34",X"78",X"FE",X"08",X"CC",X"13",X"13",X"FE",X"0F",X"CC",X"13",X"13",X"CD",X"AD",X"12",X"CD",
+		X"07",X"13",X"23",X"23",X"5E",X"23",X"56",X"21",X"09",X"20",X"73",X"23",X"72",X"3E",X"30",X"CD",
+		X"D5",X"14",X"21",X"05",X"20",X"34",X"7E",X"A7",X"D3",X"06",X"C2",X"96",X"12",X"21",X"7B",X"20",
+		X"36",X"00",X"2E",X"2F",X"34",X"2E",X"14",X"36",X"00",X"CD",X"78",X"1A",X"C9",X"CD",X"52",X"1A",
+		X"2E",X"25",X"7E",X"FE",X"0B",X"DA",X"BB",X"12",X"3E",X"03",X"77",X"47",X"FE",X"07",X"DA",X"C3",
+		X"12",X"06",X"06",X"3E",X"18",X"D6",X"03",X"05",X"C2",X"C5",X"12",X"4F",X"CD",X"07",X"13",X"23",
+		X"23",X"EB",X"69",X"26",X"27",X"CD",X"00",X"03",X"2E",X"25",X"CD",X"52",X"1A",X"7E",X"0F",X"0F",
+		X"11",X"E8",X"44",X"DA",X"E9",X"12",X"11",X"F8",X"44",X"CD",X"07",X"13",X"CD",X"EF",X"02",X"CD",
+		X"07",X"13",X"7E",X"0F",X"0F",X"01",X"20",X"00",X"DA",X"FE",X"12",X"01",X"E0",X"FF",X"21",X"28",
+		X"21",X"71",X"23",X"70",X"C3",X"BC",X"00",X"2E",X"04",X"C3",X"52",X"1A",X"2E",X"24",X"CD",X"52",
+		X"1A",X"34",X"C9",X"F5",X"3E",X"FF",X"CD",X"04",X"02",X"3E",X"04",X"CD",X"FB",X"01",X"CD",X"C1",
+		X"00",X"3E",X"20",X"CD",X"FB",X"01",X"CD",X"83",X"1A",X"CD",X"BC",X"00",X"CD",X"69",X"13",X"3E",
+		X"04",X"CD",X"04",X"02",X"2E",X"26",X"CD",X"52",X"1A",X"7E",X"0F",X"DA",X"49",X"13",X"21",X"12",
+		X"30",X"11",X"14",X"40",X"06",X"04",X"C3",X"51",X"13",X"21",X"12",X"2D",X"11",X"18",X"40",X"06",
+		X"0A",X"CD",X"60",X"02",X"CD",X"B6",X"00",X"CD",X"4C",X"00",X"3E",X"80",X"CD",X"D5",X"14",X"CD",
+		X"92",X"13",X"21",X"30",X"20",X"36",X"00",X"F1",X"C9",X"21",X"03",X"24",X"22",X"2D",X"21",X"21",
+		X"1C",X"40",X"22",X"2F",X"21",X"0E",X"71",X"C5",X"2A",X"2D",X"21",X"CD",X"BB",X"13",X"22",X"2D",
+		X"21",X"2A",X"2F",X"21",X"CD",X"CF",X"13",X"22",X"2F",X"21",X"C1",X"0D",X"C2",X"77",X"13",X"CD",
+		X"FC",X"00",X"0E",X"79",X"21",X"1C",X"33",X"22",X"2D",X"21",X"21",X"03",X"32",X"22",X"2F",X"21",
+		X"C5",X"AF",X"2A",X"2D",X"21",X"CD",X"D1",X"13",X"22",X"2D",X"21",X"AF",X"2A",X"2F",X"21",X"CD",
+		X"BD",X"13",X"22",X"2F",X"21",X"C1",X"0D",X"C2",X"A0",X"13",X"C9",X"3E",X"FF",X"06",X"1A",X"E5",
+		X"77",X"23",X"CD",X"E3",X"13",X"05",X"C2",X"C0",X"13",X"E1",X"11",X"20",X"00",X"19",X"C9",X"3E",
+		X"FF",X"06",X"1A",X"E5",X"77",X"2B",X"CD",X"E3",X"13",X"05",X"C2",X"D4",X"13",X"E1",X"11",X"E0",
+		X"FF",X"19",X"C9",X"1E",X"20",X"D3",X"06",X"1D",X"C2",X"E5",X"13",X"C9",X"DB",X"02",X"E6",X"04",
+		X"C8",X"3A",X"03",X"20",X"A7",X"C0",X"31",X"00",X"24",X"06",X"04",X"C5",X"CD",X"1E",X"14",X"C1",
+		X"05",X"C2",X"FB",X"13",X"3E",X"01",X"32",X"03",X"20",X"CD",X"B6",X"00",X"FB",X"11",X"22",X"40",
+		X"21",X"16",X"30",X"06",X"04",X"CD",X"60",X"02",X"CD",X"C1",X"00",X"C3",X"18",X"00",X"21",X"03",
+		X"24",X"01",X"DF",X"1A",X"C5",X"E5",X"36",X"00",X"23",X"05",X"C2",X"26",X"14",X"E1",X"11",X"20",
+		X"00",X"19",X"C1",X"0D",X"C2",X"24",X"14",X"C9",X"CD",X"50",X"0C",X"E6",X"10",X"CA",X"4D",X"14",
+		X"21",X"14",X"20",X"AF",X"BE",X"C0",X"23",X"BE",X"C0",X"34",X"23",X"34",X"C9",X"21",X"15",X"20",
+		X"36",X"00",X"C9",X"21",X"16",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"69",X"14",X"34",X"2A",
+		X"33",X"20",X"01",X"10",X"05",X"09",X"22",X"1A",X"20",X"2A",X"1A",X"20",X"CD",X"C3",X"08",X"2A",
+		X"1A",X"20",X"3A",X"54",X"20",X"A7",X"7D",X"C2",X"88",X"14",X"FE",X"E0",X"D2",X"8D",X"14",X"C6",
+		X"03",X"6F",X"22",X"1A",X"20",X"C3",X"CB",X"08",X"FE",X"C0",X"C3",X"7C",X"14",X"2A",X"1A",X"20",
+		X"22",X"BD",X"20",X"21",X"BB",X"20",X"34",X"21",X"16",X"46",X"11",X"16",X"20",X"06",X"07",X"C3",
+		X"8B",X"03",X"21",X"BB",X"20",X"AF",X"BE",X"C8",X"23",X"BE",X"C2",X"BD",X"14",X"34",X"2A",X"BD",
+		X"20",X"11",X"CD",X"14",X"01",X"08",X"01",X"CD",X"76",X"03",X"C3",X"D5",X"01",X"AF",X"77",X"2B",
+		X"77",X"2A",X"BD",X"20",X"01",X"08",X"01",X"CD",X"76",X"03",X"C3",X"8C",X"08",X"A9",X"5C",X"BE",
+		X"7F",X"FE",X"7F",X"7E",X"95",X"32",X"00",X"20",X"3A",X"00",X"20",X"A7",X"D3",X"06",X"C2",X"D8",
+		X"14",X"C9",X"21",X"82",X"20",X"AF",X"BE",X"C8",X"3A",X"1A",X"20",X"D6",X"08",X"21",X"83",X"20",
+		X"BE",X"D0",X"C6",X"12",X"BE",X"D8",X"3A",X"1B",X"20",X"23",X"D6",X"03",X"BE",X"D0",X"C6",X"09",
+		X"BE",X"D8",X"2A",X"83",X"20",X"22",X"8D",X"20",X"CD",X"5B",X"0A",X"21",X"82",X"20",X"36",X"00",
+		X"21",X"8B",X"20",X"34",X"C9",X"21",X"82",X"20",X"AF",X"BE",X"C8",X"23",X"5E",X"23",X"56",X"EB",
+		X"E5",X"CD",X"5B",X"0A",X"E1",X"11",X"F9",X"FF",X"19",X"22",X"83",X"20",X"7D",X"FE",X"18",X"D2",
+		X"42",X"0A",X"22",X"87",X"20",X"21",X"85",X"20",X"36",X"FF",X"21",X"82",X"20",X"36",X"00",X"C9",
+		X"21",X"85",X"20",X"AF",X"BE",X"C8",X"23",X"34",X"7E",X"FE",X"01",X"CA",X"83",X"15",X"FE",X"04",
+		X"C2",X"59",X"15",X"11",X"24",X"44",X"C3",X"86",X"15",X"FE",X"07",X"D8",X"11",X"3C",X"44",X"CD",
+		X"86",X"15",X"21",X"00",X"00",X"22",X"81",X"20",X"22",X"85",X"20",X"CD",X"E0",X"15",X"21",X"88",
+		X"20",X"D2",X"7A",X"15",X"CD",X"E7",X"15",X"C3",X"7D",X"15",X"CD",X"07",X"16",X"21",X"14",X"20",
+		X"36",X"00",X"C9",X"11",X"0C",X"44",X"2A",X"87",X"20",X"CD",X"76",X"03",X"01",X"0C",X"02",X"C3",
+		X"D5",X"01",X"21",X"8B",X"20",X"AF",X"BE",X"C8",X"23",X"34",X"7E",X"FE",X"01",X"CA",X"CE",X"15",
+		X"FE",X"04",X"C2",X"AB",X"15",X"11",X"B4",X"44",X"C3",X"D1",X"15",X"FE",X"07",X"D8",X"2A",X"8D",
+		X"20",X"CD",X"76",X"03",X"01",X"10",X"02",X"CD",X"8C",X"08",X"21",X"00",X"00",X"22",X"8B",X"20",
+		X"21",X"81",X"20",X"36",X"00",X"CD",X"6F",X"1A",X"CD",X"D7",X"15",X"C3",X"7D",X"15",X"11",X"94",
+		X"44",X"2A",X"8D",X"20",X"C3",X"89",X"15",X"CD",X"E0",X"15",X"DA",X"ED",X"15",X"C3",X"0D",X"16",
+		X"CD",X"07",X"13",X"7E",X"0F",X"0F",X"C9",X"AF",X"3A",X"34",X"20",X"BE",X"D0",X"21",X"80",X"20",
+		X"34",X"7E",X"FE",X"03",X"DA",X"FF",X"15",X"36",X"00",X"3E",X"E8",X"2B",X"86",X"77",X"C9",X"FE",
+		X"02",X"3E",X"F0",X"DA",X"FB",X"15",X"C9",X"AF",X"3A",X"34",X"20",X"BE",X"D8",X"21",X"7E",X"20",
+		X"34",X"7E",X"FE",X"03",X"DA",X"1F",X"16",X"36",X"00",X"3E",X"15",X"2B",X"86",X"77",X"C9",X"FE",
+		X"02",X"3E",X"0D",X"DA",X"1B",X"16",X"C9",X"21",X"91",X"20",X"AF",X"BE",X"C8",X"23",X"34",X"7E",
+		X"FE",X"01",X"CA",X"BA",X"16",X"FE",X"04",X"CA",X"C9",X"16",X"FE",X"07",X"D8",X"CD",X"CF",X"16",
+		X"21",X"00",X"00",X"22",X"91",X"20",X"CD",X"5F",X"1A",X"21",X"95",X"20",X"34",X"7E",X"FE",X"03",
+		X"D2",X"5E",X"16",X"3E",X"50",X"32",X"C2",X"20",X"CD",X"8C",X"02",X"C3",X"7D",X"15",X"CD",X"88",
+		X"16",X"21",X"C1",X"20",X"70",X"78",X"C6",X"20",X"CD",X"2E",X"03",X"2A",X"93",X"20",X"CD",X"76",
+		X"03",X"CD",X"45",X"03",X"11",X"34",X"04",X"CD",X"45",X"03",X"11",X"34",X"04",X"CD",X"45",X"03",
+		X"21",X"96",X"20",X"34",X"23",X"36",X"0A",X"C9",X"3A",X"01",X"20",X"0F",X"0F",X"06",X"03",X"0F",
+		X"D8",X"06",X"05",X"0F",X"D8",X"06",X"07",X"0F",X"D8",X"06",X"09",X"C9",X"21",X"96",X"20",X"AF",
+		X"BE",X"C8",X"23",X"BE",X"CA",X"A9",X"16",X"35",X"C9",X"CD",X"8C",X"02",X"01",X"18",X"01",X"CD",
+		X"D2",X"16",X"21",X"96",X"20",X"36",X"00",X"C3",X"7D",X"15",X"11",X"94",X"44",X"2A",X"93",X"20",
+		X"CD",X"76",X"03",X"01",X"10",X"02",X"C3",X"D5",X"01",X"11",X"B4",X"44",X"C3",X"BD",X"16",X"01",
+		X"10",X"02",X"2A",X"93",X"20",X"CD",X"76",X"03",X"C3",X"8C",X"08",X"21",X"81",X"20",X"AF",X"BE",
+		X"C0",X"CD",X"07",X"13",X"E5",X"7E",X"FE",X"FF",X"C2",X"ED",X"16",X"E1",X"C9",X"07",X"DA",X"F9",
+		X"16",X"E1",X"23",X"23",X"23",X"23",X"C3",X"E4",X"16",X"E1",X"E5",X"CD",X"40",X"0D",X"4D",X"44",
+		X"CD",X"E0",X"15",X"21",X"7F",X"20",X"DA",X"2F",X"17",X"2E",X"7D",X"7E",X"B8",X"D2",X"F1",X"16",
+		X"C6",X"04",X"B8",X"DA",X"F1",X"16",X"21",X"83",X"20",X"71",X"23",X"78",X"FE",X"30",X"DA",X"F1",
+		X"16",X"FE",X"F0",X"D2",X"F1",X"16",X"70",X"21",X"FF",X"FF",X"22",X"81",X"20",X"E1",X"C9",X"7E",
+		X"B8",X"D2",X"F1",X"16",X"C6",X"06",X"B8",X"DA",X"F1",X"16",X"C3",X"16",X"17",X"3A",X"AA",X"20",
+		X"A7",X"C8",X"21",X"A2",X"20",X"CD",X"F0",X"0D",X"CD",X"5D",X"17",X"21",X"AE",X"20",X"35",X"7E",
+		X"A7",X"C2",X"57",X"17",X"C3",X"82",X"17",X"21",X"A0",X"20",X"C3",X"A1",X"0D",X"7D",X"E6",X"07",
+		X"D3",X"02",X"CD",X"76",X"03",X"C5",X"E5",X"1A",X"D3",X"04",X"DB",X"03",X"B6",X"77",X"23",X"13",
+		X"AF",X"D3",X"04",X"DB",X"03",X"B6",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"65",
+		X"17",X"C9",X"2A",X"A8",X"20",X"EB",X"1A",X"2A",X"AF",X"20",X"2D",X"CA",X"BA",X"17",X"22",X"AF",
+		X"20",X"32",X"AE",X"20",X"13",X"1A",X"E6",X"0F",X"07",X"01",X"BF",X"17",X"26",X"00",X"6F",X"09",
+		X"E5",X"C1",X"21",X"A0",X"20",X"0A",X"77",X"03",X"23",X"0A",X"77",X"13",X"1A",X"6F",X"13",X"1A",
+		X"67",X"22",X"A2",X"20",X"EB",X"23",X"22",X"A8",X"20",X"C9",X"AF",X"32",X"AA",X"20",X"C9",X"00",
+		X"02",X"02",X"02",X"02",X"00",X"02",X"FE",X"00",X"FE",X"FE",X"FE",X"FE",X"00",X"FE",X"02",X"01",
+		X"02",X"02",X"01",X"02",X"FF",X"01",X"FE",X"FF",X"FE",X"FE",X"FF",X"FE",X"01",X"FF",X"02",X"FF",
+		X"FF",X"24",X"06",X"D7",X"30",X"10",X"00",X"D7",X"30",X"04",X"07",X"D7",X"50",X"0A",X"06",X"CF",
+		X"58",X"04",X"05",X"BC",X"58",X"04",X"07",X"B4",X"50",X"0A",X"06",X"AC",X"58",X"04",X"05",X"98");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn04.vhd

@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn04 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn04 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"58",X"10",X"00",X"90",X"31",X"0C",X"06",X"D0",X"38",X"08",X"00",X"D0",X"38",X"08",X"00",X"D0",
+		X"38",X"04",X"07",X"D0",X"48",X"05",X"06",X"C8",X"50",X"04",X"05",X"BE",X"4E",X"08",X"00",X"B8",
+		X"38",X"0C",X"06",X"B0",X"38",X"08",X"00",X"B0",X"38",X"04",X"07",X"B0",X"48",X"05",X"06",X"A8",
+		X"50",X"04",X"05",X"9E",X"4E",X"08",X"00",X"98",X"38",X"0C",X"09",X"90",X"59",X"0C",X"0E",X"A6",
+		X"67",X"08",X"00",X"98",X"60",X"0B",X"06",X"A6",X"78",X"0A",X"00",X"90",X"78",X"0B",X"06",X"A6",
+		X"90",X"0A",X"00",X"90",X"90",X"0C",X"06",X"A6",X"A8",X"0A",X"00",X"A6",X"A8",X"0C",X"06",X"A6",
+		X"BC",X"0B",X"00",X"90",X"A8",X"0C",X"06",X"A6",X"C0",X"0A",X"00",X"A6",X"C0",X"0C",X"06",X"A6",
+		X"D4",X"0B",X"00",X"90",X"C0",X"0C",X"06",X"A6",X"D8",X"0C",X"07",X"A6",X"D8",X"0C",X"06",X"A6",
+		X"F0",X"00",X"00",X"00",X"00",X"92",X"18",X"01",X"04",X"E1",X"17",X"00",X"00",X"00",X"00",X"00",
+		X"17",X"00",X"1E",X"1E",X"1E",X"1E",X"FF",X"FF",X"FF",X"FF",X"36",X"00",X"CD",X"DC",X"18",X"3E",
+		X"04",X"CD",X"FB",X"01",X"2A",X"33",X"20",X"CD",X"76",X"03",X"0E",X"05",X"E5",X"C5",X"11",X"D0",
+		X"19",X"D5",X"06",X"02",X"C5",X"E5",X"01",X"12",X"02",X"CD",X"D5",X"01",X"3E",X"05",X"CD",X"D5",
+		X"14",X"E1",X"C1",X"05",X"C2",X"B4",X"18",X"D1",X"C1",X"E1",X"0D",X"C2",X"AC",X"18",X"01",X"12",
+		X"02",X"CD",X"8C",X"08",X"CD",X"C1",X"00",X"3E",X"04",X"C3",X"04",X"02",X"21",X"2F",X"20",X"36",
+		X"00",X"2E",X"14",X"36",X"00",X"C9",X"3A",X"17",X"20",X"A7",X"3E",X"02",X"C2",X"FB",X"01",X"C3",
+		X"04",X"02",X"3A",X"1D",X"20",X"A7",X"3E",X"01",X"C3",X"EC",X"18",X"3A",X"27",X"20",X"A7",X"3E",
+		X"08",X"C3",X"EC",X"18",X"3A",X"91",X"20",X"A7",X"3E",X"08",X"C3",X"EC",X"18",X"3E",X"DF",X"CD",
+		X"04",X"02",X"3E",X"DF",X"C3",X"17",X"02",X"3A",X"E4",X"20",X"A7",X"C8",X"3A",X"54",X"20",X"A7",
+		X"3E",X"01",X"C2",X"0E",X"02",X"C3",X"17",X"02",X"CD",X"95",X"19",X"D8",X"CD",X"5F",X"0C",X"CD",
+		X"47",X"0B",X"CD",X"17",X"19",X"C3",X"92",X"15",X"CD",X"C2",X"07",X"CD",X"95",X"19",X"D8",X"CD",
+		X"81",X"09",X"CD",X"F1",X"0E",X"CD",X"4B",X"19",X"C3",X"A2",X"14",X"CD",X"5A",X"19",X"21",X"34",
+		X"20",X"7E",X"2E",X"7F",X"BE",X"D8",X"C6",X"08",X"77",X"C9",X"21",X"34",X"20",X"7E",X"2E",X"7D",
+		X"BE",X"D0",X"D6",X"08",X"77",X"C9",X"CD",X"79",X"19",X"CD",X"95",X"19",X"D8",X"CD",X"5F",X"0C",
+		X"CD",X"9C",X"09",X"CD",X"DB",X"16",X"C3",X"6C",X"0F",X"3A",X"05",X"20",X"A7",X"3E",X"04",X"C2",
+		X"0E",X"02",X"C3",X"17",X"02",X"CD",X"95",X"19",X"D8",X"CD",X"BC",X"09",X"CD",X"E2",X"0F",X"CD",
+		X"56",X"0D",X"C3",X"9C",X"16",X"3A",X"7B",X"20",X"0F",X"C9",X"CD",X"71",X"03",X"C5",X"E5",X"1A",
+		X"D3",X"04",X"DB",X"03",X"A6",X"CA",X"AD",X"19",X"3E",X"01",X"32",X"11",X"20",X"DB",X"03",X"AE",
+		X"77",X"23",X"13",X"AF",X"D3",X"04",X"DB",X"03",X"A6",X"CA",X"C1",X"19",X"3E",X"01",X"32",X"11",
+		X"20",X"DB",X"03",X"AE",X"77",X"E1",X"01",X"20",X"00",X"09",X"C1",X"05",X"C2",X"9D",X"19",X"C9",
+		X"00",X"00",X"07",X"00",X"00",X"00",X"42",X"00",X"00",X"00",X"15",X"02",X"11",X"49",X"8F",X"00",
+		X"EF",X"05",X"2F",X"08",X"D1",X"21",X"1D",X"20",X"00",X"00",X"17",X"00",X"09",X"11",X"07",X"00",
+		X"07",X"00",X"47",X"00",X"00",X"02",X"21",X"40",X"49",X"10",X"05",X"00",X"00",X"80",X"01",X"08",
+		X"09",X"40",X"07",X"00",X"03",X"00",X"01",X"00",X"49",X"02",X"49",X"44",X"00",X"80",X"09",X"02",
+		X"00",X"40",X"87",X"08",X"02",X"00",X"03",X"00",X"DB",X"02",X"E6",X"03",X"21",X"27",X"21",X"F5",
+		X"86",X"77",X"F1",X"2E",X"27",X"26",X"22",X"86",X"77",X"C9",X"CD",X"44",X"1A",X"7E",X"3D",X"C8",
+		X"4F",X"21",X"01",X"25",X"11",X"26",X"40",X"C5",X"01",X"10",X"01",X"CD",X"D5",X"01",X"C1",X"0D",
+		X"C2",X"34",X"1A",X"C9",X"CD",X"52",X"1A",X"2E",X"27",X"7E",X"C9",X"CD",X"52",X"1A",X"2E",X"25",
+		X"7E",X"C9",X"3A",X"DB",X"20",X"0F",X"DA",X"5C",X"1A",X"26",X"21",X"C9",X"26",X"22",X"C9",X"3E",
+		X"50",X"32",X"C2",X"20",X"C3",X"8C",X"02",X"3E",X"01",X"32",X"C1",X"20",X"C3",X"8C",X"02",X"21",
+		X"01",X"50",X"22",X"C1",X"20",X"C3",X"8C",X"02",X"21",X"29",X"09",X"11",X"36",X"21",X"06",X"06",
+		X"C3",X"8B",X"03",X"21",X"2F",X"09",X"C3",X"7B",X"1A",X"21",X"12",X"20",X"AF",X"BE",X"3E",X"10",
+		X"CA",X"04",X"02",X"35",X"C3",X"FB",X"01",X"21",X"E9",X"20",X"3A",X"DB",X"20",X"0F",X"D0",X"23",
+		X"C9",X"CD",X"97",X"1A",X"AF",X"BE",X"C8",X"CD",X"52",X"1A",X"21",X"C4",X"20",X"D2",X"B2",X"1A",
+		X"2E",X"C7",X"7E",X"06",X"15",X"B8",X"D8",X"CD",X"44",X"1A",X"34",X"CD",X"2A",X"1A",X"CD",X"97",
+		X"1A",X"36",X"00",X"21",X"12",X"20",X"36",X"50",X"C9",X"FE",X"FF",X"CA",X"25",X"1B",X"FE",X"FE",
+		X"CA",X"1A",X"1B",X"21",X"3B",X"21",X"36",X"80",X"23",X"77",X"23",X"EB",X"21",X"5D",X"1B",X"87",
+		X"4F",X"06",X"00",X"09",X"7E",X"23",X"66",X"6F",X"C3",X"F9",X"1A",X"3A",X"3B",X"21",X"A7",X"C8",
+		X"21",X"3D",X"21",X"35",X"C0",X"EB",X"2A",X"3E",X"21",X"7E",X"A7",X"CA",X"25",X"1B",X"FE",X"FF",
+		X"CA",X"14",X"1B",X"12",X"23",X"7E",X"06",X"08",X"D3",X"01",X"07",X"05",X"C2",X"08",X"1B",X"23",
+		X"22",X"3E",X"21",X"C9",X"3A",X"3C",X"21",X"F2",X"D3",X"1A",X"3E",X"01",X"32",X"3D",X"21",X"3E",
+		X"80",X"32",X"3B",X"21",X"C9",X"3E",X"FF",X"06",X"08",X"D3",X"01",X"07",X"05",X"C2",X"29",X"1B",
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+		X"32",X"3A",X"21",X"C9",X"AF",X"32",X"37",X"21",X"3C",X"32",X"3A",X"21",X"C9",X"08",X"45",X"9C",
+		X"45",X"C6",X"45",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn05-1.vhd

@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn05_1 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn05_1 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"01",X"01",X"00",X"00",X"02",X"02",X"01",X"00",X"01",X"02",X"02",X"02",X"02",X"00",X"00",X"01",
+		X"01",X"00",X"00",X"00",X"06",X"0E",X"0E",X"03",X"15",X"04",X"11",X"18",X"1B",X"1B",X"05",X"08",
+		X"0D",X"04",X"13",X"08",X"0B",X"13",X"00",X"00",X"07",X"07",X"02",X"1C",X"8B",X"77",X"8B",X"1C",
+		X"02",X"07",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"00",X"F0",
+		X"00",X"70",X"00",X"30",X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"1C",X"00",X"1C",X"00",X"1C",
+		X"00",X"3E",X"00",X"BE",X"00",X"E0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"80",X"B0",X"C0",X"AD",
+		X"C0",X"DC",X"00",X"9E",X"00",X"9E",X"00",X"1E",X"00",X"04",X"00",X"38",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"00",X"F0",X"00",X"70",X"00",X"30",
+		X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"1C",X"00",X"1C",X"00",X"1C",X"00",X"3E",X"00",X"BE",
+		X"00",X"E0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"80",X"B0",X"C0",X"AD",X"C0",X"DC",X"00",X"9E",
+		X"00",X"9E",X"00",X"1E",X"00",X"04",X"80",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",
+		X"00",X"04",X"00",X"1E",X"00",X"9E",X"00",X"9E",X"C0",X"DC",X"C0",X"AD",X"80",X"B0",X"00",X"9C",
+		X"00",X"9C",X"00",X"9C",X"00",X"E0",X"00",X"BE",X"00",X"3E",X"00",X"1C",X"00",X"1C",X"00",X"1C",
+		X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"30",X"00",X"70",X"00",X"F0",X"00",X"38",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"80",X"03",X"00",X"04",X"00",X"1E",X"00",X"9E",X"00",X"9E",X"C0",
+		X"DC",X"C0",X"AD",X"80",X"B0",X"00",X"9C",X"00",X"9C",X"00",X"9C",X"00",X"E0",X"00",X"BE",X"00",
+		X"3E",X"00",X"1C",X"00",X"1C",X"00",X"1C",X"00",X"18",X"00",X"18",X"00",X"18",X"00",X"30",X"00",
+		X"70",X"00",X"F0",X"00",X"38",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"30",X"00",X"80",X"1B",X"00",X"C0",X"FF",X"00",X"C0",
+		X"67",X"00",X"C0",X"0B",X"00",X"00",X"08",X"00",X"00",X"08",X"00",X"00",X"08",X"00",X"00",X"10",
+		X"1E",X"00",X"10",X"3F",X"00",X"90",X"7F",X"00",X"E0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF",
+		X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"80",
+		X"01",X"00",X"80",X"07",X"00",X"80",X"03",X"00",X"F0",X"00",X"00",X"78",X"01",X"00",X"78",X"02",
+		X"1E",X"38",X"04",X"3F",X"38",X"88",X"7F",X"00",X"D0",X"FF",X"00",X"E0",X"FF",X"00",X"E0",X"FF",
+		X"00",X"C0",X"FF",X"00",X"C0",X"FF",X"00",X"80",X"7F",X"00",X"00",X"3F",X"00",X"00",X"1E",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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+		X"12",X"02",X"0E",X"11",X"04",X"1C",X"21",X"1B",X"1B",X"07",X"08",X"1C",X"12",X"02",X"0E",X"11",
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+		X"1D",X"26",X"1D",X"29",X"1D",X"2F",X"05",X"23",X"1D",X"26",X"00",X"00",X"7F",X"04",X"0F",X"03",
+		X"83",X"40",X"01",X"38",X"11",X"0C",X"01",X"00",X"01",X"01",X"03",X"8C",X"07",X"1A",X"0F",X"40",
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+		X"C2",X"06",X"18",X"39",X"C3",X"02",X"18",X"3F",X"C2",X"03",X"18",X"45",X"FF",X"FF",X"FF",X"FF",
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+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06

@@ -0,0 +1 @@
+

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn06.vhd

@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn06 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn06 is
+	type rom is array(0 to  1023) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0E",X"0E",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
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+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
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+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
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+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
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+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
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+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0D",X"0E",X"0E",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07

@@ -0,0 +1 @@
+

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/roms/tn07.vhd

@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity tn07 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of tn07 is
+	type rom is array(0 to  1023) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0D",X"0D",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0E",X"0E",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"09",X"09",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0B",X"0B",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0D",X"09",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0F",X"0F",X"0F",X"0D",
+		X"0D",X"0D",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"09",X"0F",X"0D",X"0D");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/spram.vhd

@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:27:39  November 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:27:39  November 20, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "BlueShark"

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.qsf

@@ -0,0 +1,172 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 15:17:52  June 06, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		BlueShark_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlueShark_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/BlueShark_Overlay.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY BlueShark_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------------
+# start ENTITY(BlueShark_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(BlueShark_mist)
+# --------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/BlueShark.sdc

@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/README.txt

@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Blue Shark port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+ToDo: Color Prom
+      Controls + DIP
+

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/clean.bat

@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_Overlay.vhd

@@ -0,0 +1,112 @@
+--Blue Shark Color Overlay Gehstock 2019
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+
+entity BlueShark_Overlay is
+	port(
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
+		CLK               : in    std_logic;
+		Rst_n_s           : in    std_logic;
+		HSync             : in    std_logic;
+		VSync             : in    std_logic;
+		AD                : in    std_logic_vector(15 downto 0);
+		O_VIDEO_R         : out   std_logic;
+		O_VIDEO_G         : out   std_logic;
+		O_VIDEO_B         : out   std_logic;
+		O_HSYNC           : out   std_logic;
+		O_VSYNC           : out   std_logic
+		);
+end BlueShark_Overlay;
+
+architecture rtl of BlueShark_Overlay is
+
+		signal HCnt            : std_logic_vector(11 downto 0);
+	signal VCnt            : std_logic_vector(11 downto 0);
+	signal HSync_t1        : std_logic;
+	signal Overlay_B1      : boolean;
+	signal Overlay_B1_VCnt : boolean;
+	signal VideoRGB        : std_logic_vector(2 downto 0);
+	signal col_data        : std_logic_vector(3 downto 0);
+	signal col_addr        : std_logic_vector(9 downto 0);
+begin	
+	process (Rst_n_s, Clk)
+		variable cnt : unsigned(3 downto 0);
+	begin
+		if Rst_n_s = '0' then
+			cnt := "0000";
+		elsif Clk'event and Clk = '1' then
+			if cnt = 9 then
+				cnt := "0000";
+			else
+				cnt := cnt + 1;
+			end if;
+		end if;
+	end process;
+	
+  p_overlay : process(Rst_n_s, Clk)
+	variable HStart : boolean;
+  begin
+	if Rst_n_s = '0' then
+	  HCnt <= (others => '0');
+	  VCnt <= (others => '0');
+	  HSync_t1 <= '0';
+	  Overlay_B1_VCnt <= false;
+	  Overlay_B1 <= false;
+	elsif Clk'event and Clk = '1' then
+	  HSync_t1 <= HSync;
+	  HStart := (HSync_t1 = '0') and (HSync = '1');
+
+	  if HStart then
+		HCnt <= (others => '0');
+	  else
+		HCnt <= HCnt + "1";
+	  end if;
+
+	  if (VSync = '0') then
+		VCnt <= (others => '0');
+	  elsif HStart then
+		VCnt <= VCnt + "1";
+	  end if;
+
+	  if HStart then
+		if (Vcnt>= x"28") and (Vcnt <= x"35") then--Top Start
+		  Overlay_B1_VCnt <= true;
+		else
+		  Overlay_B1_VCnt <= false;
+		end if;
+	  end if;
+
+	  if (HCnt <= x"0") and Overlay_B1_VCnt then--Left Start
+		Overlay_B1 <= true;
+	  elsif (HCnt >= x"228") then--Right End
+		Overlay_B1 <= false;
+	  end if;
+	end if;
+  end process;
+
+  p_video_out_comb : process(Video, Overlay_B1)
+  begin
+	if (Video = '0') then
+	  VideoRGB  <= "000";
+	else
+	  if Overlay_B1 then
+		VideoRGB  <= "001";
+	  else
+		VideoRGB  <= "111";
+	  end if;
+	end if;
+  end process;
+
+  
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_HSYNC   <= HSync;
+  O_VSYNC   <= VSync;
+
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_memory.sv

@@ -0,0 +1,68 @@
+module BlueShark_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+
+
+sprom #(
+	.init_file("./roms/blueshrk_h.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/blueshrk_g.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/blueshrk_f.hex"),
+	.widthad_a(11), 
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[10:0]),
+	.q(rom_data_2)
+	);
+
+
+always @(Addr, rom_data_0, rom_data_1, rom_data_2) begin
+	Rom_out = 8'b00000000;
+		case (Addr[15:11])
+			5'b00000 : Rom_out = rom_data_0;
+			5'b00001 : Rom_out = rom_data_1;
+			5'b00010 : Rom_out = rom_data_2;
+			default : Rom_out = 8'b00000000;
+		endcase
+end
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/BlueShark_mist.sv

@@ -0,0 +1,214 @@
+module BlueShark_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"BlueShark;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Overlay, On, Off;",
+	"T6,Reset;",
+	"V,v0.00.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+/*Dip Switch:SW
+1		2		3		4		5		6		7		8		Function	Option
+Unused
+				Off*
+				On
+Unused				
+								Off*
+								On
+Replay								
+										Off	On	 			14000
+										On		Off*	 		18000*
+										Off	Off	 		22000
+										On		On	 			None
+*/
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(~btn_one_player),
+	.Sel2Player(~btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.DIP("00000000"),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(HSync),
+	.VSync(VSync)
+	);
+		
+BlueShark_memory BlueShark_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);		
+	  
+BlueShark_Overlay BlueShark_Overlay (
+	.Video(Video),
+	.Overlay(~status[5]),
+	.CLK(clk_core),
+	.Rst_n_s(Rst_n_s),
+	.HSync(HSync),
+	.VSync(VSync),
+	.AD(AD),
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({r,r,r}),
+	.G({g,g,g}),
+	.B({b,b,b}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ce_divider(0),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_fire1 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T8080se.vhd

@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_ALU.vhd

@@ -0,0 +1,361 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Pack.vhd

@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/T80/T80_Reg.vhd

@@ -0,0 +1,114 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0242 : Initial release
+--
+--      0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal      RegsH   : Register_Image(0 to 7);
+	signal      RegsL   : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/build_id.tcl

@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders.vhd

@@ -0,0 +1,243 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		Coin            : in  std_logic;
+		Sel1Player      : in  std_logic;
+		Sel2Player      : in  std_logic;
+		Fire            : in  std_logic;
+		MoveLeft        : in  std_logic;
+		MoveRight       : in  std_logic;
+		DIP             : in  std_logic_vector(7 downto 0);
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+
+	signal GDB0         : std_logic_vector(7 downto 0);
+	signal GDB1         : std_logic_vector(7 downto 0);
+	signal GDB2         : std_logic_vector(7 downto 0);
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: entity work.mw8080
+		port map(
+			Rst_n => Rst_n,--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(9 downto 8) select
+		GDB <= GDB0 when "00",
+				GDB1 when "01",
+				GDB2 when "10",
+				S when others;
+
+	GDB0(0) <= '1';             -- Unused
+	GDB0(1) <= '1';             -- Unused
+	GDB0(2) <= '1';             -- Unused
+	GDB0(3) <= '1';             -- Unused
+	GDB0(4) <= '1';             -- Unused
+	GDB0(5) <= '1';             -- Unused
+	GDB0(6) <= '1';             -- Unused
+	GDB0(7) <= '1';             -- Unused
+
+	GDB1(0) <= '1';	-- PADDLE
+	GDB1(1) <= '1';	-- PADDLE
+	GDB1(2) <= '1';	-- PADDLE
+	GDB1(3) <= '1';	-- PADDLE
+	GDB1(4) <= '1';	-- PADDLE
+	GDB1(5) <= '1';	-- PADDLE
+	GDB1(6) <= '1';	-- PADDLE
+	GDB1(7) <= '0';	-- PADDLE
+
+	GDB2(0) <= not Fire;
+	GDB2(1) <= not Coin;
+	GDB2(2) <= '1';	-- unknown
+	GDB2(3) <= '1';	-- TILT
+	GDB2(4) <= '1';	-- unknown
+	GDB2(5) <= '1';	-- Replay
+	GDB2(6) <= '1';	-- Replay
+	GDB2(7) <= '1';	-- TEST
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/invaders_audio.vhd

@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/mw8080.vhd

@@ -0,0 +1,335 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/pll.vhd

@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 10,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 20,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_f.hex

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Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_g.hex

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Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/roms/blueshrk_h.hex

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Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/spram.vhd

@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;

Arcade_MiST/Midway-Taito 8080 Hardware/BlueShark_MiST/rtl/sprom.vhd

@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;

Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Boothill"

Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/Boothill.qsf

@@ -0,0 +1,176 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 20:29:53  August 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Boothill_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpaceWalk_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/romh.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/romg.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/romf.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/rome.vhd
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE "D:/Github/Mist_FPGA/common/mist/mist.qip"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY SpaceWalk_mist
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------------
+# start ENTITY(SpaceWalk_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(SpaceWalk_mist)
+# --------------------------

Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/README.txt

@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Booth Hill port to MiST by Gehstock 
+-- 05 June 2019
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F1          : Start
+--   SPACE       : Fire
+--   RIGHT/LEFT  : Movement
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+
+Work in Progress
+

Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/clean.bat

@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause

Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/SpaceWalk_mist.sv

@@ -0,0 +1,198 @@
+module SpaceWalk_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Boot Hill;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+
+wire clk_core, clk_sys;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(),
+	.c0(clk_core),
+	.c1(clk_sys)
+);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] kbjoy;
+wire  [7:0] joystick_0,joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hsync,vsync;
+wire 			hs, vs;
+wire 			r,g,b;
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire [5:0]SoundCtrl6;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | status[6] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.Coin(btn_coin),
+	.Sel1Player(btn_one_player),
+	.Sel2Player(btn_two_players),
+	.Fire(~m_fire),
+	.MoveLeft(~m_left),
+	.MoveRight(~m_right),
+	.MoveUp(~m_up),
+	.MoveDown(~m_down),	
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.SoundCtrl6(SoundCtrl6),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+		
+invaders_memory invaders_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+		
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S0(SoundCtrl3 | SoundCtrl4),
+	.S1(SoundCtrl4),
+	.S2(SoundCtrl5 | SoundCtrl6),//hi
+	.S3(SoundCtrl6),//lo
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(3)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R({Video,Video,Video}),
+	.G({Video,Video,Video}),
+	.B({Video,Video,Video}),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.ce_divider(0),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule

Arcade_MiST/Midway-Taito 8080 Hardware/Boothill_MiST/rtl/T80/T8080se.vhd

@@ -0,0 +1,194 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 8080 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original 8080
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--      STACK status output not supported
+--
+-- File history :
+--
+--      0237 : First version
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T8080se is
+	generic(
+		Mode : integer := 2;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK                     : in std_logic;
+		CLKEN           : in std_logic;
+		READY           : in std_logic;
+		HOLD            : in std_logic;
+		INT             : in std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0)
+	);
+end T8080se;
+
+architecture rtl of T8080se is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead               : std_logic;
+	signal Write                : std_logic;
+	signal IORQ                 : std_logic;
+	signal INT_n                : std_logic;
+	signal HALT_n               : std_logic;
+	signal BUSRQ_n              : std_logic;
+	signal BUSAK_n              : std_logic;
+	signal DO_i                 : std_logic_vector(7 downto 0);
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal TState               : std_logic_vector(2 downto 0);
+	signal One                  : std_logic;
+
+begin
+
+	INT_n <= not INT;
+	BUSRQ_n <= HOLD;
+	HLDA <= not BUSAK_n;
+	SYNC <= '1' when TState = "001" else '0';
+	VAIT <= '1' when TState = "010" else '0';
+	One <= '1';
+
+	DO(0) <= not IntCycle_n when TState = "001" else DO_i(0);   -- INTA
+	DO(1) <= Write when TState = "001" else DO_i(1);    -- WO_n
+	DO(2) <= DO_i(2);   -- STACK not supported !!!!!!!!!!
+	DO(3) <= not HALT_n when TState = "001" else DO_i(3);       -- HLTA
+	DO(4) <= IORQ and Write when TState = "001" else DO_i(4);   -- OUT
+	DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0';        -- M1
+	DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);       -- INP
+	DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);    -- MEMR
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 0)
+		port map(
+			CEN => CLKEN,
+			M1_n => open,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => open,
+			HALT_n => HALT_n,
+			WAIT_n => READY,
+			INT_n => INT_n,
+			NMI_n => One,
+			RESET_n => RESET_n,
+			BUSRQ_n => One,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO_i,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			IntE => INTE);
+
+	process (RESET_n, CLK)
+	begin
+		if RESET_n = '0' then
+			DBIN <= '0';
+			WR_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK'event and CLK = '1' then
+			if CLKEN = '1' then
+				DBIN <= '0';
+				WR_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and READY = '0') then
+						DBIN <= IntCycle_n;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
+						DBIN <= '1';
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+						end if;
+					else
+						if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
+							WR_n <= '0';
+						end if;
+					end if;
+				end if;
+				if TState = "010" and READY = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;