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Update dual_port_ram.vhd

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Marcel
2023-07-13 12:03:28 +02:00
parent d3ef9c4427
commit ca0c6feb5f
1 changed files with 1 additions and 1 deletions
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Arcade_MiST/Toaplan v1 Hardware/rtl/dual_port_ram.vhd
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@@ -80,7 +80,7 @@ begin
clock_enable_output_a => "BYPASS", clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS", clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1", indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V", intended_device_family => "Cyclone III",
lpm_type => "altsyncram", lpm_type => "altsyncram",
numwords_a => LEN, numwords_a => LEN,
numwords_b => LEN, numwords_b => LEN,