mirror of
https://github.com/Gehstock/Mist_FPGA.git
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Remove Unused Toplevel
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Gehstock
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@ -137,7 +137,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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# end ENTITY(bally_mist)
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# ----------------------
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/bally_mist.sv
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set_global_assignment -name VHDL_FILE rtl/bally_top.vhd
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set_global_assignment -name VHDL_FILE rtl/bally.vhd
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set_global_assignment -name VHDL_FILE rtl/ps2kbd.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_rams.vhd
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@ -163,4 +162,5 @@ set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
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set_global_assignment -name VHDL_FILE rtl/pll.vhd
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set_global_assignment -name VERILOG_FILE rtl/game.v
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set_global_assignment -name QIP_FILE rtl/cart.qip
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set_global_assignment -name VHDL_FILE rtl/bally_check_cart.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -70,25 +70,22 @@ end;
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architecture RTL of BALLY_CHECK_CART is
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component BALLY_CHECK
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port (
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CLK : in std_logic;
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ADDR : in std_logic_vector(10 downto 0);
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DATA : out std_logic_vector(7 downto 0)
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);
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end component;
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signal dout : std_logic_vector(7 downto 0);
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begin
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-- chars 0-9, a = '-', b = 'E', c = 'H', d = 'L', e = 'P', f = blank
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u_rom : entity work.BALLY_CHECK
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port map (
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clock => CLK,
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clken => ENA,
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address => I_EXP_ADDR(10 downto 0),
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q => dout
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);
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u_rom : entity work.sprom
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generic map (
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init_file => ".\roms\balcheck.hex",
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widthad_a => 11,
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width_a => 8
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)
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port map (
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address => I_EXP_ADDR(10 downto 0),
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clock => CLK,
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q => dout
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);
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p_dout : process(dout, I_EXP_ADDR)
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begin
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@ -20,6 +20,7 @@ module bally_mist(
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localparam CONF_STR = {
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"BALLY;BIN;",
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// "O2,Check Cart, On, Off;",
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"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"T6,Reset;",
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"V,v1.00.",`BUILD_DATE
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@ -28,9 +29,11 @@ localparam CONF_STR = {
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wire clk_28;//28.5712
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wire clk_14;//14.2856
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wire clk_7;//7.1428
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wire clk_1;//1.0204
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wire reset = status[0] | status[6] | buttons[1] | ioctl_downl;
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wire [12:0] cart_addr;
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wire [7:0] cart_do;
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wire [7:0] cart_di, cart_do;
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wire cart_cs;
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wire ioctl_downl;
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wire [7:0] ioctl_index;
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@ -49,19 +52,35 @@ wire [7:0] joystick_1;
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wire scandoubler_disable;
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wire ypbpr;
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wire ps2_kbd_clk, ps2_kbd_data;
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wire [7:0] switch_col;
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wire [7:0] switch_row;
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wire [7:0] audio;
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wire pix_ena;
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wire hs, vs;
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wire [3:0] r,g,b;
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wire [15:0] exp_addr;
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wire [7:0] exp_data_out;
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wire [7:0] exp_data_in;
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wire exp_oe_l;
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wire exp_m1_l;
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wire exp_mreq_l;
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wire exp_iorq_l;
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wire exp_wr_l;
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wire exp_rd_l;
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wire [3:0] check_cart_msb;
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wire [7:4] check_cart_lsb;
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pll pll
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(
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.inclk0(CLOCK_27),
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.c0(clk_28),
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.c1(clk_14),
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.c2(clk_7)
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.c2(clk_7),
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.c3(clk_1)
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);
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video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer
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@ -125,7 +144,7 @@ cart cart (
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.wren ( ioctl_downl && ioctl_wr),
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.q ( cart_do )
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);
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/*
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BALLY_TOP BALLY_TOP (
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.cas_addr(cart_addr),
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.cas_data(cart_do),
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@ -142,17 +161,86 @@ BALLY_TOP BALLY_TOP (
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.pix_ena(pix_ena),
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.clk_14(clk_14),
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.clk_7(clk_7),
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.reset((status[0] | status[6] | buttons[1] | ioctl_downl))
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);
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.reset(reset)
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);*/
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BALLY_PS2_IF BALLY_PS2_IF (
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.I_PS2_CLK(ps2_kbd_clk),
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.I_PS2_DATA(ps2_kbd_data),
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.I_COL (switch_col),
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.O_ROW (switch_row),
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.I_RESET_L (~reset),
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.I_1MHZ_ENA(clk_1),
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.CLK (clk_7)
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);
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BALLY BALLY (
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.O_AUDIO(audio),
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.O_VIDEO_R(r),
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.O_VIDEO_G(g),
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.O_VIDEO_B(b),
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.O_HSYNC(hs),
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.O_VSYNC(vs),
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.O_COMP_SYNC_L(),
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.O_FPSYNC(),
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.O_CAS_ADDR(cart_addr),
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.O_CAS_DATA(),
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.I_CAS_DATA(cart_do),
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.O_CAS_CS_L(cart_cs),
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.O_EXP_ADDR(exp_addr),
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.O_EXP_DATA(exp_data_out),
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.I_EXP_DATA(exp_data_in),
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.I_EXP_OE_L(exp_oe_l),
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.O_EXP_M1_L(exp_m1_l),
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.O_EXP_MREQ_L(exp_mreq_l),
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.O_EXP_IORQ_L(exp_iorq_l),
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.O_EXP_WR_L(exp_wr_l),
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.O_EXP_RD_L(exp_rd_l),
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.O_SWITCH_COL(switch_col),
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.I_SWITCH_ROW(switch_row),
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.I_RESET_L(~reset),
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.ENA(1'b1),
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.pix_ena(pix_ena),
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.CLK(clk_14),
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.CLK7(clk_7)
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);
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dac dac
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(
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.clk_i(clk_28),
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.res_n_i(1'b1),
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.res_n_i(~reset),
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.dac_i(audio),
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.dac_o(AUDIO_L)
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);
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assign AUDIO_R = AUDIO_L;
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/*
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BALLY_CHECK_CART BALLY_CHECK_CART (
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.I_EXP_ADDR(exp_addr),
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.I_EXP_DATA(exp_data_out),
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.O_EXP_DATA(exp_data_in),
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.O_EXP_OE_L(exp_oe_l),
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.I_EXP_M1_L(exp_m1_l),
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.I_EXP_MREQ_L(exp_mreq_l),
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.I_EXP_IORQ_L(exp_iorq_l),
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.I_EXP_WR_L(exp_wr_l),
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.I_EXP_RD_L(exp_rd_l),
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. O_CHAR_MSB(check_cart_msb),
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.O_CHAR_LSB(check_cart_lsb),
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.I_RESET_L(~reset),
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.ENA(status[2]),
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.CLK(clk_7)
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);*/
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// if no expansion cart
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assign exp_data_in = 8'hff;
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assign exp_oe_l = 1'b1;
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endmodule
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@ -1,2 +1,2 @@
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`define BUILD_DATE "180725"
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`define BUILD_TIME "160612"
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`define BUILD_TIME "170812"
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@ -45,7 +45,8 @@ ENTITY pll IS
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC
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c2 : OUT STD_LOGIC ;
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c3 : OUT STD_LOGIC
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);
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END pll;
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@ -57,9 +58,10 @@ ARCHITECTURE SYN OF pll IS
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SIGNAL sub_wire2 : STD_LOGIC ;
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SIGNAL sub_wire3 : STD_LOGIC ;
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SIGNAL sub_wire4 : STD_LOGIC ;
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SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire5 : STD_LOGIC ;
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SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
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SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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@ -78,6 +80,10 @@ ARCHITECTURE SYN OF pll IS
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clk2_duty_cycle : NATURAL;
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clk2_multiply_by : NATURAL;
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clk2_phase_shift : STRING;
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clk3_divide_by : NATURAL;
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clk3_duty_cycle : NATURAL;
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clk3_multiply_by : NATURAL;
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clk3_phase_shift : STRING;
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compensate_clock : STRING;
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inclk0_input_frequency : NATURAL;
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intended_device_family : STRING;
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@ -135,16 +141,18 @@ ARCHITECTURE SYN OF pll IS
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END COMPONENT;
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BEGIN
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sub_wire6_bv(0 DOWNTO 0) <= "0";
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sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
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sub_wire3 <= sub_wire0(2);
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sub_wire2 <= sub_wire0(0);
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sub_wire7_bv(0 DOWNTO 0) <= "0";
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sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
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sub_wire4 <= sub_wire0(2);
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sub_wire3 <= sub_wire0(0);
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sub_wire2 <= sub_wire0(3);
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sub_wire1 <= sub_wire0(1);
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c1 <= sub_wire1;
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c0 <= sub_wire2;
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c2 <= sub_wire3;
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sub_wire4 <= inclk0;
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sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
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c3 <= sub_wire2;
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c0 <= sub_wire3;
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c2 <= sub_wire4;
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sub_wire5 <= inclk0;
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sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
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altpll_component : altpll
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GENERIC MAP (
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@ -161,6 +169,10 @@ BEGIN
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clk2_duty_cycle => 50,
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clk2_multiply_by => 55,
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clk2_phase_shift => "0",
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clk3_divide_by => 1456,
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clk3_duty_cycle => 50,
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clk3_multiply_by => 55,
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clk3_phase_shift => "0",
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compensate_clock => "CLK0",
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inclk0_input_frequency => 37037,
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intended_device_family => "Cyclone III",
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@ -196,7 +208,7 @@ BEGIN
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port_clk0 => "PORT_USED",
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port_clk1 => "PORT_USED",
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port_clk2 => "PORT_USED",
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port_clk3 => "PORT_UNUSED",
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port_clk3 => "PORT_USED",
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port_clk4 => "PORT_UNUSED",
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port_clk5 => "PORT_UNUSED",
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port_clkena0 => "PORT_UNUSED",
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@ -212,7 +224,7 @@ BEGIN
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width_clock => 5
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)
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PORT MAP (
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inclk => sub_wire5,
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inclk => sub_wire6,
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clk => sub_wire0
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);
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@ -242,12 +254,15 @@ END SYN;
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-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52"
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-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104"
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-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "208"
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-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1456"
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-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
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-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.557692"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.278846"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "7.139423"
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-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "1.019918"
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-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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@ -270,32 +285,40 @@ END SYN;
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
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-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
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-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
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-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
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-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55"
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-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55"
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-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55"
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-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55"
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-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.57120000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.28560000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "7.14280000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "1.02040000"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
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-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
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-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
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-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
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-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
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-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
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-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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@ -320,15 +343,18 @@ END SYN;
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-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
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-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
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-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
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-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
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-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
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-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
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-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
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-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
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-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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@ -345,6 +371,10 @@ END SYN;
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-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
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-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "55"
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-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1456"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "55"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@ -379,7 +409,7 @@ END SYN;
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
@ -398,12 +428,14 @@ END SYN;
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user