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New Core Sonson by Slingshot

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This commit is contained in:
Gehstock
2020-03-26 02:25:15 +01:00
parent 7864e0fd5e
commit d543ba623f
83 changed files with 1318 additions and 17042 deletions
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14
Arcade_MiST/Capcom SonSon Hardware/README.txt Normal file
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@@ -0,0 +1,14 @@
Capcom SonSon Arcade game
=========================
Based on old PACE code by Mark McDougall(tcdev)
MiST port usage
===============
- Create ROM file from the MRA file using the MRA utility.
Example: mra -z /path/to/mame/roms SonSon.mra
- Copy the ROM files to the root of the SD Card
- Copy the RBF files to the SD Card
MRA utility: https://github.com/sebdel/mra-tools-c/

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qpf → Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qpf
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68
Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf → Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf
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@@ -158,7 +158,7 @@ set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/druaga.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/sprite.stp
# Power Estimation Assignments
# ============================
@@ -190,40 +190,6 @@ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name SYSTEMVERILOG_FILE rtl/SonSon_MiST.sv
set_global_assignment -name VHDL_FILE rtl/target_top.vhd
set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/platform.vhd
set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/pace.vhd
set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller.vhd
set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
set_global_assignment -name VHDL_FILE rtl/sonson_soundboard.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name VHDL_FILE rtl/sound.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu09s.vhd
set_global_assignment -name VHDL_FILE rtl/roms/sonson/sound_rom.vhd
set_global_assignment -name VHDL_FILE ../../../common/CPU/T80/Z80.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
@@ -258,6 +224,34 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name VERILOG_FILE ../../../common/CPU/MC6809/mc6809.v
set_global_assignment -name VERILOG_FILE ../../../common/CPU/MC6809/mc6809i.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/SonSon_MiST.sv
set_global_assignment -name VHDL_FILE rtl/target_top.vhd
set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/platform.vhd
set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/pace.vhd
set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
set_global_assignment -name VHDL_FILE rtl/sonson_video_controller.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
set_global_assignment -name VHDL_FILE rtl/sonson_soundboard.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809i.v
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.sdc → Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.sdc
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@@ -54,7 +54,7 @@ set_time_format -unit ns -decimal_places 3
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
#**************************************************************
# Create Generated Clock
#**************************************************************

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/clean.bat → Arcade_MiST/Capcom SonSon Hardware/clean.bat
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42
Arcade_MiST/Capcom SonSon Hardware/meta/SonSon.mra Normal file
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@@ -0,0 +1,42 @@
<misterromdescription>
<name>SonSon</name>
<mameversion>0216</mameversion>
<setname>sonson</setname>
<manufacturer>Capcom</manufacturer>
<rbf>sonson</rbf>
<rom index="0" zip="sonson.zip" md5="d17bc11db95dd6e2d44ac342b3462259" type="merged|nonmerged">
<!-- CPU2, 8k -->
<part name="ss_6.c11"/>
<part repeat="0x2000">FF</part>
<!-- CPU1, 48k -->
<part name="ss.01e"/>
<part name="ss.02e"/>
<part name="ss.03e"/>
<!-- gfx1, 16k -->
<group width="16">
<part name="ss_7.b6"/>
<part name="ss_8.b5"/>
</group>
<!-- gfx2, 48k -->
<part name="ss_9.m5"/>
<part name="ss_10.m6"/>
<part name="ss_11.m3"/>
<part name="ss_12.m4"/>
<part name="ss_13.m1"/>
<part name="ss_14.m2"/>
<!-- other proms -->
<part name="ssb2.c4"/>
<part name="ssb3.h7"/>
<part name="ssb1.k11"/>
<part name="ssb4.b2"/>
<part name="ssb5.b1"/>
</rom>
</misterromdescription>

111
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/Graphics.VHD → Arcade_MiST/Capcom SonSon Hardware/rtl/Graphics.VHD
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@@ -20,20 +20,20 @@ entity Graphics is
sprite_reg_i : in to_SPRITE_REG_t;
sprite_ctl_i : in to_SPRITE_CTL_t;
sprite_ctl_o : out from_SPRITE_CTL_t;
spr0_hit : out std_logic;
spr0_hit : out std_logic;
graphics_i : in to_GRAPHICS_t;
graphics_o : out from_GRAPHICS_t;
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t
);
end Graphics;
architecture SYN of Graphics is
alias clk : std_logic is video_i.clk;
alias clk : std_logic is video_i.clk;
signal from_video_ctl : from_VIDEO_CTL_t;
signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
@@ -41,21 +41,21 @@ architecture SYN of Graphics is
signal sprite_ctl_o_s : from_SPRITE_CTL_t;
signal sprite_pri : std_logic;
signal rgb_data : RGB_t;
signal rgb_data : RGB_t;
-- before OSD is mixed in
signal video_o_s : to_VIDEO_t;
begin
-- dodgy OSD transparency...
video_o.clk <= video_o_s.clk;
video_o.clk <= video_o_s.clk;
video_o.rgb.r <= video_o_s.rgb.r;
video_o.rgb.g <= video_o_s.rgb.g;
video_o.rgb.b <= video_o_s.rgb.b;
video_o.hsync <= video_o_s.hsync;
video_o.vsync <= video_o_s.vsync;
video_o.hblank <= video_o_s.hblank;
video_o.vblank <= video_o_s.vblank;
video_o.hsync <= video_o_s.hsync;
video_o.vsync <= video_o_s.vsync;
video_o.hblank <= video_o_s.hblank;
video_o.vblank <= video_o_s.vblank;
graphics_o.y <= from_video_ctl.y;
-- should this be the 'real' vblank or the 'active' vblank?
@@ -63,38 +63,21 @@ begin
graphics_o.hblank <= video_o_s.hblank;
graphics_o.vblank <= video_o_s.vblank;
--graphics_o.vblank <= from_video_ctl.vblank;
pace_video_controller_inst : entity work.pace_video_controller
generic map
(
CONFIG => PACE_VIDEO_CONTROLLER_TYPE,
DELAY => PACE_VIDEO_PIPELINE_DELAY,
H_SIZE => PACE_VIDEO_H_SIZE,
V_SIZE => PACE_VIDEO_V_SIZE,
L_CROP => PACE_VIDEO_L_CROP,
R_CROP => PACE_VIDEO_R_CROP,
H_SCALE => PACE_VIDEO_H_SCALE,
V_SCALE => PACE_VIDEO_V_SCALE,
H_SYNC_POL => PACE_VIDEO_H_SYNC_POLARITY,
V_SYNC_POL => PACE_VIDEO_V_SYNC_POLARITY,
BORDER_RGB => PACE_VIDEO_BORDER_RGB
)
pace_video_controller_inst : entity work.sonson_video_controller
port map
(
-- clocking etc
video_i => video_i,
-- register interface
reg_i.h_scale => "000",
reg_i.v_scale => "000",
-- video data signals (in)
rgb_i => rgb_data,
rgb_i => rgb_data,
-- video control signals (out)
video_ctl_o => from_video_ctl,
-- VGA signals (out)
video_o => video_o_s
video_o => video_o_s
);
pace_video_mixer_inst : entity work.pace_video_mixer
@@ -105,19 +88,19 @@ begin
sprite_rgb => sprite_ctl_o_s.rgb,
sprite_set => sprite_ctl_o_s.set,
sprite_pri => sprite_pri,
video_ctl_i => from_video_ctl,
graphics_i => graphics_i,
rgb_o => rgb_data
);
GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
--bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
end generate GEN_NO_BITMAPS;
GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
end generate GEN_NO_BITMAPS;
GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
@@ -222,30 +205,30 @@ begin
ctl_o => tilemap_ctl_o_s(2),
graphics_i => graphics_i
);
);
end generate GEN_TILEMAP_2;
end generate GEN_TILEMAP_2;
tilemap_ctl_o <= tilemap_ctl_o_s;
GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
sprite_pri <= '0';
spr0_hit <= '0';
end generate GEN_NO_SPRITES;
GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
sprites_inst : sprite_array
end generate GEN_NO_SPRITES;
GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
sprites_inst : sprite_array
generic map
(
N_SPRITES => PACE_VIDEO_NUM_SPRITES,
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
port map
(
reset => video_i.reset,
-- register interface
reg_i => sprite_reg_i,
@@ -254,16 +237,16 @@ begin
graphics_i => graphics_i,
row_a => sprite_ctl_o_s.a,
row_d => sprite_ctl_i.d,
rgb => sprite_ctl_o_s.rgb,
set => sprite_ctl_o_s.set,
pri => sprite_pri,
spr0_set => spr0_hit
);
row_a => sprite_ctl_o_s.a,
row_d => sprite_ctl_i.d,
end generate GEN_SPRITES;
rgb => sprite_ctl_o_s.rgb,
set => sprite_ctl_o_s.set,
pri => sprite_pri,
spr0_set => spr0_hit
);
end generate GEN_SPRITES;
sprite_ctl_o <= sprite_ctl_o_s;

144
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv → Arcade_MiST/Capcom SonSon Hardware/rtl/SonSon_MiST.sv
View File

@@ -1,38 +1,3 @@
/***************************************************************************
Son Son memory map (preliminary)
driver by Mirko Buffoni
MAIN CPU:
0000-0fff RAM
1000-13ff Video RAM
1400-17ff Color RAM
2020-207f Sprites
4000-ffff ROM
read:
3002 IN0
3003 IN1
3004 IN2
3005 DSW0
3006 DSW1
write:
3000 horizontal scroll
3008 watchdog reset
3018 flipscreen (inverted)
3010 command for the audio CPU
3019 trigger FIRQ on audio CPU
SOUND CPU:
0000-07ff RAM
e000-ffff ROM
read:
a000 command from the main CPU
write:
2000 8910 #1 control
2001 8910 #1 write
4000 8910 #2 control
4001 8910 #2 write
TODO:
- Fix Service Mode Output Test: press p1/p2 shot to insert coin
- Flip Screen DIP is noted in service manual and added to DIP LOCATIONS, but not working.
***************************************************************************/
module SonSon_MiST(
output LED,
output [5:0] VGA_R,
@@ -66,12 +31,12 @@ module SonSon_MiST(
`include "rtl/build_id.v"
localparam CONF_STR = {
"SONSON;ROM;",
"SONSON;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Freeze,Off,On;",
"O7,Flip,Off,On;",
//"O7,Flip,Off,On;",
"O8,Test,Off,On;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
@@ -87,13 +52,13 @@ wire test = status[8];
assign LED = ~ioctl_downl;
assign SDRAM_CKE = 1;
assign SDRAM_CLK = clk_sd;
wire clk_sys, clk_vid, clk_sd;
wire clk_sys, clk_sd;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys),//20
.c1(clk_vid),//40
.c0(clk_sys),//24
.c2(clk_sd),
.locked(pll_locked)
);
@@ -133,11 +98,12 @@ user_io(
);
wire [15:0] cpu_rom_addr;
//wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [12:0] tile_rom_addr;
//wire [12:0] tile_addr;
wire [12:0] snd_rom_addr;
wire [15:0] snd_do;
wire [13:1] tile_rom_addr;
wire [15:0] tile_do;
wire ioctl_downl;
@@ -147,7 +113,7 @@ wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sd ),
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
@@ -164,7 +130,7 @@ sdram sdram(
.init_n ( pll_locked ),
.clk ( clk_sd ),
// port1 used for main + sound CPU
// port1 used for main CPU + tiledata
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
@@ -175,17 +141,19 @@ sdram sdram(
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, cpu_rom_addr[15:1]} ),
.cpu1_q ( rom_do ),
.snd_addr ( ioctl_downl ? 16'hffff : (16'h6000 + tile_rom_addr[12:1]) ),
.snd_q ( tile_do ),
.tile_addr ( ioctl_downl ? 16'hffff : {1'b1, 2'b00, tile_rom_addr} ),
.tile_q ( tile_do ),
// port2 for sprite graphics
.port2_req ( ),
// port2 for sound CPU
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( ),
.port2_ds ( ),
.port2_we ( ),
.port2_d ( ),
.port2_q ( )
.port2_a ( ioctl_addr[23:1] ),
.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.snd_addr ( snd_rom_addr[12:1] ),
.snd_q ( snd_do )
);
// ROM download controller
@@ -198,7 +166,6 @@ always @(posedge clk_sys) begin
port2_req <= ~port2_req;
end
end
// async clock domain crossing here (clk_snd -> clk_sys)
end
// reset signal generation
@@ -217,18 +184,28 @@ always @(posedge clk_sys) begin
end
wire [11:0] audio;
wire [9:0] snd_l, snd_r;
wire hs, vs, hb, vb;
wire blankn = ~(hb | vb);
reg blankn;
wire [3:0] g,b,r;
wire vma;
reg clk_vid_en; // 6 MHz
always @(posedge clk_sys) begin
reg [1:0] count;
count <= count + 1'd1;
clk_vid_en <= 0;
if (count == 0) clk_vid_en <= 1;
if (clk_vid_en) blankn <= ~(hb | vb);
end
target_top target_top(
.clk_sys(clk_sys),
.clk_vid(clk_vid),
.clk_vid_en(clk_vid_en),
.reset_in(reset),
.vma(vma),
.snd_l(),
.snd_r(),
.snd_l(snd_l),
.snd_r(snd_r),
.vid_hs(hs),
.vid_vs(vs),
.vid_hb(hb),
@@ -236,16 +213,18 @@ target_top target_top(
.vid_r(r),
.vid_g(g),
.vid_b(b),
.inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireC}),
.inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2C}),
.inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireA}),
.inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2A}),
.inputs_sys(~{2'b00,m_coin2,m_coin1,2'b00,m_two_players,m_one_player}),
.inputs_dip1(~{flip,test,"011111"}),
.inputs_dip2(~{freeze,"1111111"}),
.inputs_dip1(~{flip,test,6'b011111}),
.inputs_dip2(~{freeze,7'b1111111}),
.cpu_rom_addr(cpu_rom_addr),
.cpu_rom_do(cpu_rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
.snd_rom_addr(snd_rom_addr),
.snd_rom_do(snd_rom_addr[0] ? snd_do[15:8] : snd_do[7:0]),
.tile_rom_addr(tile_rom_addr),
.tile_rom_do(tile_do)
);
);
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
@@ -255,35 +234,40 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.HSync ( ~hs ),
.VSync ( ~vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( { 1'b1, rotate } ),
.ce_divider ( 1'b0 ),
.scandoubler_disable( 1),// scandoublerD ),
.ce_divider ( 1'b1 ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.blend ( blend ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
wire dac_o;
assign AUDIO_L = dac_o;
assign AUDIO_R = dac_o;
dac #(
.C_bits(12))
dac(
.C_bits(10))
dac_l(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(dac_o)
.dac_i(snd_l),
.dac_o(AUDIO_L)
);
dac #(
.C_bits(10))
dac_r(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(snd_r),
.dac_o(AUDIO_R)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/YM2149.sv → Arcade_MiST/Capcom SonSon Hardware/rtl/YM2149.sv
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/bitmapctl_e.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/bitmapctl_e.vhd
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/build_id.tcl → Arcade_MiST/Capcom SonSon Hardware/rtl/build_id.tcl
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dpram.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/dpram.vhd
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dprom_2r.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/dprom_2r.vhd
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105
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/pace.vhd
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@@ -13,7 +13,7 @@ entity PACE is
(
-- clocks and resets
clkrst_i : in from_CLKRST_t;
vma : out std_logic;
-- controller inputs
inputs_p1 : in std_logic_vector(7 downto 0);
inputs_p2 : in std_logic_vector(7 downto 0);
@@ -29,10 +29,12 @@ entity PACE is
audio_o : out to_AUDIO_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
tile_rom_addr : out std_logic_vector(12 downto 0);
tile_rom_do : in std_logic_vector(15 downto 0)
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
tile_rom_addr : out std_logic_vector(12 downto 0);
tile_rom_do : in std_logic_vector(15 downto 0);
snd_rom_addr : out std_logic_vector(12 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0)
);
end entity PACE;
@@ -54,50 +56,53 @@ architecture SYN of PACE is
signal to_graphics : to_GRAPHICS_t;
signal from_graphics : from_GRAPHICS_t;
signal to_sound : to_SOUND_t;
signal from_sound : from_sound_t;
signal snd_irq : std_logic;
signal snd_data : std_logic_vector(7 downto 0);
signal video_out : to_VIDEO_t;
begin
video_o <= video_out;
platform_inst : entity work.platform
port map
(
-- clocking and reset
clkrst_i => clkrst_i,
vma => vma,
-- controller inputs
inputs_p1 => inputs_p1,
inputs_p2 => inputs_p2,
inputs_sys => inputs_sys,
inputs_dip1 => inputs_dip1,
inputs_dip2 => inputs_dip2,
inputs_p1 => inputs_p1,
inputs_p2 => inputs_p2,
inputs_sys => inputs_sys,
inputs_dip1 => inputs_dip1,
inputs_dip2 => inputs_dip2,
-- graphics
bitmap_i => from_bitmap_ctl,
bitmap_o => to_bitmap_ctl,
tilemap_i => from_tilemap_ctl,
tilemap_o => to_tilemap_ctl,
sprite_reg_o => to_sprite_reg,
sprite_i => from_sprite_ctl,
sprite_o => to_sprite_ctl,
spr0_hit => spr0_hit,
graphics_i => from_graphics,
graphics_o => to_graphics,
-- sound
snd_i => from_sound,
snd_o => to_sound,
snd_irq => snd_irq,
snd_data => snd_data,
platform_i => platform_i,
platform_o => platform_o,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do,
tile_rom_addr => tile_rom_addr,
tile_rom_do => tile_rom_do
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do,
tile_rom_addr => tile_rom_addr,
tile_rom_do => tile_rom_do
);
graphics_inst : entity work.Graphics
@@ -113,48 +118,30 @@ begin
sprite_ctl_i => to_sprite_ctl,
sprite_ctl_o => from_sprite_ctl,
spr0_hit => spr0_hit,
graphics_i => to_graphics,
graphics_o => from_graphics,
-- video (incl. clk)
video_i => video_i,
video_o => video_o
video_i => video_i,
video_o => video_out
);
SOUND_BLOCK : block
signal snd_data_l : std_logic_vector(7 downto 0);
signal snd_data_r : std_logic_vector(7 downto 0);
signal snd_a : std_logic_vector(15 downto 0);
begin
snd_a <= std_logic_vector(resize(unsigned(to_sound.a), snd_a'length));
sound_inst : entity work.Sound
generic map
sound_inst : entity work.sonson_soundboard
port map
(
CLK_MHz => CLK0_FREQ_MHz
)
port map
(
sysclk => clkrst_i.clk(0), -- fudge for now
reset => clkrst_i.rst(0),
-- clocking and reset
clkrst_i => clkrst_i,
sndif_rd => to_sound.rd,
sndif_wr => to_sound.wr,
sndif_addr => snd_a,
sndif_datai => to_sound.d,
sound_irq => snd_irq,
sound_data => snd_data,
vblank => video_out.vblank,
snd_clk => audio_o.clk,
snd_data_l => snd_data_l,
snd_data_r => snd_data_r,
sndif_datao => from_sound.d
);
audio_out_l => audio_o.ldata(9 downto 0),
audio_out_r => audio_o.rdata(9 downto 0),
snd_rom_addr => snd_rom_addr,
snd_rom_do => snd_rom_do
);
-- route audio to both channels
audio_o.ldata <= snd_data_l & "00000000";
audio_o.rdata <= snd_data_r & "00000000";
end block SOUND_BLOCK;
end SYN;

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/pace_pkg.vhd
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg_body.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/pace_pkg_body.vhd
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469
Arcade_MiST/Capcom SonSon Hardware/rtl/platform.vhd Normal file
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@@ -0,0 +1,469 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.sprite_pkg.all;
use work.platform_pkg.all;
entity platform is
port
(
-- clocking and reset
clkrst_i : in from_CLKRST_t;
-- controller inputs
inputs_p1 : in std_logic_vector(7 downto 0);
inputs_p2 : in std_logic_vector(7 downto 0);
inputs_sys : in std_logic_vector(7 downto 0);
inputs_dip1 : in std_logic_vector(7 downto 0);
inputs_dip2 : in std_logic_vector(7 downto 0);
bitmap_i : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
bitmap_o : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
tilemap_i : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
tilemap_o : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
sprite_reg_o : out to_SPRITE_REG_t;
sprite_i : in from_SPRITE_CTL_t;
sprite_o : out to_SPRITE_CTL_t;
spr0_hit : in std_logic;
snd_irq : out std_logic;
snd_data : out std_logic_vector(7 downto 0);
-- various graphics information
graphics_i : in from_GRAPHICS_t;
graphics_o : out to_GRAPHICS_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
tile_rom_addr : out std_logic_vector(12 downto 0);
tile_rom_do : in std_logic_vector(15 downto 0)
);
end platform;
architecture SYN of platform is
alias clk_24M : std_logic is clkrst_i.clk(0);
alias rst_24M : std_logic is clkrst_i.rst(0);
alias clk_video : std_logic is clkrst_i.clk(1);
signal cpu_reset : std_logic;
-- uP signals
signal clk_E : std_logic;
signal clk_Q : std_logic;
signal cpu_r_wn : std_logic;
signal cpu_a : std_logic_vector(15 downto 0);
signal cpu_d_i : std_logic_vector(7 downto 0);
signal cpu_d_o : std_logic_vector(7 downto 0);
signal cpu_irq : std_logic;
signal cpu_bs : std_logic;
signal cpu_ba : std_logic;
-- ROM signals
signal rom_cs : std_logic;
signal rom_d_o : std_logic_vector(7 downto 0);
-- RAM signals
signal wram_cs : std_logic;
signal wram_wr : std_logic;
signal wram_d_o : std_logic_vector(7 downto 0);
signal vram_cs : std_logic;
signal vram_d_o : std_logic_vector(7 downto 0);
signal vram_wr : std_logic;
signal cram_cs : std_logic;
signal cram_d_o : std_logic_vector(7 downto 0);
signal cram_wr : std_logic;
signal sprite_cs : std_logic;
-- I/O signals
signal scroll_cs : std_logic;
signal in0_cs : std_logic;
signal in1_cs : std_logic;
signal in2_cs : std_logic;
signal dsw1_cs : std_logic;
signal dsw2_cs : std_logic;
signal snd_cs : std_logic;
signal vblank_r : std_logic;
COMPONENT mc6809i
GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" );
PORT
(
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
RnW : OUT STD_LOGIC;
E : IN STD_LOGIC;
Q : IN STD_LOGIC;
BS : OUT STD_LOGIC;
BA : OUT STD_LOGIC;
nIRQ : IN STD_LOGIC;
nFIRQ : IN STD_LOGIC;
nNMI : IN STD_LOGIC;
AVMA : OUT STD_LOGIC;
BUSY : OUT STD_LOGIC;
LIC : OUT STD_LOGIC;
nHALT : IN STD_LOGIC;
nRESET : IN STD_LOGIC;
nDMABREQ : IN STD_LOGIC;
RegData : OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
);
END COMPONENT;
begin
wram_cs <= '1' when STD_MATCH(cpu_a, "0000------------") else '0';-- RAM $0000-$0FFF
vram_cs <= '1' when STD_MATCH(cpu_a, "000100----------") else '0';-- video ram $1000-$13FF
cram_cs <= '1' when STD_MATCH(cpu_a, "000101----------") else '0';-- colour ram $1400-$17FF
sprite_cs <= '1' when STD_MATCH(cpu_a, X"20"&"001-----") else
'1' when STD_MATCH(cpu_a, X"20"&"01------") else
'0';-- sprite 'ram' $2020-$207F
-- I/O
scroll_cs <= '1' when STD_MATCH(cpu_a, X"3000") else '0';
in0_cs <= '1' when STD_MATCH(cpu_a, X"3002") else '0';
in1_cs <= '1' when STD_MATCH(cpu_a, X"3003") else '0';
in2_cs <= '1' when STD_MATCH(cpu_a, X"3004") else '0';
dsw1_cs <= '1' when STD_MATCH(cpu_a, X"3005") else '0';
dsw2_cs <= '1' when STD_MATCH(cpu_a, X"3006") else '0';
rom_cs <= '1' when (cpu_a > X"3FFF") else '0';
snd_cs <= '1' when cpu_a(15 downto 4) = x"301" else '0';
-- memory block write enables
wram_wr <= wram_cs and not cpu_r_wn;
vram_wr <= vram_cs and not cpu_r_wn;
cram_wr <= cram_cs and not cpu_r_wn;
-- memory read mux
cpu_d_i <= wram_d_o when wram_cs = '1' else
vram_d_o when vram_cs = '1' else
cram_d_o when cram_cs = '1' else
inputs_p1 when in0_cs = '1' else
inputs_p2 when in1_cs = '1' else
inputs_sys when in2_cs = '1' else
inputs_dip1 when dsw1_cs = '1' else
inputs_dip2 when dsw2_cs = '1' else
-- flip off, service off, coin A, 1C1C
-- (X"80" or X"40" or X"10" or X"0F") when dsw1_cs = '1' else
-- freeze off, easy, 20K/80K/100K, 3 lives
-- (X"80" or X"60" or X"08" or X"03") when dsw2_cs = '1' else
rom_d_o when rom_cs = '1' else
(others => 'Z');
-- sound control
process (clk_24M, rst_24M)
variable count : unsigned(3 downto 0);
begin
if rst_24M = '1' then
snd_irq <= '0';
snd_data <= (others => '0');
elsif rising_edge(clk_24M) then
if snd_cs = '1' then
if cpu_a(3) = '1' then
snd_irq <= cpu_d_o(0);
else
snd_data <= cpu_d_o;
end if;
end if;
end if;
end process;
-- system timing
process (clk_24M)
variable count : unsigned(3 downto 0);
begin
if rising_edge(clk_24M) then
count := count + 1;
if count(1 downto 0) = "11" then
case count(3 downto 2) is
when "00" => clk_E <= '0';
when "01" => clk_Q <= '1';
when "10" => clk_E <= '1';
when "11" => clk_Q <= '0';
end case;
end if;
end if;
end process;
cpu_reset <= rst_24M;
cpu_inst : mc6809i
port map
(
D => cpu_d_i,
DOut => cpu_d_o,
ADDR => cpu_a,
RnW => cpu_r_wn,
E => clk_E,
Q => clk_Q,
BS => cpu_bs,
BA => cpu_ba,
nIRQ => not cpu_irq,
nFIRQ => '1',
nNMI => '1',
AVMA => open,
BUSY => open,
LIC => open,
nHALT => '1',
nRESET => not cpu_reset,
nDMABREQ => '1',
RegData => open
);
--WRAm_cs
wram_inst : entity work.spram
generic map
(
widthad_a => 12,
width_a => 8
)
port map
(
address => cpu_a(11 downto 0),
clock => clk_24M,
data => cpu_d_o,
wren => wram_wr,
q => wram_d_o
);
-- irq vblank interrupt
process (clk_24M, rst_24M)
begin
if rst_24M = '1' then
cpu_irq <= '0';
elsif rising_edge(clk_24M) then
vblank_r <= graphics_i.vblank;
if vblank_r = '0' and graphics_i.vblank = '1' then
cpu_irq <= '1';
elsif cpu_ba = '0' and cpu_bs = '1' then
cpu_irq <= '0';
end if;
end if;
end process;
-- scroll register
process (clk_24M, rst_24M)
begin
if rst_24M = '1' then
graphics_o.bit8(0) <= (others => '0');
elsif rising_edge(clk_24M) then
if scroll_cs and not cpu_r_wn then
graphics_o.bit8(0) <= cpu_d_o;
end if;
end if;
end process;
cpu_rom_addr <= cpu_a(15 downto 0);
rom_d_o <= cpu_rom_do;
-- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE
vram_inst : entity work.dpram
generic map
(
init_file => "./roms/vram.hex",
widthad_a => 10
)
port map
(
clock_b => clk_24M,
address_b => cpu_a(9 downto 0),
wren_b => vram_wr,
data_b => cpu_d_o,
q_b => vram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).map_a(9 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).map_d(7 downto 0)
);
tilemap_o(1).map_d(tilemap_o(1).map_d'left downto 8) <= (others => 'Z');
-- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE
cram_inst : entity work.dpram
generic map
(
init_file => "./roms/cram.hex",
widthad_a => 10
)
port map
(
clock_b => clk_24M,
address_b => cpu_a(9 downto 0),
wren_b => cram_wr,
data_b => cpu_d_o,
q_b => cram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).attr_a(9 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).attr_d(7 downto 0)
);
tilemap_o(1).attr_d(tilemap_o(1).attr_d'left downto 8) <= (others => 'Z');
tile_rom_addr <= tilemap_i(1).tile_a(12 downto 0);
tilemap_o(1).tile_d(15 downto 0) <= tile_rom_do;
BLK_SPRITES : block
signal bit0_1 : std_logic_vector(7 downto 0); -- offset 0
signal bit0_2 : std_logic_vector(7 downto 0); -- offset 0
signal bit0_3 : std_logic_vector(7 downto 0); -- offset 16
signal bit0_4 : std_logic_vector(7 downto 0); -- offset 16
signal bit1_1 : std_logic_vector(7 downto 0);
signal bit1_2 : std_logic_vector(7 downto 0);
signal bit1_3 : std_logic_vector(7 downto 0);
signal bit1_4 : std_logic_vector(7 downto 0);
signal bit2_1 : std_logic_vector(7 downto 0);
signal bit2_2 : std_logic_vector(7 downto 0);
signal bit2_3 : std_logic_vector(7 downto 0);
signal bit2_4 : std_logic_vector(7 downto 0);
signal sprite_a_00 : std_logic_vector(12 downto 0);
signal sprite_a_16 : std_logic_vector(12 downto 0);
begin
-- registers
sprite_reg_o.clk <= clk_24M;
sprite_reg_o.clk_ena <= '1';
sprite_reg_o.a <= cpu_a(sprite_reg_o.a'range);
sprite_reg_o.d <= cpu_d_o;
sprite_reg_o.wr <= sprite_cs and not cpu_r_wn;
-- - sprite data consists of:
-- 16 consecutive bytes for the 1st half
-- then the next 16 bytes for the 2nd half
-- - because we need to fetch an entire row at once
-- use dual-port memory to access both halves of each row
-- generate address for each port
sprite_a_00 <= sprite_i.a(12 downto 5) & '0' & sprite_i.a(3 downto 0);
sprite_a_16 <= sprite_i.a(12 downto 5) & '1' & sprite_i.a(3 downto 0);
-- sprite rom (bit 0, part 1/2)
ss_9_m5_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/ss_9_m5.hex",
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
address_a => sprite_a_00,
q_a => bit0_1,
address_b => sprite_a_16,
q_b => bit0_3
);
-- sprite rom (bit 0, part 2/2)
ss_10_m6_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/ss_10_m6.hex",
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
address_a => sprite_a_00,
q_a => bit0_2,
address_b => sprite_a_16,
q_b => bit0_4
);
sprite_o.d(15 downto 0) <= (bit0_1 & bit0_3) when sprite_i.a(13) = '0' else
(bit0_2 & bit0_4);
-- sprite rom (bit 1, part 1/2)
ss_11_m3_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/ss_11_m3.hex",
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
address_a => sprite_a_00,
q_a => bit1_1,
address_b => sprite_a_16,
q_b => bit1_3
);
-- sprite rom (bit 1, part 2/2)
ss_12_m4_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/ss_12_m4.hex",
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
address_a => sprite_a_00,
q_a => bit1_2,
address_b => sprite_a_16,
q_b => bit1_4
);
sprite_o.d(31 downto 16) <= (bit1_1 & bit1_3) when sprite_i.a(13) = '0' else
(bit1_2 & bit1_4);
-- sprite rom (bit 2, part 1/2)
ss_13_m1_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/ss_13_m1.hex",
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
address_a => sprite_a_00,
q_a => bit2_1,
address_b => sprite_a_16,
q_b => bit2_3
);
-- sprite rom (bit 2, part 2/2)
ss_14_m2_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/ss_14_m2.hex",
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
address_a => sprite_a_00,
q_a => bit2_2,
address_b => sprite_a_16,
q_b => bit2_4
);
sprite_o.d(47 downto 32) <= (bit2_1 & bit2_3) when sprite_i.a(13) = '0' else
(bit2_2 & bit2_4);
end block BLK_SPRITES;
-- unused outputs
graphics_o.bit16(0) <= (others => '0');
end SYN;

35
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform_pkg.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/platform_pkg.vhd
View File

@@ -8,35 +8,24 @@ use work.video_controller_pkg.all;
package platform_pkg is
constant PACE_HAS_PLL : boolean := true;
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz; --40
constant PACE_CLK0_DIVIDE_BY : natural := 27;
constant PACE_CLK0_MULTIPLY_BY : natural := 20; -- 20MHz
constant PACE_CLK0_MULTIPLY_BY : natural := 24; -- 20MHz
constant PACE_CLK1_DIVIDE_BY : natural := 27;
constant PACE_CLK1_MULTIPLY_BY : natural := 40; -- 40MHz
constant PACE_VIDEO_H_SCALE : integer := 2;
constant PACE_VIDEO_V_SCALE : integer := 2;
constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1';
constant PACE_CLK1_MULTIPLY_BY : natural := 6; -- 40MHz
constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK;
constant PACE_VIDEO_NUM_BITMAPS : natural := 0;
constant PACE_VIDEO_NUM_TILEMAPS : natural := 1;
constant PACE_VIDEO_NUM_SPRITES : natural := 24;
constant PACE_VIDEO_H_SIZE : integer := 256; -- 240
constant PACE_VIDEO_V_SIZE : integer := 256; -- 240
constant PACE_VIDEO_L_CROP : integer := (256-240)/2;
constant PACE_VIDEO_R_CROP : integer := PACE_VIDEO_L_CROP;
constant PACE_VIDEO_PIPELINE_DELAY : integer := 3;
constant PACE_INPUTS_NUM_BYTES : integer := 4;
--
-- Platform-specific constants (optional)
--
constant PACE_VIDEO_NUM_BITMAPS : natural := 0;
constant PACE_VIDEO_NUM_TILEMAPS : natural := 1;
constant PACE_VIDEO_NUM_SPRITES : natural := 24;
constant PACE_VIDEO_PIPELINE_DELAY : integer := 3;
constant PACE_INPUTS_NUM_BYTES : integer := 4;
--
-- Platform-specific constants (optional)
--
constant CLK0_FREQ_MHz : natural :=
27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.qip → Arcade_MiST/Capcom SonSon Hardware/rtl/pll.qip
View File

90
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.v → Arcade_MiST/Capcom SonSon Hardware/rtl/pll.v
View File

@@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@@ -40,14 +40,12 @@ module pll (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
@@ -58,24 +56,22 @@ module pll (
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire6 = 1'h0;
wire locked = sub_wire0;
wire [2:2] sub_wire3 = sub_wire1[2:2];
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.inclk (sub_wire5),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
@@ -111,17 +107,13 @@ module pll (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 20,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 27,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 40,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 40,
altpll_component.clk2_divide_by = 3,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 83,
altpll_component.clk2_multiply_by = 8,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
@@ -156,7 +148,7 @@ module pll (
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
@@ -197,14 +189,11 @@ endmodule
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "40"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "56.025002"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "72.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -225,33 +214,25 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "83"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "56.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "72.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
@@ -275,32 +256,25 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "83"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
@@ -334,7 +308,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -354,7 +328,6 @@ endmodule
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
@@ -362,7 +335,6 @@ endmodule
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/cram.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/cram.hex
View File

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_10_m6.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_10_m6.hex
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_11_m3.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_11_m3.hex
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_12_m4.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_12_m4.hex
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_13_m1.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_13_m1.hex
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_14_m2.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_14_m2.hex
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_9_m5.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/ss_9_m5.hex
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/vram.hex → Arcade_MiST/Capcom SonSon Hardware/rtl/roms/vram.hex
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34
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv → Arcade_MiST/Capcom SonSon Hardware/rtl/sdram.sv
View File

@@ -46,8 +46,10 @@ module sdram (
input [15:0] port1_d,
output [15:0] port1_q,
input [15:1] cpu1_addr,
input [16:1] cpu1_addr,
output reg [15:0] cpu1_q,
input [16:1] tile_addr,
output reg [15:0] tile_q,
input port2_req,
output reg port2_ack,
@@ -61,6 +63,8 @@ module sdram (
output reg [15:0] snd_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
@@ -70,8 +74,8 @@ localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single acc
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
@@ -147,16 +151,20 @@ assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [15:1] addr_last[2];
reg [15:1] addr_last2[2];
reg [16:1] addr_last[2];
reg [16:1] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_REQ = 2'd2;
localparam PORT_TILE = 2'd2;
localparam PORT_REQ = 2'd3;
localparam PORT_SND = 2'd1;
@@ -172,12 +180,15 @@ always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_ack) begin
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 9'd0, cpu1_addr };
addr_latch_next[0] = { 8'd0, cpu1_addr };
end else if (tile_addr != addr_last[PORT_TILE]) begin
next_port[0] = PORT_TILE;
addr_latch_next[0] = { 8'd0, tile_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
@@ -186,7 +197,7 @@ end
// PORT2: bank 2,3
always @(*) begin
if (port2_req ^ port2_ack) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (snd_addr != addr_last2[PORT_SND]) begin
@@ -238,11 +249,12 @@ always @(posedge clk) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][15:1];
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
@@ -266,6 +278,7 @@ always @(posedge clk) begin
{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port1_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
@@ -307,6 +320,7 @@ always @(posedge clk) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_TILE: begin tile_q <= sd_din; end
default: ;
endcase;
end

262
Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd Normal file
View File

@@ -0,0 +1,262 @@
library ieee;
use work.pace_pkg.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
entity sonson_soundboard is
port(
clkrst_i : in from_CLKRST_t;
sound_irq : in std_logic;
sound_data : in std_logic_vector(7 downto 0);
vblank : in std_logic;
audio_out_l : out std_logic_vector(9 downto 0);
audio_out_r : out std_logic_vector(9 downto 0);
snd_rom_addr : out std_logic_vector(12 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0)
);
end sonson_soundboard;
architecture SYN of sonson_soundboard is
component YM2149
port (
CLK : in std_logic;
CE : in std_logic;
RESET : in std_logic;
A8 : in std_logic := '1';
A9_L : in std_logic := '0';
BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write)
BC : in std_logic; -- Bus control
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CHANNEL_A : out std_logic_vector(7 downto 0);
CHANNEL_B : out std_logic_vector(7 downto 0);
CHANNEL_C : out std_logic_vector(7 downto 0);
SEL : in std_logic;
MODE : in std_logic;
ACTIVE : out std_logic_vector(5 downto 0);
IOA_in : in std_logic_vector(7 downto 0);
IOA_out : out std_logic_vector(7 downto 0);
IOB_in : in std_logic_vector(7 downto 0);
IOB_out : out std_logic_vector(7 downto 0)
);
end component;
COMPONENT mc6809i
GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" );
PORT
(
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
RnW : OUT STD_LOGIC;
E : IN STD_LOGIC;
Q : IN STD_LOGIC;
BS : OUT STD_LOGIC;
BA : OUT STD_LOGIC;
nIRQ : IN STD_LOGIC;
nFIRQ : IN STD_LOGIC;
nNMI : IN STD_LOGIC;
AVMA : OUT STD_LOGIC;
BUSY : OUT STD_LOGIC;
LIC : OUT STD_LOGIC;
nHALT : IN STD_LOGIC;
nRESET : IN STD_LOGIC;
nDMABREQ : IN STD_LOGIC;
RegData : OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
);
END COMPONENT;
alias clk : std_logic is clkrst_i.clk(0);
alias reset : std_logic is clkrst_i.rst(0);
signal clk_E : std_logic;
signal clk_Q : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal cpu_ba : std_logic;
signal cpu_bs : std_logic;
signal wram_cs : std_logic;
signal wram_we : std_logic;
signal wram_do : std_logic_vector( 7 downto 0);
signal rom_cs : std_logic;
signal snd_rd : std_logic;
signal clk_en_snd : std_logic; -- 1.5 MHz
signal ay1_cs : std_logic;
signal ay1_chan_a : std_logic_vector(7 downto 0);
signal ay1_chan_b : std_logic_vector(7 downto 0);
signal ay1_chan_c : std_logic_vector(7 downto 0);
signal ay1_do : std_logic_vector(7 downto 0);
signal ay1_port_b_do : std_logic_vector(7 downto 0);
signal ay2_cs : std_logic;
signal ay2_chan_a : std_logic_vector(7 downto 0);
signal ay2_chan_b : std_logic_vector(7 downto 0);
signal ay2_chan_c : std_logic_vector(7 downto 0);
signal ay2_do : std_logic_vector(7 downto 0);
signal vblank_r : std_logic;
begin
-- cs
snd_rd <= '1' when cpu_addr(15 downto 13) = "101" else '0'; -- a000
wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- 0000-07ff RAM
rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; -- e000-ffff ROM
ay1_cs <= '1' when cpu_addr(15 downto 13) = "001" else '0'; -- 2000
ay2_cs <= '1' when cpu_addr(15 downto 13) = "010" else '0'; -- 4000
-- write enables
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
-- mux cpu in data between roms/io/wram
cpu_di <= wram_do when wram_cs = '1' else
sound_data when snd_rd = '1' else
ay1_do when ay1_cs = '1' else
ay2_do when ay2_cs = '1' else
snd_rom_do when rom_cs = '1' else X"FF";
process (clk)
variable count : unsigned(3 downto 0);
begin
if rising_edge(clk) then
count := count + 1;
if count(1 downto 0) = "11" then
case count(3 downto 2) is
when "00" => clk_E <= '0';
when "01" => clk_Q <= '1';
when "10" => clk_E <= '1';
when "11" => clk_Q <= '0';
end case;
end if;
clk_en_snd <= '0';
if count = "0000" then
clk_en_snd <= '1';
end if;
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
cpu_irq <= '0';
elsif rising_edge(clk) then
vblank_r <= vblank;
if vblank_r = '0' and vblank = '1' then
cpu_irq <= '1';
elsif cpu_ba = '0' and cpu_bs = '1' then
cpu_irq <= '0';
end if;
end if;
end process;
cpu_inst : mc6809i
port map
(
D => cpu_di,
DOut => cpu_do,
ADDR => cpu_addr,
RnW => cpu_rw,
E => clk_E,
Q => clk_Q,
BS => cpu_bs,
BA => cpu_ba,
nIRQ => not cpu_irq,
nFIRQ => sound_irq,
nNMI => '1',
AVMA => open,
BUSY => open,
LIC => open,
nHALT => '1',
nRESET => not reset,
nDMABREQ => '1',
RegData => open
);
snd_rom_addr <= cpu_addr(12 downto 0);
cpu_ram : entity work.spram
generic map( widthad_a => 11)
port map(
clock => clk,
wren => wram_we,
address => cpu_addr(10 downto 0),
data => cpu_do,
q => wram_do
);
ay83910_inst1: YM2149
port map (
CLK => clk,
CE => clk_en_snd,
RESET => reset,
A8 => '1',
A9_L => not ay1_cs,
BDIR => not cpu_rw,
BC => not cpu_addr(0) or cpu_rw,
DI => cpu_do,
DO => ay1_do,
CHANNEL_A => ay1_chan_a,
CHANNEL_B => ay1_chan_b,
CHANNEL_C => ay1_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => (others => '0'),
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => open
);
audio_out_l <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
ay83910_inst2: YM2149
port map (
CLK => clk,
CE => clk_en_snd,
RESET => reset,
A8 => '1',
A9_L => not ay2_cs,
BDIR => not cpu_rw,
BC => not cpu_addr(0) or cpu_rw,
DI => cpu_do,
DO => ay2_do,
CHANNEL_A => ay2_chan_a,
CHANNEL_B => ay2_chan_b,
CHANNEL_C => ay2_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => (others => '0'),
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => open
);
audio_out_r <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
end SYN;

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@@ -0,0 +1,129 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.video_controller_pkg.all;
entity sonson_video_controller is
port
(
-- clocking etc
video_i : in from_VIDEO_t;
-- video input data
rgb_i : in RGB_t;
-- control signals (out)
video_ctl_o : out from_VIDEO_CTL_t;
-- video output control & data
video_o : out to_VIDEO_t
);
end sonson_video_controller;
architecture SYN of sonson_video_controller is
alias clk : std_logic is video_i.clk;
alias clk_ena : std_logic is video_i.clk_ena;
alias reset : std_logic is video_i.reset;
signal hcnt : unsigned(8 downto 0);
signal vcnt : unsigned(8 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
signal hblank : std_logic; -- hblank mux
signal hblank1 : std_logic; -- normal hblank
signal hblank2 : std_logic; -- shifted hblank for some games
signal vblank : std_logic;
begin
-------------------
-- Video scanner --
-------------------
-- Note: this is not what the hardware originally has.
-- hcnt [x180..x1FF-x000..x0FF] => 128+256 = 384 pixels, 384/6Mhz => 1 line is 64us (15.6KHz)
-- vcnt [x1FA..x1FF-x000..x0FF] => 6+256 = 262 lines, 1 frame is 262 x 64us = 16.76ms (59.6Hz)
process (reset, clk, clk_ena)
begin
if reset='1' then
hcnt <= (others=>'0');
vcnt <= '1'&X"FC";
elsif rising_edge(clk) and clk_ena = '1'then
hcnt <= hcnt + 1;
if hcnt = '0'&x"FF" then
hcnt <= '1'&x"80";
vcnt <= vcnt + 1;
if vcnt = '0'&x"FF" then
vcnt <= '1'&x"FA";
end if;
end if;
end if;
end process;
process (reset, clk, clk_ena)
begin
if reset = '1' then
hsync <= '0';
vsync <= '0';
hblank <= '1';
vblank <= '1';
elsif rising_edge(clk) and clk_ena = '1' then
-- display blank
if hcnt = '0'&x"0F" then
hblank <= '0';
if vcnt = '0'&x"00" then
vblank <= '0';
end if;
end if;
if hcnt = '0'&x"FF" then
hblank <= '1';
if vcnt = '0'&x"FF" then
vblank <= '1';
end if;
end if;
-- display sync
if hcnt = '1'&x"A8" then
hsync <= '1';
if vcnt = '1'&x"FC" then
vsync <= '1';
end if;
end if;
if hcnt = '1'&x"DF" then
hsync <= '0';
if vcnt = '1'&x"FE" then
vsync <= '0';
end if;
end if;
-- registered rgb output
if hblank = '1' or vblank = '1' then
video_o.rgb <= RGB_BLACK;
else
video_o.rgb <= rgb_i;
end if;
end if;
end process;
video_o.hsync <= hsync;
video_o.vsync <= vsync;
video_o.hblank <= hblank;
video_o.vblank <= vblank;
video_ctl_o.stb <= '1';
video_ctl_o.x <= "00"&std_logic_vector(hcnt);
video_ctl_o.y <= "00"&std_logic_vector(vcnt);
-- blank signal goes to tilemap/spritectl
video_ctl_o.hblank <= hblank;
video_ctl_o.vblank <= vblank;
-- pass-through for tile/bitmap & sprite controllers
video_ctl_o.clk <= clk;
video_ctl_o.clk_ena <= clk_ena;
-- for video DACs and TFT output
video_o.clk <= clk;
end SYN;

0
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0
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2
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_array.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_array.vhd
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@@ -73,12 +73,12 @@ begin
i := 0;
elsif rising_edge(clk) and clk_ena = '1' then
ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left);
row_a <= ctl_o(i).a;
if i = N_SPRITES-1 then
i := 0;
else
i := i + 1;
end if;
row_a <= ctl_o(i).a;
end if;
end process;

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_pkg.vhd
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0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg_body.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/sprite_pkg_body.vhd
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43
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritectl.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/spritectl.vhd
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@@ -47,10 +47,9 @@ architecture SYN of spritectl is
begin
-- handle xflip
flipData(47 downto 32) <= flip_row (ctl_i.d(47 downto 32), reg_i.xflip);
flipData(31 downto 16) <= flip_row (ctl_i.d(31 downto 16), reg_i.xflip);
flipData(15 downto 0) <= flip_row (ctl_i.d(15 downto 0), reg_i.xflip);
flipData(47 downto 32) <= ctl_i.d(47 downto 32);
flipData(31 downto 16) <= ctl_i.d(31 downto 16);
flipData(15 downto 0) <= ctl_i.d(15 downto 0);
process (clk)
@@ -61,10 +60,7 @@ begin
variable yMat : boolean; -- raster is between first and last line of sprite
variable xMat : boolean; -- raster in between left edge and end of line
-- the width of rowCount determines the scanline multipler
-- - eg. (4 downto 0) is 1:1
-- (5 downto 0) is 2:1 (scan-doubling)
variable rowCount : std_logic_vector(3+PACE_VIDEO_V_SCALE downto 0);
variable rowCount : std_logic_vector(4 downto 0);
variable clut_i : integer range 0 to 31;
variable clut_entry : sprite_clut_entry_t;
@@ -77,7 +73,7 @@ begin
if rising_edge(clk) then
if clk_ena = '1' then
x := unsigned(reg_i.x);
x := unsigned(reg_i.x) + 8;
y := unsigned(reg_i.y);
if video_ctl.hblank = '1' then
@@ -92,7 +88,7 @@ begin
-- start counting sprite row
rowCount := (others => '0');
yMat := true;
elsif rowCount(rowCount'left downto rowCount'left-4) = "10000" then
elsif rowCount(4 downto 0) = "10000" then
yMat := false;
end if;
@@ -103,21 +99,28 @@ begin
rowStore := (others => '0');
end if;
end if;
elsif video_ctl.stb = '1' then
if unsigned(video_ctl.x) = x then
-- count up at left edge of sprite
rowCount := std_logic_vector(unsigned(rowCount) + 1);
xMat := true;
end if;
if xMat then
-- shift in next pixel
pel := rowStore(32) & rowStore(16) & rowStore(0);
rowStore(47 downto 32) := '0' & rowStore(47 downto 33);
rowStore(31 downto 16) := '0' & rowStore(31 downto 17);
rowStore(15 downto 0) := '0' & rowStore(15 downto 1);
if reg_i.xflip = '1' then
pel := rowStore(47) & rowStore(31) & rowStore(15);
rowStore(47 downto 32) := rowStore(46 downto 32) & '0';
rowStore(31 downto 16) := rowStore(30 downto 16) & '0';
rowStore(15 downto 0) := rowStore(14 downto 0) & '0';
else
pel := rowStore(32) & rowStore(16) & rowStore(0);
rowStore(47 downto 32) := '0' & rowStore(47 downto 33);
rowStore(31 downto 16) := '0' & rowStore(31 downto 17);
rowStore(15 downto 0) := '0' & rowStore(15 downto 1);
end if;
end if;
end if;
@@ -149,11 +152,11 @@ begin
-- use dual-port memory to access both halves of each row
ctl_o.a(4) <= '0'; -- used for 1st/2nd port of dual-port memory
if reg_i.yflip = '1' then
ctl_o.a(3 downto 0) <= not rowCount(rowCount'left-1 downto rowCount'left-4);
ctl_o.a(3 downto 0) <= not rowCount(3 downto 0);
else
ctl_o.a(3 downto 0) <= rowCount(rowCount'left-1 downto rowCount'left-4);
ctl_o.a(3 downto 0) <= rowCount(3 downto 0);
end if;
end if; -- rising_edge(clk)
end process;

2
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritereg.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/spritereg.vhd
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@@ -26,7 +26,7 @@ architecture SYN of sptReg is
begin
process (clk)
process (clk, reg_i)
variable i : integer range 0 to 31;
begin
-- sprite registers $2020-$207F, 4 bytes per sprite

0
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109
Arcade_MiST/Capcom SonSon Hardware/rtl/target_top.vhd Normal file
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@@ -0,0 +1,109 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.platform_pkg.all;
entity target_top is
port(
clk_sys : in std_logic;
clk_vid_en : in std_logic;
reset_in : in std_logic;
snd_l : out std_logic_vector(9 downto 0);
snd_r : out std_logic_vector(9 downto 0);
vid_hs : out std_logic;
vid_vs : out std_logic;
vid_hb : out std_logic;
vid_vb : out std_logic;
vid_r : out std_logic_vector(3 downto 0);
vid_g : out std_logic_vector(3 downto 0);
vid_b : out std_logic_vector(3 downto 0);
inputs_p1 : in std_logic_vector(7 downto 0);
inputs_p2 : in std_logic_vector(7 downto 0);
inputs_sys : in std_logic_vector(7 downto 0);
inputs_dip1 : in std_logic_vector(7 downto 0);
inputs_dip2 : in std_logic_vector(7 downto 0);
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
tile_rom_addr : out std_logic_vector(12 downto 0);
tile_rom_do : in std_logic_vector(15 downto 0);
snd_rom_addr : out std_logic_vector(12 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0)
);
end target_top;
architecture SYN of target_top is
signal clkrst_i : from_CLKRST_t;
signal video_i : from_VIDEO_t;
signal video_o : to_VIDEO_t;
signal audio_i : from_AUDIO_t;
signal audio_o : to_AUDIO_t;
signal platform_i : from_PLATFORM_IO_t;
signal platform_o : to_PLATFORM_IO_t;
begin
clkrst_i.clk(0) <=clk_sys;
clkrst_i.clk(1) <= clk_sys;
clkrst_i.arst <= reset_in;
clkrst_i.arst_n <= not clkrst_i.arst;
video_i.clk <= clk_sys;
video_i.clk_ena <= clk_vid_en;
video_i.reset <= reset_in;
GEN_RESETS : for i in 0 to 3 generate
process (clkrst_i)
variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
begin
if clkrst_i.arst = '1' then
rst_r := (others => '1');
elsif rising_edge(clkrst_i.clk(i)) then
rst_r := rst_r(rst_r'left-1 downto 0) & '0';
end if;
clkrst_i.rst(i) <= rst_r(rst_r'left);
end process;
end generate GEN_RESETS;
vid_r <= video_o.rgb.r(9 downto 6);
vid_g <= video_o.rgb.g(9 downto 6);
vid_b <= video_o.rgb.b(9 downto 6);
vid_hs <= video_o.hsync;
vid_vs <= video_o.vsync;
vid_hb <= video_o.hblank;
vid_vb <= video_o.vblank;
snd_l <= audio_o.ldata(9 downto 0);
snd_r <= audio_o.rdata(9 downto 0);
pace_inst : entity work.pace
port map(
clkrst_i => clkrst_i,
inputs_p1 => inputs_p1,
inputs_p2 => inputs_p2,
inputs_sys => inputs_sys,
inputs_dip1 => inputs_dip1,
inputs_dip2 => inputs_dip2,
video_i => video_i,
video_o => video_o,
audio_i => audio_i,
audio_o => audio_o,
platform_i => platform_i,
platform_o => platform_o,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do,
tile_rom_addr => tile_rom_addr,
tile_rom_do => tile_rom_do,
snd_rom_addr => snd_rom_addr,
snd_rom_do => snd_rom_do
);
end SYN;

23
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/tilemapctl.vhd
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@@ -55,34 +55,35 @@ begin
if rising_edge(clk) then
if clk_ena = '1' then
-- video is clipped left and right (only 224 wide)
-- don't scroll the fist 5 lines
if unsigned(y) < 40 then
x_adj := unsigned(x);
else
x_adj := unsigned(x) + unsigned(scroll);
end if;
-- 1st stage of pipeline
-- - read tile from tilemap
-- - read attribute data
if stb = '1' then
ctl_o.map_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3));
ctl_o.attr_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3));
if x_adj(2 downto 0) = "000" then
ctl_o.map_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3));
ctl_o.attr_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3));
end if;
end if;
-- 2nd stage of pipeline
-- - read tile data from tile ROM
if stb = '1' then
if x_adj(2 downto 0) = "001" then
attr_d_r := ctl_i.attr_d(attr_d_r'range);
--map_d_r := ctl_i.map_d(map_d_r'range);
if x_adj(2 downto 0) = "010" then
ctl_o.tile_a(12 downto 11) <= ctl_i.attr_d(1 downto 0);
ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0);
end if;
end if;
ctl_o.tile_a(12 downto 11) <= attr_d_r(1 downto 0);
ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0);
if stb = '1' then
if x_adj(2 downto 0) = "010" then
if x_adj(2 downto 0) = "111" then
attr_d_r := ctl_i.attr_d(attr_d_r'range);
tile_d_r := ctl_i.tile_d(tile_d_r'range);
else
tile_d_r(15 downto 8) := tile_d_r(14 downto 8) & '0';

0
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl_e.vhd → Arcade_MiST/Capcom SonSon Hardware/rtl/tilemapctl_e.vhd
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0
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109
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md
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@@ -1,109 +0,0 @@
# Cycle Accurate MC6809 Core
## Details
This is a Verilog implementation of the Motorola MC6809 and MC6809E microprocessors from late 1970s. It is intentionally implemented in a manner to make it as similar as possible to the original microprocessors.
When this was implemented, other 6809 cores already had been written. These other cores were in use and had been verified. Although I've never used any of these cores, I'm confident that they're excellent replications of the instruction set. However, none (as far as I know) was verified to be cycle-accurate. Encouragement from several sources (particularly one very generous source) convinced me to invest the time.
Beyond merely cycle-accurate, the goal was to attempt to preserve as much of the actual bus signals and protocols as possible. Signals such as DMABREQ, TSC, MRDY, and LIC, while infrequently used were still implemented. Bus traffic was identified with a Logic Analyzer and matched to the 6809's specs (and, truthfully, when the specs were vague, details captured from hard MC6809/MC6809E part behavior). The particulars in the Motorola specifications were replicated.
The goal was cycle accuracy and that dictated much of the design. This was never intended to be a supercharged superset of a MC6809. If you're looking to mega-power your existing system, this might not be the best choice. (Read the section on What This Is Not for explanation.)
## Purpose, License
I invested the time in the desire that *people use it*. I haven't given away hardware designs or software since the 1980s. However, this seems like a worthwhile exception.
While the source is completely available, this is *not* an "open-source *group* project". You may modify it as you see fit. If you find errors, notifying me would be appreciated. Still, this is **not** a group project. I don't intend that to come off as rude quite so much as frank. I may choose to modify the core in the future; many "open-source group projects" seem to me to become interesting social studies in design-by-commitee, and how much time is required just to manage multiple people with multiple inclinations becomes significant. I confess that this scenario is not something that appeals to me. [Outside of a day job, I prefer to work with a very small and fairly private group.] If you're enthusiastic or appreciative, use the core in a design and I'll be thrilled - tell me about it, and I'll explain to you how thrilled I am.
Refer to the [licensing](./documentation/LICENSE.md) requirements if you choose to leverage this work.
This isn't an attempt to deal with part scarcity. Any variant of 6809 is still quite easy to obtain (at darned cheap prices, too). In truth, *far cheaper* than an FPGA.
The actual target are people who are reimplementing retro-devices (Arcade games, Computers) that have incorporated entire designs into an FPGA, but require cycle accuracy. The core's required space on an FPGA isn't overwhelming once you hit a certain range of parts and integration. (If you're looking at CPLDs, you might want to scale up a bit.)
## Implementation
The core was implemented using Motorola's original documentation. Particularly, **Figure 18** in the MC6809 and MC6809E datasheets. There is a very close mapping between those five pages of diagrams and the bus and cycle activity of the CPU.
I have noticed that some repositories of HDL tend to be only slightly more organized than *people tossing HDL files "over the wall"*. Explanations of how they work, how you as a consumer of the HDL should deal with it, etc. tend to be lacking or totally non-existent.
I do have an interest (outside of this project) in HDL education; not quite in tutorials, but in implementations of HDMI, USB, SATA, etc. and explaining clearly how an implementation works - along with the hardware standard at the same time.
Please - if you're not experienced in an HDL already, this cpu core isn't likely very useful to you as a learning mechanism. There are wonderful tutorials out there already; I highly recommend learning, experimenting, and so forth *first*, before attempting to absorb this design.
## Validation
The design was validated in multiple fashions, including against a Vectrex from 1982, a TRS-80 Color Computer 3, A slew of Williams Arcade games, and another wave of Taito Arcade games.
Literal bus compatibility was achieved using a [GODIL-40](http://www.oho-elektronik.de/) against the above scenarios. I can't say enough nice things about the [GODIL](http://www.oho-elektronik.de/) design. Slick, compact. It's darned nice work. The only bad thing is that they're in short supply. (Oh, and they're 10x-20x the price of a hard CPU. I wouldn't recommend replacing your daily-use CPUs with a soft CPU in a GODIL unless you have a strong reason for doing so.)
Functional testing was against the list of platforms above. They all work.
Actual instruction cycle testing was done with the frequent help of Erik Gavriluk, who donated his time, consideration, and even hardware to the project. In this case, MAME sports a cycle-accurate 6809 emulator; Erik generated code that ran (nearly) every instruction in every addressing mode, and then ran that through MAME and kept an absolute cycle count. I captured the soft core's bus on a GODIL running the exact same code and matched the cycle counts. To improve things, Erik provided me with the register contents after every instruction. I wrote a testbench to run the same code and validated that the registers changed after each instruction identically in each scenario and in the exact same number of cycles. The result was gratifying. (Ahem, once it worked. Believe me, the CoCo, the cycle testing, the GODIL - they *all* pointed me at problems. I won't claim that the design is flawless - nothing I've ever written truly is - but effort *has* been made to actually verify the thing, and I'll list each of the platforms and experiences. [I'll even grumpily point out that Stargate has illegal instructions in it that they're darned lucky the 6809 happened to walk over.]
Precise control signal testing (Interrupts, /HALT) were primarily done on JROK's Williams board. The Williams arcade games had a blitter, and it used /HALT to gain the bus and take action. JROK had done some extensive timing validation to prove that his implementation of the Williams design was **accurate**. I contacted him and being as he's an incredibly nice person, he gave me some advice and access to his source + prebuilt binaries. I was quite thankful - I found bus timing errors (related to /HALT and related to /IRQ latency) in the same vein (how many cycles before the next-new-instruction does each have to be asserted in order to be serviced at the beginning of the next instruction?) as a result. A very worthwhile endeavor, as I'd been convinced that I was correct; however, his code led me to swap hard CPUs with my soft core on analyzer captures and to realize that despite my intention to match the documentation perfectly there were cases where the documentation left details unclear, requiring comparison between a hard CPU and my existing timing.
## What This Is Not
This isn't an attempt to deal with parts scarcity, nor prepare for it. I can't imagine that 6809s will become *hard to get* in the next decade or so. There isn't a ton of volume required and there are lots of warehouses from companies that make their entire businesses on out-of-production parts.
This isn't an attempt to make a faster MC6809. The implementation would have been different had that been a goal. It has extensive 'dead' cycles on the bus to fit MC6809 specifications. If I conditionally remove them, it would be significantly more efficient than a real MC6809 (but once again, not cycle-accurate).
This core does not include HD6309 instructions. I did check, and without the 'dead' cycles mentioned above (the things that make it cycle-accurate), every instruction is at least as efficient as the HD6309, and most are more efficient. (I do have advantages of 40 years of technology over the original MC6809 design team, and at least 30 years over the HD6309 design team.) New registers and instructions from the HD6309 aren't there. Once again, that wasn't the goal. [I may still enable a dynamic mechanism to switch between cycle-accurate and minimum-cycles-required as an instantiation parameter.]
If your goal really is "a super 6809", I have [strong opinions](./documentation/super6809.md) on the topic.
## Perfection?
While I'd love to say that this is a perfect replica, logic-level details of the implementation of the CPU aren't available. The Motorola documentation is *excellent*, but still not complete.
I know of inconsistencies - but inconsistencies that I expect are trivial. Anything deemed as serious has been dealt with as soon as I've been made aware of it.
The instructions have been heavily validated, and I'm confident in their accuracy - but not quite so arrogant as to insist that there could not be an oversight. (I'm not a young man any longer; I've been wrong too many times to be as remotely as confident as I was when I was 16.)
Should issues be discovered, expect transparency and fixes - even if it's an incredibly rare edge case. [If you're actively using `/DMABREQ`, please contact me. You're the first.]
## How does it work?
This isn't quite the same question as the next, but if you really want to dig in and grasp the implementation, I've written a summary of the design [here](./documentation/CoreDesign.md).
## How Do I Use It?
### Samples
Application of the core in a GODIL is provided. With this, you can - although for what reason, I'm not sure - plug-replace a MC6809 or MC6809E in nearly any design (*note the oscillator in the Vectrex instead of the crystal*). This is intended to demonstrate compatibility.
A sample implementation is provided against a cheap Xilinx Spartan 6 LX9 board from eBay (China), a cheap Altera Cyclone IV EP4CE6 board (also from eBay, China), and two Cyclone V boards from terasic. These aren't attempting to run at original speeds, so I set them to 25Mhz for no reason other than "I can". These are intended to demonstrate use of the core entirely internal to an FPGA.
### General Guidelines
A list of general guidelines is provided. They are likely worth reading if you consider using this core.
## Documentation
1. [Explanation of the CPU Core design.](./documentation/CoreDesign.md)
2. [Validation Efforts.](./documentation/Validation.md)
3. [Implementation Examples](./documentation/samples.md).
## Who Am I?
Despite a certain degree of desire to remain anonymous, that seems pointless in today's world.
My name is Greg Miller; I learned assembly in 1981 on a 6809 in a TRS-80 Color Computer, leaving me *fond* of this CPU architecture.
Not surprisingly, I work in the tech industry (although quite definitely not implementing legacy hardware in FPGAs), do not represent my employer in any capacity whatsoever here, and have a family and a mortgage.
You can contact me via:
gregmiller6809@gmail.com
## Final Thoughts
I'll keep track of my [Final Thoughts](./documentation/FinalThoughts.md) on the project.
## Acknowledgements
[I do want to thank a few people](documentation/Acknowledgements.md).

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:11:34 09/23/2016
// Design Name:
// Module Name: mc6809e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc6809(
input [7:0] D,
output [7:0] DOut,
output [15:0] ADDR,
output RnW,
output E,
output Q,
output BS,
output BA,
input nIRQ,
input nFIRQ,
input nNMI,
input EXTAL,
input XTAL,
input nHALT,
input nRESET,
input MRDY,
input nDMABREQ
, output [111:0] RegData
);
reg [1:0] clk_phase=2'b00;
wire CLK;
assign CLK=EXTAL;
wire LIC;
wire BUSY;
wire AVMA;
reg rE;
reg rQ;
assign E = rE;
assign Q = rQ;
mc6809i cpucore(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ),
.nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(nDMABREQ)
,.RegData(RegData)
);
always @(negedge CLK)
begin
case (clk_phase)
2'b00:
rE <= 0;
2'b01:
rQ <= 1;
2'b10:
rE <= 1;
2'b11:
rQ <= 0;
endcase
if (MRDY == 1'b1)
clk_phase <= clk_phase + 2'b01;
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:11:34 09/23/2016
// Design Name:
// Module Name: mc6809e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc6809e(
input [7:0] D,
output [7:0] DOut,
output [15:0] ADDR,
output RnW,
input E,
input Q,
output BS,
output BA,
input nIRQ,
input nFIRQ,
input nNMI,
output AVMA,
output BUSY,
output LIC,
input nHALT,
input nRESET
);
mc6809i cpucore (.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ),
.nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(1)
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/18/2016 09:25:01 PM
// Design Name:
// Module Name: 6809 Superset module of MC6809 and MC6809E signals
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc6809s(
input [7:0] D,
output [7:0] DOut,
output [15:0] ADDR,
output RnW,
input CLK4,
output BS,
output BA,
input nIRQ,
input nFIRQ,
input nNMI,
output AVMA,
output BUSY,
output LIC,
input nRESET,
input nHALT,
input nDMABREQ,
output E,
output Q,
output reg [1:0] clk4_cnt,
output [111:0] RegData
);
reg rE;
reg rQ;
assign E = rE;
assign Q = rQ;
reg nCoreRESET;
mc6809i corecpu(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(rE), .Q(rQ), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nRESET(nCoreRESET),
.nDMABREQ(nDMABREQ), .nHALT(nHALT), .RegData(RegData) );
always @(posedge CLK4)
begin
clk4_cnt <= clk4_cnt+2'b01;
if (nRESET == 0)
begin
clk4_cnt <= 0;
nCoreRESET <= 0;
end
if ( clk4_cnt == 2'b00 ) // RISING EDGE OF E
rE <= 1;
if (clk4_cnt == 2'b01) // RISING EDGE OF Q
rQ <= 1;
if (clk4_cnt == 2'b10) // FALLING EDGE OF E
rE <= 0;
if (clk4_cnt == 2'b11) // FALLING EDGE OF Q
begin
rQ <= 0;
nCoreRESET <= 1;
end
end
endmodule

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.sprite_pkg.all;
use work.platform_pkg.all;
entity platform is
port
(
-- clocking and reset
clkrst_i : in from_CLKRST_t;
vma : out std_logic;
-- controller inputs
inputs_p1 : in std_logic_vector(7 downto 0);
inputs_p2 : in std_logic_vector(7 downto 0);
inputs_sys : in std_logic_vector(7 downto 0);
inputs_dip1 : in std_logic_vector(7 downto 0);
inputs_dip2 : in std_logic_vector(7 downto 0);
bitmap_i : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
bitmap_o : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
tilemap_i : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
tilemap_o : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
sprite_reg_o : out to_SPRITE_REG_t;
sprite_i : in from_SPRITE_CTL_t;
sprite_o : out to_SPRITE_CTL_t;
spr0_hit : in std_logic;
-- various graphics information
graphics_i : in from_GRAPHICS_t;
graphics_o : out to_GRAPHICS_t;
snd_i : in from_SOUND_t;
snd_o : out to_SOUND_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
tile_rom_addr : out std_logic_vector(12 downto 0);
tile_rom_do : in std_logic_vector(15 downto 0)
);
end platform;
architecture SYN of platform is
alias clk_20M : std_logic is clkrst_i.clk(0);
alias rst_20M : std_logic is clkrst_i.rst(0);
alias clk_video : std_logic is clkrst_i.clk(1);
signal cpu_reset : std_logic;
-- uP signals
signal clk_2M_en : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_r_wn : std_logic;
signal cpu_a : std_logic_vector(15 downto 0);
signal cpu_d_i : std_logic_vector(7 downto 0);
signal cpu_d_o : std_logic_vector(7 downto 0);
signal cpu_irq : std_logic;
-- ROM signals
signal rom_cs : std_logic;
-- RAM signals
signal wram_cs : std_logic;
signal wram_wr : std_logic;
signal wram_d_o : std_logic_vector(7 downto 0);
signal vram_cs : std_logic;
signal vram_d_o : std_logic_vector(7 downto 0);
signal vram_wr : std_logic;
signal cram_cs : std_logic;
signal cram_d_o : std_logic_vector(7 downto 0);
signal cram_wr : std_logic;
signal sprite_cs : std_logic;
-- I/O signals
signal scroll_cs : std_logic;
signal in0_cs : std_logic;
signal in1_cs : std_logic;
signal in2_cs : std_logic;
signal dsw1_cs : std_logic;
signal dsw2_cs : std_logic;
signal rom4_d_o : std_logic_vector(7 downto 0);
signal rom8_d_o : std_logic_vector(7 downto 0);
signal romC_d_o : std_logic_vector(7 downto 0);
signal rom_d_o : std_logic_vector(7 downto 0);
signal cpu_rn_w : std_logic;
COMPONENT mc6809i
GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" );
PORT
(
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
RnW : OUT STD_LOGIC;
E : IN STD_LOGIC;
Q : IN STD_LOGIC;
BS : OUT STD_LOGIC;
BA : OUT STD_LOGIC;
nIRQ : IN STD_LOGIC;
nFIRQ : IN STD_LOGIC;
nNMI : IN STD_LOGIC;
AVMA : OUT STD_LOGIC;
BUSY : OUT STD_LOGIC;
LIC : OUT STD_LOGIC;
nHALT : IN STD_LOGIC;
nRESET : IN STD_LOGIC;
nDMABREQ : IN STD_LOGIC;
RegData : OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
);
END COMPONENT;
begin
wram_cs <= '1' when STD_MATCH(cpu_a, "0000------------") else '0';-- RAM $0000-$0FFF
vram_cs <= '1' when STD_MATCH(cpu_a, "000100----------") else '0';-- video ram $1000-$13FF
cram_cs <= '1' when STD_MATCH(cpu_a, "000101----------") else '0';-- colour ram $1400-$17FF
sprite_cs <= '1' when STD_MATCH(cpu_a, X"20"&"001-----") else
'1' when STD_MATCH(cpu_a, X"20"&"01------") else
'0';-- sprite 'ram' $2020-$207F
-- I/O
scroll_cs <= '1' when STD_MATCH(cpu_a, X"3000") else '0';
in0_cs <= '1' when STD_MATCH(cpu_a, X"3002") else '0';
in1_cs <= '1' when STD_MATCH(cpu_a, X"3003") else '0';
in2_cs <= '1' when STD_MATCH(cpu_a, X"3004") else '0';
dsw1_cs <= '1' when STD_MATCH(cpu_a, X"3005") else '0';
dsw2_cs <= '1' when STD_MATCH(cpu_a, X"3006") else '0';
rom_cs <= '1' when (cpu_a > X"3FFF") else '0';
-- memory block write enables
wram_wr <= wram_cs and clk_2M_en and not cpu_r_wn;
vram_wr <= vram_cs and clk_2M_en and not cpu_r_wn;
cram_wr <= cram_cs and clk_2M_en and not cpu_r_wn;
-- memory read mux
cpu_d_i <= wram_d_o when wram_cs = '1' else
vram_d_o when vram_cs = '1' else
cram_d_o when cram_cs = '1' else
inputs_p1 when in0_cs = '1' else
inputs_p2 when in1_cs = '1' else
inputs_sys when in2_cs = '1' else
inputs_dip1 when dsw1_cs = '1' else
inputs_dip2 when dsw2_cs = '1' else
-- flip off, service off, coin A, 1C1C
-- (X"80" or X"40" or X"10" or X"0F") when dsw1_cs = '1' else
-- freeze off, easy, 20K/80K/100K, 3 lives
-- (X"80" or X"60" or X"08" or X"03") when dsw2_cs = '1' else
rom_d_o when rom_cs = '1' else
-- cpu_rom_do when rom_cs = '1' else
(others => 'Z');
-- system timing
process (clk_20M, rst_20M)
variable count : integer range 0 to 10-1;
begin
if rst_20M = '1' then
count := 0;
elsif rising_edge(clk_20M) then
clk_2M_en <= '0'; -- default
case count is
when 0 =>
clk_2M_en <= '1';
when others =>
null;
end case;
if count = count'high then
count := 0;
else
count := count + 1;
end if;
end if;
end process;
-- cpu09 core uses negative clock edge
--cpu_clk_en <= not (clk_2M_en and not platform_pause);
cpu_clk_en <= clk_2M_en;
-- add game reset later
cpu_reset <= rst_20M;
-- cpu_inst : entity work.cpu09
-- generic map
-- (
-- CLK_POL => '1'
-- )
-- port map
-- (
-- clk => clk_20M,
-- clk_en => cpu_clk_en,
-- rst => cpu_reset,
-- rw => cpu_r_wn,
-- vma => vma,
--ba => open,
--bs => open,
-- addr => cpu_a,
-- data_in => cpu_d_i,
-- data_out => cpu_d_o,
-- halt => '0',
-- hold => '0',
-- irq => cpu_irq,
-- firq => '0',
--- nmi => '0'
-- );
--changed for test
cpu_inst : mc6809i
port map
(
D => cpu_d_i,
DOut => cpu_d_o,
ADDR => cpu_a,
RnW => cpu_r_wn,
E => cpu_clk_en,
Q => clk_20M,
BS => open,
BA => open,
nIRQ => not cpu_irq,
nFIRQ => '1',
nNMI => '1',
AVMA => open,
BUSY => open,
LIC => open,
nHALT => '1',
nRESET => not cpu_reset,
nDMABREQ => '1',
RegData => open
);
--WRAm_cs
wram_inst : entity work.spram
generic map
(
widthad_a => 12,
width_a => 8
)
port map
(
address => cpu_a(11 downto 0),
clock => clk_20M,
data => cpu_d_o,
wren => wram_wr,
q => wram_d_o
);
-- irq vblank interrupt
process (clk_20M, rst_20M)
variable vblank_r : std_logic_vector(3 downto 0);
alias vblank_prev : std_logic is vblank_r(vblank_r'left);
alias vblank_um : std_logic is vblank_r(vblank_r'left-1);
begin
if rst_20M = '1' then
vblank_r := (others => '0');
cpu_irq <= '0';
elsif rising_edge(clk_20M) then
if vblank_um = '1' and vblank_prev = '0' then
cpu_irq <= '1';
elsif vblank_um = '0' then
cpu_irq <= '0';
end if;
-- numeta the vblank
vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank;
end if;
end process;
-- scroll register
process (clk_20M, rst_20M)
begin
if rst_20M = '1' then
graphics_o.bit8(0) <= (others => '0');
elsif rising_edge(clk_20M) then
if scroll_cs and clk_2M_en and not cpu_r_wn then
graphics_o.bit8(0) <= cpu_d_o;
end if;
end if;
end process;
rom_4000_inst : entity work.sprom
generic map
(
init_file => "./roms/ss_01e.hex",
widthad_a => 14
)
port map
(
clock => clk_20M,
address => cpu_a(13 downto 0),
q => rom4_d_o
);
rom_8000_inst : entity work.sprom
generic map
(
init_file => "./roms/ss_02e.hex",
widthad_a => 14
)
port map
(
clock => clk_20M,
address => cpu_a(13 downto 0),
q => rom8_d_o
);
rom_C000_inst : entity work.sprom
generic map
(
init_file => "./roms/ss_03e.hex",
widthad_a => 14
)
port map
(
clock => clk_20M,
address => cpu_a(13 downto 0),
q => romC_d_o
);
rom_d_o <= rom4_d_o when STD_MATCH(cpu_a, "01--------------") else
rom8_d_o when STD_MATCH(cpu_a, "10--------------") else
romC_d_o;
--cpu_rom_addr <= cpu_a(15 downto 0);
--rom_d_o <= cpu_rom_do;
-- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE
vram_inst : entity work.dpram
generic map
(
init_file => "./roms/vram.hex",
widthad_a => 10
)
port map
(
clock_b => clk_20M,
address_b => cpu_a(9 downto 0),
wren_b => vram_wr,
data_b => cpu_d_o,
q_b => vram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).map_a(9 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).map_d(7 downto 0)
);
tilemap_o(1).map_d(tilemap_o(1).map_d'left downto 8) <= (others => 'Z');
-- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE
cram_inst : entity work.dpram
generic map
(
init_file => "./roms/cram.hex",
widthad_a => 10
)
port map
(
clock_b => clk_20M,
address_b => cpu_a(9 downto 0),
wren_b => cram_wr,
data_b => cpu_d_o,
q_b => cram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).attr_a(9 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).attr_d(7 downto 0)
);
tilemap_o(1).attr_d(tilemap_o(1).attr_d'left downto 8) <= (others => 'Z');
--tile rom (bit 0)
ss_7_b6_inst : entity work.sprom
generic map
(
init_file => "./roms/ss_7_b6.hex",
widthad_a => 13
)
port map
(
clock => clk_video,
address => tilemap_i(1).tile_a(12 downto 0),
q => tilemap_o(1).tile_d(7 downto 0)
);
-- tile rom (bit 1)---will not fit in FPGA Block Ram
-- ss_8_b5_inst : entity work.sprom
-- generic map
-- (
--- init_file => "./roms/ss_8_b5.hex",
-- widthad_a => 13
-- )
-- port map
-- (
-- clock => clk_video,
-- address => tilemap_i(1).tile_a(12 downto 0),
-- q => tilemap_o(1).tile_d(15 downto 8)
-- );
--tile_rom_addr <= tilemap_i(1).tile_a(12 downto 0);
--tilemap_o(1).tile_d(15 downto 0) <= tile_rom_do;
BLK_SPRITES : block---will not fit in FPGA Block Ram
signal bit0_1 : std_logic_vector(7 downto 0); -- offset 0
signal bit0_2 : std_logic_vector(7 downto 0); -- offset 0
signal bit0_3 : std_logic_vector(7 downto 0); -- offset 16
signal bit0_4 : std_logic_vector(7 downto 0); -- offset 16
signal bit1_1 : std_logic_vector(7 downto 0);
signal bit1_2 : std_logic_vector(7 downto 0);
signal bit1_3 : std_logic_vector(7 downto 0);
signal bit1_4 : std_logic_vector(7 downto 0);
signal bit2_1 : std_logic_vector(7 downto 0);
signal bit2_2 : std_logic_vector(7 downto 0);
signal bit2_3 : std_logic_vector(7 downto 0);
signal bit2_4 : std_logic_vector(7 downto 0);
signal sprite_a_00 : std_logic_vector(12 downto 0);
signal sprite_a_16 : std_logic_vector(12 downto 0);
begin
-- registers
sprite_reg_o.clk <= clk_20M;
sprite_reg_o.clk_ena <= clk_2M_en;
sprite_reg_o.a <= cpu_a(sprite_reg_o.a'range);
sprite_reg_o.d <= cpu_d_o;
sprite_reg_o.wr <= sprite_cs and clk_2M_en and not cpu_r_wn;
-- - sprite data consists of:
-- 16 consecutive bytes for the 1st half
-- then the next 16 bytes for the 2nd half
-- - because we need to fetch an entire row at once
-- use dual-port memory to access both halves of each row
-- generate address for each port
-- sprite_a_00 <= sprite_i.a(12 downto 5) & '0' & sprite_i.a(3 downto 0);
-- sprite_a_16 <= sprite_i.a(12 downto 5) & '1' & sprite_i.a(3 downto 0);
-- sprite rom (bit 0, part 1/2)
-- ss_9_m5_inst : entity work.dprom_2r
-- generic map
-- (
-- init_file => "./roms/ss_9_m5.hex",
-- widthad_a => 13,
-- widthad_b => 13
-- )
-- port map
-- (
-- clock => clk_video,
-- address_a => sprite_a_00,
-- q_a => bit0_1,
-- address_b => sprite_a_16,
-- q_b => bit0_3
-- );
-- sprite rom (bit 0, part 2/2)
-- ss_10_m6_inst : entity work.dprom_2r
-- generic map
-- (
-- init_file => "./roms/ss_10_m6.hex",
-- widthad_a => 13,
-- widthad_b => 13
-- )
-- port map
-- (
-- clock => clk_video,
-- address_a => sprite_a_00,
--- q_a => bit0_2,
-- address_b => sprite_a_16,
-- q_b => bit0_4
-- );
-- sprite_o.d(15 downto 0) <= (bit0_1 & bit0_3) when sprite_i.a(13) = '0' else
-- (bit0_2 & bit0_4);
-- sprite rom (bit 1, part 1/2)
-- ss_11_m3_inst : entity work.dprom_2r
-- generic map
-- (
-- init_file => "./roms/ss_11_m3.hex",
-- widthad_a => 13,
-- widthad_b => 13
-- )
-- port map
-- (
-- clock => clk_video,
-- address_a => sprite_a_00,
-- q_a => bit1_1,
-- address_b => sprite_a_16,
-- q_b => bit1_3
-- );
-- sprite rom (bit 0, part 2/2)
-- ss_12_m4_inst : entity work.dprom_2r
-- generic map
-- (
-- init_file => "./roms/ss_12_m4.hex",
-- widthad_a => 13,
-- widthad_b => 13
-- )
-- port map
-- (
-- clock => clk_video,
-- address_a => sprite_a_00,
-- q_a => bit1_2,
-- address_b => sprite_a_16,
--- q_b => bit1_4
--- );
-- sprite_o.d(31 downto 16) <= (bit1_1 & bit1_3) when sprite_i.a(13) = '0' else
-- (bit1_2 & bit1_4);
-- sprite rom (bit 2, part 1/2)
-- ss_13_m1_inst : entity work.dprom_2r
-- generic map
-- (
-- init_file => "./roms/ss_13_m1.hex",
-- widthad_a => 13,
-- widthad_b => 13
-- )
-- port map
-- (
-- clock => clk_video,
-- address_a => sprite_a_00,
-- q_a => bit2_1,
-- address_b => sprite_a_16,
-- q_b => bit2_3
-- );
-- sprite rom (bit 2, part 2/2)
-- ss_14_m2_inst : entity work.dprom_2r
-- generic map
-- (
-- init_file => "./roms/ss_14_m2.hex",
-- widthad_a => 13,
-- widthad_b => 13
-- )
-- port map
-- (
-- clock => clk_video,
-- address_a => sprite_a_00,
-- q_a => bit2_2,
-- address_b => sprite_a_16,
-- q_b => bit2_4
-- );
-- sprite_o.d(47 downto 32) <= (bit2_1 & bit2_3) when sprite_i.a(13) = '0' else
-- (bit2_2 & bit2_4);
end block BLK_SPRITES;
-- unused outputs
graphics_o.bit16(0) <= (others => '0');
end SYN;

4
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip
View File

@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]

429
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd
View File

@@ -1,429 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_mist.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_mist IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_mist;
ARCHITECTURE SYN OF pll_mist IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 20,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 40,
clk1_phase_shift => "0",
clk2_divide_by => 50,
clk2_duty_cycle => 50,
clk2_multiply_by => 163,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "50"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "88.019997"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "163"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "13.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "88.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "163"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

BIN
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson.zip
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10
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat
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@@ -1,10 +0,0 @@
copy /b ss.01e + ss.02e + ss.03e cpu.rom
copy /b ss_7.b6 + ss_8.b5 tile.rom
copy /b ss_9.m5 + ss_10.m6 + ss_11.m3 + ss_12.m4 + ss_13.m1 + ss_14.m2 sprite.rom
copy /b cpu.rom + tile.rom + sprite.rom SONSON.ROM
make_vhdl_prom ss_6.c11 sound_rom.vhd

BIN
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make_vhdl_prom.exe
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534
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/sound_rom.vhd
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@@ -1,534 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity sound_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of sound_rom is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"86",X"FF",X"1F",X"8A",X"8E",X"00",X"00",X"CC",X"00",X"00",X"ED",X"81",X"8C",X"07",X"FF",X"23",
X"F9",X"10",X"CE",X"08",X"00",X"BD",X"E0",X"76",X"1C",X"AF",X"20",X"FE",X"34",X"FF",X"0C",X"00",
X"BD",X"E0",X"2F",X"BD",X"E1",X"3F",X"BD",X"F2",X"5D",X"BD",X"E0",X"40",X"35",X"FF",X"3B",X"96",
X"01",X"26",X"01",X"39",X"0F",X"01",X"CE",X"E6",X"78",X"96",X"02",X"84",X"1F",X"48",X"6E",X"D6",
X"5F",X"CE",X"01",X"00",X"4F",X"74",X"01",X"1A",X"49",X"74",X"01",X"19",X"49",X"74",X"01",X"18",
X"49",X"74",X"01",X"14",X"49",X"74",X"01",X"13",X"49",X"74",X"01",X"12",X"49",X"8B",X"C0",X"C6",
X"07",X"F7",X"20",X"00",X"B7",X"20",X"01",X"39",X"34",X"7E",X"B6",X"A0",X"00",X"97",X"02",X"86",
X"FF",X"97",X"01",X"35",X"7E",X"3B",X"CE",X"02",X"00",X"86",X"20",X"C6",X"1B",X"6F",X"C4",X"33",
X"C6",X"5A",X"26",X"F9",X"39",X"0B",X"3C",X"0A",X"9B",X"0A",X"02",X"09",X"73",X"08",X"EB",X"08",
X"6B",X"07",X"F2",X"07",X"80",X"07",X"14",X"06",X"AE",X"06",X"4E",X"05",X"F4",X"05",X"9E",X"05",
X"4D",X"05",X"01",X"04",X"B9",X"04",X"75",X"04",X"35",X"03",X"F9",X"03",X"C0",X"03",X"8A",X"03",
X"57",X"03",X"27",X"02",X"FA",X"02",X"CF",X"02",X"A7",X"02",X"81",X"02",X"5D",X"02",X"3B",X"02",
X"1B",X"01",X"FC",X"01",X"E0",X"01",X"C5",X"01",X"A5",X"01",X"94",X"01",X"7D",X"01",X"68",X"01",
X"53",X"01",X"40",X"01",X"2E",X"01",X"1D",X"01",X"0D",X"00",X"FE",X"00",X"F0",X"00",X"E2",X"00",
X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0",X"00",X"97",X"00",X"8F",X"00",
X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65",X"00",X"5F",X"00",X"5A",X"00",
X"55",X"00",X"50",X"00",X"4C",X"00",X"47",X"00",X"43",X"00",X"40",X"00",X"3C",X"00",X"39",X"00",
X"35",X"00",X"32",X"00",X"30",X"00",X"2D",X"00",X"2A",X"00",X"28",X"00",X"26",X"00",X"24",X"00",
X"22",X"00",X"20",X"00",X"1E",X"00",X"1C",X"00",X"1B",X"00",X"19",X"00",X"18",X"00",X"16",X"00",
X"15",X"00",X"14",X"00",X"13",X"00",X"12",X"00",X"11",X"00",X"10",X"00",X"0F",X"00",X"0E",X"BD",
X"E1",X"46",X"BD",X"E1",X"6B",X"39",X"8E",X"02",X"00",X"0F",X"0F",X"0F",X"04",X"A6",X"84",X"27",
X"0B",X"9B",X"0F",X"BD",X"E1",X"9E",X"96",X"0F",X"81",X"03",X"24",X"0E",X"0C",X"04",X"96",X"04",
X"81",X"0F",X"27",X"06",X"86",X"20",X"30",X"86",X"20",X"E3",X"39",X"8E",X"04",X"60",X"C6",X"60",
X"A6",X"84",X"26",X"08",X"8E",X"04",X"00",X"A6",X"84",X"26",X"12",X"39",X"BD",X"EE",X"5B",X"86",
X"20",X"30",X"86",X"BD",X"EE",X"5B",X"86",X"20",X"30",X"86",X"7E",X"EE",X"5B",X"BD",X"EE",X"5B",
X"86",X"20",X"30",X"86",X"BD",X"EE",X"5B",X"86",X"20",X"30",X"86",X"7E",X"EE",X"60",X"CE",X"E1",
X"A6",X"96",X"04",X"48",X"6E",X"D6",X"E1",X"C4",X"E2",X"07",X"E2",X"2F",X"E2",X"E5",X"E3",X"BC",
X"E3",X"BD",X"E4",X"24",X"E4",X"75",X"E4",X"88",X"E4",X"C6",X"E4",X"FB",X"E5",X"2F",X"E5",X"C6",
X"E5",X"C7",X"E6",X"10",X"6A",X"0D",X"27",X"1B",X"A6",X"0D",X"44",X"CE",X"E1",X"D3",X"A6",X"C6",
X"A7",X"07",X"39",X"01",X"02",X"03",X"05",X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0D",X"0C",
X"0A",X"08",X"06",X"A6",X"0C",X"6C",X"0C",X"81",X"05",X"27",X"19",X"CE",X"E1",X"FF",X"A6",X"C6",
X"CE",X"E0",X"E5",X"48",X"EC",X"C6",X"A7",X"02",X"E7",X"01",X"86",X"1F",X"A7",X"0D",X"39",X"07",
X"0C",X"10",X"13",X"13",X"6F",X"84",X"39",X"6A",X"0D",X"27",X"01",X"39",X"6C",X"0C",X"A6",X"0C",
X"81",X"03",X"27",X"18",X"C6",X"3C",X"E7",X"0D",X"81",X"01",X"27",X"08",X"CC",X"00",X"26",X"A7",
X"02",X"E7",X"01",X"39",X"CC",X"00",X"2A",X"A7",X"02",X"E7",X"01",X"39",X"6F",X"84",X"39",X"A6",
X"88",X"12",X"26",X"45",X"6A",X"88",X"13",X"27",X"01",X"39",X"6C",X"88",X"12",X"CC",X"00",X"18",
X"A7",X"02",X"E7",X"01",X"CC",X"00",X"20",X"A7",X"04",X"E7",X"03",X"CC",X"00",X"28",X"A7",X"06",
X"E7",X"05",X"86",X"00",X"A7",X"0C",X"86",X"0F",X"A7",X"0D",X"86",X"07",X"A7",X"07",X"86",X"01",
X"A7",X"0E",X"86",X"10",X"A7",X"0F",X"86",X"03",X"A7",X"08",X"86",X"01",X"A7",X"88",X"10",X"86",
X"10",X"A7",X"88",X"11",X"86",X"0D",X"A7",X"09",X"39",X"BD",X"E2",X"83",X"BD",X"E2",X"A1",X"BD",
X"E2",X"BF",X"39",X"A6",X"0C",X"84",X"01",X"27",X"0C",X"6A",X"07",X"27",X"01",X"39",X"6A",X"0D",
X"27",X"50",X"6C",X"0C",X"39",X"6C",X"07",X"A6",X"07",X"A1",X"0D",X"27",X"01",X"39",X"6C",X"0C",
X"39",X"A6",X"0E",X"84",X"01",X"27",X"0C",X"6A",X"08",X"27",X"01",X"39",X"6A",X"0F",X"27",X"32",
X"6C",X"0E",X"39",X"6C",X"08",X"A6",X"08",X"A1",X"0F",X"27",X"01",X"39",X"6C",X"0E",X"39",X"A6",
X"88",X"10",X"84",X"01",X"27",X"0E",X"6A",X"09",X"27",X"01",X"39",X"6A",X"88",X"11",X"27",X"12",
X"6C",X"88",X"10",X"39",X"6C",X"09",X"A6",X"09",X"A1",X"88",X"11",X"27",X"01",X"39",X"6C",X"88",
X"10",X"39",X"6F",X"84",X"39",X"A6",X"0D",X"27",X"03",X"6A",X"0D",X"39",X"A6",X"88",X"10",X"6C",
X"88",X"10",X"81",X"10",X"27",X"21",X"E6",X"0F",X"E7",X"0D",X"CE",X"E3",X"06",X"A6",X"C6",X"A7",
X"07",X"A7",X"08",X"A7",X"09",X"39",X"09",X"0A",X"0B",X"0C",X"0D",X"0C",X"0B",X"0A",X"09",X"08",
X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"6F",X"88",X"10",X"A6",X"0C",X"6C",X"0C",X"48",X"48",
X"CE",X"E3",X"88",X"33",X"C6",X"A6",X"C4",X"81",X"FF",X"27",X"5A",X"A7",X"0F",X"A7",X"0D",X"86",
X"09",X"A7",X"07",X"A7",X"08",X"A7",X"09",X"A6",X"41",X"BD",X"E3",X"53",X"A7",X"02",X"E7",X"01",
X"A6",X"42",X"BD",X"E3",X"53",X"A7",X"04",X"E7",X"03",X"A6",X"43",X"BD",X"E3",X"53",X"A7",X"06",
X"E7",X"05",X"39",X"10",X"8E",X"E3",X"5F",X"48",X"31",X"A6",X"A6",X"A4",X"E6",X"21",X"39",X"00",
X"00",X"00",X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0",X"00",X"97",X"00",
X"8F",X"00",X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65",X"00",X"5F",X"00",
X"5A",X"00",X"55",X"00",X"50",X"6F",X"84",X"39",X"04",X"01",X"05",X"08",X"02",X"00",X"00",X"00",
X"02",X"01",X"05",X"08",X"02",X"01",X"05",X"08",X"02",X"01",X"05",X"08",X"02",X"03",X"06",X"0A",
X"02",X"00",X"00",X"00",X"02",X"03",X"06",X"0A",X"02",X"00",X"00",X"00",X"02",X"03",X"06",X"0C",
X"02",X"00",X"00",X"00",X"0C",X"05",X"08",X"0D",X"FF",X"FF",X"FF",X"FF",X"39",X"A6",X"0D",X"27",
X"2E",X"6A",X"0D",X"A6",X"0E",X"27",X"0D",X"81",X"02",X"27",X"15",X"A6",X"0D",X"81",X"20",X"27",
X"00",X"6C",X"0E",X"39",X"6C",X"07",X"A6",X"07",X"81",X"0D",X"27",X"01",X"39",X"6C",X"0E",X"39",
X"A6",X"07",X"27",X"0A",X"96",X"00",X"84",X"03",X"27",X"01",X"39",X"6A",X"07",X"39",X"39",X"6F",
X"0E",X"C6",X"30",X"A6",X"0C",X"6C",X"0C",X"CE",X"E4",X"18",X"A6",X"C6",X"81",X"FF",X"27",X"15",
X"48",X"24",X"02",X"C6",X"90",X"E7",X"0D",X"CE",X"E0",X"9D",X"EC",X"C6",X"A7",X"02",X"E7",X"01",
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X"09",X"85",X"02",X"FF",X"A6",X"0D",X"6C",X"0D",X"CE",X"E4",X"4C",X"A6",X"C6",X"81",X"FF",X"27",
X"18",X"81",X"FE",X"26",X"07",X"86",X"42",X"A7",X"01",X"8B",X"08",X"39",X"A7",X"07",X"96",X"00",
X"84",X"01",X"27",X"04",X"6A",X"01",X"6A",X"03",X"39",X"6F",X"84",X"39",X"04",X"05",X"06",X"07",
X"08",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"FE",X"03",X"04",X"05",X"06",X"07",
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X"04",X"03",X"02",X"01",X"FF",X"E6",X"01",X"A6",X"02",X"83",X"00",X"1E",X"81",X"F0",X"24",X"05",
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X"6A",X"0D",X"27",X"01",X"39",X"6C",X"0C",X"86",X"10",X"A7",X"0E",X"39",X"6A",X"0E",X"27",X"01",
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X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"09",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_7_b6.hex
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315
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sonson_soundboard.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
--SOUND CPU:
--0000-07ff RAM
--e000-ffff ROM
--read:
--a000 command from the main CPU
--write:
--2000 8910 #1 control
--2001 8910 #1 write
--4000 8910 #2 control
--4001 8910 #2 write
--WRITE_HANDLER( sonson_sh_irqtrigger_w )
--{
-- static int last;
-- if (last == 0 && data == 1)
-- {
-- setting bit 0 low then high triggers IRQ on the sound CPU
-- cpu_cause_interrupt(1,M6809_INT_FIRQ);
-- }
--- last = data;
--}
--void sonson_state::sound_map(address_map &map)
--{
-- map(0x0000, 0x07ff).ram();
-- map(0x2000, 0x2001).w("ay1", FUNC(ay8910_device::address_data_w));
-- map(0x4000, 0x4001).w("ay2", FUNC(ay8910_device::address_data_w));
-- map(0xa000, 0xa000).r("soundlatch", FUNC(generic_latch_8_device::read));
-- map(0xe000, 0xffff).rom();
--}
/* basic machine hardware */
-- {
-- {
-- CPU_M6809,
-- 2000000, /* 2 Mhz (?) */
-- readmem,writemem,0,0,
-- interrupt,1
-- },
-- {
-- CPU_M6809 | CPU_AUDIO_CPU,
-- 2000000, /* 2 Mhz (?) */
-- sound_readmem,sound_writemem,0,0,
-- interrupt,4 /* FIRQs are triggered by the main CPU */
-- },
-- },
entity sonson_soundboard is
port(
clk_2 : in std_logic;
clk_1p5 : in std_logic;
sound_rd : in std_logic;--a000 command from the main CPU
areset : in std_logic;
sound_data : in std_logic_vector(7 downto 0);
audio_out : out std_logic_vector(11 downto 0)
);
end sonson_soundboard;
architecture SYN of sonson_soundboard is
component YM2149
port (
CLK : in std_logic;
CE : in std_logic;
RESET : in std_logic;
A8 : in std_logic := '1';
A9_L : in std_logic := '0';
BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write)
BC : in std_logic; -- Bus control
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CHANNEL_A : out std_logic_vector(7 downto 0);
CHANNEL_B : out std_logic_vector(7 downto 0);
CHANNEL_C : out std_logic_vector(7 downto 0);
SEL : in std_logic;
MODE : in std_logic;
ACTIVE : out std_logic_vector(5 downto 0);
IOA_in : in std_logic_vector(7 downto 0);
IOA_out : out std_logic_vector(7 downto 0);
IOB_in : in std_logic_vector(7 downto 0);
IOB_out : out std_logic_vector(7 downto 0)
);
end component;
COMPONENT mc6809i
GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" );
PORT
(
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
RnW : OUT STD_LOGIC;
E : IN STD_LOGIC;
Q : IN STD_LOGIC;
BS : OUT STD_LOGIC;
BA : OUT STD_LOGIC;
nIRQ : IN STD_LOGIC;
nFIRQ : IN STD_LOGIC;
nNMI : IN STD_LOGIC;
AVMA : OUT STD_LOGIC;
BUSY : OUT STD_LOGIC;
LIC : OUT STD_LOGIC;
nHALT : IN STD_LOGIC;
nRESET : IN STD_LOGIC;
nDMABREQ : IN STD_LOGIC;
RegData : OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
);
END COMPONENT;
signal reset : std_logic := '1';
signal reset_cnt : integer range 0 to 1000000 := 1000000;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal clk_2M_en : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_reset : std_logic;
signal wram_cs : std_logic;
signal wram_we : std_logic;
signal wram_do : std_logic_vector( 7 downto 0);
signal rom_cs : std_logic;
signal rom_do : std_logic_vector( 7 downto 0);
signal ay1_chan_a : std_logic_vector(7 downto 0);
signal ay1_chan_b : std_logic_vector(7 downto 0);
signal ay1_chan_c : std_logic_vector(7 downto 0);
signal ay1_do : std_logic_vector(7 downto 0);
signal ay1_audio : std_logic_vector(9 downto 0);
signal ay1_port_b_do : std_logic_vector(7 downto 0);
signal ay2_chan_a : std_logic_vector(7 downto 0);
signal ay2_chan_b : std_logic_vector(7 downto 0);
signal ay2_chan_c : std_logic_vector(7 downto 0);
signal ay2_do : std_logic_vector(7 downto 0);
signal ay2_audio : std_logic_vector(9 downto 0);
signal ay1_control : std_logic;
signal ay1_write : std_logic;
signal ay2_control : std_logic;
signal ay2_write : std_logic;
signal ports_cs : std_logic;
signal ports_we : std_logic;
signal port1_bus : std_logic_vector(7 downto 0);
signal port1_data : std_logic_vector(7 downto 0);
signal port1_ddr : std_logic_vector(7 downto 0);
signal port1_in : std_logic_vector(7 downto 0);
signal port2_bus : std_logic_vector(7 downto 0);
signal port2_data : std_logic_vector(7 downto 0);
signal port2_ddr : std_logic_vector(7 downto 0);
signal port2_in : std_logic_vector(7 downto 0);
begin
-- cs
wram_cs <= '1' when cpu_addr(15 downto 12) = "0000" else '0'; --0000-07ff RAM 0000 1000 0000 0000
rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; --e000-ffff ROM 1110 0000 00000000
ay1_control <= '1' when cpu_addr(13 downto 0) = X"2000" else '0'; --2000 8910 #1 control 0010 0000 0000 0000
ay1_write <= '1' when cpu_addr(13 downto 0) = X"2001" else '0'; --2001 8910 #1 write 0010 0000 0000 0001
ay2_control <= '1' when cpu_addr(14 downto 0) = X"4000" else '0'; --4000 8910 #2 control 0100 0000 0000 0000
ay2_write <= '1' when cpu_addr(14 downto 0) = X"4001" else '0'; --4001 8910 #2 write 0100 0000 0000 0001
--ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F
--adpcm_cs <= '1' when cpu_addr(14 downto 11) = "0001" else '0'; -- 0800-0FFF / 8800-8FFF
--irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF / 9000-9FFF
-- write enables
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
--ports_we <= '1' when cpu_rw = '0' and ports_cs = '1' else '0';
--adpcm_we <= '1' when cpu_rw = '0' and adpcm_cs = '1' else '0';
--irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
-- mux cpu in data between roms/io/wram
cpu_di <= wram_do when wram_cs = '1' else
sound_data when sound_rd = '1' else
-- port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
-- port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
-- port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
-- port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
rom_do when rom_cs = '1' else X"FF";
cpu_inst : mc6809i
port map
(
D => cpu_di,
DOut => cpu_do,
ADDR => cpu_addr,
RnW => cpu_rw,
E => '1',
Q => clk_2,
BS => open,
BA => open,
nIRQ => not cpu_irq,
nFIRQ => '1',
nNMI => '1',
AVMA => open,
BUSY => open,
LIC => open,
nHALT => '1',
nRESET => not cpu_reset,
nDMABREQ => '1',
RegData => open
);
cpu_prog_rom : entity work.sound_rom
port map(
clk => clk_2,
addr => cpu_addr(12 downto 0),
data => rom_do
);
cpu_ram : entity work.spram
generic map( widthad_a => 11)
port map(
clock => clk_2,
wren => wram_we,
address => cpu_addr(11 downto 0),
data => cpu_do,
q => wram_do
);
ay83910_inst1: YM2149
port map (
CLK => clk_1p5,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(4),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay1_do,
CHANNEL_A => ay1_chan_a,
CHANNEL_B => ay1_chan_b,
CHANNEL_C => ay1_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => (others => '0'),--select_sound_r,
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => ay1_port_b_do
);
ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
ay83910_inst2: YM2149
port map (
CLK => clk_1p5,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(3),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay2_do,
CHANNEL_A => ay2_chan_a,
CHANNEL_B => ay2_chan_b,
CHANNEL_C => ay2_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => (others => '0'),
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => open
);
ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
end SYN;

107
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd
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@@ -1,107 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.platform_pkg.all;
entity target_top is
port(
vma : out std_logic;
clk_sys : in std_logic;
clk_vid : in std_logic;
reset_in : in std_logic;
snd_l : out std_logic_vector(7 downto 0);
snd_r : out std_logic_vector(7 downto 0);
vid_hs : out std_logic;
vid_vs : out std_logic;
vid_hb : out std_logic;
vid_vb : out std_logic;
vid_r : out std_logic_vector(3 downto 0);
vid_g : out std_logic_vector(3 downto 0);
vid_b : out std_logic_vector(3 downto 0);
inputs_p1 : in std_logic_vector(7 downto 0);
inputs_p2 : in std_logic_vector(7 downto 0);
inputs_sys : in std_logic_vector(7 downto 0);
inputs_dip1 : in std_logic_vector(7 downto 0);
inputs_dip2 : in std_logic_vector(7 downto 0);
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
tile_rom_addr : out std_logic_vector(12 downto 0);
tile_rom_do : in std_logic_vector(15 downto 0)
);
end target_top;
architecture SYN of target_top is
signal clkrst_i : from_CLKRST_t;
signal video_i : from_VIDEO_t;
signal video_o : to_VIDEO_t;
signal audio_i : from_AUDIO_t;
signal audio_o : to_AUDIO_t;
signal platform_i : from_PLATFORM_IO_t;
signal platform_o : to_PLATFORM_IO_t;
begin
clkrst_i.clk(0) <=clk_sys;
clkrst_i.clk(1) <= clk_vid;
clkrst_i.arst <= reset_in;
clkrst_i.arst_n <= not clkrst_i.arst;
video_i.clk <= clk_vid;
video_i.clk_ena <= '1';
video_i.reset <= reset_in;
GEN_RESETS : for i in 0 to 3 generate
process (clkrst_i.clk(i), clkrst_i.arst)
variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
begin
if clkrst_i.arst = '1' then
rst_r := (others => '1');
elsif rising_edge(clkrst_i.clk(i)) then
rst_r := rst_r(rst_r'left-1 downto 0) & '0';
end if;
clkrst_i.rst(i) <= rst_r(rst_r'left);
end process;
end generate GEN_RESETS;
vid_r <= video_o.rgb.r(9 downto 6);
vid_g <= video_o.rgb.g(9 downto 6);
vid_b <= video_o.rgb.b(9 downto 6);
vid_hs <= video_o.hsync;
vid_vs <= video_o.vsync;
vid_hb <= video_o.hblank;
vid_vb <= video_o.vblank;
snd_l <= audio_o.ldata(15 downto 8);
snd_r <= audio_o.rdata(15 downto 8);
pace_inst : entity work.pace
port map(
clkrst_i => clkrst_i,
vma => vma,
inputs_p1 => inputs_p1,
inputs_p2 => inputs_p2,
inputs_sys => inputs_sys,
inputs_dip1 => inputs_dip1,
inputs_dip2 => inputs_dip2,
video_i => video_i,
video_o => video_o,
audio_i => audio_i,
audio_o => audio_o,
platform_i => platform_i,
platform_o => platform_o,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do,
tile_rom_addr => tile_rom_addr,
tile_rom_do => tile_rom_do
);
end SYN;

455
Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd
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@@ -1,455 +0,0 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.video_controller_pkg.all;
entity pace_video_controller is
generic
(
CONFIG : PACEVideoController_t := PACE_VIDEO_NONE;
DELAY : integer := 1;
H_SIZE : integer;
V_SIZE : integer;
L_CROP : integer range 0 to 255;
R_CROP : integer range 0 to 255;
H_SCALE : integer;
V_SCALE : integer;
H_SYNC_POL : std_logic := '1';
V_SYNC_POL : std_logic := '1';
BORDER_RGB : RGB_t := RGB_BLACK
);
port
(
-- clocking etc
video_i : in from_VIDEO_t;
-- register interface
reg_i : in VIDEO_REG_t;
-- video input data
rgb_i : in RGB_t;
-- control signals (out)
video_ctl_o : out from_VIDEO_CTL_t;
-- video output control & data
video_o : out to_VIDEO_t
);
end pace_video_controller;
architecture SYN of pace_video_controller is
constant SIM_DELAY : time := 2 ns;
constant VIDEO_H_SIZE : integer := H_SIZE * H_SCALE;
constant VIDEO_V_SIZE : integer := V_SIZE * V_SCALE;
subtype reg_t is integer range 0 to 2047;
alias clk : std_logic is video_i.clk;
alias clk_ena : std_logic is video_i.clk_ena;
alias reset : std_logic is video_i.reset;
-- registers
signal h_front_porch_r : reg_t := 0;
signal h_sync_r : reg_t := 0;
signal h_back_porch_r : reg_t := 0;
signal h_border_r : reg_t := 0;
signal h_video_r : reg_t := 0;
signal v_front_porch_r : reg_t := 0;
signal v_sync_r : reg_t := 0;
signal v_back_porch_r : reg_t := 0;
signal v_border_r : reg_t := 0;
signal v_video_r : reg_t := 0;
signal border_rgb_r : RGB_t := ((others=>'0'), (others=>'0'), (others=>'0'));
-- derived values
signal h_sync_start : reg_t := 0;
signal h_back_porch_start : reg_t := 0;
signal h_left_border_start : reg_t := 0;
signal h_video_start : reg_t := 0;
signal h_right_border_start : reg_t := 0;
signal h_line_end : reg_t := 0;
signal v_sync_start : reg_t := 0;
signal v_back_porch_start : reg_t := 0;
signal v_top_border_start : reg_t := 0;
signal v_video_start : reg_t := 0;
signal v_bottom_border_start : reg_t := 0;
signal v_screen_end : reg_t := 0;
signal hsync_s : std_logic := '0';
signal vsync_s : std_logic := '0';
signal hactive_s : std_logic := '0';
signal vactive_s : std_logic := '0';
signal hblank_s : std_logic := '0';
signal vblank_s : std_logic := '0';
subtype count_t is integer range 0 to 2047;
signal x_count : count_t := 0;
signal y_count : count_t := 0;
signal x_s : unsigned(10 downto 0) := (others => '0');
signal y_s : unsigned(10 downto 0) := (others => '0');
--signal extended_reset : std_logic := '1';
alias extended_reset : std_logic is video_i.reset;
begin
-- registers
reg_proc: process (reset, clk)
begin
--if reset = '1' then
case CONFIG is
when PACE_VIDEO_VGA_240x320_60Hz =>
-- P3M, clk=11.136MHz, clk_ena=5.568MHz
h_front_porch_r <= 272-240;
h_sync_r <= 5;
h_back_porch_r <= 22;
h_border_r <= (240-VIDEO_H_SIZE)/2;
v_front_porch_r <= 326-320;
v_sync_r <= 1;
v_back_porch_r <= 5;
v_border_r <= (320-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_320x480_60Hz =>
-- VGA, clk=12.588MHz
--# 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio
--Modeline "320x240" 12.588 320 336 384 400 240 245 246 262 Doublescan
h_front_porch_r <= 16;
h_sync_r <= 48;
h_back_porch_r <= 16;
h_border_r <= (320-VIDEO_H_SIZE)/2;
v_front_porch_r <= (5*2);
v_sync_r <= (1*2);
v_back_porch_r <= (16*2);
v_border_r <= (480-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_640x480_60Hz =>
-- VGA, clk=25.175MHz
h_front_porch_r <= 16;
h_sync_r <= 96;
h_back_porch_r <= 48;
h_border_r <= (640-VIDEO_H_SIZE)/2;
v_front_porch_r <= 10;
v_sync_r <= 2;
v_back_porch_r <= 33;
v_border_r <= (480-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_800x600_60Hz =>
-- SVGA, clk=40MHz
h_front_porch_r <= 40;
h_sync_r <= 128;
h_back_porch_r <= 88;
h_border_r <= (800-VIDEO_H_SIZE)/2;
v_front_porch_r <= 1;
v_sync_r <= 4;
v_back_porch_r <= 23;
v_border_r <= (600-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_1024x768_60Hz =>
-- XVGA, clk=65MHz
h_front_porch_r <= 24;
h_sync_r <= 136;
h_back_porch_r <= 160;
h_border_r <= (1024-VIDEO_H_SIZE)/2;
v_front_porch_r <= 3;
v_sync_r <= 6;
v_back_porch_r <= 29;
v_border_r <= (768-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_1366x768_60Hz =>
-- XVGA(NAVICO ROCKY), clk=72MHz
h_front_porch_r <= 88; --64;
h_sync_r <= 44; --112;
h_back_porch_r <= 148; --248;
h_border_r <= (1366-VIDEO_H_SIZE)/2;
v_front_porch_r <= 4; --3;
v_sync_r <= 5; --6;
v_back_porch_r <= 36; --18;
v_border_r <= (768-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_1280x800_60Hz =>
-- Sentinel Mode 36, clk=103.2MHz
h_front_porch_r <= 64;
h_sync_r <= 32;
h_back_porch_r <= 362-32-64;
h_border_r <= (1280-VIDEO_H_SIZE)/2;
v_front_porch_r <= 3;
v_sync_r <= 4;
v_back_porch_r <= 38-4-3;
v_border_r <= (800-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_1280x1024_60Hz =>
-- SXGA, clk=108MHz
h_front_porch_r <= 48;
h_sync_r <= 112;
h_back_porch_r <= 248;
h_border_r <= (1280-VIDEO_H_SIZE)/2;
v_front_porch_r <= 1;
v_sync_r <= 3;
v_back_porch_r <= 38;
v_border_r <= (1024-VIDEO_V_SIZE)/2;
when PACE_VIDEO_VGA_1680x1050_60Hz =>
-- WSXGA+, clk=147.14MHz
h_front_porch_r <= 104;
h_sync_r <= 184;
h_back_porch_r <= 288;
v_front_porch_r <= 1;
v_sync_r <= 3;
v_back_porch_r <= 33;
-- WSXGA+, clk=118MHz
--h_front_porch_r <= 48;
--h_sync_r <= 32;
--h_back_porch_r <= 80;
--v_front_porch_r <= 3;
--v_sync_r <= 6;
--v_back_porch_r <= 21;
h_border_r <= (1680-VIDEO_H_SIZE)/2;
v_border_r <= (1050-VIDEO_V_SIZE)/2;
when PACE_VIDEO_ARCADE_STD_336x240_60Hz =>
-- arcade standard resolution, clk=7.16MHz
h_front_porch_r <= 34;
h_sync_r <= 34;
h_back_porch_r <= 51;
h_border_r <= (336-VIDEO_H_SIZE)/2;
v_front_porch_r <= 3;
v_sync_r <= 3;
v_back_porch_r <= 16;
v_border_r <= (240-VIDEO_V_SIZE)/2;
when PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64 =>
-- arcade standard resolution, clk=28.64MHz
h_front_porch_r <= 4*34;
h_sync_r <= 4*34;
h_back_porch_r <= 4*51;
h_border_r <= 4*(336-VIDEO_H_SIZE)/2;
v_front_porch_r <= 3;
v_sync_r <= 3;
v_back_porch_r <= 16;
v_border_r <= (240-VIDEO_V_SIZE)/2;
when PACE_VIDEO_CVBS_720x288p_50Hz =>
-- generic composite, clk=13.5MHz
h_front_porch_r <= (8+12);
h_sync_r <= 64;
h_back_porch_r <= (144-64-(8+12));
h_border_r <= (720-VIDEO_H_SIZE)/2;
v_front_porch_r <= 1;
v_sync_r <= 3;
v_back_porch_r <= 20;
v_border_r <= (288-VIDEO_V_SIZE)/2;
when PACE_VIDEO_LCM_320x240_60Hz =>
-- DE1/2, clk=18MHz
h_front_porch_r <= 59;
h_sync_r <= 1;
h_back_porch_r <= 151;
h_border_r <= (320-VIDEO_H_SIZE)*3/2;
v_front_porch_r <= 8;
v_sync_r <= 1;
v_back_porch_r <= 13;
v_border_r <= (240-VIDEO_V_SIZE)/2;
when others =>
null;
end case;
h_video_r <= VIDEO_H_SIZE;
v_video_r <= VIDEO_V_SIZE;
border_rgb_r <= BORDER_RGB;
--end if;
end process reg_proc;
-- register some arithmetic
init_proc: process (reset, clk, clk_ena)
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
h_sync_start <= h_front_porch_r - 1;
h_back_porch_start <= h_sync_start + h_sync_r;
h_left_border_start <= h_back_porch_start + h_back_porch_r;
h_video_start <= h_left_border_start + h_border_r;
h_right_border_start <= h_video_start + h_video_r;
h_line_end <= h_right_border_start + h_border_r;
v_sync_start <= v_front_porch_r - 1;
v_back_porch_start <= v_sync_start + v_sync_r;
v_top_border_start <= v_back_porch_start + v_back_porch_r;
v_video_start <= v_top_border_start + v_border_r;
v_bottom_border_start <= v_video_start + v_video_r;
v_screen_end <= v_bottom_border_start + v_border_r;
end if;
end process init_proc;
reset_proc: process (reset, clk)
variable count_v : integer;
begin
if reset = '1' then
--extended_reset <= '1';
count_v := 7;
elsif rising_edge(clk) then
if count_v = 0 then
--extended_reset <= '0';
else
count_v := count_v - 1;
end if;
end if;
end process reset_proc;
-- video control outputs
timer_proc: process (extended_reset, clk, clk_ena)
begin
if extended_reset = '1' then
hblank_s <= '1';
vblank_s <= '1';
hactive_s <= '0';
vactive_s <= '0';
hsync_s <= not H_SYNC_POL;
x_count <= 0;
y_count <= 0;
elsif rising_edge(clk) and clk_ena = '1' then
if x_count = h_line_end then
hblank_s <= '1';
hactive_s <= '0'; -- for 0 borders
if y_count = v_screen_end then
vblank_s <= '1';
vactive_s <= '0'; -- for 0 borders
y_count <= 0;
else
y_s <= y_s + 1;
if y_count = v_sync_start then
vsync_s <= V_SYNC_POL;
elsif y_count = v_back_porch_start then
vsync_s <= not V_SYNC_POL;
elsif y_count = v_video_start then
vblank_s <= '0'; -- for 0 borders
vactive_s <= '1';
y_s <= (others => '0');
-- check the borders last in case they're 0
elsif y_count = v_top_border_start then
vblank_s <= '0';
elsif y_count = v_bottom_border_start then
vactive_s <= '0';
end if;
y_count <= y_count + 1;
end if;
x_count <= 0;
else
x_s <= x_s + 1;
if x_count = h_sync_start then
hsync_s <= H_SYNC_POL;
elsif x_count = h_back_porch_start then
hsync_s <= not H_SYNC_POL;
elsif x_count = h_video_start then
hblank_s <= '0'; -- for 0 borders
hactive_s <= '1';
x_s <= (others => '0');
-- check the borders last in case they're 0
elsif x_count = h_left_border_start then
hblank_s <= '0';
elsif x_count = h_right_border_start then
hactive_s <= '0';
end if;
x_count <= x_count + 1;
end if;
end if; -- rising_edge(clk) and clk_ena = '1'
end process timer_proc;
-- pass-through for tile/bitmap & sprite controllers
video_ctl_o.clk <= clk;
video_ctl_o.clk_ena <= clk_ena;
-- for video DACs and TFT output
video_o.clk <= clk;
BLK_VIDEO_O : block
constant PIPELINE_DELAY : natural := DELAY+1;
-- won't synthesize correctly under ISE if these are variables
signal hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
signal vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
begin
video_o_proc: process (extended_reset, clk, clk_ena)
variable hsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
variable vsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
--variable hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
--variable vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
variable hblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
variable vblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
alias hsync_v : std_logic is hsync_v_r(hsync_v_r'left);
alias vsync_v : std_logic is vsync_v_r(vsync_v_r'left);
alias hactive_v : std_logic is hactive_v_r(hactive_v_r'left);
alias vactive_v : std_logic is vactive_v_r(vactive_v_r'left);
alias hblank_v : std_logic is hblank_v_r(hblank_v_r'left);
alias vblank_v : std_logic is vblank_v_r(vblank_v_r'left);
variable stb_cnt_v : unsigned(3 downto 0); -- up to 16x scaling
begin
if extended_reset = '1' then
hsync_v_r := (others => not H_SYNC_POL);
vsync_v_r := (others => not V_SYNC_POL);
hactive_v_r <= (others => '0');
vactive_v_r <= (others => '0');
hblank_v_r := (others => '0');
vblank_v_r := (others => '0');
stb_cnt_v := (others => '1');
elsif rising_edge(clk) and clk_ena = '1' then
-- register control signals and handle scaling
video_ctl_o.hblank <= not hactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers
video_ctl_o.vblank <= not vactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers
-- handle scaling
video_ctl_o.stb <= stb_cnt_v(H_SCALE-1) after SIM_DELAY;
if hactive_s = '1' and vactive_s = '1' then
stb_cnt_v := stb_cnt_v + 2;
elsif hblank_s = '0' and vblank_s = '0' then
stb_cnt_v := (others => '1');
end if;
video_ctl_o.x <= std_logic_vector(resize(x_s(x_s'left downto H_SCALE-1), video_ctl_o.x'length)) after SIM_DELAY;
video_ctl_o.y <= std_logic_vector(resize(y_s(y_s'left downto V_SCALE-1), video_ctl_o.y'length)) after SIM_DELAY;
-- register video outputs
if hactive_v = '1' and vactive_v = '1' then
-- active video
if x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or
x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY) then
video_o.rgb <= RGB_BLACK after SIM_DELAY;
else
video_o.rgb <= rgb_i after SIM_DELAY;
end if;
elsif hblank_v = '0' and vblank_v = '0' then
-- border
video_o.rgb <= border_rgb_r after SIM_DELAY;
else
video_o.rgb.r <= (others => '0') after SIM_DELAY;
video_o.rgb.g <= (others => '0') after SIM_DELAY;
video_o.rgb.b <= (others => '0') after SIM_DELAY;
end if;
video_o.hsync <= hsync_v after SIM_DELAY;
video_o.vsync <= vsync_v after SIM_DELAY;
video_o.hblank <= hblank_v after SIM_DELAY;
video_o.vblank <= vblank_v after SIM_DELAY;
-- pipelined signals
hsync_v_r := hsync_v_r(hsync_v_r'left-1 downto 0) & hsync_s;
vsync_v_r := vsync_v_r(vsync_v_r'left-1 downto 0) & vsync_s;
hactive_v_r <= hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s;
vactive_v_r <= vactive_v_r(vactive_v_r'left-1 downto 0) & vactive_s;
hblank_v_r := hblank_v_r(hblank_v_r'left-1 downto 0) & hblank_s;
vblank_v_r := vblank_v_r(vblank_v_r'left-1 downto 0) & vblank_s;
end if;
end process video_o_proc;
end block BLK_VIDEO_O;
end SYN;