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Code Issues Releases Wiki Activity

Some Cleanup on Victory

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This commit is contained in:
Marcel 2019-05-19 17:23:30 +02:00
parent 2eb88954e5
commit df8d36dd1f
12 changed files with 20 additions and 228 deletions
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BIN
Arcade_MiST/Crazy Climber Hardware/Swimmer_MiST/Snapshot/Swimmer.rbf Normal file
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Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Release/Victory.rbf
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3
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf
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@ -18,7 +18,7 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 15:41:07 May 10, 2019
# Date created = 23:19:48 May 18, 2019
#
# -------------------------------------------------------------------------- #
#
@ -53,7 +53,6 @@ set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd
set_global_assignment -name VHDL_FILE rtl/ROM/k_rom.vhd
set_global_assignment -name VHDL_FILE rtl/ROM/h_rom.vhd
set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd
set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd

4
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv
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@ -1,5 +1,5 @@
//============================================================================
// Arcade: Galaxian
// Arcade: Victory
//
// Port to MiSTer
// Copyright (C) 2017 Sorgelig
@ -44,7 +44,7 @@ localparam CONF_STR = {
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
"V,v1.21.",`BUILD_DATE
};
assign LED = 1;

4
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.v
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@ -1,2 +1,2 @@
`define BUILD_DATE "190510"
`define BUILD_TIME "154516"
`define BUILD_DATE "190518"
`define BUILD_TIME "233058"

59
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd
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@ -73,10 +73,8 @@ architecture RTL of galaxian is
-------- CPU RAM ----------------------------
signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0');
-------- ADDRESS DECDER ----------------------
signal W_BD_G : std_logic := '0';
signal W_CPU_RAM_CS : std_logic := '0';
signal W_CPU_RAM_RD : std_logic := '0';
-- signal W_CPU_RAM_WR : std_logic := '0';
signal W_CPU_ROM_CS : std_logic := '0';
signal W_DIP_OE : std_logic := '0';
signal W_H_FLIP : std_logic := '0';
@ -86,14 +84,11 @@ architecture RTL of galaxian is
signal W_OBJ_RAM_WR : std_logic := '0';
signal W_PITCH : std_logic := '0';
signal W_SOUND_WE : std_logic := '0';
signal W_STARS_ON : std_logic := '0';
signal W_STARS_OFFn : std_logic := '0';
signal W_SW0_OE : std_logic := '0';
signal W_SW1_OE : std_logic := '0';
signal W_V_FLIP : std_logic := '0';
signal W_VID_RAM_RD : std_logic := '0';
signal W_VID_RAM_WR : std_logic := '0';
signal W_WDR_OE : std_logic := '0';
--------- INPORT -----------------------------
signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0');
--------- VIDEO -----------------------------
@ -111,11 +106,6 @@ architecture RTL of galaxian is
signal W_FS : std_logic_vector( 2 downto 0) := (others => '0');
signal blx_comb : std_logic := '0';
signal W_1VF : std_logic := '0';
signal W_256HnX : std_logic := '0';
signal W_8HF : std_logic := '0';
signal W_DAC_A : std_logic := '0';
signal W_DAC_B : std_logic := '0';
signal W_MISSILEn : std_logic := '0';
signal W_SHELLn : std_logic := '0';
signal W_MS_D : std_logic := '0';
@ -128,9 +118,6 @@ architecture RTL of galaxian is
signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0');
signal rst_count : std_logic_vector( 3 downto 0) := (others => '0');
signal W_COL : std_logic_vector( 2 downto 0) := (others => '0');
signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0');
signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0');
signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0');
signal W_VID : std_logic_vector( 1 downto 0) := (others => '0');
signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0');
signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0');
@ -165,9 +152,6 @@ begin
I_VID_RAM_WR => W_VID_RAM_WR,
I_DRIVER_WR => W_DRIVER_WE,
O_C_BLnX => W_C_BLnX,
O_8HF => W_8HF,
O_256HnX => W_256HnX,
O_1VF => W_1VF,
O_MISSILEn => W_MISSILEn,
O_SHELLn => W_SHELLn,
O_BD => W_VID_DO,
@ -196,18 +180,8 @@ begin
BUSAK_n => open,
DOE => open
);
-- mc_cpu_ram : entity work.MC_CPU_RAM
-- port map (
-- I_CLK => W_CPU_RAM_CLK,
-- I_ADDR => W_A(9 downto 0),
-- I_D => W_BDI,
-- I_WE => W_CPU_WR,
-- I_OE => W_CPU_RAM_RD,
-- O_D => W_CPU_RAM_DO
-- );
mc_cpu_ram2 : entity work.MC_CPU_RAM2
mc_cpu_ram : entity work.MC_CPU_RAM
port map (
I_CLK => W_CPU_RAM_CLK,
I_ADDR => W_A(10 downto 0),
@ -216,6 +190,7 @@ begin
I_OE => W_CPU_RAM_RD,
O_D => W_CPU_RAM_DO
);
mc_adec : entity work.MC_ADEC
port map(
I_CLK_12M => W_CLK_12M,
@ -246,14 +221,11 @@ begin
O_SW0_OE => W_SW0_OE,
O_SW1_OE => W_SW1_OE,
O_DIP_OE => W_DIP_OE,
O_WDR_OE => W_WDR_OE,
O_DRIVER_WE => W_DRIVER_WE,
O_SOUND_WE => W_SOUND_WE,
O_PITCH => W_PITCH,
O_H_FLIP => W_H_FLIP,
O_V_FLIP => W_V_FLIP,
O_BD_G => W_BD_G,
O_STARS_ON => W_STARS_ON
O_V_FLIP => W_V_FLIP
);
-- active high buttons
@ -301,30 +273,11 @@ begin
I_COL => W_COL,
I_C_BLnX => W_C_BLnX,
O_C_BLXn => W_C_BLXn,
O_STARS_OFFn => W_STARS_OFFn,
O_R => W_VIDEO_R,
O_G => W_VIDEO_G,
O_B => W_VIDEO_B
);
mc_stars : entity work.MC_STARS
port map (
I_CLK_18M => W_CLK_18M,
I_CLK_6M => W_CLK_6M,
I_H_FLIP => W_H_FLIP,
I_V_SYNC => W_V_SYNC_int,
I_8HF => W_8HF,
I_256HnX => W_256HnX,
I_1VF => W_1VF,
I_2V => W_V_CNT(1),
I_STARS_ON => '0',--W_STARS_ON -- No Stars on Victory,
I_STARS_OFFn => W_STARS_OFFn,
O_R => W_STARS_R,
O_G => W_STARS_G,
O_B => W_STARS_B,
O_NOISE => open
);
mc_sound_a : entity work.MC_SOUND_A
port map(
I_CLK_12M => W_CLK_12M,
@ -368,9 +321,9 @@ begin
W_MS_G <= not blx_comb and W_MS_D;
W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ;
W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
W_R <= W_VIDEO_R or (W_MS_R & W_MS_R & "0");
W_G <= W_VIDEO_G or (W_MS_G & W_MS_G & "0");
W_B <= W_VIDEO_B or (W_MS_B & W_MS_B & "0");
process(W_CLK_6M)
begin

39
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd
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@ -15,39 +15,7 @@
-- 2004- 5- 6 first release.
-- 2004- 8-23 Improvement with T80-IP.
---------------------------------------------------------------------
--
--GALAXIAN Address Map
--
-- Address Item(R..read-mode W..wight-mode) Parts
--0000 - 1FFF CPU-ROM..R ( 7H or 7K )
--2000 - 3FFF CPU-ROM..R ( 7L )
--4000 - 47FF CPU-RAM..RW ( 7N & 7P )
--5000 - 57FF VID-RAM..RW
--5800 - 5FFF OBJ-RAM..RW
--6000 - SW0..R LAMP......W
--6800 - SW1..R SOUND.....W
--7000 - DIP..R
--7001 NMI_ON....W
--7004 STARS_ON..W
--7006 H_FLIP....W
--7007 V-FLIP....W
--7800 WDR..R PITCH.....W
--8000 - 87FF CPU-RAM..RW
--W MODE
--6000 1P START
--6001 2P START
--6002 COIN LOCKOUT
--6003 COIN COUNTER
--6004 - 6007 SOUND CONTROL(OSC)
--
--6800 SOUND CONTROL(FS1)
--6801 SOUND CONTROL(FS2)
--6802 SOUND CONTROL(FS3)
--6803 SOUND CONTROL(HIT)
--6805 SOUND CONTROL(SHOT)
--6806 SOUND CONTROL(VOL1)
--6807 SOUND CONTROL(VOL2)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
@ -89,8 +57,7 @@ entity MC_ADEC is
O_PITCH : out std_logic;
O_H_FLIP : out std_logic;
O_V_FLIP : out std_logic;
O_BD_G : out std_logic;
O_STARS_ON : out std_logic
O_BD_G : out std_logic
);
end;
@ -212,7 +179,6 @@ begin
O_CPU_RAM_RD <= not W_8N_Q(0);--4000
O_PITCH <= not W_8M_Q(7);
-- STARS_ON_ENA <= not W_8M_Q(6);
O_SOUND_WE <= not W_8M_Q(5);
O_DRIVER_WE <= not W_8M_Q(4);
O_OBJ_RAM_WR <= not W_8M_Q(3);
@ -243,7 +209,6 @@ begin
end if;
end process;
O_STARS_ON <= W_9N_Q(4);
O_H_FLIP <= W_9N_Q(6);
O_V_FLIP <= W_9N_Q(7);

35
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd
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@ -25,39 +25,6 @@ library ieee;
-- mc_top.v use
entity MC_CPU_RAM is
port (
I_CLK : in std_logic;
I_ADDR : in std_logic_vector(9 downto 0);
I_D : in std_logic_vector(7 downto 0);
I_WE : in std_logic;
I_OE : in std_logic;
O_D : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of MC_CPU_RAM is
signal W_D : std_logic_vector(7 downto 0) := (others => '0');
begin
O_D <= W_D when I_OE ='1' else (others=>'0');
ram_inst : work.spram generic map(10,8)
port map
(
address => I_ADDR,
clock => I_CLK,
data => I_D,
wren => I_WE,
q => W_D
);
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- mc_top.v use
entity MC_CPU_RAM2 is
port (
I_CLK : in std_logic;
I_ADDR : in std_logic_vector(10 downto 0);
@ -67,7 +34,7 @@ entity MC_CPU_RAM2 is
O_D : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of MC_CPU_RAM2 is
architecture RTL of MC_CPU_RAM is
signal W_D : std_logic_vector(7 downto 0) := (others => '0');
begin

2
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd
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@ -26,7 +26,6 @@ port (
I_C_BLnX : in std_logic;
O_C_BLXn : out std_logic;
O_STARS_OFFn : out std_logic;
O_R : out std_logic_vector(2 downto 0);
O_G : out std_logic_vector(2 downto 0);
O_B : out std_logic_vector(2 downto 0)
@ -44,7 +43,6 @@ begin
W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0);
O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0);
O_STARS_OFFn <= W_6M_DO(1);
--always@(posedge I_CLK_6M or negedge W_6M_CLR)
process(I_CLK_6M, W_6M_CLR)

90
Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_stars.vhd
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@ -1,90 +0,0 @@
------------------------------------------------------------------------------
-- FPGA MOONCRESTA STARS
--
-- Version : 2.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MC_STARS is
port (
I_CLK_18M : in std_logic;
I_CLK_6M : in std_logic;
I_H_FLIP : in std_logic;
I_V_SYNC : in std_logic;
I_8HF : in std_logic;
I_256HnX : in std_logic;
I_1VF : in std_logic;
I_2V : in std_logic;
I_STARS_ON : in std_logic;
I_STARS_OFFn : in std_logic;
O_R : out std_logic_vector(1 downto 0);
O_G : out std_logic_vector(1 downto 0);
O_B : out std_logic_vector(1 downto 0);
O_NOISE : out std_logic
);
end;
architecture RTL of MC_STARS is
signal CLK_1C : std_logic := '0';
signal W_2D_Qn : std_logic := '0';
signal W_3B : std_logic := '0';
signal noise : std_logic := '0';
signal W_2A : std_logic := '0';
signal W_4P : std_logic := '0';
signal CLK_1AB : std_logic := '0';
signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0');
signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0');
begin
O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
W_3B <= W_2D_Qn xor W_1AB_Q(4);
W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
O_NOISE <= noise ;
process(I_2V)
begin
if rising_edge(I_2V) then
noise <= W_2D_Qn;
end if;
end process;
process(CLK_1C, I_V_SYNC)
begin
if(I_V_SYNC = '1') then
W_1C_Q <= (others => '0');
elsif rising_edge(CLK_1C) then
W_1C_Q <= W_1C_Q(0) & '1';
end if;
end process;
process(CLK_1AB, I_STARS_ON)
begin
if(I_STARS_ON = '0') then
W_1AB_Q <= (others => '0');
W_2D_Qn <= '1';
elsif rising_edge(CLK_1AB) then
W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
W_2D_Qn <= not W_1AB_Q(15);
end if;
end process;
end RTL;

4
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.v
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@ -1,2 +1,2 @@
`define BUILD_DATE "190517"
`define BUILD_TIME "155807"
`define BUILD_DATE "190518"
`define BUILD_TIME "015429"

8
Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd
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@ -380,7 +380,7 @@ begin
V4 => vcnt(2),
V2 => vcnt(1),
V1 => vcnt(0),
FLIP => '0'--control_reg(3)
FLIP => control_reg(5)
);
p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab)
@ -463,7 +463,7 @@ begin
end if;
wr0_l <= decb(0);--101000 00 100000 1010000 10 000000
wr1_l <= decb(1);
wr2_l <= decb(2);
wr2_l <= decb(2);--spriteram2
end process;
p_control_reg : process
@ -579,7 +579,7 @@ begin
--
I_HBLANK => hblank,
I_VBLANK => vblank,
I_FLIP => '0',--control_reg(3),
I_FLIP => control_reg(5),
I_WR2_L => wr2_l,
--
O_RED => O_VIDEO_R,
@ -609,7 +609,7 @@ begin
--
I_WR1_L => wr1_l,
I_WR0_L => wr0_l,
I_SOUND_ON => '1',--control_reg(1),
I_SOUND_ON => control_reg(3),
--
O_AUDIO => O_AUDIO,
ENA_6 => ena_6,