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Xevious: new core

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Gyorgy Szombathelyi 2019-12-01 11:18:40 +01:00
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Arcade_MiST/Galaga Hardware/Xevious_MiST/README.txt Normal file
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---------------------------------------------------------------------------------
-- Xevious by Dar (darfpga@aol.fr) (01 May 2017)
-- http://darfpga.blogspot.fr
--
-- Terasic board DE2-35 or MAX10 DE10 Lite
--
-- Modified for external SDRAM controller as ROM storage for MiST by Slingshot
--
-- Use xevious_cpu_gfx_8bits.bin as XEVIOUS.ROM
--
---------------------------------------------------------------------------------
-- gen_ram.vhd & io_ps2_keyboard
--------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
---------------------------------------------------------------------------------
-- T80/T80se - Version : 0247
-----------------------------
-- Z80 compatible microprocessor core
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- MAX10 DE10 Lite Top version 0.2 : (01/05/2017)
--
-- add digital audio out sgtl5000 support with teensy audio shield on top of
-- arduino usb host shield
--
-- MAX10 DE10 Lite Top version 0.1 : (14/04/2017)
--
-- add usb host max3421e support with arduino shield
--
-- BEWARE : arduino shield has to be modified (see instruction on my blog)
--
-- Keyboard PS/2 available at gpio pins
-- Beware voltage translation for PS2 keyboard connection : do it at your own risk
-- Don't do this by yourself if you have no electronic skill, you may damage the board
--
-- Sound PWM output available at gpio pins
--
-- USB keyboard or joystick available (with arduino shield)
-- See more explanation in file xevious_de10_lite.vhd
--
-- No external SRAM required, Use internal RAM for xevious_cpu_gfx_8bits.vhd
--
---------------------------------------------------------------------------------
--
-- Video 15KHz is OK,
--
-- This is not VGA, you have to use a TV set with SCART plug
--
-- SCART(TV) pin - signal - VGA(DE10) pin
-- 15 - red - 1
-- 11 - green - 2
-- 7 - blue - 3
-- 5,9,13 - gnd - 5,6,7
-- (comp. sync)20 - csync - 13 (HS)
-- (fast commut)16 - commut - 14 (VS)
-- 17,18 - gnd - 8,10
--
---------------------------------------------------------------------------------
--
-- XEVIOUS VHDL VERSION
--
-- Todo : replace cs51xx rough emulation
--
-- Version 0.3 -- 28/02/2017
-- Fixed cs54xx audio 2 (mb88 JMP instruction fixed)
--
-- Version 0.2 -- 26/02/2017 --
-- Replace cs50xx rough emulation by mb88 processor
-- mb88.vhd : tstR and tbit fixed
--
-- Version 0.1 -- 15/02/2017 --
-- Add ship explosion with mb88 processor
---------------------------------------------------------------------------------
-- Features :
-- TV 15KHz mode only (atm)
-- Cocktail mode : todo
-- Replace cs51xx with true mb88 processor : todo
--
-- Sound ok, Ship explode ok with true mb88 processor
-- Use with MAME roms from xevious.zip
--
-- Use make_xevious_proms.bat to build vhd file and bin from binaries
-- IMPORTANT -- for DE2-35 SRAM have to be loaded with rom data before loading
-- xevious_de2.sof
--
-- Use DE2 Control Panel to load xevious_cpu_gfx_16bits.bin to DE2 SRAM
--
-- 1) Switch ON DE2
-- 2) Launch QuartusII and program DE2 with "DE2_USB_API.sof"
-- 3) Launch DE2 control panel
-- a) Menu Open -> Open USB port 0
-- b) (Test connexion) Tab PS2 & 7-SEG : select '3' on HEX7 and click on SET, digit on DE2 should diplay '3'
-- c) Tab SRAM / frame Sequential Write : check box 'File length'. Click on Write a file to SRAM and choose xevious_cpu_gfx_16bits.bin
-- d) wait for compete write
-- e) (check write) frame Random Access : click Read (Adress 0), rData should display '3E3E'
-- f) VERY IMPORTANT : Menu Open -> Close USB port
-- DO NOT SWITCH OFF DE2 or you will need to reload SRAM
-- 4) go back to QuartusII and program DE2 with "xevious_de2.sof"
-- Explanation : Xevious make use of large amount of data (prom). All these data could not fit into DE2-35 FPGA.
-- I choose to put all 3 CPUs program, foreground graphics, background graphics and sprite graphics data
-- to external memory. This lead to 68Ko of data. As DE2-35 use a 16bits width SRAM since and DE2 control panel doesn't allow
-- to load 8bits width data all data have been duplicated on both 8bits LSB and 8bits MSB. So xevious_cpu_gfx_16bits.bin
-- is 136Ko.
-- For other boards one have to consider that the external data are accessed with a 18Mhz multiplexed addressing scheme. So
-- external device have to have a 55ns max access time. Of course big enough FPGA may directly implement these data bank without
-- requiring external device. It is to notice that 55ns will be not so easy to reach with Flash or SDRAM memories.
-- Xevious Hardware caracteristics :
--
-- 3xZ80 CPU accessing each own program rom and shared ram/devices
-- 16Ko program for CPU1
-- 8Ko program for CPU2
-- 4Ko program for CPU3
--
-- One char tile map 64x28 (called foreground/fg)
-- 1 colors/64sets among 128 colors
-- 4Ko ram (code + attr/color), 4Ko rom graphics, 8pixels of 1bits/byte
-- Horizontal scrolling (horizontal for TV scan = vertical for upright cabinet)
-- full emulation in vhdl
-- One background tile map 64x28 (called background/bg)
-- 4 colors/128sets among 128 colors
-- 4Ko ram (code + attr/color), 8Ko rom graphics, 8pixels of 2bits/ 2bytes
-- Horizontal/Vertical scrolling
-- full emulation in vhdl
--
-- 64 sprites with priorities, flip H/V, 2x size H/V,
-- 8 colors/64sets among 128 colors.
-- 24Ko rom graphics, 4pixels of 3bits / 1.5byte
-- 4 colors/64sets among 128 colors.
-- 8Ko rom graphics, 4pixels of 2bits / byte
-- full emulation in vhdl (improved capabilities : more sprites/scanline)
--
-- Char/sprites color palette 128 colors among 4096
-- 12bits 4red/4green/4blue
-- full emulation in vhdl
--
-- Terrain data
-- 8Ko + 4Ko + 4Ko rom
--
-- Namco 06XX for 51/54XX control
-- simplified emulation in vhdl
--
-- Namco 50XX for protection management
-- true mb88 processor ok
-- Namco 51XX for coin/credit management
-- simplified emulation in vhdl : 1coin/1credit, 1 or 2 players start
--
-- Namco 54XX for sound effects
-- true mb88 processor ok
--
-- Namco sound waveform and frequency synthetizer
-- full original emulation in vhdl
--
-- Namco such as address generator, H/V counters and shift registers
-- full emulation in vhdl from what I think they should do.
--
-- Working ram : 2Kx8bits + 3x2Kx8bits + 2x4Kox8bits (all shared)
-- Sprites ram : 1 scan line delay flip/flop 512x4bits
-- Sound registers ram : 2x16x4bits
-- Sound sequencer rom : 256x4bits (3 sequential 4 bits adders)
-- Sound wavetable rom : 256x4bits 8 waveform of 32 samples of 4bits/level
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- DE2-35 Top level for Xevious by Dar (darfpga@aol.fr) (January 2017)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
--
-- Main features :
-- PS2 keyboard input
-- Wm8731 sound output
-- 68Ko external SRAM (136Ko for 16bits width)
--
-- Uses 1 pll for 18MHz and 11MHz generation from 50MHz
--
-- Board key :
-- 0 : reset
--
-- Keyboard inputs :
-- F3 : Add coin
-- F2 : Start 2 players
-- F1 : Start 1 player
-- SPACE : Fire
-- RIGHT arrow : Move right
-- LEFT arrow : Move left
-- UP arrow : Move up
-- DOWN arrow : Move down
-- CTRL : Launch bomb
--
-- Dip switch and other details : see xevious.vhd
---------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+-------------------------------------------------+
Fitter Status : Successful - Fri Apr 14 21:57:50 2017
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : xevious_de2
Top-level Entity Name : xevious_de2
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 10,744 / 33,216 ( 32 % )
Total combinational functions : 9,815 / 33,216 ( 30 % )
Dedicated logic registers : 3,054 / 33,216 ( 9 % )
Total registers : 3054
Total pins : 88 / 475 ( 19 % )
Total virtual pins : 0
Total memory bits : 295,936 / 483,840 ( 61 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )
+--------------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+-------------------------------------------------+
Fitter Status : Successful - Fri Apr 14 22:11:20 2017
Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Revision Name : xevious_de10_lite
Top-level Entity Name : xevious_de10_lite
Family : MAX 10
Device : 10M50DAF484C6GES
Timing Models : Preliminary
Total logic elements : 11,849 / 49,760 ( 24 % )
Total combinational functions : 10,942 / 49,760 ( 22 % )
Dedicated logic registers : 3,256 / 49,760 ( 7 % )
Total registers : 3256
Total pins : 137 / 360 ( 38 % )
Total virtual pins : 0
Total memory bits : 852,992 / 1,677,312 ( 51 % )
Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )
UFM blocks : 0 / 1 ( 0 % )
ADC blocks : 0 / 2 ( 0 % )
+------------------------------------+-------------------------------------------------+
---------------
VHDL File list
---------------
rtl_dar/xevious_de2.vhd Top level for de2 board
rtl_dar/xevious.vhd Main logic
rtl_dar/pll50_to_11_and_18.vhd PLL 11MHz and 18 MHz from 50MHz alt. mf (DE2-CycloneII)
rtl_dar/gen_video.vhd Video genertor H/V counter, blanking and syncs
rtl_dar/sound_machine.vhd Namco sound waveform/frequency synthetizer
rtl_dar/mb88.vhd mb88 fujitsu 4bits microprocessor
rtl_dar/sp_palette_msb.vhd sprites color LUT msb 3bits 64sets => 64 colors PROM
rtl_dar/sp_palette_lsb.vhd sprites color LUT lsb 3bits 64sets => 64 colors PROM
rtl_dar/red.vhd 128 colors 4bits palette red PROM
rtl_dar/green.vhd 128 colors 4bits palette green PROM
rtl_dar/blue.vhd 128 colors 4bits palette blue PROM
rtl_dar/bg_palette_msb.vhd background color LUT msb 2bits 64sets => 64 colors PROM
rtl_dar/bg_palette_lsb.vhd background color LUT lsb 2bits 64sets => 64 colors PROM
rtl_dar/terrain_2c.vhd terrain map PROM
rtl_dar/terrain_2b.vhd terrain map PROM
rtl_dar/terrain_2a.vhd terrain map PROM
rtl_dar/sound_seq.vhd Sound slice adder sequencer PROM
rtl_dar/sound_samples.vhd Sound wavetable PROM
rtl_dar/cs54xx_prog.vhd Namco custom chip 54xx pgm PROM
rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification)
wm_8731_dac.vhd DE1/DE2 audio dac
io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
kbd_joystick.vhd Keyboard key to player/coin input
xevious_de10_lite.vhd Top level for de10 lite
decodeur_7_seg.vhd 7 segments decoder (for usb report display)
usb_report_pkg.vhd usb report buffer
usb_keyboard_decoder.vhd usb keyboard report to game input
usb_joystick_decoder.vhd usb joystick report to game input
usb_host_max3421e.vhd usb host for max3421e controler
max10_pll_18M_11M.vhd PLL 11MHz and 18 MHz from 50MHz alt. mf (DE10_lite-MAX10)
rtl_T80/T80se.vhd T80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
rtl_T80/T80_Reg.vhd
rtl_T80/T80_Pack.vhd
rtl_T80/T80_MCode.vhd
rtl_T80/T80_ALU.vhd
rtl_T80/T80.vhd
----------------------
Quartus project files
----------------------
de2/xevious_de2.qsf de2 settings (files,pins...)
de2/xevious_de2.qpf de2 project
(CycloneII support : maximum release Quartus 13.1)
de10_lite/xevious_de10_lite.qsf de10_lite settings (files,pins...)
de10_lite/xevious_de10_lite.qpf de10_lite project
-----------------------------
Required ROMs (Not included)
-----------------------------
You need the following 29 ROMs binary files from xevious.zip
(MAME xevious)
xvi_1.3p , xvi_2.3m , xvi_3.2m , xvi_4.2l , xvi_5.3f , xvi_6.3j , xvi_7.2c ,
xvi_12.3b , xvi_13.3c , xvi_14.3d , xvi_15.4m , xvi_17.4p , xvi_16.4n , xvi_18.4r ,
xvi_9.2a , xvi_10.2b , xvi_11.2c , xvi_8bpr.6a , xvi_9bpr.6d , xvi10bpr.6e ,
xvi_7bpr.4h , xvi_6bpr.4f , xvi_4bpr.3l , xvi_5bpr.3m , xvi_1bpr.5n , xvi_2bpr.7n .
50xx.bin , 51xx.bin , 54xx.bin
------
Tools
------
You need to build vhdl/bin files from the binary file :
- Unzip the roms file in the tools/xevious_unzip_win64/roms directory (or win32 or linux)
- Double click (execute) the script tools/make_xevious_proms.bat to get the following files
The following 15 files will be converted to vhld (rom) files.
(bpr files are 4bits width prom, vhdl files are 8bits width, compiler will optimize to the right size automaticaly)
xvi_9.2a => terrain_2a.vhd
xvi_10.2b => terrain_2b.vhd
xvi_11.2c => terrain_2c.vhd
xvi_8bpr.6a => red.vhd
xvi_9bpr.6d => green.vhd
xvi10bpr.6e => blue.vhd
xvi_7bpr.4h => bg_palette_lsb.vhd
xvi_6bpr.4f => bg_palette_msb.vhd
xvi_4bpr.3l => sp_palette_lsb.vhd
xvi_5bpr.3m => sp_palette_msb.vhd
xvi_1bpr.5n => sound_seq.vhd
xvi_2bpr.7n => sound_samples.vhd
50xx.bin => cs50xx_prog.vhd
51xx.bin => cs51xx_prog.vhd (N.U. atm)
54xx.bin => cs54xx_prog.vhd
The following 14 files will produce "xevious_cpu_gfx_8bits.bin" and "xevious_cpu_gfx_16bits.bin"
xvi_1.3p , xvi_2.3m , xvi_3.2m , xvi_4.2l, xvi_5.3f , xvi_6.3j, xvi_7.2c,
xvi_12.3b, xvi_13.3c, xvi_14.3d, xvi_15.4m, xvi_17.4p, xvi_16.4n, xvi_18.4r,
"xevious_cpu_gfx_8bits.bin" has to be used if your board has 8bits width SRAM
"xevious_cpu_gfx_16bits.bin" has to be used if your board has 16bits width SRAM (DE2-35)
*DO NOT REDISTRIBUTE ANY OF THESE FILES*
VHDL files are needed to compile and include roms into the project
The script make_xevious_proms.bat uses make_vhdl_prom and duplicate_byte executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
Source code of make_vhdl_prom.c and duplicate_byte.c is also delivered.
---------------------------------
Compiling for de2
---------------------------------
You can build the project with ROM image embeded in the sof file. DO NOT REDISTRIBUTE THESE FILES.
3 steps
- put the VHDL ROM files (.vhd) into the project directory
- build xevious_de2
- load DE2 SRAM with "xevious_cpu_gfx_16bits.bin" by using DE2 control panel software (see begining of this readme file)
- then program xevious_de2.sof
----------------------------
Big enough FPGA (~100Ko RAM)
(Already done for de10_lite)
----------------------------
You can easily mofidy make_xevious_prom.bat to produce xevious_cpu_gfx_8bits.vhld from xevious_cpu_gfx_8bits.bin.
*DO NOT REDISTRIBUTE ANY OF THESE FILES*
Remove SRAM external link.
Add and use this new entity in your own board to top level file as shown here after:
architecture struct of xevious_xxboardxx is
signal clock_18n : std_logic;
...
signal rom_bus_addr : std_logic_vector(16 downto 0);
signal rom_bus_do : std_logic_vector(7 downto 0);
...
begin
...
clock_18n <= not clock_18;
...
xevious : entity work.xevious
port map(
...
rom_bus_addr_o => rom_bus_addr,
rom_bus_do => rom_bus_do,
...
);
xevious_cpu_gfx_rom : entity work.xevious_cpu_gfx_8bits
port map(
clk => clock_18n,
addr => rom_bus_addr,
data => rom_bus_do
);
...
end struct;
*DO NOT REDISTRIBUTE FILES CONTAINING ROM DATA WHATEVER THE FORM*
------------------------
End of file
------------------------

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Arcade_MiST/Galaga Hardware/Xevious_MiST/Xevious_MiST.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 17:44:51 March 04, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "17:44:51 March 04, 2019"
# Revisions
PROJECT_REVISION = "Xevious_MiST"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:36:26 March 08, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# xevious_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_46 -to UART_TX
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name TOP_LEVEL_ENTITY xevious_mist
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# -------------------------
# start ENTITY(xevious_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(xevious_mist)
# -----------------------
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/rom.stp
set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/xevious_mist.sv
set_global_assignment -name VHDL_FILE rtl/xevious.vhd
set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/sound_machine.vhd
set_global_assignment -name VHDL_FILE rtl/mb88.vhd
set_global_assignment -name VHDL_FILE rtl/roms/terrain_2c.vhd
set_global_assignment -name VHDL_FILE rtl/roms/terrain_2b.vhd
set_global_assignment -name VHDL_FILE rtl/roms/terrain_2a.vhd
set_global_assignment -name VHDL_FILE rtl/roms/sp_palette_msb.vhd
set_global_assignment -name VHDL_FILE rtl/roms/sp_palette_lsb.vhd
set_global_assignment -name VHDL_FILE rtl/roms/sound_seq.vhd
set_global_assignment -name VHDL_FILE rtl/roms/sound_samples.vhd
set_global_assignment -name VHDL_FILE rtl/roms/red.vhd
set_global_assignment -name VHDL_FILE rtl/roms/green.vhd
set_global_assignment -name VHDL_FILE rtl/roms/cs54xx_prog.vhd
set_global_assignment -name VHDL_FILE rtl/roms/cs51xx_prog.vhd
set_global_assignment -name VHDL_FILE rtl/roms/cs50xx_prog.vhd
set_global_assignment -name VHDL_FILE rtl/roms/blue.vhd
set_global_assignment -name VHDL_FILE rtl/roms/bg_palette_msb.vhd
set_global_assignment -name VHDL_FILE rtl/roms/bg_palette_lsb.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name SIGNALTAP_FILE output_files/rom.stp
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Galaga Hardware/Xevious_MiST/Xevious_MiST.sdc Normal file
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#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
#
#************************************************************
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
# SDRAM delays
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_ram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_ram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
-- q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
-- rAddrReg <= addr;
---- qReg <= ram(to_integer(unsigned(addr)));
q <= ram(to_integer(unsigned(addr)));
end if;
end process;
--q <= ram(to_integer(unsigned(addr)));
end architecture;

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---------------------------------------------------------------------------------
-- Xevious video horizontal/vertical and sync generator by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.ALL;
entity gen_video is
port(
clk : in std_logic;
enable : in std_logic;
hcnt : out std_logic_vector(8 downto 0);
vcnt : out std_logic_vector(8 downto 0);
hsync : out std_logic;
vsync : out std_logic;
csync : out std_logic; -- composite sync for TV
blankn : out std_logic
);
end gen_video;
architecture struct of gen_video is
signal hclkReg : unsigned (1 DOWNTO 0);
signal hblank : std_logic;
signal vblank : std_logic;
signal hcntReg : unsigned (8 DOWNTO 0) := to_unsigned( 0,9);
signal vcntReg : unsigned (8 DOWNTO 0) := to_unsigned(15,9);
signal hsync0 : std_logic;
signal hsync1 : std_logic;
signal hsync2 : std_logic;
begin
hcnt <= std_logic_vector(hcntReg);
vcnt <= std_logic_vector(vcntReg);
hsync <= hsync0;
-- Compteur horizontal : 511-128+1=384 pixels (48 tiles)
-- 128 à 191 : 64 pixels debut de ligne (8 dont 2 dernières tiles affichées)
-- 192 à 447 : 256 pixels centre de ligne (32 tiles affichées)
-- 448 à 511 : 64 pixels fin de ligne (8 dont 2 premières tiles affichées)
-- Compteur vertical : 263-000+1=264 lignes (33 tiles)
-- 000 à 015 : 16 lignes debut de trame (2 tiles)
-- 016 à 239 : 224 lignes centrales (28 tiles affichées)
-- 240 à 263 : 24 lignes fin de trame (3 tiles
-- Synchro horizontale : hcnt=[495-511/128-140] (29 pixels)
-- Synchro verticale : vcnt=[260-263/000-003] ( 8 lignes)
process(clk)
begin
if rising_edge(clk) and enable = '1' then -- clk & ena at 6MHz : 1 pixel
if hcntReg = 511 then
hcntReg <= to_unsigned (128,9);
else
hcntReg <= hcntReg + 1;
end if;
if hcntReg = 511 then
if vcntReg = 263 then
vcntReg <= to_unsigned(0,9);
else
vcntReg <= vcntReg + 1;
end if;
end if;
if hcntReg = (495) then hsync0 <= '0'; -- 1
elsif hcntReg = (495+29-384) then hsync0 <= '1';
end if;
if hcntReg = (495) then hsync1 <= '0';
elsif hcntReg = (495+13) then hsync1 <= '1'; -- 11
elsif hcntReg = (495 +192-384) then hsync1 <= '0';
elsif hcntReg = (495+13+192-384) then hsync1 <= '1'; -- 11
end if;
if hcntReg = (495) then hsync2 <= '0';
elsif hcntReg = (495-28) then hsync2 <= '1';
end if;
if vcntReg = 252-1+2 then csync <= hsync1;
elsif vcntReg = 253-1+2 then csync <= hsync1;
elsif vcntReg = 254-1+2 then csync <= hsync1; -- and hsync2;
elsif vcntReg = 255-1+2 then csync <= hsync2; -- not(hsync1);
elsif vcntReg = 256-1+2 then csync <= hsync2; -- not(hsync1);
elsif vcntReg = 257-1+2 then csync <= hsync2; -- not(hsync1) or not(hsync2);
elsif vcntReg = 258-1+2 then csync <= hsync1;
elsif vcntReg = 259-1+2 then csync <= hsync1;
elsif vcntReg = 260-1+2 then csync <= hsync1;
else csync <= hsync0;
end if;
if vcntReg = 260 then vsync <= '0';
elsif vcntReg = 003 then vsync <= '1';
end if;
if hcntReg = (447+16+8+1) then hblank <= '1';
elsif hcntReg = (191-16+8+1) then hblank <= '0';
end if;
if vcntReg = (240+2) then vblank <= '1';
elsif vcntReg = (016+2) then vblank <= '0';
end if;
blankn <= not (hblank or vblank);
end if;
end process;
end architecture;

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---------------------------------------------------------------------------------
-- mb88 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
--
-- Version 0.3 -- 28/02/2017 --
-- fixed instruction JMP (0xC0..0xFF) let r_pa be incremented when r_pc = 0x3F
--
-- Version 0.2 -- 26/02/2017 --
-- corrected r_stf for tstR instruction (0x24)
-- corrected r_stf for tbit instruction (0x38-0x3B)
--
-- Version 0.1 -- 25/02/2017 --
-- outO instruction write to ol,oh depending on r_cf
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- Todo : Timer, Serial
-- Features :
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mb88 is
port(
clock : in std_logic;
ena : in std_logic;
reset_n : in std_logic;
r0_port_in : in std_logic_vector(3 downto 0);
r1_port_in : in std_logic_vector(3 downto 0);
r2_port_in : in std_logic_vector(3 downto 0);
r3_port_in : in std_logic_vector(3 downto 0);
r0_port_out : out std_logic_vector(3 downto 0);
r1_port_out : out std_logic_vector(3 downto 0);
r2_port_out : out std_logic_vector(3 downto 0);
r3_port_out : out std_logic_vector(3 downto 0);
k_port_in : in std_logic_vector(3 downto 0);
ol_port_out : out std_logic_vector(3 downto 0);
oh_port_out : out std_logic_vector(3 downto 0);
p_port_out : out std_logic_vector(3 downto 0);
stby_n : in std_logic;
tc_n : in std_logic;
irq_n : in std_logic;
sc_in_n : in std_logic;
si_n : in std_logic;
sc_out_n : out std_logic;
so_n : out std_logic;
to_n : out std_logic;
rom_addr : out std_logic_vector(10 downto 0);
rom_data : in std_logic_vector( 7 downto 0)
);
end mb88;
architecture struct of mb88 is
signal reset : std_logic;
signal clock_n : std_logic;
signal ram_addr : std_logic_vector(6 downto 0);
signal ram_we : std_logic;
signal ram_di : std_logic_vector(3 downto 0);
signal ram_do : std_logic_vector(3 downto 0);
signal r_pc : std_logic_vector(5 downto 0) := (others=>'0');
signal r_pa : std_logic_vector(4 downto 0) := (others=>'0');
signal r_si : std_logic_vector(1 downto 0) := (others=>'0');
signal r_a : std_logic_vector(3 downto 0) := (others=>'0');
signal r_x : std_logic_vector(3 downto 0) := (others=>'0');
signal r_y : std_logic_vector(3 downto 0) := (others=>'0');
signal r_stf : std_logic := '1';
signal r_zf : std_logic := '0';
signal r_cf : std_logic := '0';
signal r_vf : std_logic := '0';
signal r_sf : std_logic := '0';
signal r_nf : std_logic := '0';
signal r_pio : std_logic_vector(7 downto 0) := (others=>'0');
signal r_th : std_logic_vector(3 downto 0) := (others=>'0');
signal r_tl : std_logic_vector(3 downto 0) := (others=>'0');
signal r_tp : std_logic_vector(5 downto 0) := (others=>'0');
signal r_ctr : std_logic_vector(5 downto 0) := (others=>'0');
signal r_sb : std_logic_vector(3 downto 0) := (others=>'0');
signal r_sbcnt : std_logic_vector(3 downto 0) := (others=>'0');
signal interrupt_pending : std_logic := '0';
signal irq_n_r : std_logic := '0';
subtype stack_size is integer range 0 to 3;
type stack_def is array(stack_size) of std_logic_vector(15 downto 0);
signal stack : stack_def := (others=>(others=>'0'));
subtype ram_size is integer range 0 to 127;
type ram_def is array(ram_size) of std_logic_vector(3 downto 0);
signal ram : ram_def := (others=>(others=>'0'));
signal single_byte_op : std_logic := '1';
signal op_code : std_logic_vector(7 downto 0) := X"00";
signal a_p1 : std_logic_vector(3 downto 0);
signal a_p1_z : std_logic;
signal a_p1_c : std_logic;
signal a_m1 : std_logic_vector(3 downto 0);
signal a_m1_z : std_logic;
signal a_m1_c : std_logic;
signal y_p1 : std_logic_vector(3 downto 0);
signal y_p1_z : std_logic;
signal y_p1_c : std_logic;
signal y_m1 : std_logic_vector(3 downto 0);
signal y_m1_z : std_logic;
signal y_m1_c : std_logic;
signal m_p1 : std_logic_vector(3 downto 0);
signal m_p1_z : std_logic;
signal m_p1_c : std_logic;
signal m_m1 : std_logic_vector(3 downto 0);
signal m_m1_z : std_logic;
signal m_m1_c : std_logic;
signal adc : std_logic_vector(4 downto 0);
signal adc_z : std_logic;
signal adc_c : std_logic;
signal sbc : std_logic_vector(4 downto 0);
signal sbc_z : std_logic;
signal sbc_c : std_logic;
signal cma : std_logic_vector(4 downto 0);
signal cma_z : std_logic;
signal cma_c : std_logic;
signal a_pim : std_logic_vector(4 downto 0);
signal a_pim_z: std_logic;
signal a_pim_c: std_logic;
signal im_my : std_logic_vector(4 downto 0);
signal im_my_z: std_logic;
signal im_my_c: std_logic;
signal im_ma : std_logic_vector(4 downto 0);
signal im_ma_z: std_logic;
signal im_ma_c: std_logic;
signal a_and_m : std_logic_vector(3 downto 0);
signal a_and_m_z : std_logic;
signal a_or_m : std_logic_vector(3 downto 0);
signal a_or_m_z : std_logic;
signal a_xor_m : std_logic_vector(3 downto 0);
signal a_xor_m_z : std_logic;
signal nega : std_logic_vector(3 downto 0);
signal nega_z : std_logic;
signal rola : std_logic_vector(3 downto 0);
signal rola_z : std_logic;
signal rora : std_logic_vector(3 downto 0);
signal rora_z : std_logic;
signal do_da : std_logic;
signal daa : std_logic_vector(3 downto 0);
signal daa_z : std_logic;
signal daa_c : std_logic;
signal das : std_logic_vector(3 downto 0);
signal das_z : std_logic;
signal das_c : std_logic;
signal dca : std_logic_vector(3 downto 0);
signal dca_z : std_logic;
signal dca_c : std_logic;
signal x_z : std_logic;
signal y_z : std_logic;
signal tl_z : std_logic;
signal th_z : std_logic;
signal sb_z : std_logic;
signal k_port_in_z : std_logic;
signal r0_port_in_z : std_logic;
signal r1_port_in_z : std_logic;
signal r2_port_in_z : std_logic;
signal r3_port_in_z : std_logic;
signal sel_bit_y : std_logic_vector(3 downto 0);
signal m_set_bit : std_logic_vector(3 downto 0);
signal m_clr_bit : std_logic_vector(3 downto 0);
signal m_tst_bit : std_logic;
signal mem : std_logic_vector(3 downto 0);
signal mem_z : std_logic;
signal imm_x7_z : std_logic;
signal imm_xF_z : std_logic;
begin
clock_n <= not clock;
reset <= not reset_n;
rom_addr <= r_pa & r_pc;
ram_addr <= X"0" & rom_data(2 downto 0) when ((rom_data >= X"50") and (rom_data <= X"57")) else r_x(2 downto 0) & r_y;
ram_we <= '1' when(( (rom_data = X"1D") or (rom_data = X"1A") or
(rom_data = X"0A") or (rom_data = X"0B") or
(rom_data = X"2A") or
(rom_data = X"19") or (rom_data = X"09") or
((rom_data >= X"30") and (rom_data <= X"37") ) or
((rom_data >= X"50") and (rom_data <= X"57") )
) and (single_byte_op = '1')and ena = '1')
else '0';
with rom_data select
ram_di <= r_a when X"1D", r_a when X"1A",
r_a when X"0A", r_a when X"0B",
r_sb when X"2A",
m_m1 when X"19", m_p1 when X"09",
m_set_bit when X"30", m_clr_bit when X"34",
m_set_bit when X"31", m_clr_bit when X"35",
m_set_bit when X"32", m_clr_bit when X"36",
m_set_bit when X"33", m_clr_bit when X"37",
r_a when X"50", r_y when X"54",
r_a when X"51", r_y when X"55",
r_a when X"52", r_y when X"56",
r_a when X"53", r_y when X"57",
X"A" when others;
a_p1 <= r_a + X"1";
a_p1_z <= '1' when a_p1 = X"0" else '0';
a_p1_c <= '1' when a_p1 = X"0" else '0';
a_m1 <= r_a - X"1";
a_m1_z <= '1' when a_m1 = X"0" else '0';
a_m1_c <= '1' when a_m1 = X"F" else '0';
y_p1 <= r_y + X"1";
y_p1_z <= '1' when y_p1 = X"0" else '0';
y_p1_c <= '1' when y_p1 = X"0" else '0';
y_m1 <= r_y - X"1";
y_m1_z <= '1' when y_m1 = X"0" else '0';
y_m1_c <= '1' when y_m1 = X"F" else '0';
m_p1 <= ram_do + X"1";
--m_p1_z <= '1' when m_p1 = X"0" else '0';
--m_p1_c <= '1' when m_p1 = X"0" else '0';
m_m1 <= ram_do - X"1";
--m_m1_z <= '1' when m_m1 = X"0" else '0';
--m_m1_c <= '1' when m_m1 = X"F" else '0';
with rom_data(2 downto 0) select
m_set_bit <= ram_do or X"1" when "000",
ram_do or X"2" when "001",
ram_do or X"4" when "010",
ram_do or X"8" when others;
with rom_data(2 downto 0) select
m_clr_bit <= ram_do and not X"1" when "000",
ram_do and not X"2" when "001",
ram_do and not X"4" when "010",
ram_do and not X"8" when others;
m_tst_bit <= ram_do(to_integer(unsigned(rom_data(1 downto 0))));
rola <= r_a(2 downto 0) & r_cf;
rola_z <= '1' when rola = X"0" else '0';
rora <= r_cf & r_a(3 downto 1);
rora_z <= '1' when rora = X"0" else '0';
nega <= not(r_a) + X"1";
nega_z <= '1' when nega = X"0" else '0';
adc <= ('0'&ram_do) + ('0'&r_a) + ("0000"&r_cf);
adc_z <= '1' when adc(3 downto 0) = X"0" else '0';
adc_c <= '1' when adc(4) = '1' else '0';
sbc <= ('0'&ram_do) - ('0'&r_a) - ("0000"&r_cf);
sbc_z <= '1' when sbc(3 downto 0) = X"0" else '0';
sbc_c <= '1' when sbc(4) = '1' else '0';
cma <= ('0'&ram_do) - ('0'&r_a);
cma_z <= '1' when cma(3 downto 0) = X"0" else '0';
cma_c <= '1' when cma(4) = '1' else '0';
a_pim <= ('0'&rom_data(3 downto 0)) + ('0'&r_a);
a_pim_z <= '1' when a_pim(3 downto 0) = X"0" else '0';
a_pim_c <= '1' when a_pim(4) = '1' else '0';
im_my <= ('0'&rom_data(3 downto 0)) - ('0'&r_y);
im_my_z <= '1' when im_my(3 downto 0) = X"0" else '0';
im_my_c <= '1' when im_my(4) = '1' else '0';
im_ma <= ('0'&rom_data(3 downto 0)) - ('0'&r_a);
im_ma_z <= '1' when im_ma(3 downto 0) = X"0" else '0';
im_ma_c <= '1' when im_ma(4) = '1' else '0';
a_and_m <= r_a and ram_do;
a_and_m_z <= '1' when a_and_m = X"0" else '0';
a_or_m <= r_a or ram_do;
a_or_m_z <= '1' when a_or_m = X"0" else '0';
a_xor_m <= r_a xor ram_do;
a_xor_m_z <= '1' when a_xor_m = X"0" else '0';
do_da <= '1' when (r_a > X"9") or (r_cf = '1') else '0';
daa <= r_a + X"6";
daa_z <= '1' when daa = X"0" else '0';
daa_c <= '1' when r_a > X"9" else '0';
das <= r_a + X"A";
das_z <= '1' when das = X"0" else '0';
das_c <= '1' when r_a > X"5" else '0';
dca <= r_a + X"F";
dca_z <= '1' when dca = X"0" else '0';
dca_c <= '1' when dca = X"F" else '0';
x_z <= '1' when r_x = X"0" else '0';
y_z <= '1' when r_y = X"0" else '0';
tl_z <= '1' when r_tl = X"0" else '0';
th_z <= '1' when r_th = X"0" else '0';
sb_z <= '1' when r_sb = X"0" else '0';
k_port_in_z <= '1' when k_port_in = X"0" else '0';
r0_port_in_z <= '1' when r0_port_in = X"0" else '0';
r1_port_in_z <= '1' when r1_port_in = X"0" else '0';
r2_port_in_z <= '1' when r2_port_in = X"0" else '0';
r3_port_in_z <= '1' when r3_port_in = X"0" else '0';
with r_y(1 downto 0) select
sel_bit_y <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
imm_x7_z <= '1' when rom_data(2 downto 0) = "000" else '0';
imm_xF_z <= '1' when rom_data(3 downto 0) = "0000" else '0';
process (clock_n) -- register data before memory value update at middle cycle
begin
if rising_edge(clock_n) then
mem <= ram_do;
if ram_do = X"0" then mem_z <= '1'; else mem_z <= '0'; end if;
if m_p1 = X"0" then m_p1_z <= '1'; else m_p1_z <= '0'; end if;
if m_p1 = X"0" then m_p1_c <= '1'; else m_p1_c <= '0'; end if;
if m_m1 = X"0" then m_m1_z <= '1'; else m_m1_z <= '0'; end if;
if m_m1 = X"F" then m_m1_c <= '1'; else m_m1_c <= '0'; end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
-- mem <= ram_do;
-- if ram_do = X"0" then mem_z <= '1'; else mem_z <= '0'; end if;
irq_n_r <= irq_n;
r_nf <= not irq_n;
if irq_n = '0' and irq_n_r = '1' and r_pio(2) = '1' then
interrupt_pending <= '1';
end if;
if reset = '1' then
r_pc <= (others=>'0');
r_pa <= (others=>'0');
r_si <= (others=>'0');
r_a <= (others=>'0');
r_x <= (others=>'0');
r_y <= (others=>'0');
r_stf <= '1';
r_zf <= '0';
r_cf <= '0';
r_vf <= '0';
r_sf <= '0';
r_nf <= '0';
r_pio <= (others=>'0');
r_th <= (others=>'0');
r_tl <= (others=>'0');
r_tp <= (others=>'0');
r_ctr <= (others=>'0');
r_sb <= (others=>'0');
r_sbcnt <= (others=>'0');
interrupt_pending <= '0';
stack <= (others=>(others=>'0'));
single_byte_op <= '1';
else
if ena = '1' then
op_code <= rom_data;
single_byte_op <= '1';
if r_pc = "111111" then
r_pc <= "000000";
r_pa <= r_pa + "0001";
else
r_pc <= r_pc + "000001";
end if;
if single_byte_op = '1' then
if interrupt_pending = '1' then
stack(to_integer(unsigned(r_si)))(13 downto 0) <= (r_cf & r_zf & r_stf & r_pa & r_pc);
r_pc <= "000010";
r_pa <= "00000";
r_si <= r_si + "01";
interrupt_pending <= '0';
else -- no irq
case rom_data is
when X"00" => r_stf <='1'; -- nop
when X"01" => r_stf <='1'; -- outO portO <- A //!PLA todo
if r_cf = '0' then ol_port_out <= r_a; end if;
if r_cf = '1' then oh_port_out <= r_a; end if;
when X"02" => r_stf <='1'; p_port_out <= r_a; -- outP portP <- A
when X"03" => r_stf <='1'; -- outR(Y) portR(Y) <- A
if r_y = X"0" then r0_port_out <= r_a; end if;
if r_y = X"1" then r1_port_out <= r_a; end if;
if r_y = X"2" then r2_port_out <= r_a; end if;
if r_y = X"3" then r3_port_out <= r_a; end if;
when X"04" => r_stf <='1'; r_y <= r_a; -- tay Y <- A
when X"05" => r_stf <='1'; r_th <= r_a; -- tath TH <- A
when X"06" => r_stf <='1'; r_tl <= r_a; -- tatl TL <- A
when X"07" => r_stf <='1'; r_sb <= r_a; -- tas SB <- A
when X"08" => r_stf <= not y_p1_c; r_y <= y_p1; r_zf <= y_p1_z; -- icy Y <- Y+1
when X"09" => r_stf <= not m_p1_c; r_zf <= m_p1_z; -- icm M[X,Y] <- M[X,Y]+1
when X"0A" => r_stf <= not y_p1_c; r_y <= y_p1; r_zf <= y_p1_z; -- stic M[X,Y] <- A; Y <- Y+1
when X"0B" => r_stf <='1'; r_a <= mem; r_zf <= mem_z; -- x A <- M[X,Y]; M[X,Y] <- A
when X"0C" => r_stf <= not r_a(3); r_a <= rola; r_zf <= rola_z; r_cf <= r_a(3); -- rol
when X"0D" => r_stf <='1'; r_a <= mem; r_zf <= mem_z; -- l A <- M[X,Y];
when X"0E" => r_stf <= not adc_c; r_a <= adc(3 downto 0); r_zf <= adc_z; r_cf <= adc_c; -- adc A <- M[X,Y]+A+CF;
when X"0F" => r_stf <= not a_and_m_z; r_a <= a_and_m; r_zf <= a_and_m_z; -- and A <- A & M[X,Y];
when X"10" =>
if do_da = '1' then r_stf <= not daa_c; r_a <= daa; r_cf <= daa_c; -- daa A <- A + 6 ; si A>9 or CF
else r_stf <= '1'; r_cf <= '0'; end if;
when X"11" =>
if do_da = '1' then r_stf <= not das_c; r_a <= das; r_cf <= das_c; -- das A <- A + 10; si A>9 or CF
else r_stf <= '1'; r_cf <= '0'; end if;
when X"12" => r_stf <='1'; r_a <= k_port_in; r_zf <= k_port_in_z; -- inK A <- K
when X"13" => r_stf <='1'; -- inR A <- R(Y)
if r_y = X"0" then r_a <= r0_port_in; r_zf <= r0_port_in_z; end if;
if r_y = X"1" then r_a <= r1_port_in; r_zf <= r1_port_in_z; end if;
if r_y = X"2" then r_a <= r2_port_in; r_zf <= r2_port_in_z; end if;
if r_y = X"3" then r_a <= r3_port_in; r_zf <= r3_port_in_z; end if;
when X"14" => r_stf <='1'; r_a <= r_y; r_zf <= y_z; -- tya A <- Y
when X"15" => r_stf <='1'; r_a <= r_th; r_zf <= th_z; -- ttha A <- TH
when X"16" => r_stf <='1'; r_a <= r_tl; r_zf <= tl_z; -- ttla A <- TH
when X"17" => r_stf <='1'; r_a <= r_sb; r_zf <= sb_z; -- tsa A <- SB
when X"18" => r_stf <= not y_m1_c; r_y <= y_m1; -- dcy Y <- Y-1
when X"19" => r_stf <= not m_m1_c; r_zf <= m_m1_z; -- dcm M[X,Y] <- M[X,Y]-1
when X"1A" => r_stf <= not y_m1_c; r_y <= y_m1; r_zf <= y_m1_z; -- stdc M[X,Y] <- A; Y <- Y-1
when X"1B" => r_stf <='1'; r_a <= r_x; r_x <= r_a; r_zf <= x_z; -- xx A <- X, X <- A
when X"1C" => r_stf <= not r_a(0); r_a <= rora; r_zf <= rora_z; r_cf <= r_a(0); -- ror
when X"1D" => r_stf <='1'; -- st M[X,Y] <- A
when X"1E" => r_stf <= not sbc_c; r_a <= sbc(3 downto 0); r_zf <= sbc_z; r_cf <= sbc_c; -- sbc A <- M[X,Y]-A-CF;
when X"1F" => r_stf <= not a_or_m_z; r_a <= a_or_m; r_zf <= a_or_m_z; -- or A <- A | M[X,Y];
when X"20" => r_stf <='1'; -- setR
if r_y(3 downto 2) = "00" then r0_port_out <= (r0_port_in or sel_bit_y ); end if;
if r_y(3 downto 2) = "01" then r1_port_out <= (r1_port_in or sel_bit_y ); end if;
if r_y(3 downto 2) = "10" then r2_port_out <= (r2_port_in or sel_bit_y ); end if;
if r_y(3 downto 2) = "11" then r3_port_out <= (r3_port_in or sel_bit_y ); end if;
when X"21" => r_stf <='1'; r_cf <= '1'; -- setCF
when X"22" => r_stf <='1'; -- clrR
if r_y(3 downto 2) = "00" then r0_port_out <= (r0_port_in and not sel_bit_y ); end if;
if r_y(3 downto 2) = "01" then r1_port_out <= (r1_port_in and not sel_bit_y ); end if;
if r_y(3 downto 2) = "10" then r2_port_out <= (r2_port_in and not sel_bit_y ); end if;
if r_y(3 downto 2) = "11" then r3_port_out <= (r3_port_in and not sel_bit_y ); end if;
when X"23" => r_stf <='1'; r_cf <= '0'; -- clrCF
when X"24" => -- tstR
if r_y(3 downto 2) = "00" then r_stf <= not r0_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if;
if r_y(3 downto 2) = "01" then r_stf <= not r1_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if;
if r_y(3 downto 2) = "10" then r_stf <= not r2_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if;
if r_y(3 downto 2) = "11" then r_stf <= not r3_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if;
when X"25" => r_stf <= not r_nf; -- tsti (interrupt)
when X"26" => r_stf <= not r_vf; r_vf <= '0'; -- tstv (timer overflow)
when X"27" => r_stf <= not r_sf; r_sf <= '0'; -- tsts (serial)
when X"28" => r_stf <= not r_cf; -- tstc (CF)
when X"29" => r_stf <= not r_zf; -- tstz (ZF)
when X"2A" => r_stf <= '1'; r_zf <= sb_z; -- sts M[X,Y] <- SB
when X"2B" => r_stf <= '1'; r_sb <= mem; r_zf <= mem_z; -- ls SB <- M[X,Y]
when X"2C" => r_stf <= '1'; -- rts
r_pa <= stack(to_integer(unsigned(r_si-"01")))(10 downto 6);
r_pc <= stack(to_integer(unsigned(r_si-"01")))( 5 downto 0);
r_si <= r_si - "01";
when X"2D" => r_stf <= not nega_z; r_a <= nega; -- negA A <- -A
when X"2E" => r_stf <= not cma_z; r_zf <= cma_z; r_cf <= cma_c; -- c M[X,Y]-A ?=
when X"2F" => r_stf <= not a_xor_m_z; r_a <= a_xor_m; r_zf <= a_xor_m_z;-- eor A <- A xor M[X,Y];
when X"30" | X"31" | X"32" | X"33" => r_stf <='1'; -- sbit M[X,Y](op&3) <- 1
when X"34" | X"35" | X"36" | X"37" => r_stf <='1'; -- rbit M[X,Y](op&3) <- 0
when X"38" | X"39" | X"3A" | X"3B" => r_stf <= not m_tst_bit; -- tbit M[X,Y](op&3) == 1
when X"3C" => -- rti
r_pa <= stack(to_integer(unsigned(r_si-"01")))(10 downto 6);
r_pc <= stack(to_integer(unsigned(r_si-"01")))( 5 downto 0);
r_stf <= stack(to_integer(unsigned(r_si-"01")))(11);
r_zf <= stack(to_integer(unsigned(r_si-"01")))(12);
r_cf <= stack(to_integer(unsigned(r_si-"01")))(13);
r_si <= r_si - "01";
when X"3D" => single_byte_op <= '0'; -- jpa
when X"3E" => single_byte_op <= '0'; -- en
when X"3F" => single_byte_op <= '0'; -- dis
when X"40" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"1"); -- setd RO(op&3) <- 1
when X"41" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"2"); -- setd RO(op&3) <- 1
when X"42" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"4"); -- setd RO(op&3) <- 1
when X"43" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"8"); -- setd RO(op&3) <- 1
when X"44" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"1"); -- setd RO(op&3) <- 0
when X"45" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"2"); -- setd RO(op&3) <- 0
when X"46" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"4"); -- setd RO(op&3) <- 0
when X"47" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"8"); -- setd RO(op&3) <- 0
when X"48" | X"49" | X"4A" | X"4B" => -- tstd R2(op&3) ?=
r_stf <= not r2_port_in(to_integer(unsigned(rom_data(1 downto 0))));
when X"4C" | X"4D" | X"4E" | X"4F" => -- tba A(op&3) ?=
r_stf <= not r_a(to_integer(unsigned(rom_data(1 downto 0))));
when X"50" | X"51" | X"52" | X"53" => -- xd A <-> M[0,op&3]
r_stf <= '1'; r_a <= mem; r_zf <= mem_z;
when X"54" | X"55" | X"56" | X"57" => -- xyd Y <-> M[0,op&3]
r_stf <= '1'; r_y <= mem; r_zf <= mem_z;
when X"58" | X"59" | X"5A" | X"5B" | X"5C" | X"5D" | X"5E" | X"5F" => -- lxi imm (op&7)
r_stf <='1'; r_x <= '0' & rom_data(2 downto 0); r_zf <= imm_x7_z;
when X"60" | X"61" | X"62" | X"63" | X"64" | X"65" | X"66" | X"67" => -- call addr
single_byte_op <= '0';
when X"68" | X"69" | X"6A" | X"6B" | X"6C" | X"6D" | X"6E" | X"6F" => -- jpl addr
single_byte_op <= '0';
when X"70" | X"71" | X"72" | X"73" | X"74" | X"75" | X"76" | X"77" |
X"78" | X"79" | X"7A" | X"7B" | X"7C" | X"7D" | X"7E" | X"7F" => -- ai A <- A+imm (op&F)
r_stf <= not a_pim_c; r_a <= a_pim(3 downto 0); r_zf <= a_pim_z; r_cf <= a_pim_c;
when X"80" | X"81" | X"82" | X"83" | X"84" | X"85" | X"86" | X"87" |
X"88" | X"89" | X"8A" | X"8B" | X"8C" | X"8D" | X"8E" | X"8F" => -- lyi Y <- imm (op&F)
r_stf <='1'; r_y <= rom_data(3 downto 0); r_zf <= imm_xF_z;
when X"90" | X"91" | X"92" | X"93" | X"94" | X"95" | X"96" | X"97" |
X"98" | X"99" | X"9A" | X"9B" | X"9C" | X"9D" | X"9E" | X"9F" => -- li A <- imm (op&F)
r_stf <='1'; r_a <= rom_data(3 downto 0); r_zf <= imm_xF_z;
when X"A0" | X"A1" | X"A2" | X"A3" | X"A4" | X"A5" | X"A6" | X"A7" |
X"A8" | X"A9" | X"AA" | X"AB" | X"AC" | X"AD" | X"AE" | X"AF" => -- cyi imm - Y ?=
r_stf <= not im_my_z; r_zf <= im_my_z; r_cf <= im_my_c;
when X"B0" | X"B1" | X"B2" | X"B3" | X"B4" | X"B5" | X"B6" | X"B7" |
X"B8" | X"B9" | X"BA" | X"BB" | X"BC" | X"BD" | X"BE" | X"BF" => -- ci imm - A ?=
r_stf <= not im_ma_z; r_zf <= im_ma_z; r_cf <= im_ma_c;
when others => r_stf <='1'; -- jmp addr if ST (op_code C0..FF)
if r_stf = '1' then r_pc <= rom_data(5 downto 0); end if; -- (let r_pa be incremented when r_pc = 0x3F)
end case;
end if ;
else -- 2 bytes op_code, rom_data = 2nd byte
case op_code is
when X"3D" => r_stf <='1'; r_pa <= rom_data(4 downto 0); r_pc <= r_a & "00"; -- jpa PA <- data&0x1f; PC <- A*4
when X"3E" => r_stf <='1'; r_pio <= r_pio or rom_data; -- en PIO <- PIO or imm data
when X"3F" => r_stf <='1'; r_pio <= r_pio and not rom_data; -- dis PIO <- PIO and not imm data
when X"60" | X"61" | X"62" | X"63" | X"64" | X"65" | X"66" | X"67" => -- call addr if ST
r_stf <= '1';
if r_stf = '1' then
stack(to_integer(unsigned(r_si)))(10 downto 0) <= (r_pa & r_pc) + '1';
r_pc <= rom_data(5 downto 0);
r_pa <= op_code(2 downto 0) & rom_data(7 downto 6);
r_si <= r_si + "01";
end if;
when X"68" | X"69" | X"6A" | X"6B" | X"6C" | X"6D" | X"6E" | X"6F" => -- jpl if ST
r_stf <= '1';
if r_stf = '1' then
r_pc <= rom_data(5 downto 0);
r_pa <= op_code(2 downto 0) & rom_data(7 downto 6);
end if;
when others => r_stf <='1';
end case;
end if;
end if;
end if;
end if;
end process;
-- RAM
process(clock_n)
begin
if rising_edge(clock_n) then
if ram_we = '1' then
ram(to_integer(unsigned(ram_addr))) <= ram_di;
end if;
end if;
end process;
ram_do <= ram(to_integer(unsigned(ram_addr)));
end struct;

337
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/pll.v Normal file
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@ -0,0 +1,337 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 3,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 8,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "72.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "72.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

54
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/bg_palette_lsb.vhd Normal file
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@ -0,0 +1,54 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity bg_palette_lsb is
port (
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of bg_palette_lsb is
type rom is array(0 to 511) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"0A",X"0B",X"0D",X"0E",X"0C",X"09",X"06",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"0C",X"00",X"0B",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0B",X"0A",X"0A",
X"0A",X"08",X"09",X"06",X"00",X"00",X"00",X"00",X"0A",X"02",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"0A",X"08",X"09",X"0B",X"06",X"09",X"05",X"07",X"0A",X"00",X"05",X"09",X"06",X"02",X"0C",X"00",
X"05",X"0D",X"0C",X"00",X"06",X"08",X"09",X"0B",X"00",X"0D",X"03",X"0F",X"09",X"09",X"0A",X"0B",
X"0C",X"0A",X"0B",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"08",X"0B",X"0A",
X"0C",X"0D",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"02",X"00",
X"00",X"0D",X"02",X"0C",X"0C",X"0D",X"02",X"00",X"00",X"0D",X"03",X"0F",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"0F",X"0D",X"01",X"04",X"00",X"00",X"09",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"0A",X"00",X"04",X"08",X"06",X"0C",X"05",X"05",X"00",X"00",X"05",X"00",X"06",X"09",X"04",X"00",
X"00",X"0D",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"03",X"00",
X"00",X"0D",X"03",X"0C",X"0C",X"0D",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

54
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/bg_palette_msb.vhd Normal file
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@ -0,0 +1,54 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity bg_palette_msb is
port (
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of bg_palette_msb is
type rom is array(0 to 511) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",
X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"01",X"02",X"02",X"02",X"02",X"02",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"01",X"00",X"00",
X"00",X"01",X"00",X"00",X"00",X"01",X"01",X"01",X"00",X"03",X"00",X"00",X"01",X"01",X"01",X"01",
X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"01",X"01",X"00",
X"00",X"01",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"02",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"02",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",
X"00",X"03",X"00",X"03",X"03",X"03",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"02",X"01",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",
X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",
X"00",X"03",X"00",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/blue.vhd Normal file
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@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity blue is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of blue is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"06",X"0F",X"0C",X"02",X"0A",X"0F",X"0F",X"00",X"0C",X"02",X"00",X"04",X"02",X"02",X"05",
X"03",X"03",X"09",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"01",X"0C",X"07",X"02",X"02",
X"04",X"02",X"00",X"00",X"07",X"08",X"00",X"07",X"0B",X"0C",X"06",X"08",X"0C",X"0A",X"00",X"00",
X"06",X"0B",X"00",X"00",X"06",X"04",X"00",X"00",X"00",X"0A",X"00",X"00",X"0F",X"0F",X"0E",X"02",
X"00",X"00",X"00",X"00",X"04",X"0F",X"0F",X"00",X"00",X"00",X"06",X"06",X"08",X"0A",X"09",X"08",
X"08",X"02",X"0B",X"00",X"02",X"0F",X"04",X"0F",X"00",X"00",X"00",X"0A",X"06",X"04",X"04",X"0C",
X"06",X"04",X"02",X"03",X"00",X"0C",X"02",X"04",X"08",X"0A",X"04",X"02",X"00",X"0F",X"0F",X"00",
X"00",X"00",X"00",X"00",X"08",X"04",X"08",X"04",X"08",X"04",X"08",X"04",X"0C",X"0A",X"06",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/cs50xx_prog.vhd Normal file
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@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity cs50xx_prog is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of cs50xx_prog is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"68",X"40",X"50",X"1B",X"51",X"48",X"F0",X"55",X"5B",X"80",X"0D",X"04",X"5A",X"98",X"0F",X"0B",
X"3F",X"04",X"D4",X"0D",X"21",X"01",X"08",X"0D",X"23",X"01",X"08",X"25",X"DE",X"DB",X"25",X"DE",
X"14",X"0C",X"B0",X"D3",X"9F",X"21",X"01",X"23",X"01",X"55",X"51",X"1B",X"50",X"3E",X"04",X"3C",
X"59",X"54",X"12",X"0A",X"55",X"80",X"13",X"55",X"0A",X"54",X"51",X"1B",X"50",X"3E",X"04",X"3C",
X"58",X"80",X"90",X"1B",X"0A",X"C4",X"1B",X"71",X"B8",X"C3",X"3E",X"04",X"57",X"59",X"90",X"0B",
X"08",X"3D",X"02",X"18",X"14",X"57",X"58",X"84",X"2E",X"DB",X"CC",X"72",X"04",X"57",X"90",X"59",
X"0B",X"B0",X"E4",X"CC",X"08",X"3D",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"68",X"53",X"00",X"00",X"68",X"C0",X"00",X"00",X"69",X"02",X"00",X"00",X"69",X"0C",X"00",X"00",
X"69",X"16",X"00",X"00",X"69",X"20",X"00",X"00",X"0D",X"69",X"30",X"00",X"0D",X"69",X"39",X"00",
X"0D",X"69",X"3E",X"00",X"0D",X"69",X"4F",X"00",X"0D",X"69",X"60",X"00",X"0D",X"69",X"71",X"00",
X"0D",X"69",X"82",X"00",X"0D",X"69",X"93",X"00",X"0D",X"69",X"A4",X"00",X"0D",X"69",X"B5",X"00",
X"08",X"57",X"5A",X"80",X"90",X"0A",X"C5",X"5D",X"0A",X"C8",X"5E",X"0A",X"CB",X"5F",X"0A",X"CE",
X"95",X"52",X"81",X"56",X"5B",X"81",X"64",X"E2",X"95",X"52",X"89",X"56",X"5B",X"81",X"64",X"E2",
X"96",X"52",X"81",X"56",X"5B",X"89",X"64",X"E2",X"96",X"52",X"89",X"56",X"5B",X"89",X"64",X"E2",
X"97",X"52",X"81",X"56",X"58",X"89",X"64",X"E2",X"97",X"52",X"89",X"56",X"58",X"89",X"64",X"E2",
X"68",X"4C",X"93",X"52",X"56",X"81",X"56",X"65",X"30",X"57",X"68",X"4C",X"93",X"52",X"56",X"89",
X"56",X"65",X"30",X"57",X"68",X"4C",X"90",X"52",X"56",X"89",X"56",X"65",X"30",X"57",X"68",X"4C",
X"94",X"52",X"56",X"81",X"56",X"65",X"30",X"57",X"89",X"56",X"81",X"5C",X"64",X"E2",X"68",X"4C",
X"08",X"57",X"5B",X"80",X"1D",X"88",X"1D",X"6C",X"3F",X"08",X"57",X"53",X"68",X"4C",X"08",X"57",
X"5B",X"80",X"52",X"0D",X"77",X"04",X"52",X"5A",X"53",X"B0",X"69",X"C6",X"53",X"3D",X"08",X"08",
X"57",X"5B",X"80",X"52",X"0D",X"76",X"04",X"52",X"5A",X"53",X"B0",X"69",X"C6",X"53",X"3D",X"08",
X"08",X"57",X"5B",X"80",X"52",X"0D",X"75",X"04",X"52",X"5A",X"53",X"B0",X"69",X"C6",X"53",X"3D",
X"08",X"08",X"57",X"5B",X"80",X"52",X"0D",X"77",X"04",X"52",X"5A",X"53",X"B0",X"69",X"C9",X"53",
X"3D",X"09",X"08",X"57",X"5B",X"80",X"52",X"0D",X"76",X"04",X"52",X"5A",X"53",X"B0",X"69",X"C9",
X"53",X"3D",X"09",X"08",X"57",X"5B",X"80",X"52",X"0D",X"75",X"04",X"52",X"5A",X"53",X"B0",X"69",
X"C9",X"53",X"3D",X"09",X"08",X"57",X"5B",X"80",X"52",X"0D",X"77",X"04",X"52",X"5A",X"53",X"B0",
X"69",X"CC",X"53",X"3D",X"0A",X"08",X"57",X"5B",X"80",X"52",X"0D",X"76",X"04",X"52",X"5A",X"53",
X"B0",X"69",X"CC",X"53",X"3D",X"0A",X"53",X"3D",X"0D",X"53",X"3D",X"0E",X"53",X"3D",X"0F",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"95",X"6A",X"EC",X"00",X"91",X"6A",X"EB",X"00",X"91",X"6A",X"D2",X"00",X"92",X"6A",X"EB",X"00",
X"92",X"6A",X"D2",X"00",X"93",X"6A",X"EB",X"00",X"94",X"6A",X"EB",X"00",X"95",X"6A",X"EB",X"00",
X"96",X"6A",X"EB",X"00",X"97",X"6A",X"EB",X"00",X"98",X"6A",X"EB",X"00",X"99",X"6A",X"EB",X"00",
X"91",X"18",X"6A",X"EB",X"92",X"18",X"6A",X"EB",X"93",X"18",X"6A",X"EB",X"95",X"18",X"6A",X"EB",
X"91",X"6A",X"EB",X"00",X"92",X"6A",X"EB",X"00",X"93",X"6A",X"EB",X"00",X"94",X"6A",X"EB",X"00",
X"95",X"6A",X"EB",X"00",X"96",X"6A",X"EB",X"00",X"98",X"6A",X"EB",X"00",X"91",X"18",X"6A",X"EB",
X"91",X"18",X"6A",X"C6",X"91",X"18",X"6A",X"CC",X"91",X"18",X"6A",X"D8",X"91",X"18",X"6A",X"E4",
X"92",X"18",X"6A",X"EB",X"94",X"18",X"6A",X"EB",X"96",X"18",X"6A",X"EB",X"91",X"18",X"6A",X"EA",
X"91",X"6A",X"D2",X"00",X"93",X"6A",X"EB",X"00",X"94",X"6A",X"D2",X"00",X"96",X"6A",X"EB",X"00",
X"97",X"6A",X"D2",X"00",X"99",X"6A",X"EB",X"00",X"91",X"18",X"6A",X"C6",X"91",X"18",X"6A",X"D2",
X"91",X"18",X"6A",X"E4",X"92",X"18",X"6A",X"C0",X"92",X"18",X"6A",X"CC",X"92",X"18",X"6A",X"DE",
X"93",X"18",X"6A",X"EB",X"96",X"18",X"6A",X"EB",X"99",X"18",X"6A",X"EB",X"91",X"18",X"18",X"D2",
X"0B",X"71",X"10",X"0B",X"18",X"ED",X"0B",X"72",X"10",X"0B",X"18",X"ED",X"0B",X"74",X"10",X"0B",
X"18",X"ED",X"0B",X"75",X"10",X"0B",X"18",X"ED",X"0B",X"76",X"10",X"0B",X"18",X"ED",X"0B",X"77",
X"10",X"0B",X"18",X"ED",X"0B",X"78",X"10",X"0B",X"18",X"ED",X"18",X"18",X"23",X"0E",X"F2",X"10",
X"1A",X"F6",X"10",X"6B",X"0B",X"1A",X"0D",X"71",X"10",X"6B",X"0B",X"1A",X"14",X"23",X"0C",X"B0",
X"6A",X"F6",X"08",X"99",X"0A",X"0A",X"0A",X"0A",X"0A",X"0A",X"95",X"1D",X"6C",X"3F",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"95",X"6C",X"24",X"00",X"91",X"6C",X"23",X"00",X"91",X"6C",X"0C",X"00",X"92",X"6C",X"23",X"00",
X"92",X"6C",X"0C",X"00",X"93",X"6C",X"23",X"00",X"94",X"6C",X"23",X"00",X"95",X"6C",X"23",X"00",
X"96",X"6C",X"23",X"00",X"97",X"6C",X"23",X"00",X"98",X"6C",X"23",X"00",X"99",X"6C",X"23",X"00",
X"91",X"18",X"6C",X"23",X"92",X"18",X"6C",X"23",X"93",X"18",X"6C",X"23",X"95",X"18",X"6C",X"23",
X"91",X"6C",X"23",X"00",X"92",X"6C",X"23",X"00",X"93",X"6C",X"23",X"00",X"94",X"6C",X"23",X"00",
X"95",X"6C",X"23",X"00",X"96",X"6C",X"23",X"00",X"98",X"6C",X"23",X"00",X"91",X"18",X"6C",X"23",
X"91",X"18",X"6C",X"04",X"91",X"18",X"6C",X"08",X"91",X"18",X"6C",X"10",X"91",X"18",X"6C",X"18",
X"92",X"18",X"6C",X"23",X"94",X"18",X"6C",X"23",X"96",X"18",X"6C",X"23",X"91",X"18",X"6C",X"22",
X"91",X"6C",X"0C",X"00",X"93",X"6C",X"23",X"00",X"94",X"6C",X"0C",X"00",X"96",X"6C",X"23",X"00",
X"97",X"6C",X"0C",X"00",X"99",X"6C",X"23",X"00",X"91",X"18",X"6C",X"04",X"91",X"18",X"6C",X"0C",
X"91",X"18",X"6C",X"18",X"92",X"18",X"6C",X"00",X"92",X"18",X"6C",X"08",X"92",X"18",X"6C",X"14",
X"93",X"18",X"6C",X"23",X"96",X"18",X"6C",X"23",X"99",X"18",X"6C",X"23",X"91",X"18",X"18",X"CC",
X"0B",X"7F",X"DD",X"DB",X"0B",X"7E",X"DD",X"DB",X"0B",X"7C",X"DD",X"DB",X"0B",X"7B",X"DD",X"DB",
X"0B",X"7A",X"DD",X"DB",X"0B",X"79",X"DD",X"DB",X"0B",X"78",X"DD",X"23",X"DE",X"21",X"11",X"0B",
X"18",X"E5",X"18",X"18",X"23",X"1E",X"11",X"FC",X"1A",X"23",X"91",X"1E",X"11",X"FC",X"1A",X"14",
X"23",X"0C",X"B0",X"E9",X"08",X"90",X"0A",X"0A",X"0A",X"0A",X"0A",X"0A",X"1D",X"6C",X"3F",X"94",
X"52",X"5B",X"80",X"0D",X"04",X"56",X"04",X"08",X"5A",X"64",X"CD",X"5A",X"80",X"52",X"90",X"1D",
X"88",X"1D",X"52",X"B0",X"6C",X"6A",X"56",X"33",X"94",X"52",X"08",X"94",X"52",X"56",X"81",X"56",
X"64",X"E2",X"5C",X"94",X"52",X"89",X"56",X"81",X"64",X"E2",X"95",X"52",X"5B",X"80",X"0D",X"04",
X"56",X"04",X"5D",X"0D",X"B0",X"6C",X"8B",X"08",X"5A",X"64",X"CD",X"B0",X"6C",X"8B",X"5A",X"56",
X"32",X"95",X"52",X"14",X"77",X"04",X"56",X"5B",X"87",X"65",X"85",X"96",X"52",X"5B",X"80",X"0D",
X"04",X"56",X"04",X"5E",X"0D",X"B0",X"EA",X"08",X"5A",X"64",X"CD",X"B0",X"EA",X"5A",X"56",X"31",
X"96",X"52",X"14",X"77",X"04",X"56",X"5B",X"8F",X"65",X"85",X"97",X"52",X"5B",X"80",X"0D",X"04",
X"56",X"04",X"5F",X"0D",X"B0",X"68",X"4C",X"08",X"5A",X"64",X"CD",X"B0",X"68",X"4C",X"5A",X"56",
X"30",X"97",X"52",X"14",X"77",X"04",X"56",X"58",X"8F",X"65",X"85",X"68",X"4C",X"0D",X"1B",X"52",
X"1B",X"2E",X"DC",X"1B",X"52",X"1B",X"08",X"14",X"0C",X"B0",X"CD",X"2C",X"90",X"28",X"E0",X"2C",
X"91",X"2C",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"08",X"0D",X"1B",X"52",
X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"08",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",
X"56",X"1B",X"08",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"08",X"0D",X"1B",
X"52",X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"08",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",
X"52",X"56",X"1B",X"08",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"08",X"2C",
X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"90",X"0A",X"0D",X"1B",X"52",X"56",
X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"90",X"0A",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",
X"56",X"1B",X"90",X"0A",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"90",X"0A",
X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"90",X"0A",X"0D",X"1B",X"52",X"56",
X"1B",X"0A",X"1B",X"52",X"56",X"1B",X"90",X"0A",X"0D",X"1B",X"52",X"56",X"1B",X"0A",X"1B",X"52",
X"56",X"1B",X"90",X"0A",X"2C",X"0D",X"1B",X"52",X"56",X"1B",X"0E",X"CF",X"10",X"21",X"D0",X"10",
X"1A",X"1B",X"52",X"56",X"1B",X"18",X"0D",X"1B",X"52",X"56",X"1B",X"0E",X"E0",X"10",X"21",X"E1",
X"10",X"1A",X"1B",X"52",X"56",X"1B",X"18",X"0D",X"1B",X"52",X"56",X"1B",X"0E",X"F1",X"10",X"21",
X"F2",X"10",X"1A",X"1B",X"52",X"56",X"1B",X"18",X"0D",X"1B",X"52",X"56",X"1B",X"0E",X"6D",X"C3",
X"10",X"21",X"C4",X"10",X"1A",X"1B",X"52",X"56",X"1B",X"18",X"0D",X"1B",X"52",X"56",X"1B",X"0E",
X"D4",X"10",X"21",X"D5",X"10",X"1A",X"1B",X"52",X"56",X"1B",X"18",X"0D",X"1B",X"52",X"56",X"1B",
X"0E",X"E5",X"10",X"21",X"E6",X"10",X"1A",X"1B",X"52",X"56",X"1B",X"18",X"0D",X"1B",X"52",X"56",
X"1B",X"0E",X"F6",X"10",X"21",X"F7",X"10",X"1A",X"90",X"0E",X"1D",X"1B",X"52",X"56",X"1B",X"18",
X"2C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

86
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/cs51xx_prog.vhd Normal file
View File

@ -0,0 +1,86 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity cs51xx_prog is
port (
clk : in std_logic;
addr : in std_logic_vector(9 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of cs51xx_prog is
type rom is array(0 to 1023) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"68",X"7E",X"50",X"12",X"3F",X"04",X"3D",X"01",X"54",X"1B",X"51",X"59",X"83",X"25",X"D0",X"CD",
X"25",X"D0",X"00",X"12",X"B0",X"DC",X"57",X"8A",X"9A",X"1D",X"57",X"90",X"1A",X"AF",X"CD",X"51",
X"1B",X"54",X"56",X"84",X"56",X"50",X"3E",X"04",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"68",X"22",X"00",X"00",X"68",X"08",X"00",X"00",X"90",X"53",X"68",X"22",X"91",X"52",X"68",X"22",
X"90",X"52",X"68",X"22",X"91",X"53",X"68",X"22",X"68",X"22",X"00",X"00",X"68",X"22",X"00",X"00",
X"6A",X"4F",X"00",X"00",X"6A",X"4F",X"00",X"00",X"6A",X"4F",X"00",X"00",X"6A",X"4F",X"00",X"00",
X"6A",X"4F",X"00",X"00",X"6A",X"4F",X"00",X"00",X"6A",X"4F",X"00",X"00",X"6A",X"4F",X"58",X"80",
X"90",X"1B",X"0A",X"C2",X"1B",X"71",X"B8",X"C1",X"59",X"8F",X"9C",X"1D",X"5A",X"8A",X"9F",X"0A",
X"1D",X"90",X"07",X"91",X"53",X"3E",X"64",X"59",X"88",X"90",X"1D",X"58",X"89",X"16",X"1D",X"83",
X"0D",X"B1",X"68",X"BE",X"5A",X"82",X"13",X"84",X"1A",X"13",X"85",X"1D",X"81",X"13",X"87",X"1D",
X"80",X"13",X"86",X"1D",X"9F",X"88",X"0A",X"0A",X"0A",X"0A",X"90",X"07",X"69",X"7E",X"83",X"13",
X"4F",X"6A",X"39",X"59",X"8A",X"0B",X"BA",X"CA",X"0B",X"E7",X"0B",X"85",X"0B",X"08",X"0B",X"08",
X"0B",X"0F",X"2D",X"7F",X"18",X"1F",X"18",X"1F",X"18",X"1D",X"4C",X"61",X"87",X"84",X"0D",X"4D",
X"61",X"A4",X"84",X"0D",X"4E",X"61",X"C6",X"62",X"65",X"82",X"13",X"5A",X"0B",X"18",X"0B",X"18",
X"0B",X"0F",X"2D",X"7F",X"08",X"1F",X"08",X"1F",X"08",X"1D",X"58",X"83",X"0D",X"B0",X"69",X"F9",
X"59",X"88",X"0D",X"B0",X"69",X"20",X"8A",X"0D",X"B0",X"CF",X"18",X"0D",X"B0",X"D9",X"E0",X"5A",
X"83",X"0D",X"4E",X"69",X"D9",X"4F",X"69",X"D7",X"E0",X"B1",X"CF",X"5A",X"83",X"3A",X"69",X"D9",
X"59",X"8F",X"9C",X"0F",X"1D",X"8B",X"0D",X"B0",X"EB",X"69",X"3D",X"16",X"8F",X"B4",X"69",X"39",
X"3B",X"F4",X"69",X"3D",X"33",X"8B",X"19",X"69",X"3D",X"B0",X"69",X"3D",X"37",X"8C",X"0D",X"B0",
X"C3",X"69",X"52",X"16",X"8F",X"BC",X"69",X"4F",X"3A",X"CB",X"D2",X"32",X"8C",X"19",X"D2",X"B8",
X"D2",X"36",X"58",X"83",X"0D",X"B0",X"EF",X"8A",X"59",X"0D",X"B0",X"E1",X"18",X"0D",X"B1",X"E1",
X"E9",X"B0",X"E4",X"EF",X"15",X"4C",X"E9",X"8F",X"09",X"15",X"4C",X"EF",X"8F",X"09",X"09",X"8F",
X"59",X"0D",X"02",X"59",X"8A",X"0D",X"B0",X"69",X"7C",X"9F",X"07",X"FE",X"90",X"07",X"58",X"89",
X"3E",X"60",X"16",X"2E",X"68",X"97",X"C2",X"83",X"0D",X"8D",X"09",X"2E",X"DF",X"90",X"1D",X"82",
X"0D",X"88",X"0A",X"23",X"0E",X"10",X"0A",X"90",X"0E",X"1D",X"BA",X"DF",X"99",X"1A",X"1D",X"8B",
X"09",X"E3",X"19",X"2C",X"81",X"0D",X"8E",X"09",X"2E",X"69",X"C1",X"90",X"1D",X"80",X"0D",X"88",
X"0B",X"1F",X"0B",X"08",X"23",X"0E",X"10",X"0A",X"90",X"0E",X"1D",X"BA",X"69",X"C1",X"99",X"1A",
X"1D",X"8C",X"09",X"C5",X"19",X"2C",X"91",X"88",X"1D",X"08",X"23",X"0E",X"10",X"0A",X"90",X"0E",
X"1D",X"BA",X"D6",X"99",X"1A",X"1D",X"2C",X"92",X"DA",X"91",X"89",X"59",X"23",X"1E",X"11",X"0A",
X"90",X"1E",X"1D",X"62",X"65",X"92",X"58",X"83",X"1D",X"59",X"8D",X"90",X"0A",X"1D",X"83",X"0D",
X"B0",X"69",X"20",X"89",X"0A",X"9A",X"1D",X"69",X"20",X"5A",X"83",X"91",X"0F",X"87",X"1D",X"82",
X"91",X"0F",X"23",X"0C",X"87",X"1F",X"1D",X"58",X"82",X"0D",X"5A",X"B0",X"D4",X"80",X"13",X"62",
X"72",X"86",X"1D",X"D8",X"80",X"13",X"86",X"1D",X"5A",X"83",X"92",X"0F",X"23",X"1C",X"89",X"1D",
X"82",X"92",X"0F",X"89",X"1F",X"1D",X"58",X"82",X"0D",X"5A",X"81",X"B0",X"F4",X"13",X"62",X"72",
X"88",X"1D",X"69",X"20",X"13",X"88",X"1D",X"69",X"20",X"59",X"89",X"90",X"07",X"0A",X"1D",X"8D",
X"0A",X"1D",X"5A",X"84",X"9B",X"0A",X"0A",X"58",X"83",X"91",X"1D",X"9F",X"02",X"69",X"7E",X"1B",
X"51",X"56",X"5A",X"0D",X"23",X"01",X"08",X"0D",X"21",X"01",X"08",X"AC",X"DE",X"84",X"56",X"51",
X"1B",X"50",X"3E",X"04",X"3C",X"59",X"89",X"0D",X"84",X"5A",X"1D",X"59",X"8A",X"0D",X"5A",X"85",
X"1D",X"2C",X"3D",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"9F",X"2C",X"00",X"00",X"9E",X"2C",X"00",X"00",X"9D",X"2C",X"00",X"00",X"95",X"2C",X"00",X"00",
X"9C",X"2C",X"00",X"00",X"99",X"2C",X"00",X"00",X"97",X"2C",X"00",X"00",X"96",X"2C",X"00",X"00",
X"9B",X"2C",X"00",X"00",X"93",X"2C",X"00",X"00",X"9A",X"2C",X"00",X"00",X"94",X"2C",X"00",X"00",
X"91",X"2C",X"00",X"00",X"92",X"2C",X"00",X"00",X"90",X"2C",X"00",X"00",X"98",X"2C",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

86
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/cs54xx_prog.vhd Normal file
View File

@ -0,0 +1,86 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity cs54xx_prog is
port (
clk : in std_logic;
addr : in std_logic_vector(9 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of cs54xx_prog is
type rom is array(0 to 1023) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"C6",X"C6",X"52",X"12",X"3D",X"06",X"58",X"80",X"90",X"1B",X"0A",X"CA",X"1B",X"71",X"B8",X"C9",
X"3E",X"04",X"59",X"84",X"0D",X"1C",X"18",X"0D",X"1C",X"1A",X"0D",X"1C",X"1A",X"0D",X"1C",X"1A",
X"0D",X"1C",X"1D",X"1C",X"83",X"2F",X"71",X"08",X"0A",X"0D",X"80",X"38",X"F8",X"23",X"01",X"88",
X"20",X"08",X"0D",X"21",X"0E",X"1A",X"68",X"41",X"88",X"22",X"23",X"90",X"01",X"89",X"0D",X"0E",
X"1A",X"0D",X"7F",X"68",X"90",X"58",X"19",X"68",X"90",X"59",X"86",X"19",X"68",X"90",X"08",X"19",
X"68",X"90",X"08",X"19",X"0D",X"B1",X"D8",X"DF",X"B2",X"FF",X"90",X"85",X"1D",X"92",X"E6",X"5B",
X"81",X"0D",X"59",X"85",X"1D",X"91",X"23",X"0C",X"04",X"5B",X"0D",X"B0",X"F5",X"50",X"08",X"0D",
X"B0",X"F8",X"88",X"59",X"D3",X"50",X"08",X"0D",X"59",X"87",X"1A",X"50",X"1D",X"68",X"90",X"85",
X"0D",X"7F",X"68",X"90",X"0D",X"23",X"1C",X"23",X"0E",X"1C",X"1D",X"91",X"88",X"1D",X"68",X"66",
X"89",X"59",X"93",X"0F",X"B1",X"D8",X"8E",X"09",X"8A",X"0D",X"8E",X"38",X"DE",X"90",X"21",X"01",
X"38",X"E5",X"89",X"20",X"E7",X"89",X"22",X"8D",X"0D",X"7F",X"68",X"FC",X"58",X"19",X"68",X"FC",
X"59",X"8B",X"19",X"68",X"FC",X"08",X"19",X"68",X"FC",X"08",X"19",X"0D",X"B1",X"68",X"C0",X"C9",
X"B2",X"68",X"EC",X"90",X"8A",X"1D",X"92",X"68",X"D0",X"5B",X"89",X"0D",X"59",X"8A",X"1D",X"91",
X"23",X"0C",X"78",X"04",X"5B",X"0D",X"B0",X"68",X"E3",X"50",X"08",X"0D",X"B0",X"68",X"E6",X"59",
X"8D",X"68",X"BA",X"50",X"08",X"0D",X"59",X"8C",X"1A",X"50",X"1D",X"FC",X"8A",X"0D",X"7F",X"FC",
X"0D",X"23",X"1C",X"23",X"0E",X"1C",X"1D",X"91",X"8D",X"1D",X"68",X"D0",X"5A",X"8F",X"0D",X"8B",
X"3B",X"C3",X"90",X"81",X"03",X"88",X"0D",X"8A",X"23",X"0E",X"1D",X"89",X"0D",X"8B",X"0E",X"1D",
X"59",X"80",X"38",X"E1",X"5A",X"86",X"0D",X"23",X"8A",X"0E",X"1D",X"87",X"0D",X"8B",X"0E",X"1D",
X"59",X"8F",X"0D",X"7F",X"68",X"12",X"5A",X"8C",X"19",X"68",X"12",X"08",X"19",X"68",X"12",X"08",
X"19",X"68",X"12",X"8F",X"59",X"19",X"0D",X"B0",X"69",X"47",X"5A",X"0D",X"1C",X"23",X"0E",X"1C",
X"1D",X"7F",X"68",X"12",X"91",X"59",X"1D",X"5A",X"84",X"0D",X"8D",X"1D",X"7F",X"D7",X"85",X"0D",
X"8E",X"1D",X"8C",X"90",X"1D",X"68",X"12",X"85",X"0D",X"8E",X"1D",X"B0",X"E3",X"8F",X"1D",X"59",
X"1D",X"68",X"12",X"90",X"8C",X"1D",X"68",X"12",X"1B",X"53",X"54",X"80",X"13",X"5A",X"8F",X"1D",
X"54",X"53",X"1B",X"52",X"3E",X"04",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"FC",X"00",X"00",X"00",X"69",X"C0",X"00",X"00",X"69",X"DC",X"00",X"00",X"6A",X"55",X"00",X"00",
X"6A",X"5D",X"00",X"00",X"69",X"F9",X"00",X"00",X"6A",X"40",X"00",X"00",X"69",X"68",X"00",X"00",
X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",
X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"FC",X"00",X"00",X"00",X"52",X"3E",X"04",X"3C",
X"1B",X"53",X"54",X"5B",X"80",X"0D",X"59",X"85",X"1D",X"88",X"93",X"1D",X"5B",X"87",X"0D",X"59",
X"1A",X"5B",X"0D",X"59",X"1D",X"54",X"53",X"1B",X"52",X"3E",X"04",X"3C",X"1B",X"53",X"54",X"5B",
X"88",X"0D",X"59",X"8A",X"1D",X"8D",X"93",X"0A",X"5B",X"0D",X"51",X"08",X"0D",X"59",X"8C",X"1A",
X"51",X"1D",X"53",X"1B",X"52",X"54",X"3E",X"04",X"3C",X"1B",X"53",X"54",X"5A",X"81",X"0D",X"8C",
X"1D",X"82",X"0D",X"8D",X"1D",X"83",X"0D",X"8E",X"1D",X"80",X"0D",X"8F",X"1D",X"92",X"59",X"1D",
X"53",X"1B",X"52",X"54",X"3E",X"04",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"1B",X"53",X"54",X"5A",X"89",X"55",X"3F",X"04",X"25",X"CB",X"C8",X"25",X"CB",X"80",X"13",X"55",
X"1A",X"12",X"1A",X"55",X"E5",X"1B",X"53",X"54",X"87",X"55",X"3F",X"04",X"E5",X"1B",X"53",X"5B",
X"54",X"8F",X"55",X"3F",X"04",X"25",X"E8",X"E5",X"25",X"E8",X"80",X"13",X"55",X"1A",X"12",X"1A",
X"14",X"55",X"23",X"0C",X"BE",X"E5",X"53",X"1B",X"52",X"54",X"3E",X"04",X"3C",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/green.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity green is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of green is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"06",X"08",X"0C",X"02",X"0A",X"07",X"04",X"09",X"0C",X"08",X"06",X"09",X"03",X"05",X"05",
X"08",X"08",X"08",X"06",X"0B",X"06",X"04",X"03",X"02",X"04",X"06",X"07",X"09",X"09",X"08",X"08",
X"08",X"06",X"06",X"05",X"07",X"08",X"00",X"08",X"07",X"08",X"0B",X"06",X"0B",X"05",X"0C",X"00",
X"04",X"08",X"05",X"0A",X"08",X"04",X"0F",X"0A",X"06",X"06",X"0A",X"00",X"00",X"0F",X"0E",X"02",
X"06",X"0B",X"05",X"08",X"04",X"0F",X"08",X"00",X"00",X"03",X"04",X"04",X"05",X"08",X"07",X"06",
X"02",X"06",X"05",X"04",X"07",X"08",X"04",X"0C",X"06",X"00",X"0E",X"0C",X"0C",X"0C",X"08",X"0C",
X"0F",X"0B",X"07",X"03",X"08",X"04",X"04",X"06",X"0A",X"0C",X"08",X"04",X"0F",X"00",X"00",X"04",
X"02",X"08",X"04",X"04",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0A",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/red.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity red is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of red is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"06",X"03",X"00",X"05",X"0A",X"02",X"05",X"09",X"0C",X"04",X"04",X"09",X"06",X"05",X"05",
X"07",X"05",X"05",X"08",X"0D",X"0C",X"07",X"04",X"02",X"02",X"02",X"03",X"05",X"09",X"07",X"08",
X"0A",X"08",X"07",X"06",X"07",X"08",X"0F",X"04",X"03",X"00",X"0D",X"00",X"0A",X"02",X"00",X"0A",
X"02",X"04",X"05",X"0A",X"08",X"08",X"0F",X"0F",X"0F",X"02",X"0E",X"0C",X"00",X"0F",X"0E",X"02",
X"0C",X"0D",X"00",X"00",X"04",X"00",X"00",X"08",X"06",X"00",X"0C",X"04",X"05",X"08",X"07",X"06",
X"02",X"08",X"02",X"05",X"0B",X"0F",X"0C",X"00",X"0A",X"04",X"0E",X"0F",X"0F",X"0F",X"0C",X"0C",
X"0F",X"0B",X"07",X"03",X"0F",X"04",X"04",X"06",X"0A",X"0C",X"0A",X"08",X"00",X"08",X"0F",X"08",
X"04",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"04",X"02",X"08",X"04",X"0F",X"0F",X"0F",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/sound_samples.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity sound_samples is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of sound_samples is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09",X"07",
X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05",X"07",
X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04",
X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00",
X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"0E",X"0E",X"0E",X"00",X"00",X"00",X"0E",X"0E",X"0E",X"0E",X"0E",X"00",X"00",X"00",X"00",X"00",
X"0E",X"0E",X"00",X"00",X"0C",X"0C",X"0D",X"03",X"0E",X"0E",X"0C",X"0C",X"0C",X"0C",X"0D",X"07",
X"01",X"02",X"02",X"02",X"02",X"00",X"00",X"0B",X"01",X"02",X"02",X"0E",X"0E",X"00",X"00",X"07",
X"0E",X"0C",X"07",X"0A",X"0C",X"07",X"05",X"0C",X"0E",X"0D",X"08",X"0A",X"0B",X"06",X"02",X"07",
X"0C",X"08",X"03",X"04",X"06",X"01",X"00",X"03",X"09",X"07",X"02",X"04",X"07",X"02",X"00",X"07",
X"0C",X"0E",X"0E",X"0E",X"0E",X"0C",X"0B",X"09",X"07",X"06",X"05",X"05",X"05",X"06",X"08",X"0A",
X"0B",X"0B",X"09",X"06",X"04",X"02",X"02",X"02",X"03",X"05",X"04",X"03",X"02",X"01",X"03",X"07",
X"08",X"0B",X"0E",X"0D",X"07",X"0D",X"0E",X"0D",X"0C",X"0B",X"03",X"02",X"01",X"00",X"01",X"07",
X"01",X"00",X"03",X"06",X"08",X"0E",X"0D",X"0C",X"0E",X"08",X"03",X"00",X"02",X"01",X"00",X"06");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/sound_seq.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity sound_seq is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of sound_seq is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",
X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",
X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",
X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

54
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/sp_palette_lsb.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity sp_palette_lsb is
port (
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of sp_palette_lsb is
type rom is array(0 to 511) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"09",X"05",X"05",X"01",X"04",X"06",X"05",
X"00",X"06",X"00",X"06",X"07",X"04",X"08",X"09",X"00",X"0F",X"00",X"06",X"07",X"04",X"08",X"09",
X"00",X"07",X"00",X"06",X"07",X"04",X"08",X"09",X"00",X"08",X"00",X"06",X"07",X"04",X"08",X"09",
X"00",X"00",X"00",X"06",X"07",X"04",X"08",X"09",X"00",X"0D",X"05",X"05",X"01",X"04",X"00",X"06",
X"00",X"0D",X"05",X"05",X"01",X"04",X"00",X"0F",X"00",X"0D",X"05",X"05",X"01",X"04",X"00",X"07",
X"00",X"0D",X"05",X"05",X"01",X"04",X"00",X"09",X"00",X"0D",X"05",X"05",X"01",X"04",X"00",X"00",
X"00",X"05",X"01",X"0D",X"06",X"04",X"06",X"07",X"00",X"09",X"0A",X"0B",X"0D",X"09",X"00",X"06",
X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"06",X"00",X"0D",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0D",X"00",X"00",X"00",X"00",
X"00",X"07",X"00",X"0D",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"0D",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"0D",X"00",X"00",X"00",X"00",X"00",X"06",X"07",X"07",X"09",X"09",X"00",X"06",
X"00",X"04",X"0F",X"0F",X"00",X"00",X"00",X"04",X"00",X"06",X"01",X"01",X"02",X"02",X"00",X"06",
X"00",X"0C",X"03",X"03",X"03",X"03",X"00",X"0C",X"00",X"05",X"04",X"04",X"05",X"05",X"00",X"05",
X"00",X"0C",X"06",X"06",X"07",X"07",X"00",X"0C",X"00",X"0D",X"08",X"08",X"09",X"09",X"00",X"0D",
X"00",X"0E",X"0A",X"0A",X"0B",X"0B",X"00",X"0E",X"00",X"0D",X"00",X"06",X"07",X"04",X"08",X"09",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"09",X"06",X"09",X"00",X"00",X"00",X"00",X"00",X"09",X"00",X"09",X"00",X"00",X"00",X"00",
X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"06",X"06",X"00",X"00",X"00",X"00",
X"00",X"05",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"0D",X"06",X"00",X"00",X"00",X"00",X"00",
X"00",X"06",X"0D",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"06",X"00",X"00",X"00",X"00",X"00",
X"00",X"06",X"0D",X"00",X"00",X"00",X"00",X"00",X"00",X"09",X"06",X"06",X"00",X"00",X"00",X"00",
X"00",X"09",X"00",X"06",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"03",X"00",X"00",X"00",X"00",
X"00",X"05",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"09",X"05",X"05",X"01",X"04",X"09",
X"00",X"0D",X"09",X"05",X"0C",X"0D",X"09",X"00",X"00",X"0D",X"0C",X"0D",X"0B",X"0C",X"0E",X"06",
X"00",X"0D",X"06",X"0F",X"05",X"05",X"01",X"04",X"00",X"08",X"0C",X"0F",X"04",X"0E",X"01",X"00",
X"00",X"0F",X"0F",X"00",X"0C",X"08",X"01",X"00",X"00",X"0D",X"0F",X"08",X"0F",X"05",X"05",X"01",
X"00",X"0F",X"07",X"08",X"0D",X"0F",X"05",X"05",X"00",X"0D",X"0F",X"05",X"05",X"04",X"06",X"0F",
X"00",X"0F",X"05",X"05",X"01",X"04",X"06",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

54
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/sp_palette_msb.vhd Normal file
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@ -0,0 +1,54 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity sp_palette_msb is
port (
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of sp_palette_msb is
type rom is array(0 to 511) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"0A",X"08",X"0C",X"0A",X"0E",
X"00",X"0A",X"08",X"0E",X"0E",X"0B",X"0E",X"0E",X"00",X"0A",X"08",X"0E",X"0E",X"0B",X"0E",X"0E",
X"00",X"0C",X"08",X"0E",X"0E",X"0B",X"0E",X"0E",X"00",X"0C",X"08",X"0E",X"0E",X"0B",X"0E",X"0E",
X"00",X"08",X"08",X"0E",X"0E",X"0B",X"0E",X"0E",X"00",X"0B",X"08",X"0A",X"08",X"0C",X"08",X"0A",
X"00",X"0B",X"08",X"0A",X"08",X"0C",X"08",X"0A",X"00",X"0B",X"08",X"0A",X"08",X"0C",X"08",X"0C",
X"00",X"0B",X"08",X"0A",X"08",X"0C",X"08",X"0D",X"00",X"0B",X"08",X"0A",X"08",X"0C",X"08",X"08",
X"00",X"08",X"08",X"0B",X"0B",X"0E",X"0A",X"0C",X"00",X"0E",X"0E",X"0E",X"08",X"0D",X"08",X"0A",
X"00",X"0A",X"0B",X"00",X"00",X"00",X"00",X"00",X"00",X"0B",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"0A",X"08",X"0B",X"00",X"00",X"00",X"00",X"00",X"0A",X"08",X"0B",X"00",X"00",X"00",X"00",
X"00",X"0C",X"08",X"0B",X"00",X"00",X"00",X"00",X"00",X"0C",X"08",X"0B",X"00",X"00",X"00",X"00",
X"00",X"08",X"08",X"0B",X"00",X"00",X"00",X"00",X"00",X"0A",X"0C",X"0C",X"0D",X"0D",X"08",X"0A",
X"00",X"0E",X"0E",X"0E",X"0F",X"0F",X"08",X"0E",X"00",X"0B",X"0F",X"0F",X"0F",X"0F",X"00",X"0B",
X"00",X"0E",X"0C",X"0C",X"0F",X"0F",X"08",X"0E",X"00",X"0C",X"0F",X"0F",X"0F",X"0F",X"08",X"0C",
X"00",X"0B",X"0F",X"0F",X"0F",X"0F",X"00",X"0B",X"00",X"0E",X"0F",X"0F",X"0F",X"0F",X"00",X"0E",
X"00",X"0E",X"0F",X"0F",X"0F",X"0F",X"08",X"0E",X"00",X"0B",X"08",X"0E",X"0E",X"0B",X"0E",X"0E",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"08",X"0C",X"08",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"08",X"00",X"00",X"00",X"00",
X"00",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0B",X"0A",X"0C",X"00",X"00",X"00",X"00",
X"00",X"08",X"0A",X"0C",X"00",X"00",X"00",X"00",X"00",X"0B",X"0A",X"00",X"00",X"00",X"00",X"00",
X"00",X"0A",X"0B",X"00",X"00",X"00",X"00",X"00",X"00",X"0B",X"0C",X"00",X"00",X"00",X"00",X"00",
X"00",X"0C",X"0B",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"0C",X"0A",X"00",X"00",X"00",X"00",
X"00",X"08",X"00",X"0A",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"0E",X"00",X"00",X"00",X"00",
X"00",X"0A",X"0C",X"08",X"00",X"00",X"00",X"00",X"00",X"0B",X"08",X"08",X"0A",X"08",X"0C",X"0E",
X"00",X"0B",X"08",X"08",X"0F",X"0F",X"0E",X"00",X"00",X"0B",X"0F",X"0F",X"0D",X"0D",X"0F",X"0A",
X"00",X"0D",X"0A",X"0A",X"08",X"0A",X"08",X"0C",X"00",X"0D",X"0D",X"0A",X"0E",X"0D",X"08",X"08",
X"00",X"0A",X"09",X"0E",X"0F",X"0E",X"08",X"08",X"00",X"0B",X"0A",X"0C",X"0D",X"08",X"0A",X"08",
X"00",X"0A",X"0C",X"0C",X"0B",X"0D",X"08",X"0A",X"00",X"0B",X"0D",X"08",X"0A",X"0C",X"0A",X"0A",
X"00",X"0D",X"08",X"0A",X"08",X"0C",X"0A",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

278
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/terrain_2a.vhd Normal file
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@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity terrain_2a is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of terrain_2a is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"20",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"00",X"00",X"00",X"00",X"20",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"20",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"40",X"20",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"03",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"02",X"04",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"40",X"00",X"02",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"41",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"20",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"40",X"00",X"20",X"40",X"11",X"11",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"41",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"16",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"00",X"00",X"00",X"00",X"00",
X"04",X"40",X"00",X"00",X"02",X"54",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"41",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"60",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"20",X"40",X"00",X"00",X"00",X"00",X"00",
X"04",X"00",X"00",X"00",X"60",X"40",X"05",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"33",X"20",X"22",X"22",X"22",X"22",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"26",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"02",X"06",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"20",X"22",X"22",X"06",X"00",X"00",X"00",X"00",X"00",
X"04",X"40",X"00",X"00",X"00",X"40",X"30",X"73",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"51",X"00",X"22",X"22",X"20",X"02",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"20",
X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"62",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"20",X"22",X"22",X"02",X"06",X"00",X"00",X"64",X"00",
X"04",X"40",X"00",X"00",X"06",X"02",X"04",X"00",X"00",X"40",X"02",X"00",X"06",X"00",X"00",X"00",
X"06",X"51",X"40",X"00",X"00",X"00",X"06",X"00",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"06",X"00",X"00",X"00",X"04",X"00",X"00",X"20",X"00",
X"07",X"00",X"02",X"60",X"00",X"02",X"04",X"00",X"00",X"24",X"04",X"60",X"00",X"00",X"00",X"00",
X"00",X"55",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"60",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"06",X"01",
X"07",X"00",X"22",X"60",X"06",X"20",X"40",X"00",X"40",X"42",X"02",X"00",X"00",X"00",X"00",X"00",
X"06",X"50",X"00",X"00",X"00",X"07",X"13",X"01",X"00",X"00",X"66",X"00",X"00",X"00",X"00",X"00",
X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"00",X"00",
X"00",X"00",X"00",X"07",X"00",X"00",X"06",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"10",
X"00",X"40",X"00",X"00",X"00",X"00",X"40",X"00",X"22",X"24",X"00",X"00",X"00",X"00",X"00",X"00",
X"30",X"50",X"00",X"00",X"51",X"00",X"00",X"10",X"66",X"00",X"00",X"26",X"22",X"22",X"22",X"22",
X"22",X"24",X"22",X"22",X"62",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"50",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"10",
X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"24",X"40",X"02",X"00",X"00",X"00",X"00",X"00",X"40",
X"34",X"50",X"00",X"70",X"00",X"00",X"00",X"00",X"10",X"60",X"00",X"20",X"22",X"22",X"22",X"22",
X"22",X"22",X"22",X"22",X"02",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",
X"40",X"40",X"00",X"00",X"00",X"00",X"02",X"00",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"32",X"05",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"23",X"04",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"26",X"22",X"22",X"22",X"22",X"22",X"22",X"12",X"00",X"00",
X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",
X"40",X"40",X"00",X"00",X"00",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"64",
X"50",X"05",X"50",X"05",X"00",X"00",X"00",X"00",X"00",X"10",X"01",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"22",X"22",X"22",X"22",X"22",X"22",X"02",X"00",X"00",
X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"06",
X"40",X"46",X"00",X"00",X"00",X"00",X"20",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",
X"03",X"05",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",
X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"04",
X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"02",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"04",
X"33",X"17",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"63",X"06",X"00",X"00",X"20",
X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"00",X"00",
X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"04",
X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"20",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"20",
X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"01",X"00",X"20",X"54",
X"11",X"20",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"04",
X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"36",
X"30",X"00",X"00",X"00",X"00",X"00",X"20",X"22",X"02",X"00",X"00",X"00",X"10",X"02",X"44",X"07",
X"00",X"13",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"30",X"00",X"00",X"60",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"04",
X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"74",X"00",X"00",X"00",X"07",X"15",X"31",
X"03",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"02",X"66",X"66",X"00",X"00",X"13",X"51",X"00",
X"00",X"00",X"00",X"21",X"02",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"10",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"04",
X"40",X"00",X"24",X"22",X"22",X"22",X"22",X"02",X"00",X"40",X"00",X"50",X"51",X"00",X"14",X"05",
X"01",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"02",X"06",X"60",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"10",X"11",X"02",X"04",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"50",X"00",X"00",X"00",X"06",X"00",X"00",X"00",X"22",X"00",X"00",X"04",X"00",X"04",
X"40",X"00",X"26",X"22",X"22",X"22",X"22",X"22",X"24",X"40",X"15",X"51",X"40",X"01",X"10",X"07",
X"01",X"00",X"00",X"00",X"00",X"00",X"20",X"22",X"02",X"06",X"60",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"22",X"22",X"00",X"01",X"04",X"00",X"00",X"00",X"00",X"50",X"00",X"00",
X"00",X"00",X"30",X"00",X"00",X"00",X"04",X"00",X"00",X"60",X"00",X"02",X"00",X"04",X"00",X"04",
X"40",X"60",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"05",X"00",X"00",X"00",X"40",X"07",
X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"66",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"02",X"20",X"00",X"30",X"01",X"06",X"00",X"00",X"00",X"00",X"05",X"00",
X"00",X"00",X"10",X"01",X"02",X"00",X"06",X"00",X"00",X"06",X"00",X"00",X"20",X"40",X"00",X"04",
X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"10",X"11",X"05",X"00",X"00",X"00",X"00",X"27",X"37",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"02",X"20",X"00",X"00",X"11",X"42",X"00",X"00",X"00",X"00",X"01",X"00",
X"00",X"00",X"00",X"11",X"06",X"40",X"00",X"20",X"60",X"00",X"00",X"00",X"00",X"02",X"24",X"24",
X"60",X"44",X"00",X"00",X"00",X"00",X"10",X"05",X"00",X"00",X"00",X"00",X"10",X"27",X"02",X"11",
X"00",X"00",X"00",X"04",X"04",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"22",X"22",X"00",X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"01",X"00",
X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"24",X"06",X"50",X"11",X"11",X"05",X"20",X"22",X"22",
X"60",X"42",X"00",X"00",X"00",X"10",X"05",X"00",X"00",X"00",X"00",X"60",X"20",X"02",X"10",X"00",
X"11",X"51",X"00",X"00",X"04",X"00",X"40",X"00",X"00",X"01",X"40",X"04",X"14",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",X"00",
X"00",X"00",X"00",X"00",X"60",X"22",X"22",X"42",X"02",X"10",X"00",X"00",X"30",X"00",X"00",X"00",
X"40",X"60",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"60",X"40",X"20",X"02",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"00",X"40",X"00",X"40",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"25",X"04",X"00",X"00",X"01",X"00",
X"00",X"00",X"00",X"00",X"00",X"22",X"02",X"24",X"00",X"70",X"00",X"00",X"00",X"10",X"01",X"00",
X"40",X"04",X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"20",X"04",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"07",X"00",
X"00",X"00",X"00",X"00",X"05",X"00",X"64",X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"30",X"10",
X"40",X"04",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"04",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"42",X"00",X"10",X"00",X"00",
X"00",X"00",X"00",X"00",X"03",X"20",X"20",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00",
X"77",X"42",X"00",X"00",X"07",X"00",X"00",X"00",X"40",X"06",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"04",X"00",X"40",X"00",X"00",X"00",X"00",X"33",X"00",X"20",X"04",X"70",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"42",X"02",X"00",X"00",X"70",X"07",X"00",X"00",X"00",X"10",X"00",
X"71",X"60",X"06",X"00",X"00",X"00",X"40",X"00",X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"07",X"20",X"00",X"04",X"03",X"00",X"00",
X"00",X"00",X"00",X"00",X"20",X"04",X"00",X"00",X"00",X"00",X"30",X"07",X"00",X"00",X"00",X"03",
X"01",X"07",X"00",X"12",X"00",X"00",X"04",X"02",X"24",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"20",X"42",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"07",X"00",X"00",X"50",
X"10",X"70",X"00",X"10",X"00",X"00",X"20",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"57",X"00",X"30",
X"00",X"01",X"07",X"03",X"06",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"66",X"00",X"00",X"00",X"30",X"00",X"00",X"00",
X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"22",X"22",X"22",X"22",X"16",X"00",X"00",
X"13",X"11",X"70",X"01",X"20",X"02",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"40",X"00",X"00",X"00",X"00",X"05",X"00",X"00",
X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",
X"00",X"30",X"71",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",
X"00",X"10",X"10",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"24",X"00",X"00",X"10",X"00",X"00",
X"00",X"50",X"00",X"71",X"05",X"10",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"20",X"22",X"00",X"00",X"10",X"00",X"00",
X"00",X"70",X"00",X"01",X"37",X"37",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"22",X"36",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",
X"00",X"00",X"00",X"10",X"71",X"13",X"11",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"22",X"44",X"10",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"00",
X"30",X"07",X"00",X"00",X"51",X"51",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"22",X"44",X"00",X"10",X"00",X"00",
X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"77",X"00",
X"07",X"00",X"40",X"00",X"00",X"00",X"51",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"42",X"40",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"33",
X"00",X"00",X"00",X"04",X"04",X"00",X"00",X"15",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"02",X"04",X"00",X"00",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"40",X"40",X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"06",X"20",X"26",X"04",X"00",X"00",X"00",X"00",X"03",X"00",X"00",
X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"00",X"00",
X"02",X"00",X"00",X"00",X"00",X"00",X"44",X"00",X"00",X"10",X"11",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"66",X"00",X"62",X"00",X"42",X"00",X"00",X"00",X"00",X"07",X"00",X"00",
X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"05",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"60",X"00",X"00",X"04",X"00",X"20",X"04",X"00",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"00",X"00",X"00",X"00",X"20",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"04",X"00",X"10",X"11",X"55",X"15",X"11",
X"51",X"11",X"15",X"11",X"11",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"51",X"11",
X"15",X"11",X"15",X"00",X"42",X"10",X"35",X"51",X"00",X"04",X"00",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"04",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"15",X"00",X"00",X"10",X"11",X"51",X"01",X"00",X"00",X"50",X"51",X"00",X"50",X"05",
X"05",X"00",X"00",X"06",X"15",X"05",X"00",X"00",X"01",X"42",X"00",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"00",X"00",X"00",X"00",X"00",X"10",X"11",X"15",X"05",X"00",X"60",X"72",X"73",
X"22",X"62",X"40",X"02",X"01",X"00",X"00",X"00",X"10",X"02",X"04",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"01",X"00",X"00",X"44",X"00",X"00",X"00",X"00",
X"70",X"33",X"00",X"77",X"33",X"00",X"22",X"60",X"22",X"26",X"04",X"00",X"24",X"00",X"00",X"60",
X"00",X"00",X"40",X"00",X"01",X"00",X"00",X"00",X"10",X"40",X"42",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"01",X"00",X"00",X"00",X"44",X"00",X"00",X"00",
X"50",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"04",X"01",X"00",X"00",X"00",X"00",X"25",X"20",X"04",X"10",X"00",X"00",X"00",
X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"00",X"00",X"00",X"00",X"02",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"44",X"00",X"00",
X"70",X"00",X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"40",X"01",X"00",X"00",X"00",X"00",X"05",X"04",X"42",X"10",X"00",X"00",X"00",
X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"20",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"44",X"00",
X"50",X"01",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"54",X"00",X"00",X"00",X"00",X"21",X"04",X"20",X"14",X"00",X"00",X"00",
X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"44",
X"00",X"50",X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"16",X"00",X"00",X"00",X"00",X"03",X"04",X"00",X"42",X"00",X"00",X"00",
X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"01",X"00",X"00",
X"04",X"00",X"51",X"51",X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"50",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"11",X"11",X"00",X"00",
X"40",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"50",X"04",X"00",X"10",X"00",X"00",X"00",
X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"11",X"02",X"00",X"00",
X"00",X"44",X"00",X"00",X"00",X"20",X"00",X"26",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"50",X"02",X"00",X"75",X"00",X"00",X"00",
X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"22",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"16",X"00",X"00",X"00",X"00",X"50",X"40",X"00",X"01",X"00",X"00",X"00",
X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"00",X"22",X"22",
X"02",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"20",X"20",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"60",X"70",X"00",X"00",X"00",X"00",X"50",X"02",X"66",X"07",X"00",X"00",X"00",
X"00",X"00",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"00",X"20",X"02",X"20",
X"22",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"22",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"60",X"01",X"00",X"00",X"00",X"00",X"30",X"20",X"06",X"00",X"00",X"00",X"00",
X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"02",X"00",X"22",X"00",X"00",
X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",
X"00",X"00",X"40",X"54",X"05",X"00",X"00",X"00",X"00",X"00",X"45",X"01",X"00",X"00",X"00",X"00",
X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"22",X"02",X"00",
X"00",X"40",X"06",X"55",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"54",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

534
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/terrain_2b.vhd Normal file
View File

@ -0,0 +1,534 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity terrain_2b is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of terrain_2b is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"19",X"1C",X"1F",X"20",X"19",X"1A",X"1B",X"1C",X"1E",X"10",X"00",X"00",X"00",X"00",X"00",X"07",
X"00",X"00",X"08",X"00",X"07",X"00",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"0A",X"0B",
X"0A",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",
X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",
X"07",X"08",X"0A",X"11",X"0A",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",
X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",
X"07",X"08",X"07",X"00",X"08",X"00",X"07",X"00",X"08",X"00",X"07",X"00",X"00",X"08",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"00",X"14",X"1A",X"1D",X"19",X"1C",X"1F",X"19",
X"1A",X"1D",X"20",X"1B",X"1C",X"1D",X"1E",X"19",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"0B",
X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"0A",X"11",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"2B",X"09",X"00",X"00",X"15",X"1B",X"1E",X"1A",X"1D",X"20",X"1A",
X"1B",X"1E",X"1A",X"1C",X"1D",X"1E",X"1F",X"1D",X"2D",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"0E",X"0B",
X"0E",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"0E",X"11",X"0E",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"64",
X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"02",X"02",X"02",X"02",X"02",X"64",X"09",X"00",X"00",X"15",X"1C",X"1F",X"1B",X"1E",X"19",X"1B",
X"1C",X"1F",X"1B",X"20",X"19",X"1A",X"19",X"10",X"02",X"02",X"02",X"02",X"02",X"02",X"0C",X"04",
X"0F",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"10",X"0B",
X"10",X"02",X"04",X"63",X"0C",X"04",X"0F",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"02",X"02",X"10",X"11",X"10",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"02",X"02",X"02",X"02",X"63",X"2C",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"61",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"00",X"15",X"1D",X"20",X"1C",X"1F",X"1A",X"1C",
X"1D",X"20",X"1C",X"1A",X"1B",X"1E",X"12",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",
X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"0B",
X"0A",X"00",X"09",X"13",X"00",X"03",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"28",X"11",X"27",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"00",X"22",X"1E",X"19",X"1D",X"20",X"1B",X"1D",
X"1E",X"19",X"1D",X"1C",X"19",X"1C",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"03",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"0B",
X"0A",X"00",X"09",X"13",X"00",X"00",X"03",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"2B",X"0B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"03",X"21",X"1F",X"1A",X"1E",X"19",X"1C",X"1E",
X"1F",X"1A",X"1E",X"1B",X"20",X"1F",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"03",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"0B",
X"0A",X"00",X"09",X"13",X"00",X"00",X"00",X"03",X"04",X"03",X"13",X"16",X"1C",X"1C",X"1B",X"1C",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"2B",X"0B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"13",X"09",X"03",X"03",X"11",X"20",X"1B",X"1F",X"1A",X"1D",X"1F",
X"20",X"1B",X"1F",X"19",X"1A",X"1C",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"03",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"0B",
X"0A",X"00",X"09",X"13",X"00",X"00",X"00",X"00",X"03",X"04",X"03",X"12",X"1F",X"1A",X"1C",X"1E",
X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"2B",X"0B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",
X"00",X"00",X"00",X"00",X"61",X"64",X"04",X"03",X"00",X"13",X"19",X"1C",X"20",X"1B",X"1E",X"20",
X"19",X"1C",X"20",X"1E",X"1C",X"1D",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"03",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"0B",
X"0A",X"00",X"09",X"63",X"14",X"14",X"14",X"14",X"14",X"0F",X"04",X"17",X"12",X"19",X"1B",X"1D",
X"19",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"23",X"24",X"00",X"5F",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"5E",X"01",
X"01",X"01",X"01",X"01",X"2B",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"5E",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"02",X"02",X"02",X"02",X"64",X"04",X"03",X"00",X"00",X"19",X"1A",X"1D",X"19",X"1C",X"1F",X"19",
X"1A",X"1D",X"1C",X"1D",X"1E",X"1B",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"62",X"02",
X"02",X"02",X"02",X"02",X"0F",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"0E",X"0B",
X"0E",X"01",X"04",X"13",X"00",X"00",X"00",X"03",X"04",X"04",X"04",X"16",X"00",X"1B",X"1C",X"1B",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"26",X"26",X"01",X"04",X"01",X"01",X"01",X"01",X"04",X"01",X"01",X"04",X"04",X"04",
X"5E",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"0C",
X"01",X"01",X"01",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"03",X"00",X"00",X"00",X"15",X"1B",X"1E",X"1A",X"1D",X"20",X"1A",
X"1B",X"1E",X"1D",X"1C",X"1F",X"1E",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"04",X"01",
X"01",X"01",X"01",X"01",X"01",X"04",X"2C",X"02",X"02",X"02",X"02",X"02",X"0F",X"0C",X"10",X"0B",
X"10",X"02",X"04",X"13",X"00",X"00",X"03",X"04",X"03",X"00",X"16",X"04",X"17",X"08",X"00",X"00",
X"00",X"00",X"00",X"61",X"5E",X"01",X"01",X"04",X"0C",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"63",X"02",X"25",X"25",X"02",X"5F",X"00",X"00",X"00",X"00",X"5F",X"67",X"5F",X"5F",X"5E",X"04",
X"5E",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"16",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"1C",X"1F",X"1B",X"1E",X"19",X"1B",
X"1C",X"1F",X"1E",X"1D",X"20",X"1F",X"11",X"00",X"00",X"00",X"00",X"00",X"03",X"04",X"03",X"00",
X"00",X"00",X"00",X"00",X"00",X"09",X"09",X"00",X"00",X"00",X"00",X"00",X"09",X"00",X"0A",X"0B",
X"28",X"00",X"09",X"63",X"02",X"0C",X"04",X"03",X"00",X"00",X"17",X"04",X"16",X"07",X"00",X"00",
X"00",X"00",X"61",X"64",X"64",X"02",X"02",X"62",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"16",X"00",X"24",X"23",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"5F",X"67",X"61",X"5F",
X"5E",X"04",X"5E",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"17",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"1D",X"20",X"1C",X"1F",X"1A",X"1C",
X"1D",X"20",X"1F",X"19",X"1E",X"20",X"11",X"00",X"00",X"00",X"00",X"03",X"04",X"03",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"09",X"09",X"00",X"00",X"00",X"00",X"00",X"18",X"00",X"20",X"0B",
X"21",X"00",X"09",X"04",X"01",X"01",X"04",X"5E",X"5F",X"00",X"00",X"16",X"04",X"17",X"00",X"00",
X"00",X"61",X"64",X"64",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"16",X"00",X"0B",X"2B",X"00",X"00",X"00",X"00",X"00",X"00",X"12",X"1C",X"12",X"1B",X"1F",X"65",
X"61",X"5F",X"5E",X"04",X"5E",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"0D",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"12",X"19",X"1D",X"20",X"1B",X"1D",
X"1E",X"19",X"20",X"1F",X"1A",X"1D",X"14",X"00",X"00",X"00",X"03",X"04",X"03",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"09",X"09",X"00",X"00",X"00",X"00",X"00",X"0D",X"00",X"00",X"21",
X"11",X"00",X"09",X"09",X"00",X"00",X"5F",X"5E",X"04",X"04",X"04",X"04",X"04",X"16",X"00",X"00",
X"5F",X"64",X"64",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"0D",X"27",X"11",X"28",X"00",X"00",X"00",X"00",X"1B",X"16",X"1D",X"19",X"1B",X"1D",X"1F",X"1E",
X"65",X"5F",X"00",X"5F",X"5E",X"04",X"5E",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"02",X"02",X"63",X"02",X"02",X"02",X"02",X"02",X"02",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1A",X"1E",X"19",X"1C",X"1E",
X"1F",X"1A",X"1D",X"1E",X"1B",X"20",X"24",X"01",X"01",X"01",X"04",X"04",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"04",X"09",X"00",X"00",X"00",X"00",X"00",X"0D",X"00",X"00",X"28",
X"11",X"0A",X"09",X"09",X"00",X"00",X"00",X"00",X"5F",X"02",X"02",X"02",X"64",X"04",X"0C",X"5E",
X"04",X"64",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"61",
X"13",X"28",X"11",X"27",X"00",X"00",X"00",X"12",X"19",X"1D",X"19",X"1F",X"1D",X"1A",X"20",X"1F",
X"1D",X"1F",X"67",X"5F",X"00",X"5F",X"5E",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"5E",X"5F",X"00",X"00",X"00",X"08",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"1F",X"1A",X"1D",X"1F",
X"20",X"1B",X"1E",X"1F",X"1C",X"1E",X"23",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
X"02",X"02",X"02",X"02",X"02",X"04",X"09",X"00",X"00",X"00",X"00",X"00",X"0D",X"00",X"00",X"0A",
X"11",X"0A",X"09",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"17",X"04",X"04",X"04",
X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",
X"61",X"23",X"21",X"00",X"00",X"00",X"19",X"1D",X"20",X"1C",X"20",X"1E",X"1C",X"19",X"1F",X"1E",
X"1C",X"1D",X"1A",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"5F",X"5E",X"04",X"5E",X"02",X"02",X"02",
X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"1D",X"20",X"1B",X"1E",X"20",
X"1F",X"1C",X"1D",X"1E",X"19",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"03",X"04",X"04",X"01",X"01",X"01",X"01",X"01",X"2B",X"01",X"01",X"0E",
X"11",X"0E",X"04",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"16",X"04",X"0D",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"61",X"18",
X"00",X"24",X"28",X"00",X"00",X"17",X"16",X"1C",X"1F",X"1B",X"1F",X"1D",X"1B",X"20",X"1E",X"1D",
X"1B",X"1C",X"20",X"16",X"1F",X"68",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"5F",X"5E",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"7F",X"19",X"1C",X"1F",X"19",
X"1E",X"1D",X"1A",X"1C",X"1A",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"09",X"64",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"63",X"10",
X"11",X"10",X"63",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"17",X"04",X"64",
X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"13",X"61",
X"27",X"11",X"27",X"00",X"00",X"10",X"1E",X"1B",X"1E",X"1A",X"1E",X"1C",X"1A",X"1F",X"1D",X"1C",
X"1A",X"1B",X"1F",X"1A",X"1C",X"1E",X"67",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"1A",X"1D",X"20",X"1A",
X"1D",X"1E",X"19",X"1F",X"1B",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"09",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"04",
X"64",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"00",
X"28",X"34",X"12",X"16",X"16",X"1B",X"1D",X"1A",X"1D",X"19",X"1D",X"1B",X"20",X"1E",X"1C",X"1B",
X"19",X"1A",X"1E",X"19",X"1B",X"1E",X"12",X"68",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"5F",
X"14",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1A",X"1B",X"1E",X"19",X"1B",
X"1C",X"1F",X"1A",X"1E",X"1C",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"09",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",
X"04",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"16",X"00",
X"21",X"35",X"1D",X"20",X"1D",X"1A",X"1C",X"19",X"1C",X"20",X"1C",X"1A",X"1F",X"1D",X"1B",X"1A",
X"20",X"19",X"1D",X"20",X"1A",X"1D",X"1B",X"10",X"1F",X"68",X"00",X"00",X"00",X"5F",X"67",X"1F",
X"1C",X"1F",X"67",X"67",X"67",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"13",X"20",X"1C",X"1F",X"1A",X"1C",
X"1B",X"20",X"1C",X"1B",X"1D",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"17",X"04",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"09",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"16",X"22",
X"11",X"36",X"1C",X"1F",X"1C",X"19",X"1B",X"20",X"1B",X"1F",X"1B",X"19",X"1E",X"82",X"86",X"88",
X"8A",X"20",X"1C",X"1F",X"19",X"1C",X"1A",X"1F",X"19",X"1E",X"14",X"67",X"67",X"5F",X"12",X"1D",
X"20",X"1B",X"10",X"1B",X"1C",X"1F",X"68",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"13",X"19",X"1D",X"20",X"1B",X"1D",
X"1A",X"1E",X"1D",X"19",X"1E",X"12",X"00",X"00",X"12",X"04",X"04",X"64",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"16",X"04",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"09",X"18",X"61",X"51",X"00",X"00",X"00",X"00",X"00",X"00",X"12",X"19",X"1B",X"56",X"57",X"21",
X"34",X"19",X"1B",X"1E",X"1B",X"20",X"1A",X"1F",X"1A",X"1E",X"1A",X"20",X"1D",X"83",X"04",X"04",
X"8B",X"1F",X"8A",X"88",X"86",X"82",X"19",X"1E",X"1D",X"1C",X"10",X"1B",X"1C",X"16",X"1D",X"1C",
X"1F",X"1A",X"1C",X"1B",X"1F",X"1A",X"1E",X"14",X"14",X"67",X"14",X"5F",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"13",X"1A",X"1E",X"19",X"1C",X"1E",
X"19",X"1D",X"1F",X"1B",X"1F",X"10",X"00",X"00",X"16",X"04",X"04",X"04",X"17",X"00",X"00",X"00",
X"00",X"00",X"17",X"04",X"04",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"04",X"0C",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"0C",
X"04",X"04",X"04",X"04",X"00",X"00",X"00",X"17",X"1C",X"16",X"1A",X"20",X"75",X"53",X"37",X"11",
X"35",X"20",X"1A",X"1D",X"1A",X"1F",X"19",X"1E",X"19",X"1D",X"19",X"1F",X"1C",X"84",X"04",X"04",
X"8C",X"1E",X"8B",X"04",X"04",X"83",X"20",X"1D",X"1C",X"20",X"1D",X"1B",X"1A",X"1E",X"1C",X"1B",
X"1E",X"19",X"1B",X"1A",X"1E",X"19",X"1B",X"19",X"1C",X"16",X"1C",X"1F",X"14",X"67",X"62",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"1B",X"1F",X"1A",X"1D",X"1F",
X"20",X"1C",X"19",X"1A",X"20",X"15",X"00",X"00",X"04",X"04",X"04",X"04",X"12",X"00",X"00",X"00",
X"00",X"00",X"18",X"04",X"01",X"01",X"04",X"01",X"01",X"01",X"17",X"00",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"04",X"2B",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"64",X"0C",X"04",X"64",X"17",X"1C",X"1C",X"16",X"1C",X"75",X"53",X"04",X"04",X"55",X"36",X"11",
X"36",X"1F",X"19",X"1C",X"19",X"1E",X"20",X"1D",X"20",X"1C",X"20",X"1E",X"1B",X"85",X"87",X"89",
X"8D",X"1D",X"8C",X"04",X"04",X"84",X"1F",X"1C",X"85",X"87",X"89",X"8D",X"20",X"1D",X"1B",X"1A",
X"1D",X"20",X"1A",X"19",X"1D",X"20",X"1A",X"20",X"82",X"86",X"88",X"8A",X"1D",X"19",X"1F",X"65",
X"62",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"12",X"20",X"1B",X"1E",X"20",
X"1F",X"1B",X"1C",X"1D",X"19",X"10",X"00",X"00",X"64",X"04",X"04",X"04",X"12",X"00",X"00",X"00",
X"00",X"03",X"04",X"03",X"00",X"00",X"62",X"02",X"02",X"64",X"16",X"00",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"2C",X"61",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",X"07",X"08",
X"00",X"00",X"51",X"52",X"16",X"20",X"1C",X"1F",X"1B",X"7C",X"04",X"04",X"04",X"7C",X"36",X"11",
X"37",X"1E",X"20",X"1B",X"20",X"1D",X"1F",X"1C",X"1F",X"1B",X"1F",X"1D",X"1A",X"20",X"1E",X"1D",
X"1B",X"1C",X"8D",X"89",X"87",X"85",X"1E",X"1B",X"84",X"04",X"04",X"8C",X"1F",X"1C",X"1A",X"19",
X"1C",X"1F",X"19",X"20",X"1C",X"1F",X"19",X"1F",X"83",X"04",X"04",X"8B",X"1C",X"20",X"1D",X"12",
X"1F",X"67",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"1C",X"1F",X"19",
X"1E",X"1A",X"19",X"1C",X"1A",X"16",X"17",X"00",X"13",X"04",X"04",X"04",X"64",X"14",X"14",X"14",
X"0C",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"17",X"04",X"03",X"00",X"00",X"0D",X"0A",
X"11",X"0A",X"13",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",
X"1C",X"1C",X"16",X"19",X"1C",X"1F",X"1B",X"1E",X"1A",X"7C",X"04",X"04",X"53",X"75",X"37",X"34",
X"19",X"1D",X"1F",X"1A",X"1F",X"1C",X"1E",X"1B",X"1E",X"1A",X"1E",X"1C",X"19",X"1F",X"1D",X"1C",
X"1A",X"1B",X"1F",X"1A",X"1C",X"1F",X"1D",X"1A",X"83",X"04",X"04",X"8B",X"1E",X"1B",X"19",X"20",
X"1B",X"1E",X"20",X"1F",X"1B",X"1E",X"20",X"1E",X"84",X"04",X"04",X"8C",X"1B",X"1F",X"1C",X"20",
X"16",X"17",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"15",X"1D",X"20",X"1A",
X"1D",X"20",X"1E",X"19",X"1B",X"1F",X"16",X"17",X"61",X"02",X"02",X"5F",X"08",X"08",X"07",X"18",
X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"04",X"0C",X"02",X"63",X"10",
X"11",X"10",X"63",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"16",X"1E",
X"1A",X"1C",X"1E",X"20",X"1B",X"1E",X"1A",X"1D",X"20",X"54",X"53",X"73",X"75",X"1C",X"32",X"34",
X"1F",X"1C",X"1E",X"19",X"70",X"73",X"73",X"73",X"74",X"74",X"73",X"70",X"20",X"1E",X"1C",X"1B",
X"19",X"1A",X"1E",X"19",X"1B",X"1E",X"1C",X"19",X"82",X"86",X"88",X"8A",X"1D",X"1A",X"20",X"1F",
X"1A",X"1D",X"1F",X"1E",X"1A",X"1D",X"1F",X"1D",X"85",X"87",X"89",X"8D",X"1A",X"1E",X"1B",X"1F",
X"1A",X"1C",X"16",X"1F",X"65",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"1E",X"1F",X"1B",
X"1C",X"1F",X"1A",X"20",X"1C",X"19",X"1D",X"12",X"00",X"00",X"07",X"08",X"07",X"07",X"61",X"64",
X"16",X"00",X"00",X"17",X"1C",X"17",X"1B",X"1C",X"1B",X"00",X"00",X"03",X"01",X"01",X"01",X"0E",
X"11",X"0E",X"2B",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"16",X"20",X"1D",X"1F",
X"19",X"1B",X"1D",X"1F",X"1A",X"1D",X"19",X"77",X"7B",X"73",X"75",X"1A",X"19",X"32",X"46",X"45",
X"33",X"31",X"30",X"30",X"46",X"45",X"5A",X"5D",X"5A",X"5A",X"5D",X"5B",X"74",X"70",X"1B",X"1A",
X"20",X"19",X"50",X"70",X"73",X"73",X"73",X"73",X"70",X"50",X"20",X"1E",X"1C",X"19",X"1F",X"1E",
X"19",X"1C",X"1E",X"1D",X"19",X"1C",X"1E",X"1C",X"1F",X"1D",X"20",X"1C",X"19",X"1D",X"1A",X"1E",
X"19",X"1B",X"1D",X"1E",X"1E",X"69",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"1F",X"1E",X"1C",
X"1B",X"1E",X"19",X"1B",X"1D",X"1A",X"1B",X"1C",X"28",X"64",X"02",X"02",X"02",X"02",X"64",X"64",
X"61",X"00",X"00",X"15",X"1C",X"19",X"1E",X"1C",X"1A",X"12",X"00",X"00",X"00",X"00",X"00",X"0A",
X"11",X"0A",X"13",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"12",X"1C",X"19",X"1D",X"19",X"1D",
X"1D",X"20",X"1A",X"77",X"75",X"75",X"76",X"73",X"75",X"19",X"1C",X"20",X"59",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"5A",X"5B",X"5C",X"5C",
X"5C",X"5B",X"5D",X"5A",X"5A",X"5B",X"5C",X"5B",X"5D",X"5B",X"74",X"70",X"1B",X"1F",X"1E",X"1C",
X"20",X"1A",X"19",X"1B",X"20",X"1B",X"20",X"1D",X"1C",X"19",X"1C",X"1E",X"1D",X"1C",X"20",X"1D",
X"1D",X"19",X"20",X"1C",X"13",X"17",X"17",X"00",X"00",X"00",X"00",X"00",X"19",X"20",X"1D",X"1D",
X"1A",X"1D",X"1F",X"1A",X"1E",X"19",X"20",X"1F",X"27",X"5E",X"01",X"01",X"01",X"04",X"5E",X"61",
X"00",X"00",X"00",X"1A",X"1B",X"20",X"1D",X"1B",X"19",X"1E",X"1C",X"1C",X"17",X"00",X"00",X"0A",
X"11",X"0A",X"0D",X"00",X"00",X"00",X"00",X"00",X"00",X"12",X"1D",X"1B",X"20",X"1C",X"20",X"1C",
X"1B",X"1C",X"78",X"75",X"77",X"77",X"1D",X"20",X"1E",X"1F",X"1B",X"59",X"52",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"5A",X"5D",X"5B",X"74",X"70",X"1B",
X"1F",X"1C",X"1D",X"20",X"1F",X"1A",X"19",X"1B",X"1F",X"1E",X"1B",X"1D",X"20",X"1D",X"1F",X"1C",
X"1E",X"1A",X"1D",X"1B",X"11",X"00",X"6B",X"00",X"00",X"00",X"00",X"00",X"12",X"19",X"1C",X"1E",
X"19",X"1C",X"1A",X"19",X"1F",X"1A",X"1B",X"1C",X"15",X"00",X"00",X"00",X"61",X"16",X"00",X"00",
X"00",X"00",X"00",X"10",X"1A",X"1F",X"1C",X"1A",X"20",X"1D",X"1B",X"19",X"1D",X"12",X"00",X"27",
X"11",X"0A",X"0D",X"00",X"00",X"00",X"00",X"00",X"18",X"1F",X"1C",X"1A",X"1F",X"1B",X"1F",X"1B",
X"1F",X"1E",X"79",X"1B",X"19",X"1F",X"1C",X"19",X"1D",X"59",X"53",X"54",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"5A",X"5D",X"5B",
X"74",X"73",X"74",X"01",X"74",X"73",X"70",X"1A",X"19",X"1F",X"1A",X"1F",X"1C",X"19",X"1E",X"1B",
X"1F",X"1B",X"1E",X"10",X"00",X"00",X"17",X"03",X"00",X"00",X"00",X"11",X"1F",X"1A",X"1B",X"1F",
X"1A",X"20",X"1B",X"1E",X"20",X"1F",X"1D",X"1E",X"10",X"00",X"00",X"5F",X"6A",X"61",X"00",X"00",
X"00",X"00",X"00",X"15",X"19",X"1E",X"1B",X"19",X"1F",X"1C",X"1A",X"20",X"1C",X"1A",X"00",X"00",
X"24",X"28",X"12",X"17",X"00",X"00",X"00",X"00",X"10",X"1E",X"1B",X"19",X"1E",X"1A",X"1E",X"1A",
X"19",X"75",X"7A",X"1E",X"1D",X"20",X"1B",X"57",X"58",X"52",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"5A",X"5D",X"5D",X"5D",X"5A",X"5A",X"5B",X"74",X"73",X"70",X"19",X"20",X"1B",X"20",X"1D",X"1A",
X"20",X"1C",X"16",X"17",X"00",X"00",X"00",X"03",X"17",X"00",X"00",X"12",X"20",X"1B",X"1A",X"20",
X"1B",X"1E",X"1F",X"1D",X"19",X"1E",X"1C",X"1F",X"2A",X"14",X"5E",X"5E",X"61",X"00",X"00",X"00",
X"00",X"00",X"00",X"17",X"16",X"1D",X"1A",X"20",X"1E",X"1B",X"19",X"1F",X"1B",X"16",X"00",X"00",
X"23",X"21",X"2E",X"65",X"5F",X"00",X"00",X"19",X"1A",X"1D",X"1A",X"20",X"1D",X"75",X"73",X"71",
X"75",X"7A",X"75",X"20",X"1F",X"1C",X"59",X"4F",X"51",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"5A",X"5D",X"5B",X"74",X"70",X"1B",X"1C",X"19",
X"70",X"71",X"51",X"00",X"00",X"5F",X"14",X"14",X"16",X"00",X"14",X"1B",X"1A",X"1C",X"19",X"19",
X"1C",X"1F",X"20",X"1C",X"1A",X"1D",X"20",X"19",X"29",X"14",X"5F",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"1B",X"16",X"1F",X"1D",X"1A",X"20",X"1E",X"1A",X"1E",X"10",X"00",
X"22",X"11",X"29",X"00",X"5F",X"67",X"02",X"5F",X"19",X"1C",X"19",X"1F",X"75",X"7B",X"75",X"19",
X"77",X"75",X"1D",X"19",X"57",X"58",X"4F",X"4F",X"4E",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"5A",X"5B",X"74",X"73",X"72",
X"5F",X"00",X"5F",X"14",X"14",X"5F",X"00",X"00",X"5F",X"5E",X"25",X"1F",X"1B",X"1D",X"20",X"1A",
X"1D",X"20",X"1A",X"19",X"1B",X"1C",X"1E",X"1A",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"16",X"19",X"1F",X"1D",X"19",X"1D",X"1F",X"11",
X"00",X"29",X"11",X"29",X"00",X"00",X"5F",X"5E",X"7D",X"1B",X"20",X"1E",X"7C",X"75",X"1D",X"20",
X"1A",X"1B",X"57",X"58",X"50",X"50",X"50",X"50",X"4D",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"4F",X"60",X"03",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"1B",X"20",X"1C",X"1E",X"1F",X"1B",
X"1E",X"19",X"1B",X"20",X"1C",X"19",X"1B",X"1F",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"1B",X"12",X"20",X"1C",X"1E",X"12",
X"00",X"00",X"29",X"11",X"29",X"00",X"14",X"1B",X"7D",X"7D",X"1E",X"1D",X"79",X"20",X"1C",X"1F",
X"20",X"56",X"47",X"47",X"47",X"47",X"47",X"47",X"48",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"52",X"4F",X"60",
X"5E",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"1A",X"19",X"1D",X"1F",X"1E",X"1B",
X"1F",X"1A",X"1C",X"1B",X"1D",X"20",X"1A",X"12",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"30",X"32",X"32",X"32",X"32",X"32",X"32",X"3A",X"37",X"18",X"1F",X"1B",X"1D",X"1A",
X"12",X"1B",X"17",X"29",X"11",X"22",X"15",X"1A",X"1F",X"70",X"76",X"76",X"75",X"1F",X"1B",X"1E",
X"55",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"4C",X"49",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"49",X"49",X"49",X"4C",X"50",X"50",
X"50",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"1A",X"1E",X"20",X"1D",X"1A",
X"20",X"1B",X"1D",X"1A",X"1E",X"1F",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"40",X"34",X"34",X"35",X"35",X"35",X"39",X"36",X"11",X"1E",X"1A",X"1C",X"20",
X"1A",X"1F",X"1C",X"10",X"29",X"21",X"14",X"19",X"1E",X"1A",X"1D",X"20",X"1B",X"1E",X"1A",X"56",
X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"4B",X"49",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"47",X"47",X"47",X"47",X"47",X"47",
X"47",X"04",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"1B",X"1F",X"19",X"1C",X"19",
X"19",X"1C",X"1E",X"19",X"1F",X"1E",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"3D",X"3F",X"44",X"35",X"35",X"35",X"34",X"36",X"13",X"1D",X"19",X"1B",X"1F",
X"19",X"1E",X"1B",X"1A",X"00",X"29",X"29",X"14",X"1D",X"19",X"1C",X"1F",X"1A",X"1D",X"19",X"47",
X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"48",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"49",X"49",X"47",X"47",X"47",X"47",X"47",X"47",
X"47",X"04",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"20",X"1A",X"1B",X"20",
X"1A",X"1D",X"1F",X"1D",X"20",X"1D",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"3B",X"3C",X"35",X"35",X"35",X"34",X"36",X"19",X"1C",X"20",X"1A",X"1E",
X"20",X"1D",X"1A",X"15",X"00",X"00",X"21",X"29",X"12",X"20",X"1B",X"10",X"10",X"1C",X"56",X"47",
X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"4C",X"49",X"49",X"49",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"4A",X"4A",X"47",X"47",X"47",X"47",X"47",X"47",
X"47",X"04",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"26",X"19",X"1B",X"1A",X"1F",
X"1B",X"1E",X"20",X"1C",X"19",X"1C",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"3D",X"3C",X"3B",X"35",X"35",X"35",X"38",X"36",X"15",X"1B",X"1F",X"19",X"1D",
X"1F",X"1C",X"19",X"19",X"00",X"00",X"22",X"11",X"29",X"1B",X"1B",X"48",X"59",X"58",X"47",X"47",
X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"4A",X"4A",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"49",X"47",X"47",X"47",X"47",X"47",X"47",
X"47",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"5F",X"5E",X"03",X"15",X"1A",X"1C",X"19",X"1E",
X"1C",X"1F",X"19",X"1F",X"1A",X"1B",X"19",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"33",X"34",X"35",X"35",X"35",X"39",X"36",X"19",X"1A",X"1E",X"20",X"1C",
X"1E",X"1B",X"20",X"00",X"00",X"00",X"00",X"29",X"2A",X"44",X"44",X"2A",X"5A",X"5B",X"5C",X"47",
X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"48",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"49",X"49",X"47",X"47",X"47",X"47",X"47",X"47",X"47",
X"47",X"16",X"00",X"00",X"00",X"00",X"5F",X"5E",X"5E",X"5F",X"00",X"15",X"1B",X"1D",X"20",X"1D",
X"1D",X"20",X"1A",X"1E",X"1B",X"1F",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"33",X"34",X"35",X"35",X"35",X"39",X"36",X"00",X"1A",X"1D",X"1F",X"1B",
X"1D",X"16",X"1B",X"00",X"00",X"00",X"00",X"00",X"45",X"45",X"48",X"40",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"45",X"46",X"45",X"46",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",X"47",
X"2F",X"17",X"00",X"00",X"5F",X"5E",X"5E",X"5F",X"00",X"00",X"00",X"15",X"1C",X"1E",X"1F",X"1C",
X"1E",X"19",X"1C",X"1B",X"1C",X"19",X"12",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"33",X"34",X"35",X"35",X"35",X"39",X"36",X"00",X"17",X"16",X"19",X"1A",
X"1B",X"00",X"00",X"00",X"A5",X"A5",X"00",X"00",X"00",X"00",X"00",X"00",X"48",X"40",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"46",X"45",X"46",X"45",X"46",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"47",X"47",X"47",X"47",X"47",X"2F",
X"04",X"5E",X"5E",X"5E",X"02",X"5F",X"00",X"00",X"00",X"00",X"13",X"1D",X"1D",X"1F",X"1E",X"1B",
X"1F",X"1A",X"1D",X"1A",X"1D",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"33",X"34",X"35",X"35",X"35",X"39",X"36",X"00",X"00",X"00",X"1B",X"1C",
X"00",X"00",X"A5",X"A6",X"A0",X"A0",X"A6",X"A7",X"A5",X"00",X"00",X"00",X"00",X"00",X"48",X"48",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"52",X"4F",X"4F",X"60",X"04",
X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"1C",X"1E",X"20",X"1D",X"1A",
X"20",X"1B",X"1F",X"19",X"1E",X"1C",X"15",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"33",X"34",X"35",X"35",X"35",X"39",X"36",X"00",X"00",X"00",X"00",X"00",
X"00",X"A4",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A7",X"A5",X"00",X"00",X"00",X"00",
X"00",X"00",X"40",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"52",X"4F",X"4F",X"60",X"03",X"03",
X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"1B",X"1D",X"1F",X"1C",X"19",
X"19",X"1C",X"19",X"20",X"1F",X"1D",X"19",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"3D",X"3F",X"35",X"35",X"35",X"38",X"36",X"00",X"00",X"00",X"00",X"00",
X"A2",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A5",X"00",X"00",
X"00",X"00",X"00",X"45",X"47",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"45",X"45",X"54",X"53",X"4F",X"4F",X"60",X"03",X"00",X"00",
X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"12",X"1A",X"1C",X"1E",X"1B",X"20",
X"1A",X"1D",X"1A",X"1E",X"20",X"12",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"42",X"34",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"00",X"00",X"00",
X"A1",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A8",
X"A9",X"00",X"00",X"00",X"00",X"00",X"40",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",
X"46",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",
X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"52",X"4F",X"6C",X"6D",X"6E",X"5F",X"00",X"00",X"00",
X"00",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"1E",X"19",X"1B",X"1D",X"1A",X"1F",
X"1B",X"1E",X"1B",X"1D",X"19",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"3B",X"43",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"00",X"00",X"A2",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A6",X"A5",X"00",X"00",X"00",X"00",X"41",X"42",X"46",X"44",X"43",X"45",X"48",X"48",X"45",
X"47",X"45",X"48",X"45",X"49",X"4A",X"48",X"45",X"47",X"43",X"44",X"46",X"45",X"46",X"45",X"46",
X"45",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"47",X"43",X"43",X"47",X"43",
X"43",X"47",X"47",X"43",X"43",X"47",X"6F",X"6E",X"14",X"5F",X"00",X"1B",X"16",X"10",X"1B",X"1B",
X"00",X"00",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"19",X"1D",X"20",X"1A",X"1C",X"19",X"1E",
X"1C",X"1F",X"1D",X"1C",X"1A",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"34",X"3B",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"00",X"00",X"A3",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A6",X"A5",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"4B",X"4C",X"00",X"00",X"00",X"00",X"00",X"45",X"47",X"43",X"44",X"44",
X"44",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"47",X"45",X"00",X"00",X"00",X"17",X"16",X"1C",
X"13",X"00",X"07",X"07",X"08",X"03",X"16",X"00",X"17",X"1C",X"16",X"1F",X"1D",X"1A",X"20",X"1E",
X"17",X"00",X"16",X"03",X"00",X"00",X"00",X"00",X"00",X"15",X"1C",X"1F",X"19",X"1B",X"20",X"1D",
X"1D",X"20",X"1E",X"19",X"1A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"33",X"34",X"34",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"00",X"00",X"A1",
X"A0",X"A0",X"A0",X"A0",X"A0",X"C3",X"DF",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"BA",X"A0",X"A4",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"4E",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"48",X"45",X"43",X"43",X"47",X"45",X"00",X"00",X"00",X"03",X"64",X"02",X"1F",X"1C",X"1B",
X"5F",X"02",X"5E",X"5E",X"0C",X"64",X"61",X"00",X"15",X"1A",X"1F",X"1D",X"1C",X"19",X"1F",X"1D",
X"20",X"17",X"17",X"04",X"03",X"00",X"00",X"00",X"00",X"14",X"1B",X"1E",X"20",X"1A",X"1F",X"1C",
X"1E",X"1A",X"1C",X"20",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"3E",X"3B",X"34",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"00",X"A2",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"C1",X"CF",X"D3",X"A0",X"A0",X"A0",X"A0",X"F7",X"FD",X"01",X"03",
X"07",X"A0",X"A0",X"BB",X"BA",X"A0",X"A6",X"A5",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"4D",X"47",X"46",X"46",X"45",X"46",X"45",X"45",X"4D",X"00",X"62",X"02",X"5E",X"04",X"5E",
X"02",X"02",X"5F",X"5F",X"62",X"00",X"00",X"03",X"0C",X"5E",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"18",X"00",X"00",X"15",X"20",X"1E",X"1C",X"1B",X"20",X"1E",X"1C",
X"1F",X"17",X"00",X"09",X"03",X"03",X"00",X"00",X"00",X"11",X"1A",X"1D",X"1F",X"19",X"1E",X"1B",
X"1F",X"1B",X"20",X"1F",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"3E",X"3C",X"3B",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"00",X"A3",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"C1",X"CD",X"D5",X"C3",X"DF",X"ED",X"EF",X"F5",X"FB",X"FF",X"06",
X"02",X"A0",X"BB",X"BA",X"BB",X"BA",X"A0",X"A0",X"A6",X"A5",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"4B",X"45",X"46",X"45",X"46",X"45",X"46",X"45",X"49",X"00",X"09",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"0C",X"0C",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"03",X"00",X"14",X"1F",X"1D",X"1B",X"1A",X"1F",X"1D",X"1B",
X"1E",X"1C",X"11",X"16",X"00",X"03",X"03",X"00",X"00",X"13",X"19",X"1C",X"1E",X"20",X"1D",X"1A",
X"20",X"1C",X"19",X"1D",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"3E",X"3B",X"3C",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"00",X"A1",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"C1",X"CD",X"D5",X"C1",X"CF",X"E9",X"EB",X"F3",X"F9",X"05",X"FE",
X"00",X"A0",X"A0",X"BB",X"BA",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A5",X"00",X"00",X"00",X"00",
X"00",X"4B",X"46",X"45",X"46",X"45",X"46",X"45",X"46",X"4E",X"17",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"03",X"11",X"1E",X"1C",X"1A",X"20",X"1E",X"1C",X"1A",
X"1D",X"1B",X"11",X"13",X"17",X"00",X"03",X"03",X"00",X"19",X"20",X"1B",X"1D",X"1F",X"1C",X"19",
X"19",X"1D",X"1A",X"1C",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"31",X"3E",X"34",X"3B",X"35",X"35",X"35",X"34",X"36",X"00",X"00",X"A2",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"BF",X"C9",X"D5",X"C1",X"CD",X"E5",X"E7",X"F1",X"04",X"F8",X"FA",
X"FC",X"A0",X"A0",X"A0",X"BB",X"BA",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A5",X"00",X"00",
X"00",X"4D",X"46",X"46",X"45",X"46",X"45",X"46",X"45",X"4B",X"13",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"17",X"12",X"1B",X"19",X"1F",X"1D",X"1B",X"19",
X"1C",X"1A",X"17",X"17",X"13",X"00",X"00",X"03",X"03",X"14",X"1F",X"1A",X"1C",X"1E",X"1B",X"20",
X"1A",X"1E",X"1D",X"1B",X"19",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"30",X"41",X"32",X"32",X"32",X"32",X"32",X"32",X"37",X"00",X"00",X"A3",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"BB",X"BD",X"CB",X"D7",X"CD",X"E5",X"E3",X"A0",X"F0",X"F2",X"F4",
X"F6",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"0B",X"A0",X"A0",X"A0",X"A0",X"A6",X"A5",
X"00",X"00",X"00",X"40",X"46",X"45",X"46",X"45",X"49",X"4D",X"15",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"64",X"11",X"1A",X"20",X"1E",X"1C",X"1A",X"20",
X"1B",X"19",X"12",X"00",X"13",X"00",X"00",X"00",X"03",X"03",X"1E",X"19",X"1B",X"1D",X"1A",X"1F",
X"1B",X"19",X"1C",X"20",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A1",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"BB",X"BA",X"C6",X"C7",X"E1",X"A0",X"E2",X"E6",X"EA",X"EE",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"0A",X"0C",X"0B",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A4",X"00",X"00",X"00",X"45",X"45",X"45",X"45",X"00",X"00",X"15",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"09",X"11",X"19",X"1F",X"1D",X"1B",X"19",X"1F",
X"1A",X"20",X"1E",X"11",X"0D",X"00",X"00",X"00",X"00",X"7E",X"1D",X"20",X"1A",X"1C",X"19",X"1E",
X"1C",X"20",X"1B",X"1F",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A2",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"BB",X"BA",X"A0",X"A0",X"E0",X"E4",X"E4",X"E8",X"EC",
X"A0",X"A0",X"D8",X"D9",X"A0",X"A0",X"0B",X"08",X"09",X"0D",X"0F",X"0B",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A4",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"17",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"09",X"19",X"20",X"1E",X"1C",X"1A",X"20",X"1E",
X"19",X"1F",X"1D",X"13",X"16",X"00",X"00",X"00",X"00",X"15",X"1C",X"1F",X"19",X"1B",X"20",X"1D",
X"1D",X"1F",X"19",X"1E",X"12",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A3",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"B9",X"A0",X"A0",X"C5",X"CC",X"CC",X"CE",X"DE",
X"A0",X"A0",X"DB",X"DA",X"DA",X"A0",X"A0",X"0E",X"0D",X"0E",X"EF",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A6",X"A5",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"62",X"02",X"02",X"62",X"03",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"09",X"15",X"1F",X"1D",X"1B",X"19",X"1F",X"1D",
X"20",X"1E",X"1C",X"11",X"16",X"61",X"00",X"00",X"17",X"1A",X"1B",X"1E",X"20",X"1A",X"1F",X"1C",
X"1E",X"1E",X"20",X"1D",X"1A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A1",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"B7",X"B3",X"B8",X"BA",X"C4",X"D6",X"C0",X"C0",X"C2",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"0E",X"A0",X"A0",X"A0",X"A0",X"A0",X"B0",X"B4",
X"A0",X"A0",X"A0",X"A0",X"AA",X"AB",X"A8",X"A9",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"62",X"02",X"0C",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"03",X"15",X"1E",X"1C",X"1A",X"20",X"1E",X"1C",
X"1F",X"1D",X"1B",X"11",X"13",X"16",X"00",X"00",X"15",X"20",X"1A",X"1D",X"1F",X"19",X"1E",X"1B",
X"1F",X"1D",X"19",X"1B",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A2",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"B5",X"B2",X"B6",X"A0",X"BB",X"BA",X"CA",X"D4",X"D4",X"D4",
X"D2",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"BB",X"A0",X"A0",X"A0",X"A0",X"BB",X"BA",X"B5",X"B1",
X"B4",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A8",X"A9",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"62",X"02",X"0C",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"16",X"00",X"12",X"1D",X"1B",X"19",X"1F",X"1D",X"1B",
X"1E",X"1C",X"1A",X"19",X"17",X"04",X"5E",X"5F",X"1A",X"1F",X"19",X"1C",X"1E",X"20",X"1D",X"1A",
X"20",X"1C",X"20",X"1A",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A3",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"B5",X"B1",X"B4",X"A0",X"A0",X"A0",X"BB",X"BC",X"C8",X"CC",X"CC",
X"CE",X"DE",X"A0",X"A0",X"A0",X"A0",X"BB",X"BA",X"A0",X"A0",X"A0",X"BB",X"BA",X"A0",X"A0",X"B5",
X"B2",X"DD",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A8",X"A9",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"62",X"0C",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"17",X"19",X"1B",X"1C",X"1A",X"20",X"1E",X"1C",X"1A",
X"1D",X"1B",X"19",X"10",X"00",X"16",X"61",X"81",X"19",X"1E",X"20",X"1B",X"1D",X"1F",X"1C",X"19",
X"19",X"20",X"1E",X"19",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A2",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"B0",X"B4",X"A0",X"A0",X"A0",X"A0",X"A0",X"BB",X"BE",X"C0",X"C0",
X"C0",X"C2",X"A0",X"A0",X"A0",X"BB",X"BA",X"A0",X"A0",X"A0",X"BB",X"BA",X"A0",X"A0",X"A0",X"A0",
X"B7",X"DC",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A6",X"A8",
X"A9",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"04",X"04",X"04",X"04",X"04",X"04",X"04",
X"04",X"04",X"04",X"04",X"04",X"5E",X"5F",X"17",X"16",X"1A",X"1B",X"19",X"1F",X"1D",X"1B",X"19",
X"1C",X"1A",X"20",X"1E",X"11",X"0D",X"13",X"19",X"20",X"1D",X"1F",X"1A",X"1C",X"1E",X"1B",X"20",
X"AC",X"AD",X"AE",X"AF",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A1",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"BA",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",X"A0",
X"A0",X"A4",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"5E",X"01",X"01",X"01",X"04",X"04",X"04",
X"04",X"04",X"04",X"64",X"62",X"00",X"17",X"16",X"1A",X"19",X"1A",X"20",X"1E",X"1C",X"1A",X"20",
X"1B",X"19",X"1F",X"1D",X"11",X"13",X"17",X"10",X"1F",X"1C",X"1E",X"19",X"1B",X"1D",X"1A",X"1F");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

278
Arcade_MiST/Galaga Hardware/Xevious_MiST/rtl/roms/terrain_2c.vhd Normal file
View File

@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity terrain_2c is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of terrain_2c is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"10",X"50",X"50",X"00",X"00",X"00",X"10",X"10",X"10",
X"10",X"10",X"10",X"10",X"08",X"08",X"08",X"08",X"04",X"04",X"04",X"04",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"10",X"00",X"04",X"00",X"04",X"04",X"04",X"04",X"04",
X"00",X"10",X"10",X"10",X"90",X"00",X"90",X"00",X"10",X"04",X"10",X"04",X"10",X"50",X"10",X"90",
X"50",X"44",X"00",X"04",X"84",X"C4",X"04",X"44",X"00",X"10",X"00",X"10",X"00",X"10",X"00",X"10",
X"00",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"10",X"00",X"10",
X"00",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"10",X"5C",X"D0",X"00",X"C0",X"5C",X"10",X"90",X"9C",X"9C",X"80",X"C0",
X"00",X"50",X"40",X"10",X"10",X"5C",X"5C",X"40",X"1C",X"C0",X"5C",X"40",X"5C",X"50",X"00",X"C0",
X"DC",X"10",X"DC",X"10",X"9C",X"50",X"40",X"00",X"80",X"80",X"1C",X"10",X"10",X"10",X"10",X"10",
X"10",X"10",X"10",X"10",X"9C",X"10",X"9C",X"10",X"00",X"50",X"00",X"00",X"02",X"30",X"30",X"10",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"02",X"00",
X"00",X"00",X"00",X"00",X"02",X"06",X"02",X"06",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",
X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"00",
X"02",X"02",X"C2",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"00",
X"00",X"00",X"02",X"00",X"02",X"02",X"00",X"00",X"02",X"00",X"C2",X"02",X"02",X"00",X"C2",X"02",
X"02",X"02",X"00",X"82",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"02",X"02",X"02",X"02",
X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"02",X"02",X"04",X"04",X"02",X"04",X"02",X"04",
X"04",X"04",X"04",X"04",X"06",X"04",X"06",X"04",X"04",X"06",X"04",X"06",X"04",X"04",X"04",X"04",
X"04",X"04",X"0A",X"0A",X"04",X"06",X"04",X"06",X"04",X"06",X"06",X"04",X"04",X"04",X"06",X"06",
X"06",X"06",X"04",X"04",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"02",X"00",X"00",X"08",X"08",
X"08",X"08",X"04",X"04",X"00",X"08",X"08",X"04",X"8C",X"8C",X"04",X"04",X"10",X"10",X"8C",X"8C",
X"10",X"10",X"0C",X"8C",X"8C",X"0C",X"04",X"04",X"10",X"10",X"D0",X"D0",X"D0",X"D0",X"00",X"00",
X"90",X"0C",X"08",X"90",X"00",X"00",X"90",X"00",X"00",X"00",X"10",X"10",X"90",X"00",X"10",X"10",
X"10",X"10",X"50",X"10",X"10",X"10",X"50",X"10",X"D0",X"D0",X"90",X"00",X"10",X"10",X"D0",X"D0",
X"90",X"00",X"50",X"90",X"10",X"90",X"50",X"90",X"10",X"10",X"10",X"D0",X"50",X"90",X"50",X"90",
X"08",X"08",X"D0",X"D0",X"12",X"12",X"50",X"50",X"D0",X"D0",X"50",X"50",X"C6",X"C6",X"90",X"90",
X"00",X"00",X"1C",X"1C",X"1C",X"9C",X"50",X"50",X"1C",X"1C",X"50",X"50",X"1C",X"9C",X"10",X"10",
X"9C",X"9C",X"10",X"10",X"00",X"00",X"1C",X"00",X"1C",X"1C",X"DC",X"DC",X"10",X"5C",X"1C",X"00",
X"00",X"9C",X"9C",X"5C",X"DC",X"1C",X"DC",X"1C",X"9C",X"10",X"9C",X"5C",X"9C",X"10",X"10",X"5C",
X"5C",X"10",X"1C",X"10",X"1C",X"00",X"10",X"1C",X"50",X"1C",X"00",X"1C",X"10",X"1C",X"50",X"1C",
X"00",X"C0",X"5C",X"C0",X"5C",X"40",X"1C",X"40",X"00",X"20",X"00",X"00",X"00",X"20",X"00",X"20",
X"40",X"20",X"00",X"20",X"00",X"00",X"40",X"20",X"20",X"20",X"40",X"40",X"00",X"00",X"20",X"20",
X"20",X"20",X"00",X"40",X"00",X"00",X"20",X"20",X"20",X"40",X"40",X"40",X"20",X"C0",X"20",X"00",
X"20",X"00",X"20",X"80",X"40",X"C0",X"20",X"A0",X"00",X"82",X"00",X"82",X"02",X"82",X"02",X"82",
X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",
X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",
X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",
X"06",X"06",X"06",X"06",X"0A",X"0A",X"0A",X"0A",X"0A",X"0A",X"0A",X"0A",X"00",X"0A",X"00",X"0A",
X"01",X"01",X"01",X"01",X"A8",X"01",X"A8",X"01",X"28",X"A8",X"00",X"A8",X"A8",X"01",X"A8",X"01",
X"00",X"E8",X"E8",X"01",X"00",X"00",X"68",X"68",X"68",X"68",X"01",X"01",X"68",X"68",X"01",X"01",
X"00",X"00",X"E8",X"E8",X"00",X"00",X"E8",X"E8",X"E8",X"E8",X"01",X"01",X"E8",X"E8",X"01",X"01",
X"00",X"00",X"1C",X"1C",X"00",X"00",X"1C",X"1C",X"00",X"00",X"1C",X"1C",X"00",X"00",X"1C",X"1C",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"C1",X"01",X"01",X"01",X"C1",X"01",X"01",X"01",X"C1",
X"C1",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"C1",X"01",X"01",X"01",X"C1",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"41",X"01",X"01",X"01",X"01",X"01",X"01",X"C1",X"01",X"01",
X"01",X"01",X"01",X"01",X"C1",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"41",X"01",X"01",X"01",X"41",X"01",
X"41",X"41",X"01",X"01",X"01",X"81",X"01",X"81",X"01",X"01",X"01",X"81",X"41",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"C1",X"01",X"01",X"01",X"C1",X"01",X"01",X"C1",X"01",X"01",X"01",X"C1",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"C1",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"81",X"01",X"81",X"81",X"81",X"01",X"01",X"81",X"81",X"01",X"01",X"01",X"01",
X"81",X"01",X"81",X"81",X"81",X"81",X"81",X"81",X"41",X"81",X"01",X"41",X"81",X"01",X"81",X"01",
X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"40",X"00",X"00",
X"00",X"C0",X"00",X"00",X"00",X"80",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",
X"00",X"80",X"00",X"00",X"00",X"40",X"00",X"40",X"00",X"40",X"40",X"00",X"00",X"40",X"40",X"00",
X"00",X"00",X"00",X"40",X"00",X"1C",X"10",X"5C",X"1C",X"50",X"00",X"1C",X"D0",X"D0",X"1C",X"1C",
X"00",X"44",X"00",X"04",X"04",X"04",X"04",X"04",X"00",X"04",X"00",X"04",X"04",X"04",X"04",X"04",
X"04",X"C4",X"04",X"C4",X"44",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"00",X"04",X"00",X"04",
X"00",X"04",X"00",X"04",X"04",X"04",X"00",X"04",X"04",X"04",X"04",X"04",X"00",X"04",X"00",X"04",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"14",X"54",X"04",X"04",X"14",X"54",X"04",X"04",X"00",X"94",X"54",X"04",X"14",X"14",X"04",X"04",
X"04",X"14",X"04",X"14",X"14",X"00",X"94",X"00",X"14",X"00",X"14",X"00",X"D4",X"00",X"94",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"04",X"20",X"20",X"C0",X"20",X"20",X"00",X"40",X"20",X"20",X"00",X"40",X"04",X"04",X"20",X"20",
X"04",X"04",X"20",X"20",X"20",X"20",X"40",X"00",X"04",X"04",X"20",X"20",X"04",X"04",X"20",X"A0",
X"20",X"A0",X"00",X"40",X"04",X"04",X"04",X"20",X"C4",X"20",X"20",X"C0",X"04",X"60",X"04",X"20",
X"20",X"00",X"60",X"00",X"20",X"40",X"00",X"C0",X"A0",X"04",X"E0",X"04",X"00",X"00",X"00",X"00",
X"00",X"00",X"1C",X"9C",X"50",X"50",X"00",X"9C",X"D0",X"00",X"9C",X"00",X"9C",X"10",X"10",X"10",
X"00",X"DC",X"1C",X"9C",X"10",X"5C",X"90",X"00",X"9C",X"1C",X"00",X"9C",X"5C",X"1C",X"5C",X"1C",
X"00",X"2C",X"02",X"02",X"00",X"00",X"AC",X"2C",X"0E",X"0E",X"04",X"04",X"02",X"02",X"04",X"44",
X"02",X"02",X"0E",X"0E",X"00",X"00",X"18",X"18",X"50",X"10",X"9C",X"DC",X"5C",X"00",X"9C",X"9C",
X"04",X"16",X"16",X"00",X"44",X"44",X"96",X"16",X"44",X"44",X"16",X"00",X"16",X"16",X"16",X"16",
X"16",X"96",X"16",X"16",X"00",X"84",X"16",X"04",X"16",X"16",X"16",X"16",X"26",X"26",X"1A",X"1A",
X"16",X"16",X"00",X"00",X"1A",X"1A",X"1A",X"1A",X"00",X"00",X"1A",X"16",X"1A",X"1A",X"1A",X"1A",
X"9A",X"1A",X"1A",X"16",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",
X"00",X"16",X"D6",X"84",X"16",X"00",X"1A",X"1A",X"1A",X"16",X"16",X"16",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"05",X"01",X"01",X"01",X"05",X"05",X"05",X"01",
X"05",X"01",X"01",X"01",X"05",X"05",X"01",X"05",X"01",X"01",X"01",X"01",X"05",X"05",X"01",X"05",
X"01",X"01",X"09",X"01",X"01",X"01",X"01",X"01",X"41",X"01",X"45",X"01",X"09",X"01",X"09",X"01",
X"41",X"41",X"41",X"45",X"01",X"01",X"01",X"01",X"4D",X"01",X"4D",X"01",X"0D",X"0D",X"11",X"01",
X"01",X"01",X"0D",X"01",X"89",X"11",X"89",X"11",X"01",X"0D",X"11",X"0D",X"01",X"01",X"01",X"4D",
X"41",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"01",X"01",X"01",X"15",X"15",X"0D",X"C1",
X"09",X"01",X"09",X"41",X"09",X"01",X"09",X"01",X"01",X"01",X"01",X"41",X"01",X"01",X"09",X"09",
X"C5",X"C5",X"11",X"11",X"01",X"01",X"01",X"01",X"01",X"09",X"01",X"09",X"09",X"01",X"09",X"09",
X"01",X"41",X"09",X"41",X"01",X"01",X"01",X"01",X"81",X"05",X"41",X"81",X"01",X"05",X"01",X"09",
X"01",X"01",X"01",X"01",X"81",X"05",X"01",X"01",X"01",X"CD",X"C5",X"01",X"01",X"01",X"C5",X"15",
X"01",X"01",X"15",X"01",X"41",X"01",X"01",X"01",X"01",X"01",X"81",X"01",X"01",X"81",X"01",X"C1",
X"01",X"01",X"01",X"41",X"01",X"41",X"01",X"01",X"01",X"01",X"05",X"01",X"01",X"01",X"C1",X"01",
X"05",X"01",X"01",X"05",X"81",X"01",X"01",X"C1",X"01",X"01",X"01",X"41",X"41",X"01",X"41",X"01",
X"01",X"01",X"0D",X"01",X"01",X"01",X"11",X"01",X"01",X"15",X"01",X"91",X"01",X"41",X"41",X"01",
X"01",X"01",X"11",X"01",X"C1",X"01",X"01",X"81",X"01",X"01",X"41",X"41",X"01",X"01",X"01",X"01",
X"01",X"41",X"01",X"01",X"41",X"41",X"11",X"41",X"41",X"41",X"8D",X"11",X"41",X"51",X"11",X"C5",
X"81",X"05",X"01",X"81",X"01",X"01",X"01",X"41",X"15",X"C1",X"09",X"01",X"01",X"41",X"01",X"01",
X"41",X"01",X"41",X"01",X"41",X"01",X"01",X"01",X"01",X"01",X"01",X"41",X"09",X"01",X"09",X"01",
X"01",X"01",X"01",X"01",X"05",X"05",X"01",X"01",X"41",X"01",X"41",X"01",X"01",X"01",X"01",X"01",
X"01",X"CD",X"01",X"01",X"01",X"01",X"01",X"CD",X"01",X"01",X"01",X"01",X"01",X"CD",X"01",X"01",
X"05",X"05",X"01",X"01",X"01",X"01",X"4D",X"81",X"0D",X"4D",X"01",X"01",X"01",X"01",X"4D",X"01",
X"01",X"01",X"05",X"0D",X"4D",X"01",X"0D",X"11",X"01",X"09",X"01",X"01",X"01",X"01",X"CD",X"CD",
X"01",X"01",X"01",X"0D",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"41",X"01",X"01",X"01",X"01",X"01",X"09",X"01",X"01",X"09",X"01",X"01",X"01",X"01",
X"01",X"01",X"09",X"01",X"01",X"01",X"01",X"01",X"09",X"01",X"09",X"01",X"01",X"01",X"01",X"41",
X"15",X"41",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"41",X"09",X"01",X"01",X"01",X"01",X"01",
X"01",X"01",X"09",X"01",X"01",X"01",X"41",X"01",X"01",X"09",X"01",X"09",X"01",X"01",X"01",X"41",
X"01",X"09",X"01",X"09",X"09",X"01",X"09",X"01",X"C1",X"C1",X"01",X"09",X"01",X"01",X"01",X"01",
X"01",X"01",X"01",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"01",
X"09",X"01",X"09",X"41",X"CD",X"CD",X"01",X"01",X"01",X"01",X"19",X"19",X"CD",X"01",X"19",X"01",
X"01",X"01",X"01",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"81",X"01",X"01",X"81",
X"01",X"01",X"01",X"01",X"05",X"05",X"01",X"81",X"01",X"01",X"09",X"41",X"09",X"09",X"01",X"09",
X"09",X"01",X"09",X"01",X"09",X"09",X"01",X"09",X"C1",X"01",X"41",X"01",X"41",X"01",X"41",X"41",
X"41",X"01",X"81",X"01",X"01",X"01",X"09",X"01",X"01",X"01",X"41",X"01",X"41",X"01",X"41",X"01",
X"00",X"01",X"02",X"03",X"2A",X"2A",X"24",X"24",X"2A",X"2A",X"02",X"03",X"00",X"28",X"28",X"24",
X"24",X"24",X"24",X"24",X"10",X"11",X"12",X"13",X"10",X"11",X"12",X"13",X"81",X"83",X"80",X"82",
X"85",X"87",X"84",X"86",X"25",X"24",X"25",X"24",X"00",X"3B",X"02",X"3B",X"44",X"44",X"44",X"44",
X"00",X"28",X"2A",X"24",X"25",X"01",X"25",X"03",X"2A",X"39",X"24",X"3A",X"24",X"2A",X"24",X"28",
X"2A",X"39",X"02",X"3B",X"44",X"44",X"44",X"44",X"00",X"26",X"02",X"25",X"00",X"25",X"02",X"25",
X"00",X"01",X"2A",X"2A",X"27",X"24",X"2F",X"24",X"27",X"24",X"26",X"24",X"00",X"27",X"02",X"26",
X"00",X"25",X"28",X"24",X"89",X"8B",X"88",X"8A",X"8D",X"8F",X"8C",X"8E",X"91",X"93",X"90",X"92",
X"95",X"97",X"94",X"96",X"99",X"9B",X"98",X"9A",X"9D",X"9F",X"9C",X"9E",X"A1",X"A3",X"A0",X"A2",
X"A5",X"A7",X"A4",X"A6",X"24",X"4A",X"28",X"A9",X"03",X"50",X"28",X"32",X"52",X"49",X"A8",X"03",
X"AD",X"26",X"AD",X"31",X"2A",X"4A",X"4A",X"A8",X"49",X"AD",X"48",X"AE",X"58",X"2A",X"AD",X"03",
X"49",X"2A",X"53",X"24",X"53",X"2A",X"AD",X"02",X"A9",X"A8",X"58",X"2A",X"2A",X"24",X"24",X"24",
X"25",X"24",X"24",X"24",X"4A",X"2A",X"49",X"24",X"00",X"27",X"02",X"03",X"C8",X"D0",X"D0",X"24",
X"01",X"05",X"03",X"04",X"01",X"05",X"03",X"05",X"07",X"07",X"06",X"06",X"0A",X"07",X"0A",X"07",
X"07",X"07",X"07",X"07",X"0C",X"0D",X"0C",X"0D",X"07",X"05",X"07",X"05",X"05",X"07",X"04",X"06",
X"0E",X"07",X"0C",X"0E",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"06",X"06",X"07",X"07",X"0B",X"07",
X"0A",X"0B",X"0B",X"0A",X"0A",X"0A",X"0A",X"07",X"0A",X"0A",X"0A",X"0A",X"0A",X"0A",X"07",X"07",
X"07",X"07",X"0A",X"07",X"0A",X"0A",X"06",X"06",X"0A",X"07",X"0B",X"0B",X"0B",X"07",X"0B",X"0A",
X"0A",X"0A",X"07",X"0B",X"C0",X"C1",X"C2",X"C3",X"C4",X"C5",X"C6",X"C7",X"C8",X"C8",X"C8",X"C8",
X"C9",X"C2",X"C9",X"C0",X"C0",X"C4",X"CA",X"CA",X"C8",X"C8",X"C2",X"C5",X"C8",X"C9",X"C8",X"CB",
X"C9",X"C0",X"CB",X"CA",X"CD",X"C0",X"CC",X"C5",X"C8",X"CD",X"C8",X"CC",X"C8",X"C8",X"C8",X"C8",
X"C8",X"C8",X"CE",X"CE",X"C8",X"CF",X"C8",X"CF",X"C8",X"D0",X"D0",X"C0",X"C8",X"C8",X"D1",X"D2",
X"D1",X"D2",X"C2",X"C4",X"D3",X"D4",X"C8",X"C8",X"90",X"D5",X"D5",X"C8",X"98",X"A0",X"D3",X"D4",
X"D3",X"D4",X"C8",X"C8",X"93",X"D5",X"D5",X"C8",X"D2",X"D1",X"C0",X"C2",X"24",X"24",X"D2",X"D1",
X"24",X"24",X"D6",X"D6",X"D6",X"D6",X"C2",X"C5",X"24",X"24",X"2C",X"2B",X"2C",X"2B",X"00",X"00",
X"D0",X"C8",X"C8",X"D0",X"00",X"02",X"28",X"01",X"00",X"02",X"28",X"2A",X"25",X"02",X"24",X"2A",
X"24",X"24",X"28",X"24",X"2B",X"2C",X"28",X"24",X"2C",X"2B",X"28",X"00",X"2B",X"2C",X"2C",X"2B",
X"28",X"00",X"28",X"28",X"24",X"27",X"28",X"26",X"28",X"24",X"24",X"28",X"26",X"27",X"27",X"26",
X"C8",X"C8",X"D2",X"D1",X"D6",X"D6",X"2A",X"2A",X"D2",X"D1",X"2B",X"2C",X"D2",X"D1",X"2C",X"2B",
X"88",X"8A",X"45",X"46",X"47",X"47",X"24",X"24",X"45",X"46",X"2B",X"2C",X"47",X"47",X"24",X"24",
X"46",X"45",X"24",X"24",X"89",X"8B",X"48",X"8A",X"45",X"46",X"46",X"45",X"24",X"48",X"47",X"8E",
X"8D",X"48",X"48",X"48",X"49",X"4A",X"4A",X"49",X"4A",X"24",X"49",X"48",X"48",X"24",X"24",X"48",
X"4B",X"24",X"4B",X"24",X"48",X"8B",X"24",X"48",X"28",X"51",X"00",X"50",X"24",X"53",X"2A",X"52",
X"A9",X"9F",X"50",X"B3",X"49",X"A9",X"50",X"AE",X"91",X"DC",X"95",X"90",X"A1",X"DE",X"95",X"DD",
X"95",X"E0",X"8F",X"DF",X"8E",X"90",X"93",X"E1",X"E2",X"E4",X"9A",X"9F",X"9F",X"A5",X"E3",X"E5",
X"E6",X"E8",X"90",X"92",X"9A",X"9B",X"E7",X"E9",X"EA",X"95",X"A5",X"9B",X"EC",X"95",X"EB",X"93",
X"EE",X"93",X"ED",X"8F",X"A0",X"A1",X"EF",X"9D",X"01",X"12",X"00",X"11",X"12",X"00",X"11",X"00",
X"00",X"00",X"00",X"00",X"00",X"0E",X"00",X"0D",X"00",X"10",X"00",X"0F",X"12",X"13",X"11",X"13",
X"01",X"13",X"00",X"01",X"13",X"13",X"13",X"13",X"09",X"09",X"09",X"09",X"14",X"14",X"14",X"14",
X"13",X"15",X"15",X"14",X"13",X"17",X"13",X"16",X"17",X"14",X"16",X"14",X"00",X"00",X"0A",X"00",
X"0A",X"00",X"09",X"0A",X"00",X"12",X"00",X"11",X"12",X"13",X"11",X"13",X"01",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"19",X"00",X"18",X"00",X"01",X"19",X"00",X"18",X"1A",X"00",X"1A",X"00",
X"03",X"10",X"10",X"00",X"00",X"01",X"15",X"16",X"15",X"16",X"00",X"00",X"17",X"17",X"00",X"00",
X"03",X"01",X"14",X"13",X"03",X"00",X"12",X"11",X"14",X"13",X"00",X"00",X"12",X"11",X"00",X"00",
X"91",X"92",X"B4",X"B5",X"93",X"94",X"B6",X"B7",X"9B",X"9A",X"B8",X"B9",X"99",X"9F",X"BA",X"BB",
X"00",X"01",X"00",X"00",X"02",X"03",X"03",X"02",X"04",X"05",X"06",X"04",X"07",X"00",X"08",X"07",
X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"09",X"0A",X"00",X"00",X"00",X"0B",X"00",X"0C",
X"0D",X"0E",X"0B",X"00",X"00",X"0E",X"0A",X"0F",X"00",X"00",X"0E",X"00",X"00",X"0E",X"00",X"00",
X"00",X"10",X"0E",X"11",X"11",X"12",X"0E",X"00",X"13",X"14",X"0E",X"15",X"16",X"17",X"0E",X"18",
X"14",X"14",X"15",X"15",X"16",X"17",X"16",X"17",X"19",X"1B",X"15",X"1A",X"1C",X"1D",X"16",X"1E",
X"00",X"1F",X"00",X"00",X"22",X"15",X"20",X"21",X"00",X"23",X"00",X"00",X"24",X"16",X"25",X"26",
X"15",X"15",X"27",X"21",X"24",X"16",X"28",X"16",X"29",X"21",X"00",X"2A",X"2B",X"24",X"00",X"2C",
X"15",X"15",X"21",X"21",X"24",X"16",X"24",X"16",X"15",X"1A",X"21",X"21",X"24",X"1C",X"24",X"16",
X"00",X"00",X"2D",X"00",X"00",X"00",X"2E",X"00",X"2D",X"00",X"19",X"1B",X"1D",X"00",X"1E",X"2E",
X"21",X"21",X"14",X"14",X"17",X"24",X"17",X"24",X"14",X"14",X"2F",X"15",X"16",X"17",X"30",X"17",
X"00",X"00",X"21",X"21",X"00",X"00",X"47",X"00",X"21",X"21",X"00",X"00",X"00",X"1D",X"00",X"00",
X"07",X"00",X"08",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"2D",X"00",X"00",X"00",X"2E",X"00",
X"00",X"31",X"32",X"15",X"16",X"33",X"34",X"00",X"00",X"35",X"0E",X"00",X"00",X"36",X"0E",X"00",
X"14",X"14",X"15",X"15",X"16",X"17",X"16",X"17",X"37",X"38",X"00",X"16",X"15",X"39",X"00",X"3A",
X"3B",X"3C",X"15",X"3D",X"3E",X"3F",X"16",X"40",X"41",X"00",X"42",X"43",X"44",X"00",X"45",X"46",
X"47",X"00",X"47",X"00",X"00",X"00",X"48",X"48",X"00",X"00",X"47",X"00",X"00",X"00",X"48",X"00",
X"49",X"4A",X"4B",X"4C",X"4D",X"4E",X"4F",X"50",X"51",X"52",X"53",X"54",X"55",X"56",X"57",X"58",
X"59",X"5A",X"35",X"00",X"00",X"5B",X"36",X"5C",X"37",X"35",X"00",X"00",X"00",X"36",X"00",X"3A",
X"5D",X"5E",X"5F",X"60",X"61",X"62",X"63",X"64",X"65",X"66",X"67",X"68",X"69",X"6A",X"6B",X"6C",
X"6D",X"6E",X"6F",X"70",X"71",X"72",X"73",X"74",X"75",X"76",X"77",X"78",X"79",X"7A",X"7B",X"7C",
X"7D",X"7E",X"7F",X"80",X"81",X"82",X"83",X"84",X"85",X"86",X"87",X"88",X"89",X"8A",X"8B",X"8C",
X"8D",X"8E",X"8F",X"90",X"91",X"92",X"92",X"93",X"94",X"95",X"95",X"94",X"96",X"97",X"98",X"99",
X"00",X"1B",X"9A",X"17",X"9A",X"17",X"17",X"17",X"00",X"9A",X"16",X"17",X"00",X"00",X"1B",X"00",
X"24",X"1B",X"17",X"24",X"17",X"17",X"17",X"17",X"48",X"17",X"00",X"48",X"24",X"1B",X"17",X"9B",
X"90",X"B2",X"94",X"A8",X"00",X"AA",X"00",X"AA",X"8C",X"A9",X"B3",X"00",X"00",X"A9",X"00",X"A8",
X"00",X"AD",X"00",X"A9",X"00",X"AD",X"00",X"AD",X"AC",X"00",X"A0",X"B0",X"00",X"00",X"A8",X"00",
X"00",X"AD",X"00",X"AC",X"00",X"A8",X"00",X"AE",X"92",X"B3",X"AD",X"00",X"00",X"B1",X"A8",X"89",
X"00",X"00",X"B0",X"B1",X"00",X"54",X"2A",X"53",X"55",X"28",X"88",X"55",X"2C",X"2B",X"56",X"57",
X"01",X"3B",X"00",X"3C",X"3D",X"44",X"3C",X"44",X"01",X"3D",X"00",X"3C",X"4D",X"44",X"4C",X"44",
X"44",X"4E",X"44",X"4F",X"39",X"44",X"3B",X"44",X"39",X"44",X"3A",X"44",X"01",X"4D",X"00",X"4C",
X"01",X"4F",X"00",X"4E",X"3F",X"43",X"01",X"3F",X"43",X"43",X"43",X"43",X"00",X"3E",X"02",X"3E",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"AC",X"B0",X"C0",X"C1",X"B1",X"B0",X"C0",X"C1",X"88",X"A8",X"B3",X"C1",X"B1",X"B1",X"C0",X"C1",
X"C2",X"A9",X"C0",X"AA",X"AB",X"94",X"AD",X"90",X"AE",X"99",X"B2",X"98",X"B3",X"9B",X"AD",X"9A",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"C4",X"10",X"10",X"03",X"11",X"12",X"00",X"03",X"13",X"14",X"02",X"01",X"C0",X"C3",X"11",X"12",
X"C0",X"C3",X"13",X"14",X"15",X"16",X"03",X"00",X"C3",X"C0",X"15",X"16",X"C1",X"C2",X"15",X"15",
X"15",X"15",X"00",X"03",X"C1",X"C2",X"C0",X"10",X"C2",X"10",X"10",X"03",X"C1",X"1A",X"C0",X"1A",
X"1A",X"01",X"1A",X"02",X"10",X"02",X"01",X"03",X"1A",X"C7",X"10",X"C0",X"00",X"00",X"00",X"00",
X"88",X"8A",X"47",X"47",X"28",X"2A",X"02",X"57",X"28",X"03",X"56",X"8A",X"48",X"24",X"24",X"24",
X"89",X"48",X"47",X"48",X"24",X"48",X"25",X"8A",X"56",X"58",X"88",X"49",X"49",X"55",X"4A",X"59",
X"8C",X"82",X"C8",X"C8",X"8D",X"8C",X"80",X"B1",X"D8",X"D9",X"C5",X"C0",X"C8",X"C8",X"C2",X"C0",
X"C8",X"C8",X"D8",X"D9",X"01",X"02",X"DA",X"DB",X"2A",X"24",X"55",X"48",X"59",X"8B",X"46",X"45",
X"C0",X"1D",X"1E",X"00",X"C0",X"C2",X"1E",X"1F",X"C2",X"C0",X"20",X"01",X"22",X"21",X"09",X"09",
X"23",X"1D",X"24",X"23",X"01",X"C2",X"20",X"C0",X"23",X"09",X"24",X"23",X"26",X"25",X"0B",X"0C",
X"26",X"25",X"00",X"00",X"29",X"27",X"28",X"27",X"01",X"03",X"00",X"20",X"2A",X"2B",X"00",X"00",
X"2A",X"2C",X"00",X"2D",X"27",X"27",X"2E",X"27",X"27",X"27",X"30",X"2F",X"00",X"31",X"0B",X"0C",
X"00",X"32",X"1D",X"C0",X"33",X"01",X"0B",X"0C",X"00",X"33",X"2D",X"34",X"80",X"80",X"81",X"80",
X"80",X"82",X"81",X"80",X"83",X"81",X"82",X"83",X"80",X"82",X"80",X"80",X"85",X"84",X"82",X"83",
X"88",X"87",X"86",X"80",X"8A",X"89",X"80",X"80",X"80",X"8D",X"8B",X"8C",X"80",X"80",X"80",X"8B",
X"80",X"8A",X"8E",X"80",X"80",X"80",X"8F",X"80",X"92",X"93",X"90",X"91",X"80",X"80",X"93",X"80",
X"83",X"94",X"80",X"83",X"96",X"93",X"89",X"95",X"90",X"98",X"91",X"97",X"80",X"9A",X"80",X"99",
X"89",X"90",X"8C",X"91",X"80",X"9C",X"80",X"9B",X"8A",X"80",X"8B",X"80",X"83",X"8F",X"80",X"9D",
X"9E",X"80",X"94",X"9E",X"8B",X"80",X"8A",X"80",X"9F",X"94",X"80",X"83",X"A1",X"80",X"A0",X"8E",
X"98",X"80",X"A1",X"80",X"80",X"80",X"A2",X"80",X"80",X"AA",X"A4",X"A9",X"80",X"80",X"83",X"9F",
X"80",X"90",X"80",X"83",X"80",X"A1",X"80",X"A3",X"81",X"80",X"83",X"98",X"A4",X"A5",X"80",X"80",
X"A5",X"A4",X"80",X"80",X"80",X"A7",X"A6",X"A8",X"82",X"80",X"80",X"80",X"80",X"90",X"80",X"80",
X"90",X"98",X"80",X"99",X"A1",X"80",X"A3",X"80",X"8E",X"80",X"98",X"8E",X"80",X"AB",X"80",X"80",
X"80",X"AD",X"80",X"AC",X"8E",X"80",X"80",X"AE",X"AF",X"88",X"A5",X"B0",X"B2",X"B1",X"A4",X"80",
X"B3",X"80",X"80",X"B4",X"A1",X"80",X"A1",X"80",X"80",X"B5",X"81",X"98",X"80",X"98",X"80",X"98",
X"80",X"B6",X"80",X"B6",X"B7",X"98",X"80",X"B8",X"81",X"80",X"94",X"81",X"80",X"80",X"B7",X"B9",
X"94",X"81",X"BA",X"94",X"B5",X"80",X"B6",X"B6",X"80",X"A3",X"80",X"9B",X"97",X"89",X"98",X"80",
X"A1",X"80",X"9D",X"80",X"9F",X"98",X"80",X"A1",X"BB",X"80",X"9F",X"BB",X"BC",X"98",X"9F",X"BD",
X"9F",X"C1",X"80",X"C0",X"B7",X"B9",X"BE",X"BE",X"80",X"89",X"B9",X"B1",X"C3",X"C2",X"80",X"80",
X"C4",X"BE",X"A5",X"BF",X"BE",X"BE",X"80",X"9F",X"BE",X"BE",X"83",X"80",X"BE",X"BB",X"80",X"A5",
X"8E",X"80",X"C5",X"8E",X"AD",X"80",X"AC",X"97",X"B3",X"B6",X"80",X"A1",X"A3",X"BD",X"AC",X"A1",
X"BD",X"80",X"99",X"80",X"AC",X"80",X"AC",X"80",X"81",X"80",X"83",X"BD",X"80",X"AD",X"80",X"AC",
X"88",X"87",X"80",X"80",X"80",X"80",X"80",X"80",X"99",X"80",X"9A",X"80",X"80",X"80",X"C6",X"C7",
X"C9",X"88",X"C8",X"CA",X"80",X"80",X"CC",X"88",X"80",X"80",X"CB",X"AF",X"AF",X"88",X"CD",X"B0",
X"80",X"80",X"88",X"87",X"80",X"80",X"88",X"AF",X"94",X"8E",X"CD",X"A6",X"80",X"80",X"8E",X"80",
X"AC",X"CE",X"AB",X"91",X"8E",X"89",X"94",X"8D",X"89",X"80",X"80",X"BA",X"80",X"80",X"87",X"88",
X"D0",X"9E",X"CF",X"94",X"82",X"90",X"80",X"D1",X"D2",X"80",X"90",X"D0",X"D3",X"80",X"90",X"D2",
X"A2",X"80",X"98",X"80",X"84",X"80",X"85",X"D2",X"80",X"D4",X"82",X"80",X"D5",X"D6",X"80",X"80",
X"90",X"84",X"80",X"85",X"80",X"BA",X"D2",X"89",X"80",X"AD",X"80",X"85",X"81",X"80",X"83",X"BD",
X"B1",X"BD",X"80",X"AD",X"80",X"80",X"D2",X"80",X"AC",X"BD",X"80",X"AD",X"D7",X"88",X"AD",X"80",
X"D4",X"D2",X"80",X"AC",X"80",X"BA",X"98",X"89",X"D8",X"80",X"BA",X"80",X"AD",X"80",X"AC",X"BD",
X"89",X"80",X"D9",X"80",X"80",X"AD",X"80",X"85",X"06",X"D5",X"82",X"80",X"80",X"82",X"DA",X"80",
X"D4",X"DB",X"82",X"80",X"AD",X"80",X"90",X"D2",X"DA",X"80",X"AD",X"80",X"85",X"D2",X"80",X"AC",
X"80",X"AD",X"80",X"AC",X"87",X"88",X"A6",X"CA",X"80",X"80",X"80",X"80",X"88",X"80",X"80",X"DC",
X"BA",X"AC",X"89",X"80",X"88",X"87",X"D2",X"80",X"DD",X"D2",X"89",X"90",X"8E",X"80",X"D2",X"8E",
X"DE",X"E0",X"98",X"DF",X"80",X"80",X"E1",X"8E",X"E2",X"E1",X"80",X"AC",X"80",X"80",X"E3",X"80",
X"80",X"9A",X"80",X"99",X"80",X"80",X"82",X"80",X"B6",X"82",X"98",X"80",X"AC",X"98",X"AC",X"A2",
X"AD",X"80",X"B6",X"80",X"E4",X"B9",X"80",X"A3",X"A2",X"80",X"98",X"80",X"99",X"80",X"9A",X"80");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input [15:1] cpu1_addr,
output reg [15:0] cpu1_q,
input [15:1] cpu2_addr,
output reg [15:0] cpu2_q,
input [15:1] cpu3_addr,
output reg [15:0] cpu3_q,
input [16:1] fg_addr,
output reg [15:0] fg_q,
input [16:1] bg0_addr,
output reg [15:0] bg0_q,
input [16:1] bg1_addr,
output reg [15:0] bg1_q,
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output [15:0] port1_q,
input [16:1] sp1_addr,
output reg [15:0] sp1_q,
input [16:1] sp2_addr,
output reg [15:0] sp2_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output [15:0] port2_q
);
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1
1 ras0
2 CAS0 data1 returned
3 RAS1 cas0
4 ras1
5 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_LAST = 3'd5;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[7];
reg [16:1] addr_last2[7];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1 = 3'd1;
localparam PORT_CPU2 = 3'd2;
localparam PORT_CPU3 = 3'd3;
localparam PORT_FG = 3'd4;
localparam PORT_BG0 = 3'd5;
localparam PORT_BG1 = 3'd6;
localparam PORT_REQ = 3'd7;
localparam PORT_SP1 = 3'd1;
localparam PORT_SP2 = 3'd2;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_ack) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if ({1'b0, cpu1_addr} != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 9'd0, cpu1_addr };
end else if ({1'b0, cpu2_addr} != addr_last[PORT_CPU2]) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 9'd0, cpu2_addr };
end else if ({1'b0, cpu3_addr} != addr_last[PORT_CPU3]) begin
next_port[0] = PORT_CPU3;
addr_latch_next[0] = { 9'd0, cpu3_addr };
end else if (fg_addr != addr_last[PORT_FG]) begin
next_port[0] = PORT_FG;
addr_latch_next[0] = { 8'd0, fg_addr };
end else if (bg0_addr != addr_last[PORT_BG0]) begin
next_port[0] = PORT_BG0;
addr_latch_next[0] = { 8'd0, bg0_addr };
end else if (bg1_addr != addr_last[PORT_BG1]) begin
next_port[0] = PORT_BG1;
addr_latch_next[0] = { 8'd0, bg1_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT2: bank 2,3
always @(*) begin
if (port2_req ^ port2_ack) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (sp1_addr != addr_last2[PORT_SP1]) begin
next_port[1] = PORT_SP1;
addr_latch_next[1] = { 1'b1, 7'd0, sp1_addr };
end else if (sp2_addr != addr_last2[PORT_SP2]) begin
next_port[1] = PORT_SP2;
addr_latch_next[1] = { 1'b1, 7'd0, sp2_addr };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][16:1];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_CPU2: begin cpu2_q <= sd_din; end
PORT_CPU3: begin cpu3_q <= sd_din; end
PORT_FG: begin fg_q <= sd_din; end
PORT_BG0: begin bg0_q <= sd_din; end
PORT_BG1: begin bg1_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
PORT_SP1: begin sp1_q <= sd_din; end
PORT_SP2: begin sp2_q <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

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---------------------------------------------------------------------------------
-- Galaga sound machine by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- 3 voices frequency/waveform synthetizer
--
-- Original hardware done with only one 4 bits sequential adder to realise
-- one 20 bits adder and two 16 bits adder.
--
-- Too nice and clever to be done another way, just doing it the same way!
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity sound_machine is
port(
clock_18 : in std_logic;
hcnt : in std_logic_vector(5 downto 0);
ena : in std_logic;
cpu_addr : in std_logic_vector(3 downto 0);
cpu_do : in std_logic_vector(3 downto 0);
ram_0_we : in std_logic;
ram_1_we : in std_logic;
audio : out std_logic_vector(9 downto 0)
);
end sound_machine;
architecture struct of sound_machine is
signal clock_18n : std_logic;
signal snd_ram_addr : std_logic_vector(3 downto 0);
signal snd_ram_di : std_logic_vector(3 downto 0);
signal snd_ram_0_we : std_logic;
signal snd_ram_1_we : std_logic;
signal snd_ram_0_do : std_logic_vector(3 downto 0);
signal snd_ram_1_do : std_logic_vector(3 downto 0);
signal snd_seq_addr : std_logic_vector(7 downto 0);
signal snd_seq_do : std_logic_vector(7 downto 0);
signal snd_samples_addr : std_logic_vector(7 downto 0);
signal snd_samples_do : std_logic_vector(7 downto 0);
signal sum : std_logic_vector(4 downto 0) := (others => '0');
signal sum_r : std_logic_vector(4 downto 0) := (others => '0');
signal sum_3_rr : std_logic := '0';
signal samples_ch0 : std_logic_vector(3 downto 0);
signal samples_ch1 : std_logic_vector(3 downto 0);
signal samples_ch2 : std_logic_vector(3 downto 0);
signal volume_ch0 : std_logic_vector(3 downto 0);
signal volume_ch1 : std_logic_vector(3 downto 0);
signal volume_ch2 : std_logic_vector(3 downto 0);
begin
clock_18n <= not clock_18;
snd_seq_addr <= '0' & not ram_0_we & hcnt(5 downto 0);
snd_ram_addr <= cpu_addr when (ram_0_we = '1' or ram_1_we = '1') else hcnt(5 downto 2);
snd_ram_di <= cpu_do when (ram_0_we = '1' or ram_1_we = '1') else sum_r(3 downto 0);
snd_ram_0_we <= (not snd_seq_do(1) and ena) or ram_0_we ;
snd_ram_1_we <= ram_1_we;
sum <= ('0' & snd_ram_0_do) + ('0' & snd_ram_1_do) + ("0000" & sum_r(4));
process (clock_18, ena)
begin
if rising_edge(clock_18) and ena = '1' then
if snd_seq_do(3) = '0' then
sum_r <= (others => '0');
sum_3_rr <= '0';
elsif snd_seq_do(0) = '0' then
sum_r <= sum;
sum_3_rr <= sum_r(3);
end if ;
snd_samples_addr <= snd_ram_0_do(2 downto 0) & sum_r(3 downto 0) & sum_3_rr;
if snd_seq_do(2) = '0' then
if hcnt(5 downto 2) = X"5" then
samples_ch0 <= snd_samples_do(3 downto 0);
volume_ch0 <= snd_ram_1_do;
end if;
if hcnt(5 downto 2) = X"A" then
samples_ch1 <= snd_samples_do(3 downto 0);
volume_ch1 <= snd_ram_1_do;
end if;
if hcnt(5 downto 2) = X"F" then
samples_ch2 <= snd_samples_do(3 downto 0);
volume_ch2 <= snd_ram_1_do;
end if;
end if;
audio <= ("00" & samples_ch0) * volume_ch0 +
("00" & samples_ch1) * volume_ch1 +
("00" & samples_ch2) * volume_ch2;
end if;
end process;
-- sound register RAM0
sound_ram_0 : entity work.gen_ram
generic map( dWidth => 4, aWidth => 4)
port map(
clk => clock_18n,
we => snd_ram_0_we,
addr => snd_ram_addr,
d => snd_ram_di,
q => snd_ram_0_do
);
-- sound register RAM1
sound_ram_1 : entity work.gen_ram
generic map( dWidth => 4, aWidth => 4)
port map(
clk => clock_18n,
we => snd_ram_1_we,
addr => snd_ram_addr,
d => snd_ram_di,
q => snd_ram_1_do
);
-- sound samples ROM
sound_samples : entity work.sound_samples
port map(
clk => clock_18n,
addr => snd_samples_addr,
data => snd_samples_do
);
-- sound compute sequencer ROM
sound_seq : entity work.sound_seq
port map(
clk => clock_18n,
addr => snd_seq_addr,
data => snd_seq_do
);
end struct;

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module xevious_mist
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"XEVIOUS;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = ~ioctl_downl;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = clk_72;
assign SDRAM_CKE = 1;
wire clk_18, clk_72;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clk_18),
.c1(clk_72),
.locked(pll_locked)
);
wire clk_sys = clk_18;
wire clk_mem = clk_72;
reg reset;
always @(posedge clk_sys)
reset <= status[0] | status[6] | buttons[1] | ioctl_downl;
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [9:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
wire [10:0] audio;
wire hs, vs;
wire blankn;
wire [3:0] r,g,b;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
wire [15:0] cpu1_addr;
wire [15:0] cpu1_q;
wire [15:0] cpu2_addr;
wire [15:0] cpu2_q;
wire [15:0] cpu3_addr;
wire [15:0] cpu3_q;
wire [16:0] fg_addr;
wire [15:0] fg_q;
wire [16:0] bg0_addr;
wire [15:0] bg0_q;
wire [16:0] bg1_addr;
wire [15:0] bg1_q;
wire [16:0] sp1_addr;
wire [15:0] sp1_q;
wire [16:0] sp2_addr;
wire [15:0] sp2_q;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_mem ),
// port1 used for CPU 1-2-3-fg-bg
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( cpu1_addr[15:1] ),
.cpu1_q ( cpu1_q ),
.cpu2_addr ( cpu2_addr[15:1] ),
.cpu2_q ( cpu2_q ),
.cpu3_addr ( cpu3_addr[15:1] ),
.cpu3_q ( cpu3_q ),
.fg_addr ( fg_addr[16:1] ),
.fg_q ( fg_q ),
.bg0_addr ( bg0_addr[16:1] ),
.bg0_q ( bg0_q ),
.bg1_addr ( bg1_addr[16:1] ),
.bg1_q ( bg1_q ),
// port2 for sprite graphx
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( ioctl_addr[23:1] ),
.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.sp1_addr ( sp1_addr[16:1] ),
.sp1_q ( sp1_q ),
.sp2_addr ( sp2_addr[16:1] ),
.sp2_q ( sp2_q )
);
// data upload controller
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
xevious xevious(
.clock_18 ( clk_sys ),
.reset ( reset ),
.cpu1_addr_o ( cpu1_addr ),
.cpu1_rom_do ( cpu1_addr[0] ? cpu1_q[15:8] : cpu1_q[7:0] ),
.cpu2_addr_o ( cpu2_addr ),
.cpu2_rom_do ( cpu2_addr[0] ? cpu2_q[15:8] : cpu2_q[7:0] ),
.cpu3_addr_o ( cpu3_addr ),
.cpu3_rom_do ( cpu3_addr[0] ? cpu3_q[15:8] : cpu3_q[7:0] ),
.fg_addr_o ( fg_addr ),
.fg_rom_do ( fg_addr[0] ? fg_q[15:8] : fg_q[7:0] ),
.bg0_addr_o ( bg0_addr ),
.bg0_rom_do ( bg0_addr[0] ? bg0_q[15:8] : bg0_q[7:0] ),
.bg1_addr_o ( bg1_addr ),
.bg1_rom_do ( bg1_addr[0] ? bg1_q[15:8] : bg1_q[7:0] ),
.sp_grphx_1_addr_o ( sp1_addr ),
.sp_grphx_1_do ( sp1_addr[0] ? sp1_q[15:8] : sp1_q[7:0] ),
.sp_grphx_2_addr_o ( sp2_addr ),
.sp_grphx_2_do ( sp2_addr[0] ? sp2_q[15:8] : sp2_q[7:0] ),
.video_r(r),
.video_g(g),
.video_b(b),
.video_hs(hs),
.video_vs(vs),
.video_blankn(blankn),
.audio(audio),
.coin(btn_coin),
.start1(btn_one_player),
.left(m_left),
.right(m_right),
.up(m_up),
.down(m_down),
.fire(m_fire),
.bomb(m_bomb),
.start2(btn_two_players)
);
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys(clk_sys),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : 0),
.G(blankn ? g : 0),
.B(blankn ? b : 0),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.ce_divider(1'b1),
.rotate({1'b1,status[2]}),
.scanlines(status[4:3]),
.scandoubler_disable(scandoublerD),
.ypbpr(ypbpr)
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(11))
dac(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
always @(posedge clk_sys) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

2
common/CPU/T80/T80.qip
View File

@ -1,6 +1,8 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80se.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Pack.vhd ]