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Code Issues Releases Wiki Activity

New Core Donkey Kong Junior

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Gehstock
2019-11-15 22:51:07 +01:00
parent d874f02d88
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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/DKongJr.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
# Date created = 04:04:47 October 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "DKongJr"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 22:45:45 November 15, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DKongJr_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkongjr_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/dkongjr_top.v
set_global_assignment -name VERILOG_FILE rtl/i8035ip.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/dkongjr_wav_sound.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_vram.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_sound.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_obj.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_logic.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_inport.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_iir_filter.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_hv_count.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_dma.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkongjr_dac.sv
set_global_assignment -name VERILOG_FILE rtl/dkongjr_col_pal.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_bram.v
set_global_assignment -name VERILOG_FILE rtl/dkongjr_adec.v
set_global_assignment -name VHDL_FILE rtl/rom/prog.vhd
set_global_assignment -name VHDL_FILE rtl/rom/vid2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/vid1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/snd1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/obj4.vhd
set_global_assignment -name VHDL_FILE rtl/rom/obj3.vhd
set_global_assignment -name VHDL_FILE rtl/rom/obj2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/obj1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/col3.vhd
set_global_assignment -name VHDL_FILE rtl/rom/col2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/col1.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80as.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/timer.vhd
set_global_assignment -name VHDL_FILE "rtl/t48_ip/t48_pack-p.vhd"
set_global_assignment -name VHDL_FILE "rtl/t48_ip/t48_core_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE rtl/t48_ip/t48_core.vhd
set_global_assignment -name VHDL_FILE "rtl/t48_ip/t48_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE "rtl/t48_ip/syn_ram-e.vhd"
set_global_assignment -name VHDL_FILE rtl/t48_ip/psw.vhd
set_global_assignment -name VHDL_FILE "rtl/t48_ip/pmem_ctrl_pack-p.vhd"
set_global_assignment -name VHDL_FILE rtl/t48_ip/pmem_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/p2.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/p1.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/opc_table.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/opc_decoder.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/int.vhd
set_global_assignment -name VHDL_FILE "rtl/t48_ip/dmem_ctrl_pack-p.vhd"
set_global_assignment -name VHDL_FILE rtl/t48_ip/dmem_ctrl.vhd
set_global_assignment -name VHDL_FILE "rtl/t48_ip/decoder_pack-p.vhd"
set_global_assignment -name VHDL_FILE rtl/t48_ip/decoder.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/db_bus.vhd
set_global_assignment -name VHDL_FILE "rtl/t48_ip/cond_branch_pack-p.vhd"
set_global_assignment -name VHDL_FILE rtl/t48_ip/cond_branch.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/clock_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/t48_ip/bus_mux.vhd
set_global_assignment -name VHDL_FILE "rtl/t48_ip/alu_pack-p.vhd"
set_global_assignment -name VHDL_FILE rtl/t48_ip/alu.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name VERILOG_FILE rtl/pll.v
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TOP_LEVEL_ENTITY dkongjr_MiST
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name SEARCH_PATH rtl/ -tag from_archive
set_global_assignment -name SEARCH_PATH rtl/rom/ -tag from_archive
set_global_assignment -name SEARCH_PATH rtl/t48_ip/ -tag from_archive
set_global_assignment -name SEARCH_PATH rtl/t80asd_ip/ -tag from_archive
# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------------
# start ENTITY(dkongjr_MiST)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(dkongjr_MiST)
# ------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/README.txt Normal file
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---------------------------------------------------------------------------------
--
-- Arcade: Donkey Kong Jr. port to MiST by Gehstock
-- 15 November 2019
--
missing Sounds
maybe Graphic Problem
---------------------------------------------------------------------------------
-- A simulation model of Pacman hardware
-- // Copyright(c) 2003 - 2005 Katsumi Degawa , All rights reserved
---------------------------------------------------------------------------------
--
-- Only Controls and OSD are rotated on Video output.
--
--
-- Keyboard inputs :
--
-- ESC : Coin
-- F2 : Start 2 players
-- F1 : Start 1 player
-- UP,DOWN,LEFT,RIGHT arrows : Movements
-- SPACE : Jump
-- Joystick support.
---------------------------------------------------------------------------------
ToDo: Sound, Rotated Controls

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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/Releases/DKongJr.rbf Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/T80/T80.vhd Normal file
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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/T80/T80_ALU.vhd Normal file
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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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------------------------------------------------------------------------------
-- 2004.10.18 WR_n active was changed from T2 to T3.
-- modification by Katsumi Degawa
------------------------------------------------------------------------------
-- t80as.vhd : The non-tristate signal edition of t80a.vhd
--
-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
--
-- 1.separate 'D' to 'DO' and 'DI'.
-- 2.added 'DOE' to 'DO' enable signal.(data direction)
-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'.
--
-- There is a mark of "--AS" in all the change points.
--
------------------------------------------------------------------------------
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80as is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
--AS-- D : inout std_logic_vector(7 downto 0)
--AS>>
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
DOE : out std_logic
--<<AS
);
end T80as;
architecture rtl of T80as is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
--AS-- signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
--AS-- MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
--AS-- A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
--AS>>
MREQ_n <= MREQ_n_i;
IORQ_n <= IORQ_n_i;
RD_n <= RD_n_i;
WR_n <= WR_n_i;
RFSH_n <= RFSH_n_i;
A <= A_i;
DOE <= Write when BUSAK_n_i = '1' else '0';
--<<AS
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
-- DInst => D,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
--AS-- DI_Reg <= to_x01(D);
--AS>>
DI_Reg <= to_x01(DI);
--<<AS
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
-- 2004.10.18 modification
-- elsif CLK_n'event and CLK_n = '1' then
elsif CLK_n'event and CLK_n = '0' then
WR_n_i <= '1';
-- if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
if TState = "010" then
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

173
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module dkongjr_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"DKONGJR;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"T6,Reset;",
"O89,Lives,3,4,5,6;",
"OAB,Bonus,7000,10000,15000,20000;",
"V,v1.00.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clock_24, clock_6;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_24),//W_CLK_24576M
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [11:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [7:0] audio;
wire hs_n, vs_n;
wire hb, vb;
wire blankn = ~vb;//~(hb | vb);
wire [2:0] r, g;
wire [1:0] b;
dkongjr_top dkong(
.I_CLK_24576M(clock_24),
.I_RESETn(~(status[0] | status[6] | buttons[1])),
.I_U1(~m_up),
.I_D1(~m_down),
.I_L1(~m_left),
.I_R1(~m_right),
.I_J1(~m_fire),
.I_U2(~m_up),
.I_D2(~m_down),
.I_L2(~m_left),
.I_R2(~m_right),
.I_J2(~m_fire),
.I_S1(~btn_one_player),
.I_S2(~btn_two_players),
.I_C1(~btn_coin),
.I_DIP_SW({ ~status[12] , 1'b0,1'b0,1'b0 , status[11:10], status[9:8]}),
.O_SOUND_DAT(audio),
.O_VGA_R(r),
.O_VGA_G(g),
.O_VGA_B(b),
.O_H_BLANK(hb),
.O_V_BLANK(vb),
.O_VGA_H_SYNCn(hs_n),
.O_VGA_V_SYNCn(vs_n)
);
mist_video #(.COLOR_DEPTH(3),.SD_HCNT_WIDTH(10)) mist_video(
.clk_sys(clock_24),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : 0),
.G(blankn ? g : 0),
.B(blankn ? {b[1], b} : 0),
.HSync(hs_n),
.VSync(vs_n),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.rotate({1'b1,status[2]}),
.ce_divider(1'b1),
.blend(status[5]),
.scandoubler_disable(scandoublerD),
.scanlines(status[4:3]),
.ypbpr(ypbpr)
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clock_24 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(8))
dac(
.clk_i(clock_24),
.res_n_i(1'b1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_coin = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
always @(posedge clock_24) begin
reg old_state;
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

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//===============================================================================
//
// Modified for Donkey Kong Junior by gaz68.
//
// FPGA DONKEY KONG ADDRESS DECODER
//
// Version : 4.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2004- 8-24 CPU_Wait was stopped. K.Degawa
// 2005- 2- 9 CPU_Wait was worked. because, Z80_ip was improved. K.Degawa
//================================================================================
module dkongjr_adec(
I_CLK12M,
I_CLK,
I_RESET_n,
I_AB,
I_DB,
I_MREQ_n,
I_RFSH_n,
I_RD_n,
I_WR_n,
I_VRAMBUSY_n,
I_VBLK_n,
O_WAIT_n,
O_NMI_n,
O_ROM_CS_n,
O_RAM1_CS_n,
O_RAM2_CS_n,
O_RAM3_CS_n,
O_DMA_CS_n,
O_6A_G_n,
O_OBJ_RQ_n,
O_OBJ_RD_n,
O_OBJ_WR_n,
O_VRAM_RD_n,
O_VRAM_WR_n,
O_SW1_OE_n,
O_SW2_OE_n,
O_SW3_OE_n,
O_DIP_OE_n,
O_4H_Q,
O_5H_Q,
O_6H_Q,
O_3D_Q
);
input I_CLK12M;
input I_CLK; // H_CNT[1] 3.072MHz
input I_RESET_n;
input [15:0]I_AB;
input [3:0]I_DB;
input I_MREQ_n;
input I_RFSH_n;
input I_RD_n;
input I_WR_n;
input I_VRAMBUSY_n;
input I_VBLK_n;
output O_ROM_CS_n; // 0000 H - 3FFF H (5E,5C,5B,5A)
output O_RAM1_CS_n; // 6000 H - 63FF H (3C,4C)
output O_RAM2_CS_n; // 6400 H - 67FF H (3B,4B)
output O_RAM3_CS_n; // 6800 H - 6BFF H (3A,4A)
output O_DMA_CS_n; // 7800 H - 783F H (DMA)
output O_6A_G_n; // 7000 H - 77FF H => Active
output O_OBJ_RQ_n; // 7000 H - 73FF H
output O_OBJ_RD_n; // 7000 H - 73FF H (R mode)
output O_OBJ_WR_n; // 7000 H - 73FF H (W mode)
output O_VRAM_RD_n; // 7400 H - 77FF H (R mode)
output O_VRAM_WR_n; // 7400 H - 77FF H (W mode)
output O_SW1_OE_n; // 7C00 H (R mode)
output O_SW2_OE_n; // 7C80 H (R mode)
output O_SW3_OE_n; // 7D00 H (R mode)
output O_DIP_OE_n; // 7D80 H (R mode)
output [1:0]O_4H_Q; // GFX (Characters) bank switch, sound
output [7:0]O_5H_Q; // FLIP,
output [7:0]O_6H_Q; // sound
output [4:0]O_3D_Q; // sound
output O_WAIT_n;
output O_NMI_n;
wire [3:0]W_2A1_Q,W_2A2_Q;
wire [7:0]W_4D_Q,W_2B_Q,W_2C_Q,W_2D_Q;
wire [7:0]W_1B_Q,W_1C_Q;
reg [7:0]W_5H_Q;
reg [1:0]W_4H_Q;
// CPU WAIT
reg W_7F1_Qn;
reg W_7F2_Q;
assign O_WAIT_n = W_7F1_Qn;
//assign O_WAIT_n = 1'b1;
always@(posedge I_CLK or negedge I_VBLK_n)
begin
if(I_VBLK_n == 1'b0)
W_7F1_Qn <= 1'b1;
else
W_7F1_Qn <= I_VRAMBUSY_n | W_2A2_Q[1];
end
always@(negedge I_CLK)
begin
W_7F2_Q <= W_7F1_Qn;
end
// CPU NMI
wire W_VBLK = ~I_VBLK_n;
reg O_NMI_n;
always@(posedge W_VBLK or negedge W_5H_Q[4])
begin
if(~W_5H_Q[4])
O_NMI_n <= 1'b1;
else
O_NMI_n <= 1'b0;
end
// ADDR DEC 0000H - 7FFFH
logic_74xx138 U_4D(
.I_G1(I_RFSH_n),
.I_G2a(I_AB[15]),
.I_G2b(I_AB[15]),
.I_Sel(I_AB[14:12]),
.O_Q(W_4D_Q)
);
assign O_ROM_CS_n = W_4D_Q[0]&W_4D_Q[1]&W_4D_Q[2]&W_4D_Q[3]&W_4D_Q[4]&W_4D_Q[5];
// ADDR DEC 7000H - 7FFFH
logic_74xx139 U_2A_1(
.I_G(W_4D_Q[7]),
.I_Sel({1'b0,I_AB[11]}),
.O_Q(W_2A1_Q)
);
assign O_DMA_CS_n = W_2A1_Q[1]|I_AB[10];
assign O_6A_G_n = W_2A1_Q[0];
logic_74xx139 U_2A_2(
.I_G(W_4D_Q[7] | I_MREQ_n),
.I_Sel(I_AB[11:10]),
.O_Q(W_2A2_Q)
);
assign O_OBJ_RQ_n = W_2A2_Q[0];
// ADDR DEC 7000H - 7FFFH (R)
logic_74xx138 U_2B(
.I_G1(1'b1),
.I_G2a(I_RD_n),
.I_G2b(I_MREQ_n),
.I_Sel({W_4D_Q[7],I_AB[11:10]}),
.O_Q(W_2B_Q)
);
assign O_OBJ_RD_n = W_2B_Q[0];
assign O_VRAM_RD_n = W_2B_Q[1];
// ADDR DEC 7000H - 7FFFH (W)
logic_74xx138 U_2C(
.I_G1(W_7F2_Q),
//.I_G1(1'b1), // No Wait
.I_G2a(I_WR_n),
.I_G2b(I_MREQ_n),
.I_Sel({W_4D_Q[7],I_AB[11:10]}),
.O_Q(W_2C_Q)
);
assign O_OBJ_WR_n = W_2C_Q[0];
assign O_VRAM_WR_n = W_2C_Q[1];
// ADDR DEC 6000H - 6FFFH (W)
logic_74xx138 U_2D(
.I_G1(1'b1),
.I_G2a(I_WR_n & I_RD_n),
.I_G2b(I_MREQ_n),
.I_Sel({W_4D_Q[6],I_AB[11:10]}),
.O_Q(W_2D_Q)
);
assign O_RAM1_CS_n = W_2D_Q[0];
assign O_RAM2_CS_n = W_2D_Q[1];
assign O_RAM3_CS_n = W_2D_Q[2];
// ADDR DEC 7C00H - 7FFFH (R)
logic_74xx138 U_1B(
.I_G1(1'b1),
.I_G2a(I_RD_n),
.I_G2b(W_2A2_Q[3]),
.I_Sel(I_AB[9:7]),
.O_Q(W_1B_Q)
);
assign O_SW1_OE_n = W_1B_Q[0];
assign O_SW2_OE_n = W_1B_Q[1];
assign O_SW3_OE_n = W_1B_Q[2];
assign O_DIP_OE_n = W_1B_Q[3];
// ADDR DEC 7C00H - 7FFFH (W)
logic_74xx138 U_1C(
.I_G1(1'b1),
.I_G2a(I_WR_n),
.I_G2b(W_2A2_Q[3]),
.I_Sel(I_AB[9:7]),
.O_Q(W_1C_Q)
);
//--- Parts 5H ---------
always@(posedge I_CLK12M or negedge I_RESET_n)
begin
if(I_RESET_n == 1'b0) begin
W_5H_Q <= 0;
end
else begin
if(W_1C_Q[3] == 1'b0) begin
case(I_AB[2:0])
3'h0 : W_5H_Q[0] <= I_DB[0];
3'h1 : W_5H_Q[1] <= I_DB[0];
3'h2 : W_5H_Q[2] <= I_DB[0];
3'h3 : W_5H_Q[3] <= I_DB[0];
3'h4 : W_5H_Q[4] <= I_DB[0];
3'h5 : W_5H_Q[5] <= I_DB[0];
3'h6 : W_5H_Q[6] <= I_DB[0];
3'h7 : W_5H_Q[7] <= I_DB[0];
endcase
end
end
end
//--- Parts 6H ---------
reg [7:0]W_6H_Q;
always@(posedge I_CLK12M or negedge I_RESET_n)
begin
if(I_RESET_n == 1'b0) begin
W_6H_Q <= 0;
end
else begin
if(W_1C_Q[2] == 1'b0) begin
case(I_AB[2:0])
3'h0 : W_6H_Q[0] <= I_DB[0];
3'h1 : W_6H_Q[1] <= I_DB[0];
3'h2 : W_6H_Q[2] <= I_DB[0];
3'h3 : W_6H_Q[3] <= I_DB[0];
3'h4 : W_6H_Q[4] <= I_DB[0];
3'h5 : W_6H_Q[5] <= I_DB[0];
3'h6 : W_6H_Q[6] <= I_DB[0];
3'h7 : W_6H_Q[7] <= I_DB[0];
endcase
end
end
end
//--- Parts 4H ---------
always@(posedge I_CLK12M or negedge I_RESET_n)
begin
if(I_RESET_n == 1'b0) begin
W_4H_Q <= 0;
end
else begin
if(W_1C_Q[1] == 1'b0) begin
case(I_AB[0])
3'h0 : W_4H_Q[0] <= I_DB[0]; // VROM signal
3'h1 : W_4H_Q[1] <= I_DB[0]; // SOUND 8035 PB6
endcase
end
end
end
// Parts 3D
reg [4:0]O_3D_Q;
always@(posedge W_1C_Q[0] or negedge I_RESET_n)
begin
if(I_RESET_n == 1'b0) begin
O_3D_Q <= 0;
end
else begin
O_3D_Q <= I_DB;
end
end
assign O_5H_Q = W_5H_Q;
assign O_6H_Q = W_6H_Q;
assign O_4H_Q = W_4H_Q;
endmodule

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module ram_1024_8_8
(
input I_CLKA,I_CLKB,
input [9:0]I_ADDRA,I_ADDRB,
input [7:0]I_DA,I_DB,
input I_CEA,I_CEB,
input I_WEA,I_WEB,
output [7:0]O_DA,O_DB
);
wire [7:0]W_DOA,W_DOB;
assign O_DA = I_CEA ? W_DOA : 8'h00;
assign O_DB = I_CEB ? W_DOB : 8'h00;
dpram #(10,8) ram_1024_8_8
(
.clock_a(I_CLKA),
.address_a(I_ADDRA),
.data_a(I_DA),
.enable_a(I_CEA),
.wren_a(I_WEA),
.q_a(W_DOA),
.clock_b(I_CLKB),
.address_b(I_ADDRB),
.data_b(I_DB),
.enable_b(I_CEB),
.wren_b(I_WEB),
.q_b(W_DOB)
);
endmodule
/////////////////////////////////////////////////////////////////////
module ram_1024_8
(
input I_CLK,
input [9:0]I_ADDR,
input [7:0]I_D,
input I_CE,
input I_WE,
output [7:0]O_D
);
wire [7:0]W_DO;
assign O_D = I_CE ? W_DO : 8'h00;
dpram #(10,8) ram_1024_8
(
.clock_a(I_CLK),
.address_a(I_ADDR),
.data_a(I_D),
.wren_a(I_WE),
.enable_a(I_CE),
.q_a(W_DO),
.clock_b(I_CLK)
);
endmodule
/////////////////////////////////////////////////////////////////////
module ram_2N
(
input I_CLK,
input [7:0]I_ADDR,
input [3:0]I_D,
input I_CE,
input I_WE,
output [3:0]O_D
);
dpram #(8,4) ram_256_4
(
.clock_a(I_CLK),
.address_a(I_ADDR),
.data_a(I_D),
.wren_a(I_WE),
.enable_a(I_CE),
.q_a(O_D),
.clock_b(I_CLK)
);
endmodule
/////////////////////////////////////////////////////////////////////
module ram_2EH7M
(
input I_CLKA,I_CLKB,
input [7:0]I_ADDRA,
input [5:0]I_ADDRB,
input [5:0]I_DA,
input [8:0]I_DB,
input I_CEA,I_CEB,
input I_WEA,I_WEB,
output [5:0]O_DA,
output [8:0]O_DB
);
dpram #(8,6) ram_256_6
(
.clock_a(I_CLKA),
.address_a(I_ADDRA),
.data_a(I_DA),
.enable_a(I_CEA),
.wren_a(I_WEA),
.q_a(O_DA),
.clock_b(I_CLKA)
);
dpram #(6,9) ram_64_9
(
.clock_a(I_CLKB),
.address_a(I_ADDRB),
.data_a(I_DB),
.enable_a(I_CEB),
.wren_a(I_WEB),
.q_a(O_DB),
.clock_b(I_CLKB)
);
endmodule
/////////////////////////////////////////////////////////////////////
module ram_2EF
(
input I_CLKA,I_CLKB,
input [7:0]I_ADDRA,I_ADDRB,
input [7:0]I_DA,I_DB,
input I_CEA,I_CEB,
input I_WEA,I_WEB,
output [7:0]O_DA,O_DB
);
dpram #(9,8) ram_512_8
(
.clock_a(I_CLKA),
.address_a({1'b0,I_ADDRA}),
.data_a(I_DA),
.enable_a(I_CEA),
.wren_a(I_WEA),
.q_a(O_DA),
.clock_b(I_CLKB),
.address_b({1'b1,I_ADDRB}),
.data_b(I_DB),
.enable_b(I_CEB),
.wren_b(I_WEB),
.q_b(O_DB)
);
endmodule
/////////////////////////////////////////////////////////////////////
module double_scan
(
input I_CLKA,I_CLKB,
input [8:0]I_ADDRA,I_ADDRB,
input [7:0]I_DA,I_DB,
input I_CEA,I_CEB,
input I_WEA,I_WEB,
output [7:0]O_DA,O_DB
);
dpram #(9,8) ram_512_8
(
.clock_a(I_CLKA),
.address_a(I_ADDRA),
.data_a(I_DA),
.enable_a(I_CEA),
.wren_a(I_WEA),
.q_a(O_DA),
.clock_b(I_CLKB),
.address_b(I_ADDRB),
.data_b(I_DB),
.enable_b(I_CEB),
.wren_b(I_WEB),
.q_b(O_DB)
);
endmodule
/////////////////////////////////////////////////////////////////////
module ram_64_8
(
input I_CLK,
input [5:0]I_ADDR,
input [7:0]I_D,
input I_CE,
input I_WE,
output [7:0]O_D
);
dpram #(6,8) ram_64_8
(
.clock_a(I_CLK),
.address_a(I_ADDR),
.data_a(I_D),
.wren_a(I_WE),
.enable_a(I_CE),
.q_a(O_D),
.clock_b(I_CLK)
);
endmodule
/////////////////////////////////////////////////////////////////////
module ram_2048_8
(
input I_CLK,
input [10:0]I_ADDR,
input [7:0]I_D,
input I_CE,
input I_WE,
output [7:0]O_D
);
dpram #(11,8) ram_2048_8
(
.clock_a(I_CLK),
.address_a(I_ADDR),
.data_a(I_D),
.wren_a(I_WE),
.enable_a(I_CE),
.q_a(O_D),
.clock_b(I_CLK)
);
endmodule
/////////////////////////////////////////////////////////////////////
module ram_4096_8
(
input I_CLK,
input [11:0]I_ADDR,
input [7:0]I_D,
input I_CE,
input I_WE,
output [7:0]O_D
);
dpram #(12,8) ram_4096_8
(
.clock_a(I_CLK),
.address_a(I_ADDR),
.data_a(I_D),
.wren_a(I_WE),
.enable_a(I_CE),
.q_a(O_D),
.clock_b(I_CLK)
);
endmodule

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//===============================================================================
// FPGA DONKEY KONG COLOR_PALETE(XILINX EDITION)
//
// Version : 3.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2005- 2- 9 The description of the ROM was changed.
// Data on the ROM are initialized at the time of the start.
//================================================================================
module dkongjr_col_pal
(
input CLK_6M,
input CLK_12M,
input [5:0]I_VRAM_D,
input [5:0]I_OBJ_D,
input I_CMPBLKn,
input I_5H_Q6,I_5H_Q7,
input [7:0]I_CNF_A,
input [7:0]I_CNF_D,
output [2:0]O_R,
output [2:0]O_G,
output [1:0]O_B
);
//------- PARTS 3ML ------------------------------------
wire [5:0]W_3ML_Y = (~(I_OBJ_D[0]|I_OBJ_D[1])) ? I_VRAM_D: I_OBJ_D;
//------- PARTS 1EF ------------------------------------
wire [9:0]W_1EF_D = {I_5H_Q7,I_5H_Q6,W_3ML_Y[5:0],W_3ML_Y[0]|W_3ML_Y[1],I_CMPBLKn};
reg [9:0]W_1EF_Q;
wire W_1EF_RST = I_CMPBLKn|W_1EF_Q[0];
always@(posedge CLK_6M or negedge W_1EF_RST)
begin
if(W_1EF_RST == 1'b0) W_1EF_Q <= 1'b0;
else W_1EF_Q <= W_1EF_D;
end
//------- PARTS 2EF ------------------------------------
wire [3:0]W_2E_DO,W_2F_DO;
col1 rom2j(
.clk(CLK_12M),
.addr(W_1EF_Q[9:2]),
.data(W_2E_DO)
);
col2 rom2k(
.clk(CLK_12M),
.addr(W_1EF_Q[9:2]),
.data(W_2F_DO)
);
assign {O_R, O_G, O_B} = {~W_2F_DO, ~W_2E_DO};
endmodule

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//============================================================================
// DAC Discharge Circuit
//
// Author: gaz68 (https://github.com/gaz68)
// October 2019
//
// Simulation of capacitor discharge circuit to pin 14 input of DAC-08.
// Components R20, C32 and Q4 on schematics.
// Adds decay to some sounds and background tunes.
//============================================================================
module dkongjr_dac
(
input I_CLK,
input I_DECAY_EN,
input I_RESET_n,
input signed [15:0]I_SND_DAT,
output signed [15:0]O_SND_DAT
);
// Exponential decay. Timing of decay steps calculated using:
// v = exp(-(t / (r * c)))
// Where:
// t = 1 / sample rate (48,000Hz)
// r = 10,000 (10KOhm)
// c = 0.00001 (10uf)
// for v scaled up to 8-bit values.
wire [14:0] exp_lut[0:255] =
'{
15'h000A, 15'h001D, 15'h0030, 15'h0043, 15'h0056, 15'h0069, 15'h007C, 15'h0090,
15'h00A3, 15'h00B7, 15'h00CA, 15'h00DE, 15'h00F2, 15'h0106, 15'h011A, 15'h012E,
15'h0142, 15'h0156, 15'h016A, 15'h017E, 15'h0193, 15'h01A7, 15'h01BC, 15'h01D1,
15'h01E5, 15'h01FA, 15'h020F, 15'h0224, 15'h0239, 15'h024F, 15'h0264, 15'h0279,
15'h028F, 15'h02A5, 15'h02BA, 15'h02D0, 15'h02E6, 15'h02FC, 15'h0312, 15'h0328,
15'h033F, 15'h0355, 15'h036C, 15'h0382, 15'h0399, 15'h03B0, 15'h03C7, 15'h03DE,
15'h03F5, 15'h040C, 15'h0424, 15'h043B, 15'h0453, 15'h046B, 15'h0483, 15'h049B,
15'h04B3, 15'h04CB, 15'h04E3, 15'h04FC, 15'h0514, 15'h052D, 15'h0546, 15'h055F,
15'h0578, 15'h0591, 15'h05AB, 15'h05C4, 15'h05DE, 15'h05F8, 15'h0612, 15'h062C,
15'h0646, 15'h0661, 15'h067B, 15'h0696, 15'h06B1, 15'h06CC, 15'h06E7, 15'h0702,
15'h071D, 15'h0739, 15'h0755, 15'h0771, 15'h078D, 15'h07A9, 15'h07C5, 15'h07E2,
15'h07FF, 15'h081C, 15'h0839, 15'h0856, 15'h0873, 15'h0891, 15'h08AF, 15'h08CD,
15'h08EB, 15'h0909, 15'h0928, 15'h0947, 15'h0966, 15'h0985, 15'h09A4, 15'h09C4,
15'h09E4, 15'h0A04, 15'h0A24, 15'h0A44, 15'h0A65, 15'h0A86, 15'h0AA7, 15'h0AC8,
15'h0AEA, 15'h0B0C, 15'h0B2E, 15'h0B50, 15'h0B72, 15'h0B95, 15'h0BB8, 15'h0BDC,
15'h0BFF, 15'h0C23, 15'h0C47, 15'h0C6B, 15'h0C90, 15'h0CB5, 15'h0CDA, 15'h0D00,
15'h0D25, 15'h0D4B, 15'h0D72, 15'h0D99, 15'h0DC0, 15'h0DE7, 15'h0E0F, 15'h0E37,
15'h0E5F, 15'h0E88, 15'h0EB1, 15'h0EDA, 15'h0F04, 15'h0F2E, 15'h0F58, 15'h0F83,
15'h0FAE, 15'h0FDA, 15'h1006, 15'h1033, 15'h105F, 15'h108D, 15'h10BA, 15'h10E9,
15'h1117, 15'h1146, 15'h1176, 15'h11A6, 15'h11D6, 15'h1207, 15'h1239, 15'h126B,
15'h129D, 15'h12D0, 15'h1304, 15'h1338, 15'h136D, 15'h13A2, 15'h13D8, 15'h140F,
15'h1446, 15'h147E, 15'h14B6, 15'h14EF, 15'h1529, 15'h1564, 15'h159F, 15'h15DB,
15'h1618, 15'h1655, 15'h1694, 15'h16D3, 15'h1713, 15'h1754, 15'h1795, 15'h17D8,
15'h181C, 15'h1860, 15'h18A6, 15'h18EC, 15'h1934, 15'h197D, 15'h19C7, 15'h1A12,
15'h1A5E, 15'h1AAB, 15'h1AFA, 15'h1B4A, 15'h1B9B, 15'h1BEE, 15'h1C42, 15'h1C98,
15'h1CEF, 15'h1D48, 15'h1DA3, 15'h1DFF, 15'h1E5D, 15'h1EBD, 15'h1F1F, 15'h1F83,
15'h1FE9, 15'h2052, 15'h20BC, 15'h2129, 15'h2199, 15'h220B, 15'h2280, 15'h22F8,
15'h2373, 15'h23F2, 15'h2473, 15'h24F9, 15'h2582, 15'h260F, 15'h26A1, 15'h2737,
15'h27D1, 15'h2871, 15'h2917, 15'h29C2, 15'h2A74, 15'h2B2D, 15'h2BED, 15'h2CB5,
15'h2D86, 15'h2E60, 15'h2F45, 15'h3035, 15'h3131, 15'h323C, 15'h3356, 15'h3483,
15'h35C3, 15'h371A, 15'h388B, 15'h3A1B, 15'h3BD0, 15'h3DB0, 15'h3FC6, 15'h421F,
15'h44CE, 15'h47F0, 15'h4BB3, 15'h5069, 15'h56B8, 15'h604C, 15'h74E6, 15'h7FFF
};
parameter div = 512; // 24.576MHz/512 = 48KHz
reg [11:0]sample;
reg sample_pls;
always@(posedge I_CLK or negedge I_RESET_n)
begin
if(! I_RESET_n) begin
sample <= 0;
sample_pls <= 0;
end else begin
sample <= (sample == div-1) ? 1'b0 : sample + 1'b1;
sample_pls <= (sample == div-1)? 1'b1 : 1'b0 ;
end
end
reg signed [8:0]expval;
reg [7:0]index;
reg [14:0]count;
reg signed [23:0]snd_out;
always@(posedge I_CLK or negedge I_RESET_n)
begin
if(!I_RESET_n) begin
expval <= 9'sd255;
count <= 0;
index <= 0;
end
else begin
if (sample_pls) begin
if (I_DECAY_EN) begin
count <= (count == 15'h7FF0) ? 15'h7FF0 : count + 1'b1;
if (count == exp_lut[index]) begin
index <= (index == 8'd255) ? 8'd255 : index + 1'b1;
expval <= (expval == 0) ? 1'b0 : expval - 1'b1;
end
end
else begin
expval <= (expval == 9'sd255) ? 9'sd255 : expval + 1'b1;
count <= 0;
index <= 0;
end
snd_out <= I_SND_DAT * expval;
end
end
end
assign O_SND_DAT = snd_out[23:8];
endmodule

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//============================================================================
// Sprite DMA.
//
// Author: gaz68 (https://github.com/gaz68)
// October 2019
//
// Simplified sprite DMA. To Do: Implement full 8257 DMA controller.
//============================================================================
module dkongjr_dma
(
input I_CLK,
input I_RSTn,
input I_DMA_TRIG,
input [7:0]I_DMA_DS,
output [9:0]O_DMA_AS,
output [9:0]O_DMA_AD,
output [7:0]O_DMA_DD,
output O_DMA_CES,
output O_DMA_CED
);
parameter dma_cnt_end = 10'h17F;
reg W_DMA_EN = 1'b0;
reg [10:0]W_DMA_CNT;
reg [7:0]W_DMA_DATA;
reg [9:0]DMA_ASr;
reg [9:0]DMA_ADr;
reg [7:0]DMA_DDr;
reg DMA_CESr, DMA_CEDr;
always @(posedge I_CLK)
begin
reg old_trig;
old_trig <= I_DMA_TRIG;
if(~old_trig & I_DMA_TRIG)
begin
DMA_ASr <= 10'h100;
DMA_ADr <= 0;
W_DMA_CNT <= 0;
W_DMA_EN <= 1'b1;
DMA_CESr <= 1'b1;
DMA_CEDr <= 1'b1;
end
else if(W_DMA_EN == 1'b1)
begin
case(W_DMA_CNT[1:0])
1: DMA_DDr <= I_DMA_DS;
2: DMA_ASr <= DMA_ASr + 1'd1;
3: DMA_ADr <= DMA_ADr + 1'd1;
default:;
endcase
W_DMA_CNT <= W_DMA_CNT + 1'd1;
W_DMA_EN <= W_DMA_CNT==dma_cnt_end*4 ? 1'b0 : 1'b1;
end
else
begin
DMA_CESr <= 1'b0;
DMA_CEDr <= 1'b0;
end
end
assign O_DMA_AS = DMA_ASr;
assign O_DMA_AD = DMA_ADr;
assign O_DMA_DD = DMA_DDr;
assign O_DMA_CES = DMA_CESr;
assign O_DMA_CED = DMA_CEDr;
endmodule

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//===============================================================================
// FPGA DONKEY KONG H&V COUNTER
//
// Version : 2.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2005- 2- 9 some changed.
//================================================================================
//-----------------------------------------------------------------------------------------
// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],H_CNT[9]
// 1/2 H 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H
//-----------------------------------------------------------------------------------------
// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]
// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V
//-----------------------------------------------------------------------------------------
// VF_CNT[0],VF_CNT[1],VF_CNT[2],VF_CNT[3],VF_CNT[4],VF_CNT[5],VF_CNT[6],VF_CNT[7]
// 1 VF 2 VF 4 VF 8 VF 16 VF 32 VF 64 VF 128 VF
module dkongjr_hv_count(
// input
I_CLK,
RST_n,
V_FLIP,
// output
O_CLK,
H_CNT,
V_CNT,
VF_CNT,
H_BLANKn,
V_BLANKn,
C_BLANKn,
H_SYNCn,
V_SYNCn
);
input I_CLK;// 24.576MHz
input RST_n;
input V_FLIP;
output O_CLK;
output [9:0]H_CNT;
output [7:0]V_CNT;
output [7:0]VF_CNT;
output H_BLANKn;
output V_BLANKn;
output C_BLANKn;
output H_SYNCn;
output V_SYNCn;
parameter H_count = 1536;
parameter H_BL_P = 511;
parameter H_BL_W = 767;
parameter V_CL_P = 576;
parameter V_CL_W = 640;
parameter V_BL_P = 239;
parameter V_BL_W = 15;
reg [10:0]H_CNT_r = 0;
always@(posedge I_CLK)
begin
H_CNT_r <= (H_CNT_r == H_count-1)? 0 : H_CNT_r+1 ;
end
assign H_CNT[9:0] = H_CNT_r[10:1];
assign O_CLK = H_CNT_r[0] ;
reg V_CLK = 1'b0;
reg H_BLANK = 1'b0;
always@(posedge O_CLK)
begin
case(H_CNT[9:0])
H_BL_P: H_BLANK <= 1;
V_CL_P: V_CLK <= 1;
H_BL_W: H_BLANK <= 0;
V_CL_W: V_CLK <= 0;
default:;
endcase
end
assign H_SYNCn = ~V_CLK;
assign H_BLANKn = ~H_BLANK;
reg [8:0]V_CNT_r;
always@(posedge V_CLK or negedge RST_n)
begin
if(RST_n == 1'b0)
V_CNT_r <= 0 ;
else
V_CNT_r <= (V_CNT_r == 255)? 504 : V_CNT_r+1 ;
end
reg V_BLANK;
always@(posedge V_CLK or negedge RST_n)
begin
if(RST_n == 1'b0)begin
V_BLANK <= 0 ;
end
else begin
case(V_CNT_r[8:0])
V_BL_P: V_BLANK <= 1;
V_BL_W: V_BLANK <= 0;
default:;
endcase
end
end
assign V_CNT[7:0] = V_CNT_r[7:0];
assign V_SYNCn = ~V_CNT_r[8];
assign V_BLANKn = ~V_BLANK;
assign C_BLANKn = ~(H_BLANK | V_BLANK);
assign VF_CNT[7:0]= V_CNT ^ {8{V_FLIP}};
endmodule

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/*MIT License
Copyright (c) 2019 Gregory Hogan (Soltan_G42)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
module iir_1st_order
#(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 15,
parameter DATA_WIDTH = 8,
parameter COUNT_BITS = 11
)
(
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2, B1, B2,
input signed [DATA_WIDTH - 1 :0] in,
output signed [DATA_WIDTH - 1:0] out
);
reg signed [DATA_WIDTH-1:0] x0,x1,y0;
reg signed [DATA_WIDTH + COEFF_WIDTH - 1 : 0] out32;
reg [COUNT_BITS - 1:0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 1, 3500/(106528/2), 'low') for a 3500 hz 1st order low-pass
// assuming 106528Hz sample rate.
//
// The Matlab output is:
// B = [0.093863 0.093863]
// A = [1.00000 -0.81227]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
//
// B = [3076 3076]
// A = [32768 -26616]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -26616 , B1 = 3076 , B2 = 3076
// B1 + B2 - A2 should sum to 2^COEFF_SCALE = 32768
//
// Sample frequency is "clk rate/div": for Genesis this is 53.69mhz/504 = 106528hz
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation: out32 <= (B1*x0 + B2*x1) - A2*y0
assign out = y0;
always @ (*) begin
out32 <= (B1*x0 + B2*x1) - A2*y0; //Previous output is y0 not y1
end
always @ (posedge clk) begin
if(reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
y0 <= 0;
end
else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[COEFF_SCALE + DATA_WIDTH - 2 : COEFF_SCALE]};
x1 <= x0;
x0 <= in;
end
end
end
endmodule //iir_1st_order
module iir_2nd_order
#(
parameter COEFF_WIDTH = 18,
parameter COEFF_SCALE = 14,
parameter DATA_WIDTH = 16,
parameter COUNT_BITS = 10
)
(
input clk,
input reset,
input [COUNT_BITS - 1 : 0] div,
input signed [COEFF_WIDTH - 1 : 0] A2, A3, B1, B2, B3,
input signed [DATA_WIDTH - 1 : 0] in,
output [DATA_WIDTH - 1 : 0] out
);
reg signed [DATA_WIDTH-1 : 0] x0,x1,x2;
reg signed [DATA_WIDTH-1 : 0] y0,y1;
reg signed [(DATA_WIDTH + COEFF_WIDTH - 1) : 0] out32;
reg [COUNT_BITS : 0] count;
// Usage:
// Design your 1st order iir low/high-pass with a tool that will give you the
// filter coefficients for the difference equation. Filter coefficients can
// be generated in Octave/matlab/scipy using a command similar to
// [B, A] = butter( 2, 5000/(48000/2), 'low') for a 5000 hz 2nd order low-pass
// assuming 48000Hz sample rate.
//
// Output is:
// B = [ 0.072231 0.144462 0.072231]
// A = [1.00000 -1.10923 0.39815]
//
// Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer
// Make sure your coefficients can be stored as a signed number with COEFF_WIDTH bits.
//
// B = [1183 2367 1183]
// A = [16384 -18174 6523]
//
// Discard A(1) because it is assumed 1.0 before scaling
//
// This leaves you with A2 = -18174 , A3 = 6523, B1 = 1183 , B2 = 2367 , B3 = 1183
// B1 + B2 + B3 - A2 - A3 should sum to 2^COEFF_SCALE = 16384
//
// Sample frequency is "clk rate/div"
//
// COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to
// handle temporary overflow during this computation:
// out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1);
assign out = y0;
always @ (*) begin
out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1); //Previous output is y0 not y1
end
always @ (posedge clk) begin
if(reset) begin
count <= 0;
x0 <= 0;
x1 <= 0;
x2 <= 0;
y0 <= 0;
y1 <= 0;
end
else begin
count <= count + 1'd1;
if (count == div - 1) begin
count <= 0;
y1 <= y0;
y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[(DATA_WIDTH + COEFF_SCALE - 2) : COEFF_SCALE]};
x2 <= x1;
x1 <= x0;
x0 <= in;
end
end
end
endmodule //iir_2nd_order

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//===============================================================================
//
// Modified for Donkey Kong Junior by gaz68.
//
// FPGA DONKEY KONG INPORT
//
// Version : 1.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
//================================================================================
module dkongjr_inport(
// input
I_SW1,
I_SW2,
I_SW3,
I_DIP,
// enable
I_SW1_OE_n,
I_SW2_OE_n,
I_SW3_OE_n,
I_DIP_OE_n,
// output
O_D
);
// B0 B1 B2 B3 B4 B5 B6 B7
//-----------------------------------------------------------------------------------
//7C00(R) sw1(MAIN) RIGHT LEFT UP DOWN JUMP
//7C80(R) sw2(SUB) RIGHT LEFT UP DOWN JUMP
//7D00(R) sw3( ) 1P 2P COIN
//7D80(R) DIP
// JUMPMAN 3 0 0
// 4 1 0
// 5 0 1
// 6 1 1
// BONUS 10000 0 0
// 15000 1 0
// 20000 0 1
// 25000 1 1
// COIN 1/1 0 0 0
// 1/2 0 1 0
// 1/3 0 0 1
// 1/4 0 1 1
// 2/1 1 0 0
// 3/1 1 1 0
// 4/1 1 0 1
// 5/1 1 1 1
// Table 0
// Upright 1
//
input [7:0]I_SW1,I_SW2,I_SW3,I_DIP;
input I_SW1_OE_n,I_SW2_OE_n,I_SW3_OE_n,I_DIP_OE_n; // Active LOW
output [7:0]O_D;
wire [7:0]W_SW1 = I_SW1_OE_n ? 8'h00: ~I_SW1;
wire [7:0]W_SW2 = I_SW2_OE_n ? 8'h00: !I_DIP[7] ? ~I_SW2 : ~I_SW1;
wire [7:0]W_SW3 = I_SW3_OE_n ? 8'h00: ~I_SW3;
wire [7:0]W_DIP = I_DIP_OE_n ? 8'h00: I_DIP;
assign O_D = W_SW1 | W_SW2 | W_SW3 | W_DIP;
endmodule

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//===============================================================================
// FPGA DONKEY KONG used LOGIC IP
//
// Version : 1.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
//================================================================================
//================================================
// 74xx109
// JK FLIP-FLOPS with PRESET & RST
// PRESET NO USE
//================================================
module logic_74xx109(
CLK,
RST,
I_J,
I_K,
O_Q
);
input CLK,RST;
input I_J,I_K;
output O_Q;
reg Q;
assign O_Q = Q;
always@(posedge CLK or negedge RST)
begin
if(RST == 1'b0) Q <= 1'b0;
else begin
case({I_J,I_K})
2'b00: Q <= 1'b0;
2'b01: Q <= Q;
2'b10: Q <= ~Q;
2'b11: Q <= 1'b1;
endcase
end
end
endmodule
//================================================
// 74xx138
// 3-to-8 line decoder
//================================================
module logic_74xx138(
I_G1,
I_G2a,
I_G2b,
I_Sel,
O_Q
);
input I_G1,I_G2a,I_G2b;
input [2:0]I_Sel;
output [7:0]O_Q;
reg [7:0]O_Q;
wire [2:0]I_G = {I_G1,I_G2a,I_G2b};
always@(I_G or I_Sel or O_Q)
begin
if(I_G == 3'b100 )begin
case(I_Sel)
3'b000: O_Q = 8'b11111110;
3'b001: O_Q = 8'b11111101;
3'b010: O_Q = 8'b11111011;
3'b011: O_Q = 8'b11110111;
3'b100: O_Q = 8'b11101111;
3'b101: O_Q = 8'b11011111;
3'b110: O_Q = 8'b10111111;
3'b111: O_Q = 8'b01111111;
endcase
end
else begin
O_Q = 8'b11111111;
end
end
endmodule
//================================================
// 74xx139
// 2-to-4 line decoder
//================================================
module logic_74xx139(
I_G,
I_Sel,
O_Q
);
input I_G;
input [1:0]I_Sel;
output [3:0]O_Q;
reg [3:0]O_Q;
always@(I_G or I_Sel or O_Q)
begin
if(I_G == 1'b0 )begin
case(I_Sel)
2'b00: O_Q = 4'b1110;
2'b01: O_Q = 4'b1101;
2'b10: O_Q = 4'b1011;
2'b11: O_Q = 4'b0111;
endcase
end
else begin
O_Q = 4'b1111;
end
end
endmodule

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//===============================================================================
// FPGA DONKEY KONG OBJ
//
// Version : 4.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2004 -8-24 OBJ ROM REMOVED K.Degawa
// 2005- 2- 9 The description of the ROM was changed.
// Data on the ROM are initialized at the time of the start.
//================================================================================
//-----------------------------------------------------------------------------------------
// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],H_CNT[9]
// 1/2 H 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H
//-----------------------------------------------------------------------------------------
// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]
// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V
//-----------------------------------------------------------------------------------------
// VF_CNT[0],VF_CNT[1],VF_CNT[2],VF_CNT[3],VF_CNT[4],VF_CNT[5],VF_CNT[6],VF_CNT[7]
// 1 VF 2 VF 4 VF 8 VF 16 VF 32 VF 64 VF 128 VF
//-----------------------------------------------------------------------------------------
module dkongjr_obj(
CLK_24M,
CLK_12M,
I_AB,
I_DB,
I_OBJ_D,
I_OBJ_WRn,
I_OBJ_RDn,
I_OBJ_RQn,
I_2PSL,
I_FLIPn,
I_H_CNT,
I_VF_CNT,
I_CMPBLKn,
//I_OBJ_D1,
//I_OBJ_D2,
//I_OBJ_D3,
//I_OBJ_D4,
//O_OBJ_AB,
//---- Debug ---------
//--------------------
O_DB,
O_OBJ_DO,
O_FLIP_VRAM,
O_FLIP_HV,
O_L_CMPBLKn
);
input CLK_24M;
input CLK_12M;
input [9:0]I_AB;
input [7:0]I_DB;
input [7:0]I_OBJ_D;
input I_OBJ_WRn;
input I_OBJ_RDn;
input I_OBJ_RQn;
input I_2PSL;
input I_FLIPn;
input I_CMPBLKn;
input [9:0]I_H_CNT;
input [7:0]I_VF_CNT;
output [7:0]O_DB;
output [5:0]O_OBJ_DO;
output O_FLIP_VRAM;
output O_FLIP_HV;
output O_L_CMPBLKn;
//output [11:0]O_OBJ_AB;
//input [7:0]I_OBJ_D1,I_OBJ_D2,I_OBJ_D3,I_OBJ_D4;
//---- Debug ---------
//--------------------
wire W_5F1_G = ~(I_H_CNT[0]&I_H_CNT[1]&I_H_CNT[2]&I_H_CNT[3]);
reg W_5B;
always@(negedge CLK_24M) W_5B <= ~(I_H_CNT[0]&I_H_CNT[1]&I_H_CNT[2]&I_H_CNT[3]);
wire [3:0]W_5F1_Q;
wire [3:0]W_5F2_QB;
logic_74xx139 U_5F1(
.I_G(W_5F1_G),
.I_Sel({~I_H_CNT[9],I_H_CNT[3]}),
.O_Q(W_5F1_Q)
);
logic_74xx139 U_5F2(
.I_G(1'b0),
.I_Sel({I_H_CNT[3],I_H_CNT[2]}),
.O_Q(W_5F2_QB)
);
reg [3:0]W_5F2_Q;
always@(negedge CLK_24M) W_5F2_Q <= W_5F2_QB;
//---------- FLIP ----------------------------------------------------
wire W_FLIP_1 = ~I_FLIPn; // INV
wire W_FLIP_2 = W_FLIP_1 ^ 1'b1; // INV => XOR
wire W_FLIP_3 = ~W_FLIP_2; // INV => XOR => INV
wire W_FLIP_4 = W_FLIP_3 | W_5F2_Q[0];
wire W_FLIP_5 = ~W_FLIP_4;
assign O_FLIP_VRAM = W_FLIP_1;
assign O_FLIP_HV = W_FLIP_3;
//------- DB CONTROL ------------------------------------------------
wire [7:0]WI_DB = I_OBJ_WRn ? 8'h00: I_DB;
wire [7:0]WO_DB;
//assign O_DB = I_OBJ_RDn ? 8'h00: WO_DB;
//------- AB CONTROL ------------------------------------------------
wire W_AB_SEL = I_OBJ_WRn & I_OBJ_RDn & I_OBJ_RQn;
wire [9:0]W_obj_AB = W_AB_SEL ? {I_2PSL,I_H_CNT[8:0]} : I_AB ;
wire W_obj_CS = W_AB_SEL ? 1'b0 : I_OBJ_WRn & I_OBJ_RDn;
//------- VFC_CNT[7:0] ------------------------------------------------
reg [7:0]W_VFC_CNT;
always@(negedge I_H_CNT[9]) W_VFC_CNT <= I_VF_CNT;
//------ PARTS 6N
reg [7:0]W_6N_Q;
always@(negedge CLK_12M) W_6N_Q <= I_OBJ_D;
wire [7:0]W_78R_A = W_6N_Q;
wire [7:0]W_78R_B = {4'b1111,I_FLIPn,W_FLIP_1,W_FLIP_1,1'b1};
wire [8:0]W_78R_Q = W_78R_A + W_78R_B + 8'b00000001;
wire [7:0]W_78P_A = W_78R_Q[7:0];
wire [7:0]W_78P_B = I_VF_CNT[7:0];
wire [8:0]W_78P_Q = W_78P_A + W_78P_B;
reg W_7H;
always@(posedge CLK_12M) W_7H <= ~(W_78P_Q[7]&W_78P_Q[6]&W_78P_Q[5]&W_78P_Q[4]);
reg [7:0]W_5L_Q;
reg CLK_4L;
always@(negedge CLK_24M) CLK_4L = ~(I_H_CNT[0]&(~I_H_CNT[1]));
wire W_6L = ~(W_5L_Q[6]|W_5L_Q[7]);
wire W_3P = ~(I_H_CNT[2]&I_H_CNT[3]&I_H_CNT[4]&I_H_CNT[5]&I_H_CNT[6]&I_H_CNT[7]&I_H_CNT[8] & W_6L);
//-- U_4L ---------------
reg W_4L_Q;
wire RST_4L = ~I_H_CNT[9];
always@(posedge CLK_4L or negedge RST_4L)
begin
if(RST_4L == 0) W_4L_Q <= 1'b0;
else W_4L_Q <= ~(W_7H&W_3P);
end
wire CLK_5L = ~(CLK_12M&(~I_H_CNT[9])&W_4L_Q&W_6L);
wire W_5L_RST = ~I_H_CNT[9];
always@(posedge CLK_5L or negedge W_5L_RST)
begin
if(W_5L_RST == 1'b0) W_5L_Q <= 0;
else W_5L_Q <= W_5L_Q +1;
end
//------ PARTS 6M ----------------------------------------------
reg [7:0]W_6M_Q;
always@(negedge CLK_12M) W_6M_Q <= W_6N_Q;
//----------------------------------------------------------------
wire [5:0]W_RAM_7M_AB = ~I_H_CNT[9] ? W_5L_Q[5:0]:I_H_CNT[7:2];
wire [8:0]W_RAM_7M_DIB = {W_6M_Q[7:0],W_3P};
wire [8:0]W_RAM_7M_DOB;
wire [8:0]W_RAM_7M_DOBn = W_RAM_7M_DOB[8:0];
reg [7:0]W_HD;
always@(negedge CLK_24M) W_HD <= W_RAM_7M_DOBn[8:1];
wire [7:0]W_78K_A = W_RAM_7M_DOBn[8:1];
wire [7:0]W_78K_B = {4'b1111,W_FLIP_5,W_FLIP_4,W_FLIP_4,1'b1};
wire [8:0]W_78K_Q = W_78K_A + W_78K_B + 8'b00000001;
wire [7:0]W_78J_A = W_78K_Q[7:0];
wire [7:0]W_78J_B = W_VFC_CNT[7:0];
wire [8:0]W_78J_Q = W_78J_A + W_78J_B;
wire [7:0]W_8H_D = W_78J_Q[7:0];
reg [7:0]W_8H_Q;
always@(posedge W_5F2_Q[0]) W_8H_Q <= W_8H_D;
reg [7:0]W_6J_Q;
always@(posedge W_5F2_Q[2]) W_6J_Q <= W_HD[7:0];
wire [7:0]W_6K_D = {W_6J_Q[7],I_CMPBLKn,~I_H_CNT[9],
~(I_H_CNT[9]|W_FLIP_2),W_6J_Q[3:0]};
reg [7:0]W_6K_Q;
always@(posedge CLK_12M)
begin
if(W_5B == 1'b0) W_6K_Q <= W_6K_D;
else W_6K_Q <= W_6K_Q;
end
assign O_L_CMPBLKn = W_6K_Q[6];
wire W_8N_Q;
logic_74xx109 U_8N(
.CLK(W_5F2_Q[0]),
.RST(I_H_CNT[9]),
.I_J(~W_RAM_7M_DOBn[0]),
.I_K(1'b1),
.O_Q(W_8N_Q)
);
wire W_6F = ~(W_8H_Q[4]&W_8H_Q[5]&W_8H_Q[6]&W_8H_Q[7]);
wire W_5J = W_8N_Q|W_6F;
wire W_6L1 = ~(W_5J|W_5B);
//------ PARTS 6H ----------------------------------------------
wire W_6H_G = ~W_5F2_Q[1];
reg [7:0]W_6H_Q;
always@(W_6H_G or W_HD[7:0])
begin
if(W_6H_G) W_6H_Q <= W_HD[7:0];
//else
// W_6H_Q <= W_6H_Q;
end
//----------------------------------------------------------------
wire [3:0]W_8B_A,W_8B_B,W_8B_Y;
wire W_8C_Qa,W_8D_Qh;
wire W_8E_Qa,W_8F_Qh;
//------ PARTS 8CD ----------------------------------------------
wire [1:0]C_8CD = W_8B_Y[1:0];
wire [15:0]I_8CD = {W_OBJ_DO_7C,W_OBJ_DO_7D};
reg [15:0]reg_8CD;
assign W_8C_Qa = reg_8CD[15];
assign W_8D_Qh = reg_8CD[0];
always@(posedge CLK_12M)
begin
case(C_8CD)
2'b00: reg_8CD <= reg_8CD;
2'b10: reg_8CD <= {reg_8CD[14:0],1'b0};
2'b01: reg_8CD <= {1'b0,reg_8CD[15:1]};
2'b11: reg_8CD <= I_8CD;
endcase
end
//------ PARTS 8EF ----------------------------------------------
wire [1:0]C_8EF = W_8B_Y[1:0];
wire [15:0]I_8EF = {W_OBJ_DO_7E,W_OBJ_DO_7F};
reg [15:0]reg_8EF;
assign W_8E_Qa = reg_8EF[15];
assign W_8F_Qh = reg_8EF[0];
always@(posedge CLK_12M)
begin
case(C_8EF)
2'b00: reg_8EF <= reg_8EF;
2'b10: reg_8EF <= {reg_8EF[14:0],1'b0};
2'b01: reg_8EF <= {1'b0,reg_8EF[15:1]};
2'b11: reg_8EF <= I_8EF;
endcase
end
//------ PARTS 8B ----------------------------------------------
assign W_8B_A = {W_8C_Qa,W_8E_Qa,1'b1,W_6L1};
assign W_8B_B = {W_8D_Qh,W_8F_Qh,W_6L1,1'b1};
assign W_8B_Y = W_6K_Q[7] ? W_8B_B:W_8B_A;
//------ PRATS 3E & 4E -----------------------------------------
reg CLK_3E;
always@(negedge CLK_24M)
CLK_3E <= ~(~(I_H_CNT[0]&W_6K_Q[5])& CLK_12M);
wire [7:0]W_3E_LD_DI = W_78K_Q[7:0];
wire W_3E_RST = W_5F1_Q[3]|W_6K_Q[5];
wire W_3E_LD = W_5F1_Q[1];
reg [7:0]W_3E_Q;
always@(posedge CLK_3E)
begin
if(W_3E_LD == 1'b0)
W_3E_Q <= W_3E_LD_DI;
else begin
if(W_3E_RST == 1'b0)
W_3E_Q <= 0 ;
else
W_3E_Q <= W_3E_Q +1;
end
end
wire [5:0]W_RAM_2EH_DO;
wire [5:0]W_3J_B = {W_6K_Q[3:0],W_8B_Y[2],W_8B_Y[3]};
wire [5:0]W_RAM_2EH_DI = W_6K_Q[5] ? 8'h00 :(W_8B_Y[2]|W_8B_Y[3])? W_3J_B: W_RAM_2EH_DO;
wire [7:0]W_RAM_2EH_AB = W_3E_Q[7:0]^{8{W_6K_Q[4]}};
ram_2EH7M U_2EH_7M(
// 256_6
.I_CLKA(CLK_24M),
.I_ADDRA(W_RAM_2EH_AB),
.I_DA(W_RAM_2EH_DI),
.I_CEA(1'b1),
.I_WEA(~CLK_3E),
.O_DA(W_RAM_2EH_DO),
// 64_9
.I_CLKB(~CLK_24M),
.I_ADDRB(W_RAM_7M_AB),
.I_DB(W_RAM_7M_DIB),
.I_CEB(1'b1),
.I_WEB(~CLK_5L),
.O_DB(W_RAM_7M_DOB)
);
//------ PARTS 3K ----------------------------------------------
reg [5:0]O_OBJ_DO;
always@(posedge CLK_24M)
begin
if(~CLK_12M)
O_OBJ_DO <= W_RAM_2EH_DO;
else
O_OBJ_DO <= O_OBJ_DO ;
end
wire [10:0]W_ROM_OBJ_AB = {W_6H_Q[6:0],W_8H_Q[3:0]^{W_6H_Q[7],W_6H_Q[7],W_6H_Q[7],W_6H_Q[7]}};
wire [7:0]W_OBJ_DO_7C,W_OBJ_DO_7D,W_OBJ_DO_7E,W_OBJ_DO_7F;
obj1 obj1 (
.clk(CLK_12M),
.addr(W_ROM_OBJ_AB),
.data(W_OBJ_DO_7C)
);
obj2 obj2 (
.clk(CLK_12M),
.addr(W_ROM_OBJ_AB),
.data(W_OBJ_DO_7D)
);
obj3 obj3 (
.clk(CLK_12M),
.addr(W_ROM_OBJ_AB),
.data(W_OBJ_DO_7E)
);
obj4 obj4 (
.clk(CLK_12M),
.addr(W_ROM_OBJ_AB),
.data(W_OBJ_DO_7F)
);
endmodule

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//============================================================================
// ROMS + Sound samples for analogur sounds.
//
// Author: gaz68 (https://github.com/gaz68)
// October 2019
//
//============================================================================
//
// Contents of A.DKONGJR.ROM file:
//
// 0x00000 - 0x01FFF 5B PROGRAM ROM (8KB)
// 0x02000 - 0x03FFF 5C PROGRAM ROM (8KB)
// 0x04000 - 0x05FFF 5E PROGRAM ROM (8KB)
// 0x06000 - 0x06FFF 3P GFX ROM (4KB)
// 0x07000 - 0x07FFF 3N GFX ROM (4KB)
// 0x08000 - 0x09FFF 5B PROGRAM ROM REPEAT (8KB)
// 0x0A000 - 0x0A7FF 7C GFX ROM (2KB)
// 0x0A800 - 0x0AFFF 7C GFX ROM REPEAT (2KB)
// 0x0B000 - 0x0B7FF 7D GFX ROM (2KB)
// 0x0B800 - 0x0BFFF 7D GFX ROM REPEAT (2KB)
// 0x0C000 - 0x0C7FF 7E GFX ROM (2KB)
// 0x0C800 - 0x0CFFF 7E GFX ROM REPEAT (2KB)
// 0x0D000 - 0x0D7FF 7F GFX ROM (2KB)
// 0x0D800 - 0x0DFFF 7F GFX ROM REPEAT (2KB)
// 0x0E000 - 0x0EFFF 3H SOUND ROM (4KB)
// 0x0F000 - 0x0F0FF 2E PROM (256B)
// 0x0F100 - 0x0F1FF 2F PROM (256B)
// 0x0F200 - 0x0F2FF 2N PROM (256B)
// 0x0F300 - 0x0FFFF EMPTY
//--------------------------------------------
// 0x10000 - 0x10FFF WALK SOUND SAMPLE 0 (4KB)
// 0x11000 - 0x11FFF WALK SOUND SAMPLE 1 (4KB)
// 0x12000 - 0x12FFF WALK SOUND SAMPLE 2 (4KB)
// 0x13000 - 0x13FFF CLIMB SOUND SAMPLE 0 (4KB)
// 0x14000 - 0x14FFF CLIMB SOUND SAMPLE 1 (4KB)
// 0x15000 - 0x15FFF CLIMB SOUND SAMPLE 2 (4KB)
// 0x16000 - 0x19FFF JUMP SOUND SAMPLE (16KB)
// 0x1A000 - 0x1DFFF LAND SOUND SAMPLE (16KB)
// 0x1E000 - 0x27FFF FALL SOUND SAMPLE (40KB)
module dkongjr_rom
(
input I_CLKA,I_CLKB,
input [17:0]I_ADDRA,
input [16:0]I_ADDRB,
input [15:0]I_ADDRC,
input [7:0]I_DA,
input I_WEA,
output [7:0]O_DB,
output [15:0]O_DC
);
reg [16:0] W_ADDRB;
// Program ROM address translation (0x0000 - 0x5FFF).
// Program ROMs are addressed as follows:
// 0x0000 - 0x0FFF ROM 5B [0x0000 - 0x0FFF] (4KB)
// 0x1000 - 0x17FF ROM 5C [0x1000 - 0x17FF] (2KB)
// 0x1800 - 0x1FFF ROM 5E [0x1800 - 0x1FFF] (2KB)
// 0x2000 - 0x27FF ROM 5C [0x0000 - 0x07FF] (2KB)
// 0x2800 - 0x2FFF ROM 5E [0x0800 - 0x0FFF] (2KB)
// 0x3000 - 0x3FFF ROM 5B [0x1000 - 0x1FFF] (4KB)
// 0x4000 - 0x47FF ROM 5E [0x0000 - 0x07FF] (2KB)
// 0x4800 - 0x4FFF ROM 5C [0x0800 - 0x0FFF] (2KB)
// 0x5000 - 0x57FF ROM 5E [0x1000 - 0x17FF] (2KB)
// 0x5800 - 0x5FFF ROM 5C [0x1800 - 0x1FFF] (2KB)
always @(*) begin
case(I_ADDRB[16:11])
6'h02: W_ADDRB = {6'h06,I_ADDRB[10:0]}; // 0x1000-0x17FF -> 0x3000-0x37FF in ROM file
6'h03: W_ADDRB = {6'h0B,I_ADDRB[10:0]}; // 0x1800-0x1FFF -> 0x5800-0x5FFF in ROM file
6'h05: W_ADDRB = {6'h09,I_ADDRB[10:0]}; // 0x2800-0x2FFF -> 0x4800-0x4FFF in ROM file
6'h06: W_ADDRB = {6'h02,I_ADDRB[10:0]}; // 0x3000-0x37FF -> 0x1000-0x17FF in ROM file
6'h07: W_ADDRB = {6'h03,I_ADDRB[10:0]}; // 0x3800-0x3FFF -> 0x1800-0x1FFF in ROM file
6'h09: W_ADDRB = {6'h05,I_ADDRB[10:0]}; // 0x4800-0x4FFF -> 0x2800-0x2FFF in ROM file
6'h0B: W_ADDRB = {6'h07,I_ADDRB[10:0]}; // 0x5800-0x5FFF -> 0x3800-0x3FFF in ROM file
default: W_ADDRB = I_ADDRB;
endcase
end
dpram #(16) roms
(
.clock_a(I_CLKA),
.wren_a(I_WEA && (I_ADDRA[17:16] == 2'b0)),
.address_a(I_ADDRA[15:0]),
.data_a(I_DA),
.clock_b(I_CLKB),
.address_b(W_ADDRB),
.q_b(O_DB)
);
// Write 8-bit download stream to wave ROM as 16-bit words.
reg [15:0]WAV_ADDR = 0;
reg [7:0]DA_L = 0;
reg [15:0]DA16 = 0;
always @(posedge I_CLKA) begin
if (I_ADDRA[17:16] > 0) begin
if (I_ADDRA[0] == 1'b0) begin
DA_L <= I_DA;
end else begin
DA16 <= {I_DA, DA_L};
WAV_ADDR <= I_ADDRA[17:1] - 17'h08000;
end
end
end
// 16-bit sound samples for analogue sounds.
dpram #(16, 16) wav_rom
(
.clock_a(I_CLKA),
.wren_a(I_WEA),
.address_a(WAV_ADDR),
.data_a(DA16),
.clock_b(I_CLKB),
.address_b(I_ADDRC),
.q_b(O_DC)
);
endmodule

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//===============================================================================
//
// Modified for Donkey Kong Junior by gaz68.
//
// FPGA DONKEY KONG SOUND_I/F
//
// Version : 4.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2004- 9- 2 T48-IP(beta3) was include. K.Degawa
// 2004- 9-14 T48-IP was changed to beta4. K.Degawa
// 2005- 2- 9 The description of the ROM was changed.
// Data on the ROM are initialized at the time of the start.
//================================================================================
module dkongjr_sound(
I_CLK1,
I_CLK2,
I_RST,
I8035_DBI,
I8035_DBO,
I8035_PAI,
I8035_PBI,
I8035_PBO,
I8035_ALE,
I8035_RDn,
I8035_PSENn,
I8035_RSTn,
I8035_INTn,
I8035_T0,
I8035_T1,
I_SOUND_DAT,
I_SOUND_CNT,
O_SOUND_DAT
);
input I_CLK1,I_CLK2;
input I_RST;
input [7:0]I8035_DBI;
output [7:0]I8035_DBO;
input [7:0]I8035_PAI;
input [7:0]I8035_PBI;
output [7:0]I8035_PBO;
input I8035_ALE;
input I8035_RDn;
input I8035_PSENn;
input [4:0]I_SOUND_DAT;
input [5:0]I_SOUND_CNT;
output I8035_INTn;
output I8035_T0;
output I8035_T1;
output I8035_RSTn;
output [7:0]O_SOUND_DAT;
assign I8035_PBO[6] = ~I_SOUND_CNT[5];
assign I8035_PBO[4] = ~I_SOUND_CNT[4];
assign I8035_T0 = ~I_SOUND_CNT[3];
assign I8035_T1 = ~I_SOUND_CNT[2];
assign I8035_PBO[5] = ~I_SOUND_CNT[1];
assign I8035_INTn = ~I_SOUND_CNT[0];
assign I8035_RSTn = I_RST;
assign I8035_PBO[3:0] = 4'b0000;
assign I8035_PBO[7] = 1'b0;
//---- Parts 4FH -----------------------------
wire [11:0]S_ROM_A;
reg [7:0]L_ROM_A;
always@(negedge I8035_ALE) L_ROM_A <= I8035_DBI ;
assign S_ROM_A = {I8035_PBI[3:0],L_ROM_A[7:0]};
//---- Parts 4C ------------------------------
reg S_D1_CS;
always@(posedge I_CLK1) S_D1_CS <= ~I8035_RDn;
wire [7:0]S_D1 = S_D1_CS ? {3'h0,I_SOUND_DAT[4:0]}: 8'h00 ;
//---- PROG ROM 3H ---------------------------
wire [7:0]S_PROG_DB;
wire [7:0]S_PROG_D = I8035_PSENn ? 8'h00 : S_PROG_DB ;
snd1 snd1 (
.clk(I_CLK2),
.addr(S_ROM_A),
.data(S_PROG_DB)
);
//---- I8035_DB IO I/F -----------------------
wire [7:0]I8035_DO = S_PROG_D | S_D1;
reg [7:0]DO;
always@(posedge I_CLK1) DO <= I8035_DO;
assign I8035_DBO = DO;
//---- DAC I/F ------------------------
assign O_SOUND_DAT = I8035_PAI;
endmodule

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//===============================================================================
// Arcade: Donkey Kong Junior by gaz68 (Oct 2019)
// https://github.com/gaz68
//
// Original Donkey Kong core by Katsumi Degawa.
//===============================================================================
//===============================================================================
// FPGA DONKEY KONG TOP
//
// Version : 4.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2004- 3- 3 first release.
// 2004- 6- 8 Quartus2 v4.0sp1 used (bug fix) K.Degawa
// 2004- 8-24 T80-IP was include. K.Degawa
// 2004- 9- 2 T48-IP(beta3) was include. K.Degawa
// 2004- 9-14 T48-IP was changed to beta4. K.Degawa
// 2005- 2- 9 Data on the ROM are initialized at the time of the start.
// added device.
// changed module I/O.
//================================================================================
//--------------------------------------------------------------------------------
module dkongjr_top
(
// FPGA_USE
input I_CLK_24576M,
input I_RESETn,
output O_PIX,
// INPORT SW IF
input I_U1,I_D1,I_L1,I_R1,I_J1,
input I_U2,I_D2,I_L2,I_R2,I_J2,
input I_S1,I_S2,I_C1,I_SF,
//input I_DEBUG,
input [7:0]I_DIP_SW,
// VGA (VIDEO) IF
output [2:0]O_VGA_R,
output [2:0]O_VGA_G,
output [1:0]O_VGA_B,
output O_H_BLANK,
output O_V_BLANK,
output O_VGA_H_SYNCn,
output O_VGA_V_SYNCn,
// SOUND IF
output signed [15:0] O_SOUND_DAT
);
assign O_H_BLANK = ~W_H_BLANKn;
assign O_V_BLANK = ~W_V_BLANKn;
wire W_CLK_24576M = I_CLK_24576M;
wire W_CLK_12288M,WB_CLK_12288M;
wire WB_CLK_06144M;
wire W_RESETn = I_RESETn;
//============ CPU MODULE ( Donkey Kong ) ====================================
//======== Assign Wire =========================================================
// INPUT DATA BUS
wire [7:0]ZDO,ZDI;
wire [7:0]WI_D = ZDI;
// INPORT DATA OUT
wire [7:0]W_SW_DO;
// ADDRESS DECODER
wire W_ROM_CSn;
wire W_RAM1_CSn;
wire W_RAM2_CSn;
wire W_RAM3_CSn;
wire W_RAM_CSn = W_RAM1_CSn & W_RAM2_CSn & W_RAM3_CSn;
//wire W_6A_Gn;
wire W_OBJ_RQn;
wire W_OBJ_RDn;
wire W_OBJ_WRn;
wire W_VRAM_RDn;
wire W_VRAM_WRn;
wire W_SW1_OEn ;
wire W_SW2_OEn ;
wire W_SW3_OEn ;
wire W_DIP_OEn ;
wire W_SW_OEn = W_SW1_OEn & W_SW2_OEn & W_SW3_OEn & W_DIP_OEn;
wire [1:0]W_4H_Q;
wire [7:0]W_5H_Q;
wire [7:0]W_6H_Q;
wire [4:0]W_3D_Q;
// INT RAM DATA
wire [7:0]W_RAM1_DO;
wire [7:0]W_RAM2_DO;
wire [7:0]W_RAM3_DO;
// EXT ROM DATA
wire [7:0]W_ROM_DO;
// H&V COUNTER
wire [9:0]W_H_CNT;
//wire [7:0]W_V_CNT;
wire W_H_BLANKn;
wire W_V_BLANKn;
wire W_C_BLANKn;
wire W_H_SYNCn;
wire W_V_SYNCn;
wire [7:0]W_OBJ_DB;
wire [7:0]W_VRAM_DB;
wire [7:0]W_OBJ_DI;
wire W_CPU_CLK;
wire W_CPU_RESETn = W_RESETn;
wire W_CPU_WAITn;
wire W_CPU_RFSHn;
wire W_CPU_M1n;
wire W_CPU_NMIn;
wire W_CPU_MREQn;
wire W_CPU_RDn;
wire W_CPU_WRn;
wire [15:0]W_CPU_A;
assign WB_CLK_06144M = W_H_CNT[0]; // 6.144MHz
assign WB_CLK_12288M = W_CLK_12288M; // 12.288MHz
assign W_CPU_CLK = W_H_CNT[1]; // 3.072MHz
T80as z80core(
.RESET_n(W_RESETn),
.CLK_n(W_CPU_CLK),
.WAIT_n(W_CPU_WAITn),
.INT_n(1'b1),
.NMI_n(W_CPU_NMIn),
.BUSRQ_n(1'b1),
.M1_n(W_CPU_M1n),
.MREQ_n(W_CPU_MREQn),
.RD_n(W_CPU_RDn),
.WR_n(W_CPU_WRn),
.RFSH_n(W_CPU_RFSHn),
.A(W_CPU_A),
.DI(ZDO),
.DO(ZDI)
);
//========= CPU DATA BUS[7:0] ==============================================
wire [7:0]WO_D = W_SW_DO | W_RAM1_DO |W_RAM2_DO |W_RAM3_DO | W_ROM_DO | W_VRAM_DB ;
assign ZDO = WO_D;
wire [11:0]OBJ_ROM_A;
reg [7:0]OBJ_ROM1_DO,OBJ_ROM2_DO,OBJ_ROM3_DO,OBJ_ROM4_DO;
reg [7:0]WB_ROM_DO;
assign W_ROM_DO = (~W_ROM_CSn & ~W_CPU_RDn)? WB_ROM_DO :8'h00;
//---------------------------------------------------------
prog ROM(
.clk(W_CLK_12288M),
.addr(W_CPU_A[14:0]),
.data(WB_ROM_DO)
);
//======== INT RAM Interface ==================================================
ram_1024_8 U_3C4C
(
.I_CLK(~W_CLK_12288M),
.I_ADDR(W_CPU_A[9:0]),
.I_D(WI_D),
.I_CE(~W_RAM1_CSn),
.I_WE(~W_CPU_WRn),
.O_D(W_RAM1_DO)
);
ram_1024_8 U_3B4B
(
.I_CLK(~W_CLK_12288M),
.I_ADDR(W_CPU_A[9:0]),
.I_D(WI_D),
.I_CE(~W_RAM2_CSn),
.I_WE(~W_CPU_WRn),
.O_D(W_RAM2_DO)
);
//---- Sprite DMA ------------------------------------------
wire [9:0]W_OBJ_AB = {W_2PSL, W_H_CNT[8:0]};
wire [9:0]W_DMA_A;
wire [7:0]W_DMA_D;
wire W_DMA_CE;
wire [9:0]W_DMA_AB;
wire [7:0]W_DMA_DB;
wire W_DMA_CEB;
ram_1024_8_8 U_3A4A
(
// A Port
.I_CLKA(~W_CLK_12288M),
.I_ADDRA(W_CPU_A[9:0]),
.I_DA(WI_D),
.I_CEA(~W_RAM3_CSn),
.I_WEA(~W_CPU_WRn),
.O_DA(W_RAM3_DO),
// B Port
.I_CLKB(W_CLK_12288M),
.I_ADDRB(W_DMA_A),
.I_DB(8'h00),
.I_CEB(W_DMA_CE),
.I_WEB(1'b0),
.O_DB(W_DMA_D)
);
dkongjr_dma sprite_dma
(
.I_CLK(W_H_CNT[0]), // 3.072 Mhz
.I_DMA_TRIG(W_DREQ),
.I_DMA_DS(W_DMA_D),
.O_DMA_AS(W_DMA_A),
.O_DMA_AD(W_DMA_AB),
.O_DMA_DD(W_DMA_DB),
.O_DMA_CES(W_DMA_CE),
.O_DMA_CED(W_DMA_CEB)
);
ram_1024_8_8 U_6PR
(
// A Port
.I_CLKA(~W_CLK_12288M),
.I_ADDRA(W_DMA_AB),
.I_DA(W_DMA_DB),
.I_CEA(W_DMA_CEB),
.I_WEA(1'b1),
.O_DA(),
// B Port
.I_CLKB(W_CLK_12288M),
.I_ADDRB(W_OBJ_AB[9:0]),
.I_DB(8'h00),
.I_CEB(1'b1),
.I_WEB(1'b0),
.O_DB(W_OBJ_DI)
);
//---- SW Interface ---------------------------------
wire [7:0]W_SW1={1'b1,1'b1,1'b1,I_J1,I_D1,I_U1,I_L1,I_R1};
wire [7:0]W_SW2={1'b1,1'b1,1'b1,I_J2,I_D2,I_U2,I_L2,I_R2};
wire [7:0]W_SW3={I_C1,1'b1,1'b1,1'b1,I_S2,I_S1,1'b1,1'b1};
dkongjr_inport inport
(
// input
.I_SW1(W_SW1),
.I_SW2(W_SW2),
.I_SW3(W_SW3),
.I_DIP(I_DIP_SW),
// enable
.I_SW1_OE_n(W_SW1_OEn),
.I_SW2_OE_n(W_SW2_OEn),
.I_SW3_OE_n(W_SW3_OEn),
.I_DIP_OE_n(W_DIP_OEn),
// output
.O_D(W_SW_DO)
);
//======== Address Decoder =====================================================
wire W_VRAMBUSYn;
dkongjr_adec adec
(
.I_CLK12M(W_CLK_12288M),
.I_CLK(W_CPU_CLK),
.I_RESET_n(W_RESETn),
.I_AB(W_CPU_A),
.I_DB(WI_D),
.I_MREQ_n(W_CPU_MREQn),
.I_RFSH_n(W_CPU_RFSHn),
.I_RD_n(W_CPU_RDn),
.I_WR_n(W_CPU_WRn),
.I_VRAMBUSY_n(W_VRAMBUSYn),
.I_VBLK_n(W_V_BLANKn),
.O_WAIT_n(W_CPU_WAITn),
.O_NMI_n(W_CPU_NMIn),
.O_ROM_CS_n(W_ROM_CSn),
.O_RAM1_CS_n(W_RAM1_CSn),
.O_RAM2_CS_n(W_RAM2_CSn),
.O_RAM3_CS_n(W_RAM3_CSn),
.O_DMA_CS_n(/*O_DMA_CSn*/),
.O_6A_G_n(/*W_6A_Gn*/),
.O_OBJ_RQ_n(W_OBJ_RQn),
.O_OBJ_RD_n(W_OBJ_RDn),
.O_OBJ_WR_n(W_OBJ_WRn),
.O_VRAM_RD_n(W_VRAM_RDn),
.O_VRAM_WR_n(W_VRAM_WRn),
.O_SW1_OE_n(W_SW1_OEn),
.O_SW2_OE_n(W_SW2_OEn),
.O_SW3_OE_n(W_SW3_OEn),
.O_DIP_OE_n(W_DIP_OEn),
.O_4H_Q(W_4H_Q),
.O_5H_Q(W_5H_Q),
.O_6H_Q(W_6H_Q),
.O_3D_Q(W_3D_Q)
);
wire W_FLIPn = W_5H_Q[2];
wire W_2PSL = W_5H_Q[3];
wire W_DREQ = W_5H_Q[5]; // DMA Trigger
//=========== VIDEO MODULE ===================================
//======== Assign Wire =======================================
wire [7:0]W_VF_CNT;
wire [5:0]W_OBJ_DAT;
wire W_FLIP_VRAM;
wire W_FLIP_HV;
wire W_L_CMPBLKn;
wire [3:0]W_VRAM_COL;
wire [1:0]W_VRAM_VID;
wire [5:0]W_VRAM_DAT = {W_VRAM_COL[3:0],W_VRAM_VID[1:0]};
//======== H & V Counter =====================================================
dkongjr_hv_count hv
(
// input
.I_CLK(W_CLK_24576M),
.RST_n(W_RESETn),
.V_FLIP(W_FLIP_HV),
// output
.O_CLK(W_CLK_12288M),
.H_CNT(W_H_CNT),
.V_CNT(/*W_V_CNT*/),
.VF_CNT(W_VF_CNT),
.H_BLANKn(W_H_BLANKn),
.V_BLANKn(W_V_BLANKn),
.C_BLANKn(W_C_BLANKn),
.H_SYNCn(W_H_SYNCn),
.V_SYNCn(W_V_SYNCn)
);
//======== OBJ (VIDEO) =====================================================
dkongjr_obj obj
(
// input
.CLK_24M(W_CLK_24576M),
.CLK_12M(WB_CLK_12288M),
.I_AB(),
.I_DB(/*W_2N_DO*/),
.I_OBJ_D(W_OBJ_DI),
.I_OBJ_WRn(1'b1),
.I_OBJ_RDn(1'b1),
.I_OBJ_RQn(1'b1),
.I_2PSL(W_2PSL),
.I_FLIPn(W_FLIPn),
.I_H_CNT(W_H_CNT),
.I_VF_CNT(W_VF_CNT),
.I_CMPBLKn(W_C_BLANKn),
// Debug
// output
.O_DB(W_OBJ_DB),
.O_OBJ_DO(W_OBJ_DAT),
.O_FLIP_VRAM(W_FLIP_VRAM),
.O_FLIP_HV(W_FLIP_HV),
.O_L_CMPBLKn(W_L_CMPBLKn)
);
//======== V-RAM (VIDEO) =====================================================
dkongjr_vram vram
(
// input
.CLK_12M(~W_CLK_12288M),
.I_AB(W_CPU_A[9:0]),
.I_DB(WI_D),
.I_VRAM_WRn(W_VRAM_WRn),
.I_VRAM_RDn(W_VRAM_RDn),
.I_FLIP(W_FLIP_VRAM),
.I_H_CNT(W_H_CNT),
.I_VF_CNT(W_VF_CNT),
.I_CMPBLK(W_C_BLANKn),
.I_4H_Q0(W_4H_Q[0]),
// Debug
// output
.O_DB(W_VRAM_DB),
.O_COL(W_VRAM_COL),
.O_VID(W_VRAM_VID),
.O_VRAMBUSYn(W_VRAMBUSYn),
.O_ESBLKn()
);
//======== COLOR PALETE =====================================================
wire [2:0]W_R;
wire [2:0]W_G;
wire [1:0]W_B;
assign O_PIX = W_H_CNT[0];
dkongjr_col_pal cpal
(
// input
.CLK_6M(W_H_CNT[0]),
.CLK_12M(W_CLK_12288M),
.I_VRAM_D(W_VRAM_DAT),
.I_OBJ_D(W_OBJ_DAT),
.I_CMPBLKn(W_L_CMPBLKn),
.I_5H_Q6(W_5H_Q[6]),
.I_5H_Q7(W_5H_Q[7]),
// output
.O_R(W_R),
.O_G(W_G),
.O_B(W_B)
);
//======== VIDEO Interface =====================================================
assign O_VGA_R = W_R;
assign O_VGA_G = W_G;
assign O_VGA_B = W_B;
assign O_VGA_H_SYNCn = W_H_SYNCn;
assign O_VGA_V_SYNCn = W_V_SYNCn;
//======== DIGTAL SOUND =====================================================
// Background music and some of the sound effects
wire [7:0]W_D_S_DAT;
wire [15:0]W_D_S_DATB;
wire [15:0]W_D_S_DATC;
wire [7:0]I8035_DBI;
wire [7:0]I8035_DBO;
wire [7:0]I8035_PAI;
wire [7:0]I8035_PBI;
wire [7:0]I8035_PBO;
wire I8035_ALE;
wire I8035_RDn;
wire I8035_PSENn;
wire I8035_CLK = WB_CLK_06144M;
wire I8035_INTn;
wire I8035_T0;
wire I8035_T1;
wire I8035_RSTn;
I8035IP SOUND_CPU
(
.I_CLK(I8035_CLK),
.I_RSTn(I8035_RSTn),
.I_INTn(I8035_INTn),
.I_EA(1'b1),
.O_PSENn(I8035_PSENn),
.O_RDn(I8035_RDn),
.O_WRn(),
.O_ALE(I8035_ALE),
.O_PROGn(),
.I_T0(I8035_T0),
.O_T0(),
.I_T1(I8035_T1),
.I_DB(I8035_DBO),
.O_DB(I8035_DBI),
.I_P1(8'h00),
.O_P1(I8035_PAI),
.I_P2(I8035_PBO),
.O_P2(I8035_PBI)
);
dkongjr_sound Digtal_sound
(
.I_CLK1(W_CLK_12288M),
.I_CLK2(W_CLK_24576M),
.I_RST(W_RESETn),
.I8035_DBI(I8035_DBI),
.I8035_DBO(I8035_DBO),
.I8035_PAI(I8035_PAI),
.I8035_PBI(I8035_PBI),
.I8035_PBO(I8035_PBO),
.I8035_ALE(I8035_ALE),
.I8035_RDn(I8035_RDn),
.I8035_PSENn(I8035_PSENn),
.I8035_RSTn(I8035_RSTn),
.I8035_INTn(I8035_INTn),
.I8035_T0(I8035_T0),
.I8035_T1(I8035_T1),
.I_SOUND_DAT(W_3D_Q),
.I_SOUND_CNT({W_4H_Q[1],W_6H_Q[6:3],W_5H_Q[0]}),
.O_SOUND_DAT(W_D_S_DAT)
);
assign O_SOUND_DAT = W_D_S_DAT;
endmodule

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//===============================================================================
//
// Modified for Donkey Kong Junior by gaz68.
//
// FPGA DONKEY KONG V RAM
//
// Version : 4.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2004- 8-24 V-RAM module changed . K.Degawa
// 2005- 2- 9 The description of the ROM was changed.
// Data on the ROM are initialized at the time of the start.
//================================================================================
//-----------------------------------------------------------------------------------------
// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],H_CNT[9]
// 1/2 H 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H
//-----------------------------------------------------------------------------------------
// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]
// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V
//-----------------------------------------------------------------------------------------
// VF_CNT[0],VF_CNT[1],VF_CNT[2],VF_CNT[3],VF_CNT[4],VF_CNT[5],VF_CNT[6],VF_CNT[7]
// 1 VF 2 VF 4 VF 8 VF 16 VF 32 VF 64 VF 128 VF
//-----------------------------------------------------------------------------------------
module dkongjr_vram(
CLK_12M,
I_AB,
I_DB,
I_VRAM_WRn,
I_VRAM_RDn,
I_FLIP,
I_H_CNT,
I_VF_CNT,
I_CMPBLK,
I_4H_Q0,
//---- Debug ----
//---------------
O_DB,
O_COL,
O_VID,
O_VRAMBUSYn,
O_ESBLKn
);
input CLK_12M;
input [9:0]I_AB;
input [7:0]I_DB;
input I_VRAM_WRn;
input I_VRAM_RDn;
input I_FLIP;
input [9:0]I_H_CNT;
input [7:0]I_VF_CNT;
input I_CMPBLK;
input I_4H_Q0;
output [7:0]O_DB;
output [3:0]O_COL;
output [1:0]O_VID;
output O_VRAMBUSYn;
output O_ESBLKn;
//---- Debug ----
//---------------
wire [7:0]WI_DB = I_VRAM_WRn ? 8'h00: I_DB;
wire [7:0]WO_DB;
assign O_DB = I_VRAM_RDn ? 8'h00: WO_DB;
wire [4:0]W_HF_CNT = I_H_CNT[8:4]^{I_FLIP,I_FLIP,I_FLIP,I_FLIP,I_FLIP};
wire [9:0]W_cnt_AB = {I_VF_CNT[7:3],W_HF_CNT[4:0]};
wire [9:0]W_vram_AB = I_CMPBLK ? W_cnt_AB : I_AB ;
wire W_vram_CS = I_CMPBLK ? 1'b0 : I_VRAM_WRn & I_VRAM_RDn;
wire W_2S4 = I_CMPBLK ? 1'b0 : 1'b1 ;
reg CLK_2M;
always@(negedge CLK_12M) CLK_2M <= ~(I_H_CNT[1]&I_H_CNT[2]&I_H_CNT[3]);
ram_1024_8 U_2PR(
.I_CLK(~CLK_12M),
.I_ADDR(W_vram_AB),
.I_D(WI_DB),
.I_CE(~W_vram_CS),
.I_WE(~I_VRAM_WRn),
.O_D(WO_DB)
);
wire [3:0]W_2N_DO;
col3 col3 (
.clk(CLK_12M),
.addr({W_vram_AB[9:7],W_vram_AB[4:0]}),
.data(W_2N_DO)
);
// Parts 2M
reg [3:0]O_COL;
always@(negedge CLK_2M) O_COL[3:0] <= W_2N_DO[3:0];
wire ROM_3PN_CE = ~I_H_CNT[9];
wire [3:0]W_4M_a,W_4M_b;
wire [3:0]W_4M_Y;
wire W_4P_Qa,W_4P_Qh,W_4N_Qa,W_4N_Qh;
wire CLK_4PN = I_H_CNT[0];
//------ PARTS 4P ----------------------------------------------
wire [1:0]C_4P = W_4M_Y[1:0];
wire [7:0]I_4P = W_3P_DO;
reg [7:0]reg_4P;
assign W_4P_Qa = reg_4P[7];
assign W_4P_Qh = reg_4P[0];
always@(posedge CLK_4PN)
begin
case(C_4P)
2'b00: reg_4P <= reg_4P;
2'b10: reg_4P <= {reg_4P[6:0],1'b0};
2'b01: reg_4P <= {1'b0,reg_4P[7:1]};
2'b11: reg_4P <= I_4P;
endcase
end
//------ PARTS 4N ----------------------------------------------
wire [1:0]C_4N = W_4M_Y[1:0];
wire [7:0]I_4N = W_3N_DO;
reg [7:0]reg_4N;
assign W_4N_Qa = reg_4N[7];
assign W_4N_Qh = reg_4N[0];
always@(posedge CLK_4PN)
begin
case(C_4N)
2'b00: reg_4N <= reg_4N;
2'b10: reg_4N <= {reg_4N[6:0],1'b0};
2'b01: reg_4N <= {1'b0,reg_4N[7:1]};
2'b11: reg_4N <= I_4N;
endcase
end
assign W_4M_a = {W_4P_Qa,W_4N_Qa,1'b1,~(CLK_2M|W_2S4)};
assign W_4M_b = {W_4P_Qh,W_4N_Qh,~(CLK_2M|W_2S4),1'b1};
assign W_4M_Y = I_FLIP ? W_4M_b:W_4M_a;
assign O_VID[0] = W_4M_Y[2];
assign O_VID[1] = W_4M_Y[3];
//------ PARTS 2K1 ----------------------------------------------
reg W_VRAMBUSY;
assign O_VRAMBUSYn = ~W_VRAMBUSY;
always@(posedge I_H_CNT[2] or negedge I_H_CNT[9])
begin
if(I_H_CNT[9] == 1'b0)
W_VRAMBUSY <= 1'b1;
else
W_VRAMBUSY <= I_H_CNT[4]&I_H_CNT[5]&I_H_CNT[6]&I_H_CNT[7];
end
//------ PARTS 2K2 ----------------------------------------------
reg W_ESBLK;
assign O_ESBLKn = ~W_ESBLK;
always@(posedge I_H_CNT[6] or negedge I_H_CNT[9])
begin
if(I_H_CNT[9] == 1'b0)
W_ESBLK <= 1'b0;
else
W_ESBLK <= ~I_H_CNT[7];
end
wire [7:0] W_3P_DO, W_3N_DO;
vid1 vid1 (
.clk(CLK_12M & ROM_3PN_CE),
.addr({1'b0,WO_DB[7:0],I_VF_CNT[2:0]}),
.data(W_3P_DO)
);
vid2 vid2 (
.clk(CLK_12M & ROM_3PN_CE),
.addr({1'b0,WO_DB[7:0],I_VF_CNT[2:0]}),
.data(W_3N_DO)
);
endmodule

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//============================================================================
// Sound sample player.
//
// Author: gaz68 (https://github.com/gaz68)
// October 2019
//
// Up to 8 channels. 16-bit signed samples.
// For DKJ analogue sounds.
//============================================================================
module dkongjr_wav_sound
(
input I_CLK,
input I_RSTn,
input [3:0]I_H_CNT,
input [11:0]I_DIV,
input [3:0]I_VOL,
input I_DMA_TRIG,
input I_DMA_STOP,
input [2:0]I_DMA_CHAN, // 8 channels
input [15:0]I_DMA_ADDR,
input [15:0]I_DMA_LEN,
input signed [15:0]I_DMA_DATA, // Data coming back from wave ROM
output [15:0]O_DMA_ADDR, // output address to wave ROM
output signed [15:0]O_SND
);
reg [15:0]W_DMA_ADDR;
reg signed [23:0]W_DMA_DATA;
reg [15:0]W_DMA_CNT;
reg W_DMA_EN = 1'b0;
reg [11:0]sample;
reg W_DMA_TRIG;
reg signed [15:0]W_SAMPL;
reg signed[8:0]W_VOL;
always@(posedge I_CLK or negedge I_RSTn)
begin
if(! I_RSTn)begin
W_DMA_EN <= 1'b0;
W_DMA_CNT <= 0;
W_DMA_DATA <= 0;
W_DMA_ADDR <= 0;
W_DMA_TRIG <= 0;
W_VOL <= 0;
sample <= 0;
end else begin
// Check for DMA trigger and enable DMA.
W_DMA_TRIG <= I_DMA_TRIG;
if(~W_DMA_TRIG & I_DMA_TRIG) begin
W_DMA_ADDR <= I_DMA_ADDR;
W_DMA_CNT <= 0;
W_DMA_EN <= 1'b1;
W_DMA_DATA <= 0;
sample <= 0;
end else if (W_DMA_EN == 1'b1) begin
case(I_VOL)
4: W_VOL <= 9'sd0; // OFF
5: W_VOL <= 9'sd26; // 10%
6: W_VOL <= 9'sd52; // 20%
7: W_VOL <= 9'sd79; // 30%
8: W_VOL <= 9'sd104; // 40%
9: W_VOL <= 9'sd130; // 50%
10: W_VOL <= 9'sd156; // 60%
0: W_VOL <= 9'sd182; // 70%
1: W_VOL <= 9'sd208; // 80%
2: W_VOL <= 9'sd234; // 90%
3: W_VOL <= 9'sd255; // 100%
default: W_VOL <= 9'sd255;
endcase
// Prefetch sample.
if (I_H_CNT == {I_DMA_CHAN,1'b1}) begin
W_DMA_DATA <= I_DMA_DATA * W_VOL;
end
sample <= (sample == I_DIV-1) ? 1'b0 : sample + 1'b1;
if (sample == I_DIV-1) begin
W_SAMPL <= W_DMA_DATA[23:8];
W_DMA_ADDR <= W_DMA_ADDR + 1'd1;
W_DMA_CNT <= W_DMA_CNT + 1'd1;
W_DMA_EN <= (W_DMA_CNT==I_DMA_LEN) || I_DMA_STOP ? 1'b0 : 1'b1;
end
end else begin
W_DMA_ADDR <= 0;
W_SAMPL <= 0;
end
end
end
assign O_DMA_ADDR = W_DMA_ADDR;
assign O_SND = W_SAMPL;
endmodule

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0');
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
numwords_b => 2**addr_width_g,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
widthad_b => addr_width_g,
width_a => data_width_g,
width_b => data_width_g,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock_a,
clock1 => clock_b,
clocken0 => enable_a,
clocken1 => enable_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => q_a,
q_b => q_b
);
END SYN;

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//===============================================================================
// FPGA DONKEY KONG T8035 I/F
//
// Version : 1.01
//
// Copyright(c) 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2004- 9- 2 T48-IP(beta3) was include. K.Degawa
// 2004- 9- 2 T48 Bug Fix K.Degawa
// 2004- 9-14 T48-IP was changed to beta4. K.Degawa
// 2005- 2- 9 It cleaned.
//================================================================================
module I8035IP(
I_CLK,
I_RSTn,
I_INTn,
I_EA,
O_PSENn,
O_RDn,
O_WRn,
O_ALE,
O_PROGn,
I_T0,
O_T0,
I_T1,
I_DB,
O_DB,
I_P1,
O_P1,
I_P2,
O_P2
);
input I_CLK;
input I_RSTn;
input I_INTn;
input I_EA;
output O_PSENn;
output O_RDn;
output O_WRn;
output O_ALE;
output O_PROGn;
input I_T0;
output O_T0;
input I_T1;
input [7:0]I_DB;
output [7:0]O_DB;
input [7:0]I_P1;
output [7:0]O_P1;
input [7:0]I_P2;
output [7:0]O_P2;
wire W_PSENn;
assign O_PSENn = W_PSENn ;
// 64 Byte RAM ------------------------------------------
wire [7:0]t48_ram_a;
wire t48_ram_we;
wire [7:0]t48_ram_do;
wire [7:0]t48_ram_di;
ram_64_8 t48_ram(
.I_CLK(I_CLK),
.I_ADDR(t48_ram_a[5:0]),
.I_D(t48_ram_di),
.I_CE(1'b1),
.I_WE(t48_ram_we),
.O_D(t48_ram_do)
);
//----------------------------------------------------------
wire xtal3_s;
t48_core t48_core(
.xtal_i(I_CLK),
.reset_i(I_RSTn),
.t0_i(I_T0),
.t0_o(O_T0),
.t0_dir_o(),
.int_n_i(I_INTn),
.ea_i(I_EA),
.rd_n_o(O_RDn),
.psen_n_o(W_PSENn),
.wr_n_o(O_WRn),
.ale_o(O_ALE),
.db_i(I_DB),
.db_o(O_DB),
.db_dir_o(),
.t1_i(I_T1),
.p2_i(I_P2),
.p2_o(O_P2),
.p2_low_imp_o(),
.p1_i(I_P1),
.p1_o(O_P1),
.p1_low_imp_o(),
.prog_n_o(O_PROGn),
.clk_i(I_CLK),
.en_clk_i(xtal3_s),
.xtal3_o(xtal3_s),
.dmem_addr_o(t48_ram_a),
.dmem_we_o(t48_ram_we),
.dmem_data_i(t48_ram_do),
.dmem_data_o(t48_ram_di),
.pmem_addr_o(),
.pmem_data_i(8'h00)
);
endmodule

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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 78,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 71,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity snd1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of snd1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"55",X"04",X"52",X"C5",X"A5",X"8A",X"40",X"8A",X"80",X"B9",X"02",X"BA",X"40",X"BB",X"40",X"FA",
X"77",X"77",X"53",X"3F",X"6A",X"AA",X"AB",X"34",X"00",X"FB",X"97",X"67",X"6B",X"AB",X"34",X"00",
X"E9",X"0F",X"FA",X"47",X"00",X"53",X"0F",X"37",X"17",X"6A",X"07",X"AA",X"AB",X"03",X"D8",X"E6",
X"3C",X"34",X"00",X"FB",X"97",X"67",X"6B",X"AB",X"34",X"00",X"04",X"22",X"D5",X"23",X"2B",X"34",
X"81",X"14",X"45",X"04",X"52",X"80",X"37",X"B4",X"33",X"C6",X"51",X"53",X"F0",X"96",X"51",X"04",
X"45",X"83",X"05",X"85",X"A5",X"B8",X"20",X"B0",X"00",X"D5",X"27",X"AE",X"AF",X"C5",X"8A",X"80",
X"14",X"73",X"26",X"74",X"A5",X"0A",X"37",X"B2",X"A8",X"27",X"AE",X"AF",X"A9",X"B4",X"35",X"14",
X"73",X"04",X"62",X"93",X"B8",X"20",X"F0",X"03",X"05",X"C6",X"69",X"F0",X"03",X"09",X"C6",X"69",
X"B8",X"08",X"A5",X"B5",X"D4",X"1A",X"D4",X"38",X"8A",X"80",X"C6",X"62",X"B9",X"03",X"34",X"3F",
X"B4",X"35",X"E9",X"8E",X"B9",X"04",X"B4",X"35",X"E9",X"96",X"FA",X"03",X"F9",X"A9",X"C6",X"86",
X"9A",X"7F",X"B4",X"35",X"E9",X"A2",X"04",X"86",X"BB",X"20",X"34",X"15",X"FB",X"77",X"77",X"53",
X"3F",X"6B",X"AB",X"26",X"74",X"E6",X"AA",X"34",X"15",X"FB",X"77",X"77",X"53",X"3F",X"6B",X"AB",
X"26",X"74",X"E6",X"B7",X"04",X"62",X"BA",X"08",X"B9",X"FF",X"8A",X"80",X"A5",X"B5",X"FA",X"AB",
X"34",X"31",X"34",X"31",X"FA",X"97",X"67",X"6A",X"F6",X"62",X"AB",X"34",X"31",X"34",X"31",X"34",
X"31",X"FA",X"AB",X"34",X"31",X"34",X"31",X"FA",X"97",X"67",X"97",X"67",X"6A",X"AA",X"04",X"CE",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"B8",X"03",X"34",X"23",X"E8",X"02",X"B8",X"03",X"34",X"0D",X"E8",X"08",X"83",X"27",X"AE",X"AF",
X"D5",X"AE",X"AF",X"C4",X"7B",X"FB",X"47",X"E7",X"53",X"1F",X"AF",X"FB",X"47",X"E7",X"53",X"E0",
X"AE",X"A4",X"35",X"FB",X"77",X"77",X"AE",X"53",X"3F",X"AF",X"FE",X"53",X"C0",X"AE",X"D5",X"C4",
X"7B",X"FB",X"77",X"77",X"AE",X"53",X"3F",X"AF",X"FE",X"53",X"C0",X"AE",X"D5",X"A4",X"35",X"FE",
X"6F",X"E6",X"44",X"1F",X"6F",X"E6",X"48",X"1F",X"AE",X"83",X"AB",X"D5",X"FB",X"1B",X"C5",X"B4",
X"33",X"C6",X"9E",X"F2",X"9F",X"A8",X"D4",X"1A",X"D4",X"38",X"D4",X"4B",X"C6",X"4B",X"B9",X"03",
X"8A",X"80",X"34",X"3F",X"D5",X"34",X"3F",X"D4",X"7B",X"E9",X"62",X"B9",X"04",X"D5",X"D4",X"7B",
X"E9",X"6D",X"FA",X"03",X"F9",X"A9",X"C6",X"58",X"9A",X"7F",X"D5",X"D4",X"7B",X"E9",X"7A",X"24",
X"58",X"AB",X"D5",X"FB",X"1B",X"C5",X"B4",X"33",X"C6",X"9E",X"F2",X"9F",X"A8",X"D4",X"1A",X"D4",
X"38",X"D4",X"4B",X"C6",X"82",X"FA",X"A9",X"D5",X"D4",X"7B",X"E9",X"97",X"24",X"8F",X"83",X"BE",
X"80",X"A4",X"A2",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"03",X"06",X"09",X"0C",X"0F",X"12",X"15",X"18",X"1B",X"1E",X"21",X"24",X"27",X"2A",X"2D",
X"30",X"33",X"36",X"39",X"3C",X"3F",X"42",X"45",X"48",X"4B",X"4E",X"51",X"54",X"57",X"5A",X"5D",
X"60",X"5D",X"5A",X"57",X"54",X"51",X"4E",X"4B",X"48",X"45",X"42",X"3F",X"3C",X"39",X"36",X"33",
X"30",X"2D",X"2A",X"27",X"24",X"21",X"1E",X"1B",X"18",X"15",X"12",X"0F",X"0C",X"09",X"06",X"03",
X"FC",X"6E",X"AC",X"FD",X"7F",X"AD",X"77",X"77",X"53",X"3F",X"A3",X"A8",X"C5",X"FC",X"6E",X"AC",
X"FD",X"7F",X"AD",X"77",X"77",X"43",X"C0",X"A3",X"D5",X"68",X"39",X"16",X"5F",X"44",X"40",X"C5",
X"83",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/Neuer Ordner/snd2.vhd Normal file
View File

@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity snd2 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of snd2 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/c_5ca.bin Normal file
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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/c_5ea.bin Normal file
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38
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/col1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity col1 is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of col1 is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"0F",X"0C",X"0A",X"0F",X"0F",X"00",X"0B",X"00",X"0F",X"0C",X"00",X"00",X"0F",X"0C",X"00",X"07",
X"0F",X"0C",X"00",X"03",X"0F",X"0C",X"04",X"00",X"0F",X"0C",X"04",X"03",X"0F",X"07",X"00",X"0A",
X"0F",X"0F",X"0C",X"09",X"0F",X"07",X"03",X"0A",X"0F",X"0E",X"0B",X"00",X"0F",X"03",X"0B",X"07",
X"0F",X"0F",X"0B",X"00",X"0F",X"0C",X"07",X"00",X"0F",X"0F",X"07",X"00",X"0F",X"0C",X"07",X"00",
X"0F",X"0C",X"0A",X"0F",X"0F",X"00",X"0B",X"00",X"0F",X"0F",X"03",X"05",X"0F",X"0F",X"03",X"05",
X"0F",X"0F",X"03",X"05",X"0F",X"0F",X"03",X"05",X"0F",X"0F",X"00",X"05",X"0F",X"07",X"00",X"0A",
X"0F",X"0F",X"0C",X"09",X"0F",X"07",X"03",X"0A",X"0F",X"0E",X"0B",X"00",X"0F",X"03",X"0B",X"07",
X"0F",X"0F",X"0B",X"00",X"0F",X"0C",X"07",X"00",X"0F",X"0F",X"07",X"00",X"0F",X"0C",X"07",X"00",
X"0F",X"0C",X"0A",X"0F",X"0F",X"0C",X"0B",X"00",X"0F",X"0C",X"04",X"0B",X"0F",X"0C",X"04",X"0B",
X"0F",X"0C",X"04",X"0B",X"0F",X"0C",X"04",X"0B",X"0F",X"0C",X"04",X"0B",X"0F",X"07",X"00",X"0A",
X"0F",X"0F",X"0C",X"09",X"0F",X"07",X"03",X"0A",X"0F",X"0E",X"0B",X"00",X"0F",X"03",X"0B",X"07",
X"0F",X"0F",X"0B",X"00",X"0F",X"0C",X"07",X"00",X"0F",X"0F",X"07",X"00",X"0F",X"04",X"07",X"00",
X"0F",X"0C",X"0A",X"0F",X"0F",X"00",X"0B",X"00",X"0F",X"04",X"00",X"00",X"0F",X"04",X"00",X"00",
X"0F",X"04",X"00",X"00",X"0F",X"04",X"00",X"00",X"0F",X"04",X"00",X"00",X"0F",X"07",X"00",X"0A",
X"0F",X"0F",X"0C",X"09",X"0F",X"07",X"03",X"0A",X"0F",X"0E",X"0B",X"00",X"0F",X"03",X"0B",X"07",
X"0F",X"0F",X"0B",X"00",X"0F",X"0C",X"00",X"00",X"0F",X"0F",X"07",X"00",X"0F",X"0C",X"07",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/col2.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity col2 is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of col2 is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"0F",X"0F",X"00",X"01",X"0F",X"09",X"00",X"00",X"0F",X"0F",X"00",X"09",X"0F",X"0F",X"00",X"01",
X"0F",X"0F",X"00",X"00",X"0F",X"0F",X"0C",X"00",X"0F",X"0F",X"0C",X"0E",X"0F",X"05",X"00",X"00",
X"0F",X"01",X"09",X"00",X"0F",X"05",X"01",X"00",X"0F",X"0F",X"00",X"00",X"0F",X"01",X"0E",X"00",
X"0F",X"01",X"0E",X"00",X"0F",X"0F",X"00",X"00",X"0F",X"01",X"00",X"00",X"0F",X"01",X"00",X"00",
X"0F",X"0F",X"00",X"01",X"0F",X"09",X"00",X"00",X"0F",X"00",X"0E",X"00",X"0F",X"00",X"0E",X"00",
X"0F",X"00",X"0E",X"00",X"0F",X"00",X"0E",X"00",X"0F",X"00",X"0E",X"00",X"0F",X"05",X"00",X"00",
X"0F",X"01",X"09",X"00",X"0F",X"05",X"01",X"00",X"0F",X"0F",X"00",X"00",X"0F",X"01",X"0E",X"00",
X"0F",X"01",X"0E",X"00",X"0F",X"0F",X"00",X"00",X"0F",X"01",X"00",X"00",X"0F",X"01",X"00",X"00",
X"0F",X"0F",X"00",X"01",X"0F",X"0F",X"00",X"00",X"0F",X"0F",X"0C",X"00",X"0F",X"0F",X"0C",X"00",
X"0F",X"0F",X"0C",X"00",X"0F",X"0F",X"0C",X"00",X"0F",X"0F",X"0C",X"00",X"0F",X"05",X"00",X"00",
X"0F",X"01",X"09",X"00",X"0F",X"05",X"01",X"00",X"0F",X"0F",X"00",X"00",X"0F",X"01",X"0E",X"00",
X"0F",X"01",X"0E",X"00",X"0F",X"0F",X"00",X"00",X"0F",X"01",X"00",X"00",X"0F",X"07",X"00",X"00",
X"0F",X"0F",X"00",X"01",X"0F",X"09",X"00",X"00",X"0F",X"01",X"00",X"09",X"0F",X"01",X"00",X"09",
X"0F",X"01",X"00",X"09",X"0F",X"01",X"00",X"09",X"0F",X"01",X"00",X"09",X"0F",X"05",X"00",X"00",
X"0F",X"01",X"09",X"00",X"0F",X"05",X"01",X"00",X"0F",X"0F",X"00",X"00",X"0F",X"01",X"0E",X"00",
X"0F",X"01",X"0E",X"00",X"0F",X"0F",X"0E",X"00",X"0F",X"01",X"00",X"00",X"0F",X"01",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/col3.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity col3 is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of col3 is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"01",X"07",X"01",X"01",X"01",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06",
X"00",X"01",X"07",X"01",X"01",X"01",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06",
X"00",X"01",X"07",X"01",X"01",X"01",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06",
X"00",X"01",X"07",X"02",X"02",X"02",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06",
X"00",X"01",X"07",X"02",X"02",X"02",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06",
X"00",X"01",X"07",X"02",X"02",X"02",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06",
X"00",X"01",X"07",X"02",X"02",X"02",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06",
X"00",X"01",X"07",X"02",X"02",X"02",X"03",X"02",X"04",X"05",X"04",X"05",X"02",X"05",X"02",X"05",
X"03",X"03",X"02",X"03",X"03",X"04",X"03",X"04",X"04",X"05",X"04",X"05",X"05",X"05",X"05",X"06");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/dkjr1 Normal file
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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/dkjr10 Normal file
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20
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/make_tron_proms.bat Normal file
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copy /b 0000 + 1000 + 1800 + 2000 + 2800 + 3000 + 4000 + 4800 + 5000 + 5800 prog.bin
make_vhdl_prom prog.bin prog.vhd
make_vhdl_prom v_3na.bin vid1.vhd
make_vhdl_prom dkjr10 vid2.vhd
make_vhdl_prom v_7c.bin obj1.vhd
make_vhdl_prom v_7d.bin obj2.vhd
make_vhdl_prom v_7e.bin obj3.vhd
make_vhdl_prom v_7f.bin obj4.vhd
make_vhdl_prom c-2e.bpr col1.vhd
make_vhdl_prom c-2f.bpr col2.vhd
make_vhdl_prom v-2n.bpr col3.vhd
make_vhdl_prom c_3h.bin snd1.vhd
pause

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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/make_vhdl_prom.exe Normal file
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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/obj1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity obj1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of obj1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"1F",X"3F",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"1F",X"1F",X"3F",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"07",
X"00",X"1C",X"1E",X"14",X"00",X"0F",X"07",X"03",X"07",X"07",X"79",X"FE",X"FF",X"CF",X"CF",X"1F",
X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"03",X"01",X"00",X"01",X"01",X"07",X"0F",X"1F",X"27",
X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"00",X"3F",X"3E",X"7F",X"EF",X"CF",X"CF",
X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"00",X"3F",X"3F",X"7F",X"EF",X"CF",X"CF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"03",X"07",X"3F",X"7F",X"EF",X"CF",X"CF",X"CF",X"EF",X"7F",X"3F",X"3F",X"F9",X"F7",
X"00",X"00",X"03",X"07",X"3F",X"7F",X"EF",X"CF",X"CF",X"CF",X"EF",X"7F",X"3F",X"1F",X"3C",X"3D",
X"00",X"00",X"04",X"1C",X"65",X"E7",X"1F",X"1F",X"1F",X"55",X"4C",X"44",X"04",X"00",X"00",X"00",
X"00",X"00",X"04",X"1C",X"64",X"E1",X"F9",X"E9",X"C1",X"55",X"4C",X"44",X"04",X"00",X"00",X"00",
X"00",X"00",X"00",X"02",X"0E",X"32",X"71",X"1F",X"1F",X"1F",X"2A",X"26",X"22",X"02",X"00",X"00",
X"00",X"00",X"00",X"02",X"0E",X"32",X"70",X"7C",X"74",X"60",X"2A",X"26",X"22",X"02",X"00",X"00",
X"00",X"03",X"07",X"07",X"0F",X"0F",X"1F",X"1F",X"1F",X"0F",X"0F",X"1C",X"3F",X"3F",X"7F",X"7F",
X"00",X"00",X"00",X"78",X"FC",X"FC",X"F8",X"FC",X"7E",X"7F",X"3F",X"3F",X"3F",X"7F",X"7F",X"FF",
X"00",X"00",X"00",X"0C",X"BF",X"FF",X"FF",X"FF",X"7F",X"E7",X"C3",X"C3",X"47",X"1F",X"3F",X"7F",
X"1F",X"0F",X"07",X"03",X"07",X"37",X"3F",X"3F",X"3F",X"37",X"07",X"03",X"07",X"0F",X"1F",X"00",
X"00",X"00",X"00",X"00",X"05",X"06",X"07",X"09",X"0F",X"1F",X"3F",X"7F",X"7F",X"7E",X"78",X"21",
X"00",X"00",X"00",X"00",X"0A",X"0C",X"0F",X"13",X"1F",X"0F",X"07",X"07",X"03",X"03",X"01",X"03",
X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"03",X"03",X"07",X"0D",X"03",X"07",X"03",
X"04",X"1C",X"65",X"E1",X"F9",X"E8",X"C0",X"55",X"4C",X"44",X"04",X"00",X"00",X"00",X"00",X"00",
X"00",X"04",X"1C",X"65",X"E1",X"F9",X"E9",X"C1",X"55",X"4C",X"44",X"04",X"00",X"00",X"00",X"00",
X"00",X"04",X"1C",X"65",X"E1",X"F9",X"E9",X"C1",X"54",X"4C",X"45",X"05",X"01",X"00",X"00",X"00",
X"00",X"02",X"0E",X"32",X"70",X"7C",X"74",X"60",X"2A",X"26",X"22",X"02",X"00",X"00",X"00",X"00",
X"00",X"00",X"02",X"0E",X"32",X"70",X"7C",X"74",X"60",X"2A",X"26",X"22",X"02",X"00",X"00",X"00",
X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"03",X"03",X"03",X"01",X"01",X"00",X"00",
X"00",X"02",X"0D",X"06",X"07",X"03",X"03",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"01",X"03",X"07",X"07",X"3F",X"07",X"07",X"07",X"03",X"01",X"00",X"00",X"00",
X"00",X"00",X"01",X"03",X"07",X"0B",X"2A",X"2B",X"2B",X"16",X"0B",X"07",X"03",X"01",X"00",X"00",
X"03",X"07",X"05",X"08",X"1B",X"19",X"05",X"3F",X"3F",X"0F",X"05",X"37",X"3F",X"3F",X"3E",X"1C",
X"00",X"01",X"0D",X"1C",X"61",X"C9",X"ED",X"C7",X"C7",X"ED",X"C9",X"61",X"9C",X"0D",X"01",X"00",
X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"79",X"79",X"7F",X"79",X"79",X"7F",X"3F",X"1F",X"0F",X"07",
X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"79",X"79",X"7F",X"79",X"79",X"7F",X"3F",X"1F",X"0F",X"07",
X"00",X"80",X"00",X"80",X"00",X"85",X"44",X"88",X"70",X"88",X"44",X"85",X"00",X"80",X"00",X"80",
X"54",X"86",X"45",X"89",X"4B",X"B7",X"FF",X"FF",X"FF",X"FF",X"FF",X"BF",X"1F",X"0F",X"00",X"00",
X"00",X"00",X"00",X"01",X"07",X"8F",X"DF",X"FF",X"FF",X"FF",X"B7",X"4B",X"89",X"45",X"86",X"54",
X"00",X"18",X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"B7",X"4B",X"89",X"45",X"86",X"54",
X"00",X"00",X"09",X"00",X"00",X"08",X"08",X"08",X"08",X"04",X"04",X"03",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"07",X"3F",X"3F",X"7F",X"5F",X"EF",X"F6",X"AC",X"CD",X"68",X"23",X"07",
X"07",X"03",X"08",X"1A",X"33",X"2B",X"3D",X"3B",X"17",X"1F",X"0F",X"07",X"01",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"03",X"03",X"07",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"06",X"04",X"04",X"01",X"06",X"0E",
X"00",X"00",X"00",X"00",X"C0",X"78",X"00",X"00",X"00",X"00",X"00",X"17",X"E7",X"87",X"06",X"06",
X"7F",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"41",X"42",X"44",X"48",X"10",X"00",X"0F",X"00",
X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/obj2.vhd Normal file
View File

@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity obj2 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of obj2 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/obj3.vhd Normal file
View File

@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity obj3 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of obj3 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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X"07",X"08",X"07",X"00",X"07",X"08",X"07",X"00",X"06",X"09",X"08",X"04",X"00",X"0F",X"04",X"00",
X"07",X"08",X"07",X"00",X"07",X"08",X"07",X"00",X"04",X"09",X"09",X"07",X"00",X"0F",X"04",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/obj4.vhd Normal file
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@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity obj4 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of obj4 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"C1",X"C0",X"C0",X"C1",X"61",X"01",
X"00",X"00",X"00",X"06",X"0B",X"01",X"01",X"01",X"00",X"C1",X"C3",X"E0",X"E4",X"7C",X"3C",X"1D",
X"00",X"00",X"00",X"00",X"00",X"18",X"0C",X"1C",X"1C",X"10",X"06",X"01",X"01",X"09",X"04",X"20",
X"00",X"00",X"00",X"00",X"0C",X"0C",X"04",X"06",X"02",X"00",X"20",X"10",X"B0",X"F8",X"FC",X"BC",
X"00",X"00",X"00",X"00",X"00",X"80",X"44",X"C6",X"02",X"03",X"01",X"60",X"E0",X"A0",X"A0",X"50",
X"00",X"00",X"00",X"0C",X"06",X"0F",X"0F",X"04",X"00",X"10",X"B8",X"F8",X"FC",X"AE",X"A6",X"AA",
X"00",X"00",X"00",X"0C",X"06",X"0F",X"0F",X"04",X"00",X"10",X"B8",X"F8",X"FC",X"AE",X"A6",X"AA",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"30",X"98",X"9C",X"9E",X"8E",X"8F",X"8F",X"83",X"80",X"90",X"00",X"20",X"40",
X"00",X"00",X"00",X"30",X"98",X"9C",X"9E",X"8E",X"8F",X"8F",X"83",X"80",X"88",X"08",X"10",X"80",
X"00",X"06",X"07",X"03",X"C1",X"C0",X"C0",X"00",X"40",X"00",X"00",X"00",X"1C",X"3C",X"00",X"00",
X"00",X"06",X"07",X"03",X"C1",X"E0",X"E0",X"C0",X"C0",X"C0",X"C0",X"C0",X"FC",X"FC",X"E0",X"C0",
X"1E",X"1C",X"00",X"00",X"C0",X"C0",X"E0",X"E3",X"C3",X"A3",X"81",X"00",X"00",X"00",X"00",X"00",
X"1E",X"1C",X"00",X"00",X"C0",X"C0",X"E0",X"E3",X"E3",X"63",X"E1",X"60",X"60",X"E0",X"E0",X"C0",
X"06",X"0A",X"92",X"80",X"70",X"E0",X"70",X"30",X"38",X"38",X"7C",X"FC",X"FC",X"9C",X"C8",X"D8",
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X"00",X"00",X"00",X"00",X"03",X"07",X"03",X"01",X"11",X"08",X"0C",X"0E",X"1E",X"BE",X"FE",X"FE",
X"00",X"00",X"00",X"00",X"10",X"D8",X"2C",X"FE",X"2C",X"D8",X"10",X"00",X"00",X"00",X"00",X"00",
X"08",X"18",X"B8",X"F8",X"F0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"18",X"10",
X"80",X"A0",X"A0",X"B0",X"E0",X"C0",X"00",X"20",X"10",X"08",X"A0",X"A0",X"28",X"08",X"18",X"10",
X"03",X"E7",X"FD",X"F8",X"F8",X"F0",X"F3",X"E7",X"FD",X"FC",X"E0",X"80",X"0C",X"1C",X"1C",X"00",
X"00",X"30",X"18",X"1C",X"1C",X"3C",X"3C",X"38",X"3C",X"3C",X"1C",X"C0",X"E0",X"C0",X"00",X"00",
X"00",X"18",X"3C",X"1C",X"0C",X"00",X"CC",X"6E",X"3E",X"BE",X"7A",X"61",X"61",X"01",X"1A",X"04",
X"00",X"38",X"3C",X"1C",X"1C",X"1E",X"1C",X"1C",X"1C",X"1C",X"3C",X"18",X"00",X"00",X"80",X"80",
X"00",X"1C",X"3C",X"FC",X"FC",X"3E",X"1E",X"1E",X"0E",X"04",X"08",X"0C",X"0C",X"0C",X"00",X"00",
X"00",X"18",X"3C",X"FC",X"3C",X"1C",X"1C",X"1C",X"3E",X"3E",X"3C",X"0C",X"00",X"80",X"C0",X"C0",
X"00",X"00",X"00",X"78",X"FC",X"F8",X"F8",X"F0",X"00",X"00",X"C0",X"E0",X"E0",X"E0",X"E0",X"00",
X"00",X"60",X"70",X"30",X"B8",X"F8",X"F8",X"F8",X"F8",X"F0",X"F0",X"F0",X"E0",X"80",X"80",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"F0",X"98",X"E8",X"F4",X"FC",X"FC",X"FC",X"F8",X"F8",X"F0",X"00",X"00",X"00",
X"E0",X"F0",X"A0",X"F0",X"90",X"32",X"93",X"21",X"20",X"70",X"F0",X"F8",X"F8",X"F0",X"30",X"00",
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X"70",X"F0",X"EC",X"DC",X"DE",X"DE",X"DE",X"5E",X"5E",X"5E",X"DE",X"DE",X"DE",X"DC",X"EC",X"F0",
X"70",X"E8",X"FC",X"EC",X"C6",X"EE",X"FE",X"6E",X"46",X"6E",X"FE",X"EE",X"C6",X"EC",X"FC",X"E8",
X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"80",X"C0",X"80",X"C0",X"80",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"18",X"08",X"38",X"38",X"18",X"18",X"30",X"18",X"30",X"38",X"10",X"08",
X"02",X"04",X"EE",X"0C",X"06",X"0C",X"06",X"06",X"0E",X"0A",X"06",X"00",X"00",X"00",X"00",X"00",
X"10",X"30",X"70",X"70",X"30",X"70",X"50",X"30",X"30",X"70",X"50",X"30",X"00",X"00",X"00",X"00",
X"E0",X"E0",X"E0",X"E0",X"F0",X"F8",X"F8",X"F8",X"F8",X"F4",X"F0",X"F0",X"28",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"80",X"00",X"00",X"00",X"00",X"00",
X"E1",X"00",X"00",X"00",X"00",X"C0",X"60",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"60",X"20",X"20",X"31",X"38",X"35",X"1F",X"1E",
X"00",X"00",X"00",X"00",X"03",X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

BIN
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/prog.bin Normal file
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1558
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/prog.vhd Normal file
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278
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/snd1.vhd Normal file
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@@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity snd1 is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of snd1 is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"55",X"04",X"37",X"C5",X"E5",X"86",X"03",X"14",X"6A",X"A5",X"B5",X"85",X"8A",X"80",X"B9",X"10",
X"BB",X"40",X"BA",X"06",X"54",X"62",X"FB",X"47",X"E7",X"53",X"1F",X"6B",X"AB",X"EA",X"14",X"BA",
X"06",X"54",X"62",X"FB",X"47",X"E7",X"53",X"1F",X"37",X"17",X"6B",X"AB",X"EA",X"21",X"F9",X"03",
X"FB",X"F6",X"35",X"9A",X"7F",X"E9",X"12",X"05",X"85",X"A5",X"B8",X"20",X"B0",X"00",X"D5",X"27",
X"AE",X"AF",X"C5",X"8A",X"80",X"A5",X"26",X"A3",X"46",X"C9",X"0A",X"37",X"92",X"79",X"B2",X"77",
X"D2",X"7B",X"80",X"53",X"0F",X"03",X"FD",X"96",X"5B",X"24",X"64",X"03",X"FD",X"96",X"61",X"24",
X"8F",X"27",X"AE",X"AF",X"B4",X"24",X"14",X"6A",X"04",X"43",X"93",X"83",X"26",X"A3",X"46",X"C9",
X"0A",X"37",X"D2",X"7B",X"92",X"79",X"83",X"24",X"00",X"44",X"00",X"B8",X"07",X"A5",X"B5",X"D4",
X"1A",X"D4",X"3A",X"8A",X"80",X"96",X"89",X"04",X"43",X"B9",X"04",X"B4",X"24",X"26",X"A3",X"E9",
X"8B",X"FA",X"03",X"FC",X"A9",X"C6",X"81",X"9A",X"7F",X"B4",X"24",X"26",X"A1",X"E9",X"99",X"04",
X"81",X"8A",X"80",X"BA",X"E0",X"FA",X"AB",X"54",X"48",X"FA",X"77",X"77",X"53",X"3F",X"37",X"17",
X"6A",X"AB",X"54",X"48",X"FA",X"AB",X"54",X"48",X"46",X"C9",X"FA",X"47",X"E7",X"53",X"1F",X"37",
X"17",X"6A",X"AA",X"03",X"C0",X"F6",X"A5",X"04",X"43",X"BA",X"06",X"FA",X"AB",X"54",X"55",X"54",
X"55",X"FA",X"97",X"67",X"6A",X"AB",X"54",X"55",X"54",X"55",X"FA",X"AB",X"54",X"55",X"54",X"55",
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X"54",X"3C",X"FA",X"77",X"77",X"53",X"3F",X"6A",X"AA",X"03",X"C0",X"E6",X"DD",X"04",X"59",X"FF",
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X"B5",X"34",X"DA",X"F9",X"53",X"3F",X"AF",X"FA",X"AE",X"D5",X"53",X"1F",X"AF",X"C5",X"F9",X"D5",
X"AE",X"23",X"FF",X"62",X"D4",X"B7",X"34",X"5B",X"E8",X"11",X"9A",X"7F",X"EB",X"11",X"BB",X"08",
X"8A",X"80",X"FC",X"D5",X"AC",X"C5",X"FD",X"D5",X"AD",X"C5",X"34",X"DA",X"F9",X"53",X"7F",X"AF",
X"D5",X"AF",X"C5",X"FA",X"AE",X"D5",X"AE",X"23",X"FF",X"62",X"D4",X"B7",X"34",X"5B",X"E8",X"3A",
X"9A",X"7F",X"EB",X"3A",X"D5",X"27",X"AE",X"AF",X"C5",X"04",X"43",X"0A",X"B2",X"62",X"76",X"63",
X"24",X"00",X"A5",X"83",X"F9",X"96",X"6C",X"FC",X"AA",X"96",X"6C",X"19",X"34",X"DA",X"37",X"AB",
X"FA",X"37",X"5B",X"AB",X"54",X"19",X"54",X"22",X"FA",X"AB",X"54",X"19",X"54",X"22",X"34",X"DA",
X"F9",X"AB",X"54",X"19",X"54",X"22",X"80",X"53",X"0F",X"03",X"FD",X"C6",X"6C",X"04",X"43",X"BB",
X"90",X"D5",X"B9",X"01",X"BA",X"04",X"BB",X"30",X"C5",X"54",X"7C",X"F2",X"AC",X"96",X"A1",X"04",
X"37",X"AA",X"54",X"7C",X"37",X"96",X"AB",X"FA",X"A9",X"24",X"C0",X"37",X"D4",X"65",X"B9",X"03",
X"D4",X"83",X"34",X"C9",X"E9",X"B0",X"FA",X"03",X"FA",X"A9",X"34",X"C9",X"E9",X"BA",X"B9",X"03",
X"27",X"AE",X"AF",X"34",X"C9",X"E9",X"C3",X"24",X"99",X"D5",X"E9",X"D2",X"B9",X"08",X"FA",X"37",
X"17",X"AA",X"FB",X"6A",X"AB",X"54",X"70",X"F5",X"C4",X"40",X"F9",X"F7",X"A9",X"FA",X"F7",X"AA",
X"F9",X"F6",X"EA",X"32",X"EC",X"F9",X"53",X"FE",X"A9",X"83",X"32",X"E5",X"F9",X"43",X"01",X"A9",
X"83",X"32",X"EC",X"F9",X"43",X"01",X"A9",X"83",X"54",X"41",X"14",X"6B",X"54",X"41",X"14",X"6B",
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X"1F",X"AF",X"FE",X"53",X"E0",X"AE",X"A4",X"24",X"FB",X"77",X"77",X"AE",X"53",X"3F",X"AF",X"FE",
X"53",X"C0",X"AE",X"A4",X"24",X"FB",X"77",X"AE",X"53",X"7F",X"AF",X"FE",X"53",X"80",X"AE",X"D5",
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X"FB",X"77",X"77",X"AE",X"53",X"3F",X"AF",X"FE",X"53",X"C0",X"AE",X"83",X"FB",X"1B",X"A3",X"A8",
X"83",X"98",X"30",X"A0",X"0C",X"A2",X"A6",X"A4",X"A2",X"18",X"A8",X"A8",X"0C",X"A8",X"AA",X"A4",
X"18",X"A0",X"30",X"A6",X"0C",X"A8",X"AB",X"AA",X"A8",X"18",X"B0",X"B0",X"0C",X"B0",X"B2",X"AA",
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X"D0",X"2F",X"08",X"FF",X"06",X"F8",X"3E",X"C0",X"1F",X"C0",X"3F",X"38",X"F8",X"F0",X"D0",X"D7",
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X"00",X"05",X"0A",X"0F",X"14",X"19",X"1E",X"23",X"28",X"2D",X"32",X"37",X"3C",X"41",X"46",X"4B",
X"50",X"55",X"5A",X"5F",X"64",X"69",X"6E",X"73",X"78",X"7D",X"82",X"87",X"8C",X"91",X"96",X"9B",
X"9F",X"9B",X"96",X"91",X"8C",X"87",X"82",X"7D",X"78",X"73",X"6E",X"69",X"64",X"5F",X"5A",X"55",
X"50",X"4B",X"46",X"41",X"3C",X"37",X"32",X"2D",X"28",X"23",X"1E",X"19",X"14",X"0F",X"0A",X"05");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity vid1 is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of vid1 is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00",
X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00",
X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00",
X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",
X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",
X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",
X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00",X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00",
X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00",
X"FC",X"FE",X"02",X"02",X"02",X"06",X"04",X"00",X"82",X"C6",X"6E",X"3C",X"18",X"FE",X"FE",X"00",
X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00",
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X"70",X"F8",X"88",X"88",X"88",X"FE",X"FE",X"00",X"7A",X"FC",X"8E",X"8A",X"82",X"FE",X"7C",X"00",
X"72",X"F6",X"9E",X"8C",X"88",X"FE",X"FE",X"00",X"0C",X"5E",X"D2",X"92",X"92",X"F6",X"64",X"00",
X"80",X"80",X"FE",X"FE",X"80",X"80",X"00",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00",
X"F0",X"F8",X"1C",X"0E",X"1C",X"F8",X"F0",X"00",X"F8",X"FE",X"1C",X"38",X"1C",X"FE",X"F8",X"00",
X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"C0",X"F0",X"1E",X"1E",X"F0",X"C0",X"00",X"00",
X"C2",X"E2",X"F2",X"BA",X"9E",X"8E",X"86",X"00",X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",
X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"00",
X"00",X"00",X"00",X"00",X"28",X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",
X"00",X"00",X"82",X"C6",X"6C",X"38",X"00",X"00",X"00",X"00",X"38",X"6C",X"C6",X"82",X"00",X"00",
X"00",X"00",X"82",X"FE",X"FE",X"82",X"00",X"00",X"82",X"FE",X"FE",X"82",X"82",X"FE",X"FE",X"82",
X"00",X"28",X"28",X"28",X"28",X"28",X"28",X"00",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"00",
X"F6",X"F6",X"00",X"00",X"F6",X"F6",X"00",X"00",X"FA",X"FA",X"00",X"00",X"FA",X"FA",X"00",X"00",
X"00",X"00",X"00",X"F6",X"F6",X"00",X"00",X"00",X"00",X"00",X"00",X"FA",X"FA",X"00",X"00",X"00",
X"00",X"00",X"00",X"E0",X"C0",X"00",X"00",X"00",X"00",X"E0",X"C0",X"00",X"E0",X"C0",X"00",X"00",
X"00",X"60",X"E0",X"00",X"60",X"E0",X"00",X"00",X"00",X"00",X"C0",X"00",X"C0",X"00",X"00",X"00",
X"FF",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"FF",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"FF",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"FF",
X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"06",X"00",X"00",
X"38",X"28",X"3E",X"00",X"00",X"00",X"00",X"00",X"3E",X"00",X"3C",X"02",X"02",X"3C",X"00",X"0E",
X"22",X"2A",X"3E",X"00",X"00",X"0E",X"3A",X"2A",X"22",X"3E",X"00",X"3E",X"08",X"10",X"3E",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"1C",X"22",X"A5",X"BD",X"81",X"42",X"3C",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"3C",X"42",X"81",X"A5",X"7C",X"40",X"00",X"38",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"28",X"38",X"00",X"40",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"A2",X"00",X"F0",X"FC",X"FE",X"FF",X"FF",X"FF",X"FF",
X"00",X"01",X"0F",X"3F",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"03",X"07",X"0F",
X"54",X"A6",X"02",X"02",X"62",X"73",X"77",X"FF",X"FF",X"8F",X"76",X"7C",X"4E",X"A6",X"D7",X"A3",
X"FF",X"FF",X"FE",X"FD",X"7F",X"87",X"03",X"80",X"1F",X"3F",X"78",X"F0",X"F1",X"F6",X"F8",X"6F",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

278
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/rom/vid2.vhd Normal file
View File

@@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity vid2 is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of vid2 is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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X"00",X"F0",X"F0",X"60",X"60",X"F0",X"F0",X"00",X"81",X"80",X"90",X"80",X"A0",X"A1",X"81",X"81",
X"00",X"F8",X"FC",X"0E",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"06",
X"06",X"06",X"06",X"06",X"0E",X"FC",X"F8",X"00",X"00",X"3C",X"42",X"42",X"42",X"42",X"42",X"42",
X"42",X"42",X"42",X"42",X"42",X"42",X"3C",X"00",X"00",X"0F",X"0F",X"06",X"06",X"0F",X"0F",X"00",
X"04",X"08",X"10",X"08",X"04",X"02",X"01",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"90",X"90",X"8A",X"80",X"40",X"00",
X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",
X"81",X"00",X"00",X"18",X"18",X"00",X"00",X"81",X"00",X"00",X"04",X"0A",X"1F",X"17",X"0D",X"06");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

446
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-------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the ALU core plus the Accumulator and the Temp Reg.
--
-- $Id: alu.vhd,v 1.8 2004/04/24 23:43:56 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.alu_pack.alu_op_t;
entity alu is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_accu_i : in boolean;
write_shadow_i : in boolean;
write_temp_reg_i : in boolean;
read_alu_i : in boolean;
-- Decoder Interface ------------------------------------------------------
carry_i : in std_logic;
carry_o : out std_logic;
aux_carry_o : out std_logic;
alu_op_i : in alu_op_t;
use_carry_i : in boolean;
da_high_i : in boolean;
da_overflow_o : out boolean;
accu_low_i : in boolean;
p06_temp_reg_i : in boolean;
p60_temp_reg_i : in boolean
);
end alu;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.nibble_t;
use work.alu_pack.all;
-- pragma translate_off
use work.t48_tb_pack.tb_accu_s;
-- pragma translate_on
architecture rtl of alu is
-- the Accumulator and Temp Reg
signal accumulator_q,
accu_shadow_q,
temp_req_q : word_t;
-- inputs to the ALU core
signal in_a_s,
in_b_s : word_t;
-- output of the ALU core
signal data_s : word_t;
signal add_result_s : alu_operand_t;
begin
-----------------------------------------------------------------------------
-- Process working_regs
--
-- Purpose:
-- Implements the working registers:
-- + Accumulator
-- + Temp Reg
--
working_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
accumulator_q <= (others => '0');
accu_shadow_q <= (others => '0');
temp_req_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_accu_i then
if accu_low_i then
accumulator_q(nibble_t'range) <= data_i(nibble_t'range);
else
accumulator_q <= data_i;
end if;
end if;
if write_shadow_i then
-- write shadow directly from t48 data bus
accu_shadow_q <= data_i;
else
-- default: update shadow Accumulator from real Accumulator
accu_shadow_q <= accumulator_q;
end if;
if p06_temp_reg_i then
-- low nibble of DA sequence
temp_req_q <= "00000110";
elsif p60_temp_reg_i then
-- high nibble of DA sequence
temp_req_q <= "01100000";
elsif write_temp_reg_i then
-- normal load from T48 bus
temp_req_q <= data_i;
end if;
end if;
end if;
end process working_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Build the inputs to the ALU core.
-- Input A:
-- Unary operators use only Input A.
-- Is always fed from the shadow Accumulator.
-- Assumption: It never happens that the Accumulator is written and then
-- read for an ALU operation in the next cycle.
-- Its contents can thus be staged through the shadow Accu.
-- Input B:
-- Is always fed from the Temp Reg.
-----------------------------------------------------------------------------
in_a_s <= accu_shadow_q;
in_b_s <= temp_req_q;
-----------------------------------------------------------------------------
-- Process alu_core
--
-- Purpose:
-- Implements the ALU core.
-- All operations defined in alu_op_t are handled here.
--
alu_core: process (in_a_s,
in_b_s,
alu_op_i,
carry_i,
use_carry_i,
add_result_s)
begin
-- default assigments
data_s <= (others => '0');
carry_o <= '0';
case alu_op_i is
-- Operation: AND -------------------------------------------------------
when ALU_AND =>
data_s <= in_a_s and in_b_s;
-- Operation: OR --------------------------------------------------------
when ALU_OR =>
data_s <= in_a_s or in_b_s;
-- Operation: XOR -------------------------------------------------------
when ALU_XOR =>
data_s <= in_a_s xor in_b_s;
-- Operation: Add -------------------------------------------------------
when ALU_ADD =>
data_s <= add_result_s(data_s'range);
carry_o <= add_result_s(add_result_s'high);
-- Operation: CPL -------------------------------------------------------
when ALU_CPL =>
data_s <= not in_a_s;
-- Operation: CLR -------------------------------------------------------
when ALU_CLR =>
data_s <= (others => '0');
-- Operation: RL --------------------------------------------------------
when ALU_RL =>
data_s(7 downto 1) <= in_a_s(6 downto 0);
carry_o <= in_a_s(7);
if use_carry_i then
data_s(0) <= carry_i;
else
data_s(0) <= in_a_s(7);
end if;
-- Operation: RR --------------------------------------------------------
when ALU_RR =>
data_s(6 downto 0) <= in_a_s(7 downto 1);
carry_o <= in_a_s(0);
if use_carry_i then
data_s(7) <= carry_i;
else
data_s(7) <= in_a_s(0);
end if;
-- Operation: Swap ------------------------------------------------------
when ALU_SWAP =>
data_s(3 downto 0) <= in_a_s(7 downto 4);
data_s(7 downto 4) <= in_a_s(3 downto 0);
-- Operation: DEC -------------------------------------------------------
when ALU_DEC =>
data_s <= add_result_s(data_s'range);
-- Operation: INC -------------------------------------------------------
when ALU_INC =>
data_s <= add_result_s(data_s'range);
-- Operation CONCAT -----------------------------------------------------
when ALU_CONCAT =>
data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0);
-- Operation: NOP -------------------------------------------------------
when ALU_NOP =>
data_s <= in_a_s;
when others =>
-- pragma translate_off
assert false
report "Unknown ALU operation selected!"
severity error;
-- pragma translate_on
end case;
end process alu_core;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process adder
--
-- Purpose:
-- Implements the adder used by several instructions.
-- This way of modelling the adder forces resource sharing of:
-- * ADD
-- * INC
-- * DEC
--
adder: process (in_a_s,
in_b_s,
alu_op_i,
carry_i,
use_carry_i)
variable add_a_v, add_b_v : alu_operand_t;
variable c_v : alu_operand_t;
variable result_v : UNSIGNED(alu_operand_t'range);
variable aux_c_v : std_logic_vector(1 downto 0);
begin
-- Carry Selection --------------------------------------------------------
c_v := (others => '0');
if use_carry_i and carry_i = '1' then
c_v(0) := '1';
end if;
-- Operand Selection ------------------------------------------------------
-- defaults for ADD
add_a_v := '0' & in_a_s;
add_b_v := '0' & in_b_s;
case alu_op_i is
when ALU_INC =>
add_b_v := (others => '0');
add_b_v(0) := '1';
when ALU_DEC =>
add_b_v := (others => '1');
when others =>
null;
end case;
-- The Adder --------------------------------------------------------------
result_v := UNSIGNED(add_a_v) +
UNSIGNED(add_b_v) +
UNSIGNED(c_v);
add_result_s <= std_logic_vector(result_v);
-- Auxiliary Carry --------------------------------------------------------
aux_c_v := in_a_s(4) & in_b_s(4);
aux_carry_o <= '0';
case aux_c_v is
when "00" | "11" =>
if result_v(4) = '1' then
aux_carry_o <= '1';
end if;
when "01" | "10" =>
if result_v(4) = '0' then
aux_carry_o <= '1';
end if;
when others =>
null;
end case;
end process adder;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process da_overflow
--
-- Purpose:
-- Detect overflow situation during DA sequence.
--
da_overflow: process (accu_shadow_q,
da_high_i)
variable da_nibble_v : nibble_t;
function da_overflow_f(data : in nibble_t) return boolean is
variable overflow_v : boolean;
begin
case data is
when "1010" |
"1011" |
"1100" |
"1101" |
"1110" |
"1111" =>
overflow_v := true;
when others =>
overflow_v := false;
end case;
return(overflow_v);
end;
begin
if da_high_i then
da_nibble_v := accu_shadow_q(7 downto 4);
else
da_nibble_v := accu_shadow_q(3 downto 0);
end if;
da_overflow_o <= da_overflow_f(da_nibble_v);
end process da_overflow;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-----------------------------------------------------------------------------
-- Testbench support.
-----------------------------------------------------------------------------
tb_accu_s <= accumulator_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output Multiplexer.
-----------------------------------------------------------------------------
data_o <= data_s
when read_alu_i else
(others => bus_idle_level_c);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: alu.vhd,v $
-- Revision 1.8 2004/04/24 23:43:56 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.7 2004/04/07 22:09:03 arniml
-- remove unused signals
--
-- Revision 1.6 2004/04/07 20:56:23 arniml
-- default assignment for aux_carry_o
--
-- Revision 1.5 2004/04/06 20:21:53 arniml
-- fix sensitivity list
--
-- Revision 1.4 2004/04/06 18:10:41 arniml
-- rework adder and force resource sharing between ADD, INC and DEC
--
-- Revision 1.3 2004/04/04 14:18:52 arniml
-- add measures to implement XCHD
--
-- Revision 1.2 2004/03/28 21:08:51 arniml
-- support for DA instruction
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

49
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/t48_ip/alu_pack-p.vhd Normal file
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-------------------------------------------------------------------------------
--
-- $Id: alu_pack-p.vhd,v 1.2 2004/04/04 14:18:53 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_width_c;
package alu_pack is
-----------------------------------------------------------------------------
-- The ALU operations
-----------------------------------------------------------------------------
type alu_op_t is (ALU_AND, ALU_OR, ALU_XOR,
ALU_CPL, ALU_CLR,
ALU_RL, ALU_RR,
ALU_SWAP,
ALU_DEC, ALU_INC,
ALU_ADD,
ALU_CONCAT,
ALU_NOP);
-----------------------------------------------------------------------------
-- The dedicated ALU arithmetic types.
-----------------------------------------------------------------------------
subtype alu_operand_t is std_logic_vector(word_width_c downto 0);
end alu_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: alu_pack-p.vhd,v $
-- Revision 1.2 2004/04/04 14:18:53 arniml
-- add measures to implement XCHD
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

111
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/t48_ip/bus_mux.vhd Normal file
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-------------------------------------------------------------------------------
--
-- The T48 Bus Connector.
-- Multiplexes all drivers of the T48 bus.
--
-- $Id: bus_mux.vhd,v 1.1 2004/03/23 21:31:52 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity bus_mux is
port (
alu_data_i : in word_t;
bus_data_i : in word_t;
dec_data_i : in word_t;
dm_data_i : in word_t;
pm_data_i : in word_t;
p1_data_i : in word_t;
p2_data_i : in word_t;
psw_data_i : in word_t;
tim_data_i : in word_t;
data_o : out word_t
);
end bus_mux;
use work.t48_pack.bus_idle_level_c;
architecture rtl of bus_mux is
begin
or_tree: if bus_idle_level_c = '0' generate
data_o <= alu_data_i or
bus_data_i or
dec_data_i or
dm_data_i or
pm_data_i or
p1_data_i or
p2_data_i or
psw_data_i or
tim_data_i;
end generate;
and_tree: if bus_idle_level_c = '1' generate
data_o <= alu_data_i and
bus_data_i and
dec_data_i and
dm_data_i and
pm_data_i and
p1_data_i and
p2_data_i and
psw_data_i and
tim_data_i;
end generate;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: bus_mux.vhd,v $
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

397
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/t48_ip/clock_ctrl.vhd Normal file
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-------------------------------------------------------------------------------
--
-- The Clock Control unit.
-- Clock States and Machine Cycles are generated here.
--
-- $Id: clock_ctrl.vhd,v 1.4 2004/04/24 23:44:25 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.all;
entity clock_ctrl is
generic (
-- divide XTAL1 by 3 to derive Clock States
xtal_div_3_g : integer := 1
);
port (
clk_i : in std_logic;
xtal_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal3_o : out boolean;
multi_cycle_i : in boolean;
assert_psen_i : in boolean;
assert_prog_i : in boolean;
assert_rd_i : in boolean;
assert_wr_i : in boolean;
mstate_o : out mstate_t;
second_cycle_o : out boolean;
ale_o : out boolean;
psen_o : out boolean;
prog_o : out boolean;
rd_o : out boolean;
wr_o : out boolean
);
end clock_ctrl;
library ieee;
use ieee.numeric_std.all;
architecture rtl of clock_ctrl is
-- The three XTAL1 cycles.
signal xtal_q : unsigned(1 downto 0);
signal xtal1_s,
xtal2_s,
xtal3_s : boolean;
signal x1_s,
x2_s,
x3_s : std_logic;
-- The five clock states.
signal mstate_q : mstate_t;
signal ale_q : boolean;
signal psen_q : boolean;
signal prog_q : boolean;
signal rd_q : boolean;
signal wr_q : boolean;
-- The Machine Cycle marker.
signal second_cycle_q : boolean;
signal multi_cycle_q : boolean;
begin
-----------------------------------------------------------------------------
-- Verify the generics
-----------------------------------------------------------------------------
-- pragma translate_off
-- XTAL1 divide by 3 --------------------------------------------------------
assert (xtal_div_3_g = 1) or (xtal_div_3_g = 0)
report "xtal_div_3_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Divide XTAL1 by 3 to derive Clock States.
-----------------------------------------------------------------------------
use_xtal_div: if xtal_div_3_g = 1 generate
xtal: process (res_i, xtal_i)
begin
if res_i = res_active_c then
xtal_q <= TO_UNSIGNED(0, 2);
elsif xtal_i'event and xtal_i = clk_active_c then
if xtal_q < 2 then
xtal_q <= xtal_q + 1;
else
xtal_q <= TO_UNSIGNED(0, 2);
end if;
end if;
end process xtal;
x1_s <= '1'
when xtal_q = 0 else
'0';
x2_s <= '1'
when xtal_q = 1 else
'0';
x3_s <= '1'
when xtal_q = 2 else
'0';
end generate;
-----------------------------------------------------------------------------
-- XTAL1 is used directly for Clock States.
-----------------------------------------------------------------------------
no_xtal_div: if xtal_div_3_g = 0 generate
xtal_q <= TO_UNSIGNED(0, 2);
x1_s <= '1';
x2_s <= '1';
x3_s <= '1';
end generate;
-- And finally the boolean flags --------------------------------------------
xtal1_s <= to_boolean(x1_s);
xtal2_s <= to_boolean(x2_s);
xtal3_s <= to_boolean(x3_s);
-----------------------------------------------------------------------------
-- Process external_signal
--
-- Purpose:
-- Control signals ALE, PSEN, PROG and RD/WR are generated here.
--
external_signals: process (res_i, xtal_i)
begin
if res_i = res_active_c then
ale_q <= false;
psen_q <= false;
prog_q <= false;
rd_q <= false;
wr_q <= false;
elsif xtal_i'event and xtal_i = clk_active_c then
case mstate_q is
when MSTATE5 =>
-- RD, WR are set at the end of XTAL2 of first machine cycle
if xtal2_s and not second_cycle_q then
if assert_rd_i then
rd_q <= true;
end if;
if assert_wr_i then
wr_q <= true;
end if;
end if;
when MSTATE1 =>
if xtal3_s then
psen_q <= false;
end if;
when MSTATE2 =>
if xtal2_s then
-- RD, WR are removed at the end of XTAL3 of second machine cycle
rd_q <= false;
wr_q <= false;
-- PROG is removed at the and of XTAL3 of second machine cycle
prog_q <= false;
end if;
when MSTATE3 =>
-- ALE is set at the end of XTAL2 of every machine cycle
if xtal2_s then
ale_q <= true;
end if;
when MSTATE4 =>
if xtal3_s then
-- PSEN is set at the end of XTAL3
if assert_psen_i then
psen_q <= true;
end if;
end if;
-- PROG is set at the and of XTAL2
if xtal2_s and multi_cycle_q and not second_cycle_q and
assert_prog_i then
prog_q <= true;
end if;
-- ALE is removed at the end of XTAL2 of every machine cycle
if xtal2_s then
ale_q <= false;
end if;
when others =>
-- recover when states are out of sync
ale_q <= false;
psen_q <= false;
prog_q <= false;
rd_q <= false;
wr_q <= false;
end case;
end if;
end process external_signals;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process states
--
-- Purpose:
-- The Clock State controller.
--
states: process (res_i, clk_i)
begin
if res_i = res_active_c then
-- Reset machine state to MSTATE3
-- This allows a proper instruction fetch for the first real instruction
-- after reset.
-- The MSTATE3 is part of a virtual NOP that has no MSTATE1 and MSTATE2.
mstate_q <= MSTATE3;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
case mstate_q is
when MSTATE5 =>
mstate_q <= MSTATE1;
when MSTATE1 =>
mstate_q <= MSTATE2;
when MSTATE2 =>
mstate_q <= MSTATE3;
when MSTATE3 =>
mstate_q <= MSTATE4;
when MSTATE4 =>
mstate_q <= MSTATE5;
when others =>
-- recover when states are out of sync
mstate_q <= MSTATE1;
-- pragma translate_off
assert false
report "Encoding of Clock States failed!"
severity error;
-- pragma translate_on
end case;
end if;
end if;
end process states;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process machine_cycle
--
-- Purpose:
-- Keep track of machine cycles.
-- Basically, this means to differ between first and second cycle.
--
machine_cycle: process (res_i, clk_i)
variable state2_v, state5_v : boolean;
begin
if res_i = res_active_c then
multi_cycle_q <= false;
second_cycle_q <= false;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
state2_v := mstate_q = MSTATE2;
state5_v := mstate_q = MSTATE5;
-- multi cycle information is delivered in State 2 from the decoder
if state2_v and multi_cycle_i then
multi_cycle_q <= true;
end if;
-- mark second machine cycle
if multi_cycle_q and state5_v then
second_cycle_q <= true;
end if;
-- reset at end of second machine cycle
if state5_v and
(multi_cycle_q and second_cycle_q) then
multi_cycle_q <= false;
second_cycle_q <= false;
end if;
end if;
end if;
end process machine_cycle;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
xtal3_o <= xtal3_s;
mstate_o <= mstate_q;
second_cycle_o <= second_cycle_q;
ale_o <= ale_q;
psen_o <= psen_q;
prog_o <= prog_q;
rd_o <= rd_q;
wr_o <= wr_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: clock_ctrl.vhd,v $
-- Revision 1.4 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.3 2004/04/18 18:56:23 arniml
-- reset machine state to MSTATE3 to allow proper instruction fetch
-- after reset
--
-- Revision 1.2 2004/03/28 12:55:06 arniml
-- move code for PROG out of if-branch for xtal3_s
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Conditional Branch Logic unit.
-- Decisions whether to take a jump or not are made here.
--
-- $Id: cond_branch.vhd,v 1.2 2004/04/24 23:44:25 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.cond_branch_pack.all;
entity cond_branch is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- Decoder Interface ------------------------------------------------------
compute_take_i : in boolean;
branch_cond_i : in branch_conditions_t;
take_branch_o : out boolean;
accu_i : in word_t;
t0_i : in std_logic;
t1_i : in std_logic;
int_n_i : in std_logic;
f0_i : in std_logic;
f1_i : in std_logic;
tf_i : in std_logic;
carry_i : in std_logic;
comp_value_i : in comp_value_t
);
end cond_branch;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.res_active_c;
use work.t48_pack.clk_active_c;
architecture rtl of cond_branch is
-- marker for branch taken
signal take_branch_s,
take_branch_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process decide_take
--
-- Purpose:
-- Decides whether a branch has to be taken or not.
--
decide_take: process (accu_i,
branch_cond_i,
t0_i, t1_i,
int_n_i,
f0_i, f1_i,
tf_i,
carry_i,
comp_value_i)
variable or_v : std_logic;
begin
-- default assignment
take_branch_s <= false;
or_v := '0';
case branch_cond_i is
-- Branch On: Accumulator Bit -------------------------------------------
when COND_ON_BIT =>
if accu_i(TO_INTEGER(UNSIGNED(comp_value_i))) = '1' then
take_branch_s <= true;
end if;
-- Branch On: Accumulator Zero ------------------------------------------
when COND_Z =>
for i in accu_i'range loop
or_v := or_v or accu_i(i);
end loop;
take_branch_s <= or_v = not comp_value_i(0);
-- Branch On: Carry -----------------------------------------------------
when COND_C =>
take_branch_s <= carry_i = comp_value_i(0);
-- Branch On: Flag 0 ----------------------------------------------------
when COND_F0 =>
take_branch_s <= f0_i = '1';
-- Branch On: Flag 1 ----------------------------------------------------
when COND_F1 =>
take_branch_s <= f1_i = '1';
-- Branch On: Interrupt -------------------------------------------------
when COND_INT =>
take_branch_s <= int_n_i = '0';
-- Branch On: Test 0 ----------------------------------------------------
when COND_T0 =>
take_branch_s <= t0_i = comp_value_i(0);
-- Branch On: Test 1 ----------------------------------------------------
when COND_T1 =>
take_branch_s <= t1_i = comp_value_i(0);
-- Branch On: Timer Flag ------------------------------------------------
when COND_TF =>
take_branch_s <= tf_i = '1';
when others =>
-- pragma translate_off
assert false
report "Unknown branch condition specified!"
severity error;
-- pragma translate_on
end case;
end process decide_take;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process reg
--
-- Purpose:
-- Implement the marker register.
--
reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
take_branch_q <= false;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if compute_take_i then
take_branch_q <= take_branch_s;
end if;
end if;
end if;
end process reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
take_branch_o <= take_branch_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: cond_branch.vhd,v $
-- Revision 1.2 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: cond_branch_pack-p.vhd,v 1.1 2004/03/23 21:31:52 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package cond_branch_pack is
-----------------------------------------------------------------------------
-- The branch conditions.
-----------------------------------------------------------------------------
type branch_conditions_t is (COND_ON_BIT, COND_Z,
COND_C,
COND_F0, COND_F1,
COND_INT,
COND_T0, COND_T1,
COND_TF);
subtype comp_value_t is std_logic_vector(2 downto 0);
end cond_branch_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: cond_branch_pack-p.vhd,v $
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The BUS unit.
-- Implements the BUS port logic.
--
-- $Id: db_bus.vhd,v 1.2 2004/04/04 14:15:45 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity db_bus is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
ea_i : in std_logic;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_bus_i : in boolean;
read_bus_i : in boolean;
-- BUS Interface ----------------------------------------------------------
output_pcl_i : in boolean;
bidir_bus_i : in boolean;
pcl_i : in word_t;
db_i : in word_t;
db_o : out word_t;
db_dir_o : out std_logic
);
end db_bus;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.to_stdLogic;
architecture rtl of db_bus is
-- the BUS output register
signal bus_q : word_t;
-- BUS direction marker
signal db_dir_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process bus_regs
--
-- Purpose:
-- Implements the BUS output register.
--
bus_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
bus_q <= (others => '0');
db_dir_q <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_bus_i then
bus_q <= data_i;
db_dir_q <= '1';
elsif ea_i = '1' or bidir_bus_i then
db_dir_q <= '0';
end if;
end if;
end if;
end process bus_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
db_o <= pcl_i
when output_pcl_i else
bus_q;
db_dir_o <= db_dir_q or to_stdLogic(output_pcl_i);
data_o <= (others => bus_idle_level_c)
when not read_bus_i else
db_i;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: db_bus.vhd,v $
-- Revision 1.2 2004/04/04 14:15:45 arniml
-- add dump_compare support
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/t48_ip/decoder.vhd Normal file
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87
Arcade_MiST/Nintendo Radar Scope Hardware/DonkeyKongJunior/rtl/t48_ip/decoder_pack-p.vhd Normal file
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-------------------------------------------------------------------------------
--
-- $Id: decoder_pack-p.vhd,v 1.2 2004/03/28 13:09:53 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
package decoder_pack is
-----------------------------------------------------------------------------
-- The Mnemonics.
-----------------------------------------------------------------------------
type mnemonic_t is (MN_ADD,
MN_ADD_A_DATA,
MN_ANL,
MN_ANL_A_DATA,
MN_ANL_EXT,
MN_CALL,
MN_CLR_A,
MN_CLR_C,
MN_CLR_F,
MN_CPL_A,
MN_CPL_C,
MN_CPL_F,
MN_DA,
MN_DEC,
MN_DIS_EN_I,
MN_DIS_EN_TCNTI,
MN_DJNZ,
MN_ENT0_CLK,
MN_IN,
MN_INC,
MN_INS,
MN_JBB,
MN_JC,
MN_JF,
MN_JMP,
MN_JMPP,
MN_JNI,
MN_JT,
MN_JTF,
MN_JZ,
MN_MOV_A_DATA,
MN_MOV_A_PSW,
MN_MOV_A_RR,
MN_MOV_PSW_A,
MN_MOV_RR,
MN_MOV_RR_DATA,
MN_MOV_T,
MN_MOVD_A_PP,
MN_MOVP,
MN_MOVX,
MN_NOP,
MN_ORL,
MN_ORL_A_DATA,
MN_ORL_EXT,
MN_OUTD_PP_A,
MN_OUTL_EXT,
MN_RET,
MN_RL,
MN_RR,
MN_SEL_MB,
MN_SEL_RB,
MN_STOP_TCNT,
MN_STRT,
MN_SWAP,
MN_XCH,
MN_XRL,
MN_XRL_A_DATA);
end decoder_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: decoder_pack-p.vhd,v $
-- Revision 1.2 2004/03/28 13:09:53 arniml
-- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Data Memory control unit.
-- All accesses to the Data Memory are managed here.
--
-- $Id: dmem_ctrl.vhd,v 1.3 2004/04/24 23:44:25 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.dmem_addr_t;
use work.t48_pack.word_t;
use work.dmem_ctrl_pack.dmem_addr_ident_t;
entity dmem_ctrl is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- Control Interface ------------------------------------------------------
data_i : in word_t;
write_dmem_addr_i : in boolean;
write_dmem_i : in boolean;
read_dmem_i : in boolean;
addr_type_i : in dmem_addr_ident_t;
bank_select_i : in std_logic;
data_o : out word_t;
-- Data Memory Interface --------------------------------------------------
dmem_data_i : in word_t;
dmem_addr_o : out dmem_addr_t;
dmem_we_o : out std_logic;
dmem_data_o : out word_t
);
end dmem_ctrl;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.to_stdLogic;
use work.dmem_ctrl_pack.all;
architecture rtl of dmem_ctrl is
signal dmem_addr_s,
dmem_addr_q : dmem_addr_t;
begin
-----------------------------------------------------------------------------
-- Process addr_decode
--
-- Purpose:
-- Decode/multiplex the address information for the Data Memory.
--
addr_decode: process (data_i,
addr_type_i,
bank_select_i,
dmem_addr_q)
variable stack_addr_v : unsigned(5 downto 0);
begin
-- default assignment
dmem_addr_s <= dmem_addr_q;
stack_addr_v := (others => '0');
case addr_type_i is
when DM_PLAIN =>
dmem_addr_s <= data_i;
when DM_REG =>
dmem_addr_s <= (others => '0');
dmem_addr_s(2 downto 0) <= data_i(2 downto 0);
-- implement bank switching
if bank_select_i = '1' then
-- dmem address 24 - 31: access proper set
dmem_addr_s(4 downto 3) <= "11";
end if;
when DM_STACK =>
-- build address from stack pointer
stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
-- dmem address 8 - 23
stack_addr_v := stack_addr_v + 8;
dmem_addr_s <= (others => '0');
dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v);
when DM_STACK_HIGH =>
dmem_addr_s(0) <= '1';
when others =>
-- do nothing
-- pragma translate_off
assert false
report "Unknown address type identification for Data Memory controller!"
severity error;
-- pragma translate_on
end case;
end process addr_decode;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process dmem_addr_reg
--
-- Purpose:
-- Implements the Data Memory Address Register.
-- This register is necessary to hold the address during a write operation
-- as we cannot hold the address in the input register of the
-- synchronous RAM (no clock suppression/gating).
--
dmem_addr_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
dmem_addr_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_dmem_addr_i then
dmem_addr_q <= dmem_addr_s;
end if;
end if;
end if;
end process dmem_addr_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping.
-----------------------------------------------------------------------------
dmem_addr_o <= dmem_addr_s
when write_dmem_addr_i and en_clk_i else
dmem_addr_q;
-- data from bus is fed through
dmem_data_o <= data_i;
-- data to bus is enabled upon read request
data_o <= dmem_data_i
when read_dmem_i else
(others => bus_idle_level_c);
-- write enable to Data Memory is fed through
dmem_we_o <= to_stdLogic(write_dmem_i);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: dmem_ctrl.vhd,v $
-- Revision 1.3 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.2 2004/04/18 18:58:29 arniml
-- clean up sensitivity list
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: dmem_ctrl_pack-p.vhd,v 1.1 2004/03/23 21:31:52 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
package dmem_ctrl_pack is
-----------------------------------------------------------------------------
-- Address Type Identifier
-----------------------------------------------------------------------------
type dmem_addr_ident_t is (DM_PLAIN,
DM_REG,
DM_STACK,
DM_STACK_HIGH);
end dmem_ctrl_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: dmem_ctrl_pack-p.vhd,v $
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Interrupt Controller.
-- It collects the interrupt sources and notifies the decoder.
--
-- $Id: int.vhd,v 1.3 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.mstate_t;
entity int is
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
clk_mstate_i : in mstate_t;
jtf_executed_i : in boolean;
tim_overflow_i : in boolean;
tf_o : out std_logic;
en_tcnti_i : in boolean;
dis_tcnti_i : in boolean;
int_n_i : in std_logic;
ale_i : in boolean;
last_cycle_i : in boolean;
en_i_i : in boolean;
dis_i_i : in boolean;
ext_int_o : out boolean;
tim_int_o : out boolean;
retr_executed_i : in boolean;
int_executed_i : in boolean;
int_pending_o : out boolean;
int_in_progress_o : out boolean
);
end int;
use work.t48_pack.all;
architecture rtl of int is
constant tim_int_c : std_logic := '0';
constant ext_int_c : std_logic := '1';
type int_state_t is (IDLE, PENDING, INT);
signal int_state_s,
int_state_q : int_state_t;
signal timer_flag_q : boolean;
signal timer_overflow_q : boolean;
signal timer_int_enable_q : boolean;
signal int_q : boolean;
signal int_enable_q : boolean;
signal ale_q : boolean;
signal int_type_q : std_logic;
signal int_in_progress_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process nstate
--
-- Purpose:
-- Determines the next state of the Interrupt controller FSM.
--
nstate: process (int_state_q,
int_type_q,
int_in_progress_q,
int_executed_i,
retr_executed_i,
clk_mstate_i,
last_cycle_i)
begin
int_state_s <= int_state_q;
case int_state_q is
when IDLE =>
if int_in_progress_q and
last_cycle_i and clk_mstate_i = MSTATE5 then
int_state_s <= PENDING;
end if;
when PENDING =>
if int_executed_i then
int_state_s <= INT;
end if;
when INT =>
if retr_executed_i then
int_state_s <= IDLE;
end if;
when others =>
int_state_s <= IDLE;
end case;
end process nstate;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implement the various registers.
-- They are designed according Figure "Interrupt Logic" of
-- "The Single Component MCS-48 System".
--
regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
timer_flag_q <= false;
timer_overflow_q <= false;
timer_int_enable_q <= false;
int_q <= false;
int_enable_q <= false;
ale_q <= false;
int_type_q <= '0';
int_state_q <= IDLE;
int_in_progress_q <= false;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
ale_q <= ale_i;
int_state_q <= int_state_s;
if jtf_executed_i then
timer_flag_q <= false;
elsif tim_overflow_i then
timer_flag_q <= true;
end if;
if (int_type_q = tim_int_c and int_executed_i) or
not timer_int_enable_q then
timer_overflow_q <= false;
elsif tim_overflow_i then
timer_overflow_q <= true;
end if;
if dis_tcnti_i then
timer_int_enable_q <= false;
elsif en_tcnti_i then
timer_int_enable_q <= true;
end if;
if last_cycle_i and
ale_q and not ale_i then
int_q <= not to_boolean(int_n_i);
end if;
if dis_i_i then
int_enable_q <= false;
elsif en_i_i then
int_enable_q <= true;
end if;
if retr_executed_i then
int_in_progress_q <= false;
elsif (int_q and int_enable_q) or
timer_overflow_q then
int_in_progress_q <= true;
if not int_in_progress_q then
int_type_q <= to_stdLogic(int_q and int_enable_q);
end if;
end if;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
tf_o <= to_stdLogic(timer_flag_q);
ext_int_o <= int_type_q = ext_int_c;
tim_int_o <= int_type_q = tim_int_c;
int_pending_o <= int_state_q = PENDING;
int_in_progress_o <= int_in_progress_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: int.vhd,v $
-- Revision 1.3 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.2 2004/06/30 21:18:28 arniml
-- Fix bug report:
-- "Program Memory bank can be switched during interrupt"
-- int module emits int_in_progress signal that is used inside the decoder
-- to hold mb low for JMP and CALL during interrupts
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Opcode Decoder.
-- Derives instruction mnemonics and multicycle information
-- using the OPC table unit.
--
-- $Id: opc_decoder.vhd,v 1.2 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.decoder_pack.mnemonic_t;
entity opc_decoder is
generic (
-- store mnemonic in flip-flops (registered-out)
register_mnemonic_g : integer := 1
);
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
read_bus_i : in boolean;
-- Decoder Interface ------------------------------------------------------
inj_int_i : in boolean;
opcode_o : out word_t;
mnemonic_o : out mnemonic_t;
multi_cycle_o : out boolean
);
end opc_decoder;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.to_boolean;
--use work.decoder_pack.MN_NOP;
use work.decoder_pack.all;
use work.t48_comp_pack.opc_table;
architecture rtl of opc_decoder is
-- the opcode register
signal opcode_q : word_t;
-- the mnemonic
signal mnemonic_s,
mnemonic_q : mnemonic_t;
signal multi_cycle_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Verify the generics
-----------------------------------------------------------------------------
-- pragma translate_off
-- Register Mnemonic --------------------------------------------------------
assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0)
report "register_mnemonic_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Opcode Decoder Table
-----------------------------------------------------------------------------
opc_table_b : opc_table
port map (
opcode_i => opcode_q,
multi_cycle_o => multi_cycle_s,
mnemonic_o => mnemonic_s
);
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implements the opcode and mnemonic registers.
--
regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
opcode_q <= (others => '0'); -- NOP
mnemonic_q <= MN_NOP;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if read_bus_i then
opcode_q <= data_i;
elsif inj_int_i then
opcode_q <= "00010100";
else
mnemonic_q <= mnemonic_s;
end if;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
opcode_o <= opcode_q;
multi_cycle_o <= to_boolean(multi_cycle_s);
mnemonic_o <= mnemonic_q
when register_mnemonic_g = 1 else
mnemonic_s;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: opc_decoder.vhd,v $
-- Revision 1.2 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Opcode Decoder Table.
-- Decodes the given opcode to instruction mnemonics.
-- Also derives the multicycle information.
--
-- $Id: opc_table.vhd,v 1.3 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.decoder_pack.mnemonic_t;
entity opc_table is
port (
opcode_i : in word_t;
multi_cycle_o : out std_logic;
mnemonic_o : out mnemonic_t
);
end opc_table;
use work.decoder_pack.all;
architecture rtl of opc_table is
begin
-----------------------------------------------------------------------------
-- Process opc_decode
--
-- Purpose:
-- Decode the opcode to the set of mnemonics.
--
opc_decode: process (opcode_i)
begin
-- default assignment
mnemonic_o <= MN_NOP;
multi_cycle_o <= '0';
case opcode_i is
-- Mnemonic ADD ---------------------------------------------------------
when "01101000" | "01101001" | "01101010" | "01101011" | -- ADD A, Rr
"01101100" | "01101101" | "01101110" | "01101111" | --
"01100000" | "01100001" | -- ADD A, @ Rr
"01111000" | "01111001" | "01111010" | "01111011" | -- ADDC A, Rr
"01111100" | "01111101" | "01111110" | "01111111" | --
"01110000" | "01110001" => -- ADDC A, @ Rr
mnemonic_o <= MN_ADD;
-- Mnemonic ADD_A_DATA --------------------------------------------------
when "00000011" | -- ADD A, data
"00010011" => -- ADDC A, data
mnemonic_o <= MN_ADD_A_DATA;
multi_cycle_o <= '1';
-- Mnemonic ANL ---------------------------------------------------------
when "01011000" | "01011001" | "01011010" | "01011011" | -- ANL A, Rr
"01011100" | "01011101" | "01011110" | "01011111" | --
"01010000" | "01010001" => -- ANL A, @ Rr
mnemonic_o <= MN_ANL;
-- Mnemonic ANL_A_DATA --------------------------------------------------
when "01010011" => -- ANL A, data
mnemonic_o <= MN_ANL_A_DATA;
multi_cycle_o <= '1';
-- Mnemonic ANL_EXT -----------------------------------------------------
when "10011000" | -- ANL BUS, data
"10011001" | "10011010" => -- ANL PP, data
mnemonic_o <= MN_ANL_EXT;
multi_cycle_o <= '1';
-- Mnemonic CALL --------------------------------------------------------
when "00010100" | "00110100" | "01010100" | "01110100" | -- CALL addr
"10010100" | "10110100" | "11010100" | "11110100" => --
mnemonic_o <= MN_CALL;
multi_cycle_o <= '1';
-- Mnemonic CLR_A -------------------------------------------------------
when "00100111" => -- CLR A
mnemonic_o <= MN_CLR_A;
-- Mnemonic CLR_C -------------------------------------------------------
when "10010111" => -- CLR C
mnemonic_o <= MN_CLR_C;
-- Mnemonic CLR_F -------------------------------------------------------
when "10000101" | -- CLR F0
"10100101" =>
mnemonic_o <= MN_CLR_F;
-- Mnemonic CPL_A -------------------------------------------------------
when "00110111" => -- CPL A
mnemonic_o <= MN_CPL_A;
-- Mnemonic CPL_C -------------------------------------------------------
when "10100111" => -- CPL C
mnemonic_o <= MN_CPL_C;
-- Mnemonic CPL_F -------------------------------------------------------
when "10010101" | -- CPL F0
"10110101" => -- CPL F1
mnemonic_o <= MN_CPL_F;
-- Mnemonic DA ----------------------------------------------------------
when "01010111" => -- DA D
mnemonic_o <= MN_DA;
-- Mnemonic DEC ---------------------------------------------------------
when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr
"11001100" | "11001101" | "11001110" | "11001111" | --
"00000111" => -- DEC A
mnemonic_o <= MN_DEC;
-- Mnemonic DIS_EN_I ----------------------------------------------------
when "00010101" | -- DIS I
"00000101" => -- EN I
mnemonic_o <= MN_DIS_EN_I;
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------
when "00110101" | -- DIS TCNTI
"00100101" => -- EN TCNTI
mnemonic_o <= MN_DIS_EN_TCNTI;
-- Mnemonic DJNZ --------------------------------------------------------
when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr
"11101100" | "11101101" | "11101110" | "11101111" => --
mnemonic_o <= MN_DJNZ;
multi_cycle_o <= '1';
-- Mnemonic ENT0_CLK ----------------------------------------------------
when "01110101" => -- ENT0 CLK
mnemonic_o <= MN_ENT0_CLK;
-- Mnemonic IN ----------------------------------------------------------
when "00001001" | "00001010" => -- IN A, Pp
mnemonic_o <= MN_IN;
multi_cycle_o <= '1';
-- Mnemonic INC ---------------------------------------------------------
when "00010111" | -- INC A
"00011000" | "00011001" | "00011010" | "00011011" | -- INC Rr
"00011100" | "00011101" | "00011110" | "00011111" | --
"00010000" | "00010001" => -- INC @ Rr
mnemonic_o <= MN_INC;
-- Mnemonic INS ---------------------------------------------------------
when "00001000" => -- INS A, BUS
mnemonic_o <= MN_INS;
multi_cycle_o <= '1';
-- Mnemonic JBB ---------------------------------------------------------
when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr
"10010010" | "10110010" | "11010010" | "11110010" => --
mnemonic_o <= MN_JBB;
multi_cycle_o <= '1';
-- Mnemonic JC ----------------------------------------------------------
when "11110110" | -- JC addr
"11100110" => -- JNC addr
mnemonic_o <= MN_JC;
multi_cycle_o <= '1';
-- Mnemonic JF ----------------------------------------------------------
when "10110110" | -- JF0 addr
"01110110" => -- JF1 addr
mnemonic_o <= MN_JF;
multi_cycle_o <= '1';
-- Mnemonic JMP ---------------------------------------------------------
when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr
"10000100" | "10100100" | "11000100" | "11100100" => --
mnemonic_o <= MN_JMP;
multi_cycle_o <= '1';
-- Mnemonic JMPP --------------------------------------------------------
when "10110011" => -- JMPP @ A
mnemonic_o <= MN_JMPP;
multi_cycle_o <= '1';
-- Mnemonic JNI ---------------------------------------------------------
when "10000110" => -- JNI addr
mnemonic_o <= MN_JNI;
multi_cycle_o <= '1';
-- Mnemonic JT ----------------------------------------------------------
when "00100110" | -- JNT0 addr
"01000110" | -- JNT1 addr
"00110110" | -- JT0 addr
"01010110" => -- JT1 addr
mnemonic_o <= MN_JT;
multi_cycle_o <= '1';
-- Mnemonic JTF ---------------------------------------------------------
when "00010110" => -- JTF addr
mnemonic_o <= MN_JTF;
multi_cycle_o <= '1';
-- Mnemonic JZ ----------------------------------------------------------
when "10010110" | -- JNZ addr
"11000110" => -- JZ addr
mnemonic_o <= MN_JZ;
multi_cycle_o <= '1';
-- Mnemonic MOV_A_DATA --------------------------------------------------
when "00100011" => -- MOV A, data
mnemonic_o <= MN_MOV_A_DATA;
multi_cycle_o <= '1';
-- Mnemonic MOV_A_PSW ---------------------------------------------------
when "11000111" => -- MOV A, PSW
mnemonic_o <= MN_MOV_A_PSW;
-- Mnemonic MOV_A_RR ----------------------------------------------------
when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr
"11111100" | "11111101" | "11111110" | "11111111" | --
"11110000" | "11110001" => -- MOV A, @ Rr
mnemonic_o <= MN_MOV_A_RR;
-- Mnemonic MOV_PSW_A ---------------------------------------------------
when "11010111" => -- MOV PSW, A
mnemonic_o <= MN_MOV_PSW_A;
-- Mnemonic MOV_RR ------------------------------------------------------
when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A
"10101100" | "10101101" | "10101110" | "10101111" | --
"10100000" | "10100001" => -- MOV @ Rr, A
mnemonic_o <= MN_MOV_RR;
-- Mnemonic MOV_RR_DATA -------------------------------------------------
when "10111000" | "10111001" | "10111010" | "10111011" | -- MOV Rr, data
"10111100" | "10111101" | "10111110" | "10111111" | --
"10110000" | "10110001" => -- MOV @ Rr, data
mnemonic_o <= MN_MOV_RR_DATA;
multi_cycle_o <= '1';
-- Mnemonic MOV_T -------------------------------------------------------
when "01100010" | -- MOV T, A
"01000010" => -- MOV A, T
mnemonic_o <= MN_MOV_T;
-- Mnemonic MOVD_A_PP ---------------------------------------------------
when "00001100" | "00001101" | "00001110" | "00001111" => -- MOVD A, Pp
mnemonic_o <= MN_MOVD_A_PP;
multi_cycle_o <= '1';
-- Mnemonic MOVP --------------------------------------------------------
when "10100011" | -- MOVP A, @ A
"11100011" => -- MOVP3 A, @ A
mnemonic_o <= MN_MOVP;
multi_cycle_o <= '1';
-- Mnemonic MOVX --------------------------------------------------------
when "10000000" | "10000001" | -- MOVX A, @ Rr
"10010000" | "10010001" => -- MOVX @ Rr, A
mnemonic_o <= MN_MOVX;
multi_cycle_o <= '1';
-- Mnemonic NOP ---------------------------------------------------------
when "00000000" => -- NOP
mnemonic_o <= MN_NOP;
-- Mnemonic ORL ---------------------------------------------------------
when "01001000" | "01001001" | "01001010" | "01001011" | -- ORL A, Rr
"01001100" | "01001101" | "01001110" | "01001111" | --
"01000000" | "01000001" => -- ORL A, @ Rr
mnemonic_o <= MN_ORL;
-- Mnemonic ORL_A_DATA --------------------------------------------------
when "01000011" => -- ORL A, data
mnemonic_o <= MN_ORL_A_DATA;
multi_cycle_o <= '1';
-- Mnemonic ORL_EXT -----------------------------------------------------
when "10001000" | -- ORL BUS, data
"10001001" | "10001010" => -- ORL Pp, data
mnemonic_o <= MN_ORL_EXT;
multi_cycle_o <= '1';
-- Mnemonic OUTD_PP_A ---------------------------------------------------
when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A
"10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A
"10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A
mnemonic_o <= MN_OUTD_PP_A;
multi_cycle_o <= '1';
-- Mnemonic OUTL_EXT ----------------------------------------------------
when "00111001" | "00111010" | -- OUTL Pp, A
"00000010" => -- OUTL BUS, A
mnemonic_o <= MN_OUTL_EXT;
multi_cycle_o <= '1';
-- Mnemonic RET ---------------------------------------------------------
when "10000011" | -- RET
"10010011" => -- RETR
mnemonic_o <= MN_RET;
multi_cycle_o <= '1';
-- Mnemonic RL ----------------------------------------------------------
when "11100111" | -- RL A
"11110111" => -- RLC A
mnemonic_o <= MN_RL;
-- Mnemonic RR ----------------------------------------------------------
when "01110111" | -- RR A
"01100111" => -- RRC A
mnemonic_o <= MN_RR;
-- Mnemonic SEL_MB ------------------------------------------------------
when "11100101" | -- SEL MB0
"11110101" => -- SEL MB1
mnemonic_o <= MN_SEL_MB;
-- Mnemonic SEL_RB ------------------------------------------------------
when "11000101" | -- SEL RB0
"11010101" => -- SEL RB1
mnemonic_o <= MN_SEL_RB;
-- Mnemonic STOP_TCNT ---------------------------------------------------
when "01100101" => -- STOP TCNT
mnemonic_o <= MN_STOP_TCNT;
-- Mnemonic START -------------------------------------------------------
when "01000101" | -- STRT CNT
"01010101" => -- STRT T
mnemonic_o <= MN_STRT;
-- Mnemonic SWAP --------------------------------------------------------
when "01000111" => -- SWAP A
mnemonic_o <= MN_SWAP;
-- Mnemonic XCH ---------------------------------------------------------
when "00101000" | "00101001" | "00101010" | "00101011" | -- XCH A, Rr
"00101100" | "00101101" | "00101110" | "00101111" | --
"00100000" | "00100001" | -- XCH A, @ Rr
"00110000" | "00110001" => -- XCHD A, @ Rr
mnemonic_o <= MN_XCH;
-- Mnemonic XRL ---------------------------------------------------------
when "11011000" | "11011001" | "11011010" | "11011011" | -- XRL A, Rr
"11011100" | "11011101" | "11011110" | "11011111" | --
"11010000" | "11010001" => -- XRL A, @ Rr
mnemonic_o <= MN_XRL;
-- Mnemonic XRL_A_DATA --------------------------------------------------
when "11010011" => -- XRL A, data
mnemonic_o <= MN_XRL_A_DATA;
multi_cycle_o <= '1';
when others =>
-- pragma translate_off
assert now = 0 ns
report "Unknown opcode."
severity warning;
-- pragma translate_on
end case;
end process opc_decode;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: opc_table.vhd,v $
-- Revision 1.3 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.2 2004/03/28 13:10:48 arniml
-- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Port 1 unit.
-- Implements the Port 1 logic.
--
-- $Id: p1.vhd,v 1.4 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity p1 is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
-- Port 1 Interface -------------------------------------------------------
p1_i : in word_t;
p1_o : out word_t;
p1_low_imp_o : out std_logic
);
end p1;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
architecture rtl of p1 is
-- the port output register
signal p1_q : word_t;
-- the low impedance marker
signal low_imp_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process p1_reg
--
-- Purpose:
-- Implements the port output register.
--
p1_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
p1_q <= (others => '1');
low_imp_q <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_p1_i then
p1_q <= data_i;
low_imp_q <= '1';
else
low_imp_q <= '0';
end if;
end if;
end if;
end process p1_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p1_data
--
-- Purpose:
-- Generates the T48 bus data.
--
p1_data: process (read_p1_i,
p1_i,
read_reg_i,
p1_q)
begin
data_o <= (others => bus_idle_level_c);
if read_p1_i then
if read_reg_i then
data_o <= p1_q;
else
data_o <= p1_i;
end if;
end if;
end process p1_data;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p1_o <= p1_q;
p1_low_imp_o <= low_imp_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: p1.vhd,v $
-- Revision 1.4 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.3 2004/05/17 14:37:53 arniml
-- reorder data_o generation
--
-- Revision 1.2 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2.vhd,v 1.6 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_pack.nibble_t;
entity p2 is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_p2_i : in boolean;
write_exp_i : in boolean;
read_p2_i : in boolean;
read_reg_i : in boolean;
read_exp_i : in boolean;
-- Port 2 Interface -------------------------------------------------------
output_pch_i : in boolean;
output_exp_i : in boolean;
pch_i : in nibble_t;
p2_i : in word_t;
p2_o : out word_t;
p2_low_imp_o : out std_logic
);
end p2;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
architecture rtl of p2 is
-- the port output register
signal p2_q : word_t;
-- the low impedance marker
signal low_imp_q : std_logic;
-- the expander register
signal exp_q : nibble_t;
begin
-----------------------------------------------------------------------------
-- Process p2_regs
--
-- Purpose:
-- Implements the port output and expander registers.
--
p2_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
p2_q <= (others => '1');
low_imp_q <= '0';
exp_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_p2_i then
p2_q <= data_i;
low_imp_q <= '1';
else
low_imp_q <= '0';
end if;
if write_exp_i then
exp_q <= data_i(exp_q'range);
end if;
end if;
end if;
end process p2_regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p2_port
--
-- Purpose:
-- Generates the output byte vector for Port 2.
--
p2_port: process (p2_q,
exp_q,
output_exp_i,
pch_i,
output_pch_i)
begin
p2_o <= p2_q;
if output_exp_i then
p2_o(nibble_t'range) <= exp_q;
end if;
if output_pch_i then
p2_o(nibble_t'range) <= pch_i;
end if;
end process p2_port;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p2_data
--
-- Purpose:
-- Generates the T48 bus data.
--
p2_data: process (read_p2_i,
p2_i,
read_reg_i,
p2_q,
read_exp_i)
begin
data_o <= (others => bus_idle_level_c);
if read_p2_i then
if read_reg_i then
data_o <= p2_q;
elsif read_exp_i then
data_o <= "0000" & p2_i(nibble_t'range);
else
data_o <= p2_i;
end if;
end if;
end process p2_data;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p2_low_imp_o <= low_imp_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: p2.vhd,v $
-- Revision 1.6 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.5 2004/05/17 13:52:46 arniml
-- Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"
--
-- Revision 1.4 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.3 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.2 2004/03/28 13:11:43 arniml
-- rework Port 2 expander handling
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Program Memory control unit.
-- All operations related to the Program Memory are managed here.
--
-- $Id: pmem_ctrl.vhd,v 1.3 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.word_t;
use work.pmem_ctrl_pack.pmem_addr_ident_t;
entity pmem_ctrl is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_pcl_i : in boolean;
read_pcl_i : in boolean;
write_pch_i : in boolean;
read_pch_i : in boolean;
inc_pc_i : in boolean;
write_pmem_addr_i : in boolean;
addr_type_i : in pmem_addr_ident_t;
read_pmem_i : in boolean;
-- Porgram Memroy Interface -----------------------------------------------
pmem_addr_o : out pmem_addr_t;
pmem_data_i : in word_t
);
end pmem_ctrl;
library ieee;
use ieee.numeric_std.all;
use work.pmem_ctrl_pack.all;
use work.t48_pack.res_active_c;
use work.t48_pack.clk_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.pmem_addr_width_c;
use work.t48_pack.dmem_addr_width_c;
use work.t48_pack.page_t;
architecture rtl of pmem_ctrl is
-- the Program Counter
signal program_counter_q : unsigned(pmem_addr_t'range);
-- the Program Memory address
signal pmem_addr_s,
pmem_addr_q : std_logic_vector(pmem_addr_t'range);
begin
-----------------------------------------------------------------------------
-- Process program_counter
--
-- Purpose:
-- Implements the Program Counter.
--
program_counter: process (res_i, clk_i)
begin
if res_i = res_active_c then
program_counter_q <= (others => '0');
pmem_addr_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- parallel load mode
if write_pcl_i then
program_counter_q(data_i'range) <= UNSIGNED(data_i);
elsif write_pch_i then
program_counter_q(pmem_addr_width_c-1 downto data_i'high+1) <=
UNSIGNED(data_i(pmem_addr_width_c - dmem_addr_width_c - 1 downto 0));
elsif inc_pc_i then
-- increment mode
program_counter_q <= program_counter_q + 1;
end if;
-- set pmem address
if write_pmem_addr_i then
pmem_addr_q <= pmem_addr_s;
end if;
end if;
end if;
end process program_counter;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process pmem_addr
--
-- Purpose:
-- Multiplex the Program Memory address.
--
pmem_addr: process (program_counter_q,
addr_type_i,
pmem_addr_q,
data_i)
begin
-- default assignment
pmem_addr_s <= STD_LOGIC_VECTOR(program_counter_q);
case addr_type_i is
when PM_PC =>
-- default is ok
null;
when PM_PAGE =>
pmem_addr_s(word_t'range) <= data_i;
-- take page address from program counter
-- => important for JMPP, MOVP!
-- they must wrap to next page when at FF!
when PM_PAGE3 =>
pmem_addr_s(word_t'range) <= data_i;
-- page address is explicitely specified
pmem_addr_s(page_t'range) <= "0011";
when others =>
null;
end case;
end process pmem_addr;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_output
--
-- Purpose:
-- Multiplex the data bus output.
--
data_output: process (read_pmem_i,
read_pcl_i,
read_pch_i,
pmem_data_i,
program_counter_q)
begin
data_o <= (others => bus_idle_level_c);
if read_pmem_i then
data_o <= pmem_data_i;
elsif read_pcl_i then
data_o <= STD_LOGIC_VECTOR(program_counter_q(data_o'range));
elsif read_pch_i then
data_o(3 downto 0) <= STD_LOGIC_VECTOR(program_counter_q(pmem_addr_width_c-1 downto data_o'high+1));
end if;
end process data_output;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
pmem_addr_o <= pmem_addr_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: pmem_ctrl.vhd,v $
-- Revision 1.3 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.2 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: pmem_ctrl_pack-p.vhd,v 1.1 2004/03/23 21:31:53 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
package pmem_ctrl_pack is
-----------------------------------------------------------------------------
-- Address Type Identifier
-----------------------------------------------------------------------------
type pmem_addr_ident_t is (PM_PC,
PM_PAGE,
PM_PAGE3);
end pmem_ctrl_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: pmem_ctrl_pack-p.vhd,v $
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Program Status Word (PSW).
-- Implements the PSW with its special bits.
--
-- $Id: psw.vhd,v 1.7 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity psw is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
read_psw_i : in boolean;
read_sp_i : in boolean;
write_psw_i : in boolean;
write_sp_i : in boolean;
-- Decoder Interface ------------------------------------------------------
special_data_i : in std_logic;
inc_stackp_i : in boolean;
dec_stackp_i : in boolean;
write_carry_i : in boolean;
write_aux_carry_i : in boolean;
write_f0_i : in boolean;
write_bs_i : in boolean;
carry_o : out std_logic;
aux_carry_i : in std_logic;
aux_carry_o : out std_logic;
f0_o : out std_logic;
bs_o : out std_logic
);
end psw;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.nibble_t;
architecture rtl of psw is
-- special bit positions in PSW
constant carry_c : natural := 3;
constant aux_carry_c : natural := 2;
constant f0_c : natural := 1;
constant bs_c : natural := 0;
-- the PSW register
signal psw_q : nibble_t;
-- the Stack Pointer
signal sp_q : unsigned(2 downto 0);
-- pragma translate_off
signal psw_s : word_t;
-- pragma translate_on
begin
-----------------------------------------------------------------------------
-- Process psw_reg
--
-- Purpose:
-- Implements the PSW register.
--
psw_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
psw_q <= (others => '0');
sp_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- T48 bus access
if write_psw_i then
psw_q <= data_i(7 downto 4);
end if;
if write_sp_i then
sp_q <= unsigned(data_i(2 downto 0));
end if;
-- increment Stack Pointer
if inc_stackp_i then
sp_q <= sp_q + 1;
end if;
-- decrement Stack Pointer
if dec_stackp_i then
sp_q <= sp_q - 1;
end if;
-- access to special bits
if write_carry_i then
psw_q(carry_c) <= special_data_i;
end if;
--
if write_aux_carry_i then
psw_q(aux_carry_c) <= aux_carry_i;
end if;
--
if write_f0_i then
psw_q(f0_c) <= special_data_i;
end if;
--
if write_bs_i then
psw_q(bs_c) <= special_data_i;
end if;
end if;
end if;
end process psw_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_out
--
-- Purpose:
-- Output multiplexer for T48 Data Bus.
--
data_out: process (read_psw_i,
read_sp_i,
psw_q,
sp_q)
begin
data_o <= (others => bus_idle_level_c);
if read_psw_i then
data_o(7 downto 4) <= psw_q;
end if;
if read_sp_i then
data_o(3 downto 0) <= '1' & std_logic_vector(sp_q);
end if;
end process data_out;
--
-----------------------------------------------------------------------------
-- pragma translate_off
tb: process (psw_q, sp_q)
begin
psw_s(7 downto 4) <= psw_q;
psw_s(3) <= '1';
psw_s(2 downto 0) <= std_logic_vector(sp_q);
end process tb;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output mapping.
-----------------------------------------------------------------------------
carry_o <= psw_q(carry_c);
aux_carry_o <= psw_q(aux_carry_c);
f0_o <= psw_q(f0_c);
bs_o <= psw_q(bs_c);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: psw.vhd,v $
-- Revision 1.7 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.6 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.5 2004/04/24 11:25:39 arniml
-- removed dummy_s - workaround not longer needed for GHDL 0.11.1
--
-- Revision 1.4 2004/04/18 18:59:01 arniml
-- add temporary workaround for GHDL 0.11
--
-- Revision 1.3 2004/04/04 14:15:45 arniml
-- add dump_compare support
--
-- Revision 1.2 2004/03/28 21:28:13 arniml
-- take auxiliary carry from direct ALU connection
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- A synchronous parametrizable RAM.
--
-- $Id: syn_ram-e.vhd,v 1.1 2004/03/24 21:32:27 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity syn_ram is
generic (
address_width_g : positive := 8
);
port (
clk_i : in std_logic;
res_i : in std_logic;
ram_addr_i : in std_logic_vector(address_width_g-1 downto 0);
ram_data_i : in std_logic_vector(7 downto 0);
ram_we_i : in std_logic;
ram_data_o : out std_logic_vector(7 downto 0)
);
end syn_ram;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: syn_ram-e.vhd,v $
-- Revision 1.1 2004/03/24 21:32:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: t48_comp_pack-p.vhd,v 1.7 2004/06/30 21:16:21 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.alu_pack.alu_op_t;
use work.cond_branch_pack.branch_conditions_t;
use work.cond_branch_pack.comp_value_t;
use work.decoder_pack.mnemonic_t;
use work.dmem_ctrl_pack.dmem_addr_ident_t;
use work.pmem_ctrl_pack.pmem_addr_ident_t;
use work.t48_pack.dmem_addr_t;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.mstate_t;
use work.t48_pack.word_t;
use work.t48_pack.nibble_t;
package t48_comp_pack is
component alu
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_accu_i : in boolean;
write_shadow_i : in boolean;
write_temp_reg_i : in boolean;
read_alu_i : in boolean;
carry_i : in std_logic;
carry_o : out std_logic;
aux_carry_o : out std_logic;
alu_op_i : in alu_op_t;
use_carry_i : in boolean;
da_high_i : in boolean;
da_overflow_o : out boolean;
accu_low_i : in boolean;
p06_temp_reg_i : in boolean;
p60_temp_reg_i : in boolean
);
end component;
component bus_mux
port (
alu_data_i : in word_t;
bus_data_i : in word_t;
dec_data_i : in word_t;
dm_data_i : in word_t;
pm_data_i : in word_t;
p1_data_i : in word_t;
p2_data_i : in word_t;
psw_data_i : in word_t;
tim_data_i : in word_t;
data_o : out word_t
);
end component;
component clock_ctrl
generic (
xtal_div_3_g : integer := 1
);
port (
clk_i : in std_logic;
xtal_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal3_o : out boolean;
multi_cycle_i : in boolean;
assert_psen_i : in boolean;
assert_prog_i : in boolean;
assert_rd_i : in boolean;
assert_wr_i : in boolean;
mstate_o : out mstate_t;
second_cycle_o : out boolean;
ale_o : out boolean;
psen_o : out boolean;
prog_o : out boolean;
rd_o : out boolean;
wr_o : out boolean
);
end component;
component cond_branch
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
compute_take_i : in boolean;
branch_cond_i : in branch_conditions_t;
take_branch_o : out boolean;
accu_i : in word_t;
t0_i : in std_logic;
t1_i : in std_logic;
int_n_i : in std_logic;
f0_i : in std_logic;
f1_i : in std_logic;
tf_i : in std_logic;
carry_i : in std_logic;
comp_value_i : in comp_value_t
);
end component;
component db_bus
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
ea_i : in std_logic;
data_i : in word_t;
data_o : out word_t;
write_bus_i : in boolean;
read_bus_i : in boolean;
output_pcl_i : in boolean;
bidir_bus_i : in boolean;
pcl_i : in word_t;
db_i : in word_t;
db_o : out word_t;
db_dir_o : out std_logic
);
end component;
component decoder
generic (
register_mnemonic_g : integer := 1
);
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
ea_i : in std_logic;
ale_i : in boolean;
int_n_i : in std_logic;
t0_dir_o : out std_logic;
data_i : in word_t;
data_o : out word_t;
alu_write_accu_o : out boolean;
alu_write_shadow_o : out boolean;
alu_write_temp_reg_o : out boolean;
alu_read_alu_o : out boolean;
bus_write_bus_o : out boolean;
bus_read_bus_o : out boolean;
dm_write_dmem_addr_o : out boolean;
dm_write_dmem_o : out boolean;
dm_read_dmem_o : out boolean;
p1_write_p1_o : out boolean;
p1_read_p1_o : out boolean;
p2_write_p2_o : out boolean;
p2_write_exp_o : out boolean;
p2_read_p2_o : out boolean;
pm_write_pcl_o : out boolean;
pm_read_pcl_o : out boolean;
pm_write_pch_o : out boolean;
pm_read_pch_o : out boolean;
pm_read_pmem_o : out boolean;
psw_read_psw_o : out boolean;
psw_read_sp_o : out boolean;
psw_write_psw_o : out boolean;
psw_write_sp_o : out boolean;
alu_carry_i : in std_logic;
alu_op_o : out alu_op_t;
alu_da_high_o : out boolean;
alu_accu_low_o : out boolean;
alu_da_overflow_i : in boolean;
alu_p06_temp_reg_o : out boolean;
alu_p60_temp_reg_o : out boolean;
alu_use_carry_o : out boolean;
bus_output_pcl_o : out boolean;
bus_bidir_bus_o : out boolean;
clk_multi_cycle_o : out boolean;
clk_assert_psen_o : out boolean;
clk_assert_prog_o : out boolean;
clk_assert_rd_o : out boolean;
clk_assert_wr_o : out boolean;
clk_mstate_i : in mstate_t;
clk_second_cycle_i : in boolean;
cnd_compute_take_o : out boolean;
cnd_branch_cond_o : out branch_conditions_t;
cnd_take_branch_i : in boolean;
cnd_comp_value_o : out comp_value_t;
cnd_f1_o : out std_logic;
cnd_tf_o : out std_logic;
dm_addr_type_o : out dmem_addr_ident_t;
tim_read_timer_o : out boolean;
tim_write_timer_o : out boolean;
tim_start_t_o : out boolean;
tim_start_cnt_o : out boolean;
tim_stop_tcnt_o : out boolean;
p1_read_reg_o : out boolean;
p2_read_reg_o : out boolean;
p2_read_exp_o : out boolean;
p2_output_pch_o : out boolean;
p2_output_exp_o : out boolean;
pm_inc_pc_o : out boolean;
pm_write_pmem_addr_o : out boolean;
pm_addr_type_o : out pmem_addr_ident_t;
psw_special_data_o : out std_logic;
psw_carry_i : in std_logic;
psw_aux_carry_i : in std_logic;
psw_f0_i : in std_logic;
psw_inc_stackp_o : out boolean;
psw_dec_stackp_o : out boolean;
psw_write_carry_o : out boolean;
psw_write_aux_carry_o : out boolean;
psw_write_f0_o : out boolean;
psw_write_bs_o : out boolean;
tim_overflow_i : in boolean
);
end component;
component dmem_ctrl
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
write_dmem_addr_i : in boolean;
write_dmem_i : in boolean;
read_dmem_i : in boolean;
addr_type_i : in dmem_addr_ident_t;
bank_select_i : in std_logic;
data_o : out word_t;
dmem_data_i : in word_t;
dmem_addr_o : out dmem_addr_t;
dmem_we_o : out std_logic;
dmem_data_o : out word_t
);
end component;
component int
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
clk_mstate_i : in mstate_t;
jtf_executed_i : in boolean;
tim_overflow_i : in boolean;
tf_o : out std_logic;
en_tcnti_i : in boolean;
dis_tcnti_i : in boolean;
int_n_i : in std_logic;
ale_i : in boolean;
last_cycle_i : in boolean;
en_i_i : in boolean;
dis_i_i : in boolean;
ext_int_o : out boolean;
tim_int_o : out boolean;
retr_executed_i : in boolean;
int_executed_i : in boolean;
int_pending_o : out boolean;
int_in_progress_o : out boolean
);
end component;
component opc_table
port (
opcode_i : in word_t;
multi_cycle_o : out std_logic;
mnemonic_o : out mnemonic_t
);
end component;
component opc_decoder
generic (
register_mnemonic_g : integer := 1
);
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
read_bus_i : in boolean;
inj_int_i : in boolean;
opcode_o : out word_t;
mnemonic_o : out mnemonic_t;
multi_cycle_o : out boolean
);
end component;
component timer
generic (
sample_t1_state_g : integer := 4
);
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
t1_i : in std_logic;
clk_mstate_i : in mstate_t;
data_i : in word_t;
data_o : out word_t;
read_timer_i : in boolean;
write_timer_i : in boolean;
start_t_i : in boolean;
start_cnt_i : in boolean;
stop_tcnt_i : in boolean;
overflow_o : out std_logic
);
end component;
component p1
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
p1_i : in word_t;
p1_o : out word_t;
p1_low_imp_o : out std_logic
);
end component;
component p2
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_p2_i : in boolean;
write_exp_i : in boolean;
read_p2_i : in boolean;
read_reg_i : in boolean;
read_exp_i : in boolean;
output_pch_i : in boolean;
output_exp_i : in boolean;
pch_i : in nibble_t;
p2_i : in word_t;
p2_o : out word_t;
p2_low_imp_o : out std_logic
);
end component;
component pmem_ctrl
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_pcl_i : in boolean;
read_pcl_i : in boolean;
write_pch_i : in boolean;
read_pch_i : in boolean;
inc_pc_i : in boolean;
write_pmem_addr_i : in boolean;
addr_type_i : in pmem_addr_ident_t;
read_pmem_i : in boolean;
pmem_addr_o : out pmem_addr_t;
pmem_data_i : in word_t
);
end component;
component psw
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
read_psw_i : in boolean;
read_sp_i : in boolean;
write_psw_i : in boolean;
write_sp_i : in boolean;
special_data_i : in std_logic;
inc_stackp_i : in boolean;
dec_stackp_i : in boolean;
write_carry_i : in boolean;
write_aux_carry_i : in boolean;
write_f0_i : in boolean;
write_bs_i : in boolean;
carry_o : out std_logic;
aux_carry_i : in std_logic;
aux_carry_o : out std_logic;
f0_o : out std_logic;
bs_o : out std_logic
);
end component;
end t48_comp_pack;

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-------------------------------------------------------------------------------
--
-- T48 Microcontroller Core
--
-- $Id: t48_core.vhd,v 1.7 2004/05/01 11:58:04 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-- Limitations :
-- =============
--
-- Compared to the original MCS-48 architecture, the following limitations
-- apply:
--
-- * Nibble-wide instructions addressing expander port implemented but
-- not verified in detail.
--
-- * Single-step mode not implemented.
-- Not selected for future implementation.
--
-- * Reading of internal Program Memory not implemented.
-- Not selected for future implementation.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t48_core is
generic (
-- divide XTAL1 by 3 to derive Clock States
xtal_div_3_g : integer := 1;
-- store mnemonic in flip-flops (registered-out)
register_mnemonic_g : integer := 1;
-- include the port 1 module
include_port1_g : integer := 1;
-- include the port 2 module
include_port2_g : integer := 1;
-- include the BUS module
include_bus_g : integer := 1;
-- include the timer module
include_timer_g : integer := 1;
-- state in which T1 is sampled (3 or 4)
sample_t1_state_g : integer := 4
);
port (
-- T48 Interface ----------------------------------------------------------
xtal_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
-- Core Interface ---------------------------------------------------------
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
end t48_core;
use work.alu_pack.alu_op_t;
use work.cond_branch_pack.branch_conditions_t;
use work.cond_branch_pack.comp_value_t;
use work.dmem_ctrl_pack.dmem_addr_ident_t;
use work.pmem_ctrl_pack.pmem_addr_ident_t;
use work.t48_comp_pack.all;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.word_t;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.mstate_t;
use work.t48_pack.to_stdLogic;
use work.t48_pack.to_boolean;
architecture struct of t48_core is
signal t48_data_s : word_t;
signal en_clk_s : boolean;
-- ALU signals
signal alu_data_s : word_t;
signal alu_write_accu_s : boolean;
signal alu_write_shadow_s : boolean;
signal alu_write_temp_reg_s : boolean;
signal alu_read_alu_s : boolean;
signal alu_carry_s : std_logic;
signal alu_aux_carry_s : std_logic;
signal alu_op_s : alu_op_t;
signal alu_use_carry_s : boolean;
signal alu_da_high_s : boolean;
signal alu_da_overflow_s : boolean;
signal alu_accu_low_s : boolean;
signal alu_p06_temp_reg_s : boolean;
signal alu_p60_temp_reg_s : boolean;
-- BUS signals
signal bus_write_bus_s : boolean;
signal bus_read_bus_s : boolean;
signal bus_output_pcl_s : boolean;
signal bus_bidir_bus_s : boolean;
signal bus_data_s : word_t;
-- Clock Controller signals
signal clk_multi_cycle_s : boolean;
signal clk_assert_psen_s : boolean;
signal clk_assert_prog_s : boolean;
signal clk_assert_rd_s : boolean;
signal clk_assert_wr_s : boolean;
signal clk_mstate_s : mstate_t;
signal clk_second_cycle_s : boolean;
signal psen_s : boolean;
signal prog_s : boolean;
signal rd_s : boolean;
signal wr_s : boolean;
signal ale_s : boolean;
signal xtal3_s : boolean;
-- Conditional Branch Logic signals
signal cnd_compute_take_s : boolean;
signal cnd_branch_cond_s : branch_conditions_t;
signal cnd_take_branch_s : boolean;
signal cnd_comp_value_s : comp_value_t;
signal cnd_f1_s : std_logic;
signal cnd_tf_s : std_logic;
-- Data Memory Controller signals
signal dm_write_dmem_addr_s : boolean;
signal dm_write_dmem_s : boolean;
signal dm_read_dmem_s : boolean;
signal dm_addr_type_s : dmem_addr_ident_t;
signal dm_data_s : word_t;
-- Decoder signals
signal dec_data_s : word_t;
-- Port 1 signals
signal p1_write_p1_s : boolean;
signal p1_read_p1_s : boolean;
signal p1_read_reg_s : boolean;
signal p1_data_s : word_t;
-- Port 2 signals
signal p2_write_p2_s : boolean;
signal p2_write_exp_s : boolean;
signal p2_read_p2_s : boolean;
signal p2_read_reg_s : boolean;
signal p2_read_exp_s : boolean;
signal p2_output_pch_s : boolean;
signal p2_output_exp_s : boolean;
signal p2_data_s : word_t;
-- Program Memory Controller signals
signal pm_write_pcl_s : boolean;
signal pm_read_pcl_s : boolean;
signal pm_write_pch_s : boolean;
signal pm_read_pch_s : boolean;
signal pm_read_pmem_s : boolean;
signal pm_inc_pc_s : boolean;
signal pm_write_pmem_addr_s : boolean;
signal pm_data_s : word_t;
signal pm_addr_type_s : pmem_addr_ident_t;
signal pmem_addr_s : pmem_addr_t;
-- PSW signals
signal psw_read_psw_s : boolean;
signal psw_read_sp_s : boolean;
signal psw_write_psw_s : boolean;
signal psw_write_sp_s : boolean;
signal psw_carry_s : std_logic;
signal psw_aux_carry_s : std_logic;
signal psw_f0_s : std_logic;
signal psw_bs_s : std_logic;
signal psw_special_data_s : std_logic;
signal psw_inc_stackp_s : boolean;
signal psw_dec_stackp_s : boolean;
signal psw_write_carry_s : boolean;
signal psw_write_aux_carry_s : boolean;
signal psw_write_f0_s : boolean;
signal psw_write_bs_s : boolean;
signal psw_data_s : word_t;
-- Timer signals
signal tim_overflow_s : boolean;
signal tim_of_s : std_logic;
signal tim_read_timer_s : boolean;
signal tim_write_timer_s : boolean;
signal tim_start_t_s : boolean;
signal tim_start_cnt_s : boolean;
signal tim_stop_tcnt_s : boolean;
signal tim_data_s : word_t;
begin
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert include_timer_g = 0 or include_timer_g = 1
report "include_timer_g must be either 1 or 0!"
severity failure;
assert include_port1_g = 0 or include_port1_g = 1
report "include_port1_g must be either 1 or 0!"
severity failure;
assert include_port2_g = 0 or include_port2_g = 1
report "include_port2_g must be either 1 or 0!"
severity failure;
assert include_bus_g = 0 or include_bus_g = 1
report "include_bus_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
en_clk_s <= to_boolean(en_clk_i);
alu_b : alu
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => alu_data_s,
write_accu_i => alu_write_accu_s,
write_shadow_i => alu_write_shadow_s,
write_temp_reg_i => alu_write_temp_reg_s,
read_alu_i => alu_read_alu_s,
carry_i => psw_carry_s,
carry_o => alu_carry_s,
aux_carry_o => alu_aux_carry_s,
alu_op_i => alu_op_s,
use_carry_i => alu_use_carry_s,
da_high_i => alu_da_high_s,
da_overflow_o => alu_da_overflow_s,
accu_low_i => alu_accu_low_s,
p06_temp_reg_i => alu_p06_temp_reg_s,
p60_temp_reg_i => alu_p60_temp_reg_s
);
bus_mux_b : bus_mux
port map (
alu_data_i => alu_data_s,
bus_data_i => bus_data_s,
dec_data_i => dec_data_s,
dm_data_i => dm_data_s,
pm_data_i => pm_data_s,
p1_data_i => p1_data_s,
p2_data_i => p2_data_s,
psw_data_i => psw_data_s,
tim_data_i => tim_data_s,
data_o => t48_data_s
);
clock_ctrl_b : clock_ctrl
generic map (
xtal_div_3_g => xtal_div_3_g
)
port map (
clk_i => clk_i,
xtal_i => xtal_i,
res_i => reset_i,
en_clk_i => en_clk_s,
xtal3_o => xtal3_s,
multi_cycle_i => clk_multi_cycle_s,
assert_psen_i => clk_assert_psen_s,
assert_prog_i => clk_assert_prog_s,
assert_rd_i => clk_assert_rd_s,
assert_wr_i => clk_assert_wr_s,
mstate_o => clk_mstate_s,
second_cycle_o => clk_second_cycle_s,
ale_o => ale_s,
psen_o => psen_s,
prog_o => prog_s,
rd_o => rd_s,
wr_o => wr_s
);
cond_branch_b : cond_branch
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
compute_take_i => cnd_compute_take_s,
branch_cond_i => cnd_branch_cond_s,
take_branch_o => cnd_take_branch_s,
accu_i => alu_data_s,
t0_i => To_X01Z(t0_i),
t1_i => To_X01Z(t1_i),
int_n_i => int_n_i,
f0_i => psw_f0_s,
f1_i => cnd_f1_s,
tf_i => cnd_tf_s,
carry_i => psw_carry_s,
comp_value_i => cnd_comp_value_s
);
use_db_bus: if include_bus_g = 1 generate
db_bus_b : db_bus
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
ea_i => ea_i,
data_i => t48_data_s,
data_o => bus_data_s,
write_bus_i => bus_write_bus_s,
read_bus_i => bus_read_bus_s,
output_pcl_i => bus_output_pcl_s,
bidir_bus_i => bus_bidir_bus_s,
pcl_i => pmem_addr_s(word_t'range),
db_i => db_i,
db_o => db_o,
db_dir_o => db_dir_o
);
end generate;
skip_db_bus: if include_bus_g = 0 generate
bus_data_s <= (others => bus_idle_level_c);
db_o <= (others => '0');
db_dir_o <= '0';
end generate;
decoder_b : decoder
generic map (
register_mnemonic_g => register_mnemonic_g
)
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
ea_i => ea_i,
ale_i => ale_s,
int_n_i => int_n_i,
t0_dir_o => t0_dir_o,
data_i => t48_data_s,
data_o => dec_data_s,
alu_write_accu_o => alu_write_accu_s,
alu_write_shadow_o => alu_write_shadow_s,
alu_write_temp_reg_o => alu_write_temp_reg_s,
alu_read_alu_o => alu_read_alu_s,
bus_write_bus_o => bus_write_bus_s,
bus_read_bus_o => bus_read_bus_s,
dm_write_dmem_addr_o => dm_write_dmem_addr_s,
dm_write_dmem_o => dm_write_dmem_s,
dm_read_dmem_o => dm_read_dmem_s,
p1_write_p1_o => p1_write_p1_s,
p1_read_p1_o => p1_read_p1_s,
pm_write_pcl_o => pm_write_pcl_s,
p2_write_p2_o => p2_write_p2_s,
p2_write_exp_o => p2_write_exp_s,
p2_read_p2_o => p2_read_p2_s,
pm_read_pcl_o => pm_read_pcl_s,
pm_write_pch_o => pm_write_pch_s,
pm_read_pch_o => pm_read_pch_s,
pm_read_pmem_o => pm_read_pmem_s,
psw_read_psw_o => psw_read_psw_s,
psw_read_sp_o => psw_read_sp_s,
psw_write_psw_o => psw_write_psw_s,
psw_write_sp_o => psw_write_sp_s,
alu_carry_i => alu_carry_s,
alu_op_o => alu_op_s,
alu_use_carry_o => alu_use_carry_s,
alu_da_high_o => alu_da_high_s,
alu_da_overflow_i => alu_da_overflow_s,
alu_accu_low_o => alu_accu_low_s,
alu_p06_temp_reg_o => alu_p06_temp_reg_s,
alu_p60_temp_reg_o => alu_p60_temp_reg_s,
bus_output_pcl_o => bus_output_pcl_s,
bus_bidir_bus_o => bus_bidir_bus_s,
clk_multi_cycle_o => clk_multi_cycle_s,
clk_assert_psen_o => clk_assert_psen_s,
clk_assert_prog_o => clk_assert_prog_s,
clk_assert_rd_o => clk_assert_rd_s,
clk_assert_wr_o => clk_assert_wr_s,
clk_mstate_i => clk_mstate_s,
clk_second_cycle_i => clk_second_cycle_s,
cnd_compute_take_o => cnd_compute_take_s,
cnd_branch_cond_o => cnd_branch_cond_s,
cnd_take_branch_i => cnd_take_branch_s,
cnd_comp_value_o => cnd_comp_value_s,
cnd_f1_o => cnd_f1_s,
cnd_tf_o => cnd_tf_s,
dm_addr_type_o => dm_addr_type_s,
tim_read_timer_o => tim_read_timer_s,
tim_write_timer_o => tim_write_timer_s,
tim_start_t_o => tim_start_t_s,
tim_start_cnt_o => tim_start_cnt_s,
tim_stop_tcnt_o => tim_stop_tcnt_s,
p1_read_reg_o => p1_read_reg_s,
p2_read_reg_o => p2_read_reg_s,
p2_read_exp_o => p2_read_exp_s,
p2_output_pch_o => p2_output_pch_s,
p2_output_exp_o => p2_output_exp_s,
pm_inc_pc_o => pm_inc_pc_s,
pm_write_pmem_addr_o => pm_write_pmem_addr_s,
pm_addr_type_o => pm_addr_type_s,
psw_special_data_o => psw_special_data_s,
psw_carry_i => psw_carry_s,
psw_aux_carry_i => psw_aux_carry_s,
psw_f0_i => psw_f0_s,
psw_inc_stackp_o => psw_inc_stackp_s,
psw_dec_stackp_o => psw_dec_stackp_s,
psw_write_carry_o => psw_write_carry_s,
psw_write_aux_carry_o => psw_write_aux_carry_s,
psw_write_f0_o => psw_write_f0_s,
psw_write_bs_o => psw_write_bs_s,
tim_overflow_i => tim_overflow_s
);
dmem_ctrl_b : dmem_ctrl
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
write_dmem_addr_i => dm_write_dmem_addr_s,
write_dmem_i => dm_write_dmem_s,
read_dmem_i => dm_read_dmem_s,
addr_type_i => dm_addr_type_s,
bank_select_i => psw_bs_s,
data_o => dm_data_s,
dmem_data_i => dmem_data_i,
dmem_addr_o => dmem_addr_o,
dmem_we_o => dmem_we_o,
dmem_data_o => dmem_data_o
);
use_timer: if include_timer_g = 1 generate
timer_b : timer
generic map (
sample_t1_state_g => sample_t1_state_g
)
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
t1_i => To_X01Z(t1_i),
clk_mstate_i => clk_mstate_s,
data_i => t48_data_s,
data_o => tim_data_s,
read_timer_i => tim_read_timer_s,
write_timer_i => tim_write_timer_s,
start_t_i => tim_start_t_s,
start_cnt_i => tim_start_cnt_s,
stop_tcnt_i => tim_stop_tcnt_s,
overflow_o => tim_of_s
);
end generate;
skip_timer: if include_timer_g = 0 generate
tim_data_s <= (others => bus_idle_level_c);
tim_of_s <= '0';
end generate;
tim_overflow_s <= to_boolean(tim_of_s);
use_p1: if include_port1_g = 1 generate
p1_b : p1
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => p1_data_s,
write_p1_i => p1_write_p1_s,
read_p1_i => p1_read_p1_s,
read_reg_i => p1_read_reg_s,
p1_i => p1_i,
p1_o => p1_o,
p1_low_imp_o => p1_low_imp_o
);
end generate;
skip_p1: if include_port1_g = 0 generate
p1_data_s <= (others => bus_idle_level_c);
p1_o <= (others => '0');
p1_low_imp_o <= '0';
end generate;
use_p2: if include_port2_g = 1 generate
p2_b : p2
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => p2_data_s,
write_p2_i => p2_write_p2_s,
write_exp_i => p2_write_exp_s,
read_p2_i => p2_read_p2_s,
read_reg_i => p2_read_reg_s,
read_exp_i => p2_read_exp_s,
output_pch_i => p2_output_pch_s,
output_exp_i => p2_output_exp_s,
pch_i => pmem_addr_s(11 downto 8),
p2_i => p2_i,
p2_o => p2_o,
p2_low_imp_o => p2_low_imp_o
);
end generate;
skip_p2: if include_port2_g = 0 generate
p2_data_s <= (others => bus_idle_level_c);
p2_o <= (others => '0');
p2_low_imp_o <= '0';
end generate;
pmem_ctrl_b : pmem_ctrl
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => pm_data_s,
write_pcl_i => pm_write_pcl_s,
read_pcl_i => pm_read_pcl_s,
write_pch_i => pm_write_pch_s,
read_pch_i => pm_read_pch_s,
inc_pc_i => pm_inc_pc_s,
write_pmem_addr_i => pm_write_pmem_addr_s,
addr_type_i => pm_addr_type_s,
read_pmem_i => pm_read_pmem_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_i
);
psw_b : psw
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => psw_data_s,
read_psw_i => psw_read_psw_s,
read_sp_i => psw_read_sp_s,
write_psw_i => psw_write_psw_s,
write_sp_i => psw_write_sp_s,
special_data_i => psw_special_data_s,
inc_stackp_i => psw_inc_stackp_s,
dec_stackp_i => psw_dec_stackp_s,
write_carry_i => psw_write_carry_s,
write_aux_carry_i => psw_write_aux_carry_s,
write_f0_i => psw_write_f0_s,
write_bs_i => psw_write_bs_s,
carry_o => psw_carry_s,
aux_carry_i => alu_aux_carry_s,
aux_carry_o => psw_aux_carry_s,
f0_o => psw_f0_s,
bs_o => psw_bs_s
);
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
ale_o <= to_stdLogic(ale_s);
t0_o <= clk_i;
psen_n_o <= to_stdLogic(not psen_s);
prog_n_o <= to_stdLogic(not prog_s);
rd_n_o <= to_stdLogic(not rd_s);
wr_n_o <= to_stdLogic(not wr_s);
xtal3_o <= to_stdLogic(xtal3_s);
pmem_addr_o <= pmem_addr_s;
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t48_core.vhd,v $
-- Revision 1.7 2004/05/01 11:58:04 arniml
-- update notice about expander port instructions
--
-- Revision 1.6 2004/04/07 22:09:03 arniml
-- remove unused signals
--
-- Revision 1.5 2004/04/04 14:18:53 arniml
-- add measures to implement XCHD
--
-- Revision 1.4 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.3 2004/03/28 21:27:50 arniml
-- update wiring for DA support
--
-- Revision 1.2 2004/03/28 13:13:20 arniml
-- connect control signal for Port 2 expander
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: t48_core_comp_pack-p.vhd,v 1.2 2004/03/29 19:39:58 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t48_core_comp_pack is
component t48_core
generic (
xtal_div_3_g : integer := 1;
register_mnemonic_g : integer := 1;
include_port1_g : integer := 1;
include_port2_g : integer := 1;
include_bus_g : integer := 1;
include_timer_g : integer := 1;
sample_t1_state_g : integer := 4
);
port (
xtal_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
end component;
component syn_rom
generic (
address_width_g : positive := 10
);
port (
clk_i : in std_logic;
rom_addr_i : in std_logic_vector(address_width_g-1 downto 0);
rom_data_o : out std_logic_vector(7 downto 0)
);
end component;
component syn_ram
generic (
address_width_g : positive := 8
);
port (
clk_i : in std_logic;
res_i : in std_logic;
ram_addr_i : in std_logic_vector(address_width_g-1 downto 0);
ram_data_i : in std_logic_vector(7 downto 0);
ram_we_i : in std_logic;
ram_data_o : out std_logic_vector(7 downto 0)
);
end component;
end t48_core_comp_pack;

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-------------------------------------------------------------------------------
--
-- $Id: t48_pack-p.vhd,v 1.1 2004/03/23 21:31:53 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t48_pack is
-----------------------------------------------------------------------------
-- Global constants
-----------------------------------------------------------------------------
-- clock active level
constant clk_active_c : std_logic := '1';
-- reset active level
constant res_active_c : std_logic := '0';
-- idle level on internal data bus
constant bus_idle_level_c : std_logic := '1';
-- global data word width
constant word_width_c : natural := 8;
-- data memory address width
constant dmem_addr_width_c : natural := 8;
-- program memory address width
constant pmem_addr_width_c : natural := 12;
-----------------------------------------------------------------------------
-- Global data types
-----------------------------------------------------------------------------
-- the global data word width type
subtype word_t is std_logic_vector(word_width_c-1 downto 0);
subtype nibble_t is std_logic_vector(word_width_c/2-1 downto 0);
-- the global data memory address type
subtype dmem_addr_t is std_logic_vector(dmem_addr_width_c-1 downto 0);
-- the global program memory address type
subtype pmem_addr_t is std_logic_vector(pmem_addr_width_c-1 downto 0);
subtype page_t is std_logic_vector(pmem_addr_width_c-1 downto word_width_c);
-- the machine states
type mstate_t is (MSTATE1, MSTATE2, MSTATE3, MSTATE4, MSTATE5);
-----------------------------------------------------------------------------
-- Global functions
-----------------------------------------------------------------------------
function to_stdLogic(input: boolean) return std_logic;
function to_boolean(input: std_logic) return boolean;
end t48_pack;
package body t48_pack is
function to_stdLogic(input: boolean) return std_logic is
begin
if input then
return '1';
else
return '0';
end if;
end to_stdLogic;
function to_boolean(input: std_logic) return boolean is
begin
if input = '1' then
return true;
else
return false;
end if;
end to_boolean;
end t48_pack;

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-------------------------------------------------------------------------------
--
-- The Timer/Counter unit.
--
-- $Id: timer.vhd,v 1.5 2004/07/11 16:51:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_pack.mstate_t;
entity timer is
generic (
-- state in which T1 is sampled (3 or 4)
sample_t1_state_g : integer := 4
);
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
t1_i : in std_logic;
clk_mstate_i : in mstate_t;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
read_timer_i : in boolean;
write_timer_i : in boolean;
-- Decoder Interface ------------------------------------------------------
start_t_i : in boolean;
start_cnt_i : in boolean;
stop_tcnt_i : in boolean;
overflow_o : out std_logic
);
end timer;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.all;
architecture rtl of timer is
-- the 8 bit counter core
signal counter_q : unsigned(word_t'range);
signal overflow_q : boolean;
-- increment signal for the counter core
type inc_type_t is (NONE, TIMER, COUNTER);
signal increment_s : boolean;
signal inc_sel_q : inc_type_t;
-- T1 edge detector
signal t1_q : std_logic;
signal t1_inc_s : boolean;
-- timer prescaler
signal prescaler_q : unsigned(4 downto 0);
signal pre_inc_s : boolean;
begin
-----------------------------------------------------------------------------
-- Verify the generics
-----------------------------------------------------------------------------
-- pragma translate_off
assert (sample_t1_state_g = 3) or (sample_t1_state_g = 4)
report "sample_t1_state_g must be either 3 or 4!"
severity failure;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Process t1_edge
--
-- Purpose:
-- Implements the edge detector for T1.
--
t1_edge: process (t1_i,
t1_q,
clk_mstate_i)
begin
t1_inc_s <= false;
-- sample in state according to generic
-- Old devices: sample at the beginning of state 3
-- New devices: sample in state 4
if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or
(sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then
-- detect falling edge
if t1_q = '1' and t1_i = '0' then
t1_inc_s <= true;
end if;
end if;
end process t1_edge;
--
-----------------------------------------------------------------------------
pre_inc_s <= clk_mstate_i = MSTATE4 and prescaler_q = 31;
-----------------------------------------------------------------------------
-- Process inc_sel
--
-- Purpose:
-- Select increment source (timer, counter or none).
--
inc_sel: process (inc_sel_q,
pre_inc_s,
t1_inc_s)
begin
-- default assignment
increment_s <= false;
case inc_sel_q is
when NONE =>
increment_s <= false;
when TIMER =>
increment_s <= pre_inc_s;
when COUNTER =>
increment_s <= t1_inc_s;
when others =>
null;
end case;
end process inc_sel;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implements the counter, the prescaler and other registers.
--
regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
overflow_q <= false;
t1_q <= '0';
prescaler_q <= (others => '0');
inc_sel_q <= NONE;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- Counter Core and overflow ------------------------------------------
overflow_q <= false;
if write_timer_i then
counter_q <= unsigned(data_i);
elsif increment_s then
counter_q <= counter_q + 1;
if counter_q = 255 then
overflow_q <= true;
end if;
end if;
-- T1 edge detector ---------------------------------------------------
if (sample_t1_state_g = 3 and clk_mstate_i = MSTATE3) or
(sample_t1_state_g = 4 and clk_mstate_i = MSTATE4) then
t1_q <= t1_i;
end if;
-- Prescaler ----------------------------------------------------------
if start_t_i then
prescaler_q <= (others => '0');
elsif clk_mstate_i = MSTATE3 then
prescaler_q <= prescaler_q + 1;
end if;
-- Increment Selector -------------------------------------------------
if start_t_i then
inc_sel_q <= TIMER;
elsif start_cnt_i then
inc_sel_q <= COUNTER;
elsif stop_tcnt_i then
inc_sel_q <= NONE;
end if;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
data_o <= std_logic_vector(counter_q)
when read_timer_i else
(others => bus_idle_level_c);
overflow_o <= to_stdLogic(overflow_q);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: timer.vhd,v $
-- Revision 1.5 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.4 2004/07/04 13:06:45 arniml
-- counter_q is not cleared during reset
-- this would match all different descriptions of the Counter as
-- a) if the software assumes that the Counter is modified during reset, it
-- will initialize the Counter anyhow
-- b) the special case 'Counter not modified during reset' is covered
--
-- Revision 1.3 2004/05/16 15:32:57 arniml
-- fix edge detector bug for counter
--
-- Revision 1.2 2004/04/15 22:05:13 arniml
-- increment prescaler with MSTATE4
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
--
-------------------------------------------------------------------------------