mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-27 02:04:37 +00:00
e74e5f77f8c5ae340ead1a886f64ae824554b026
clk_sys/4 (default) or clk_sys/2
Description
No description provided
Languages
VHDL
66.6%
Verilog
19.2%
SystemVerilog
11.7%
Tcl
2.1%
Batchfile
0.2%
Other
0.1%