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Update SEGASYS1_MAIN.v

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Marcel
2021-06-30 07:10:13 +02:00
parent cfbe30b890
commit ead26d08c4
1 changed files with 2 additions and 2 deletions
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Arcade_MiST/Sega System 1 Hardware/rtl/SEGASYS1_MAIN.v
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@@ -51,7 +51,7 @@ end
wire CPUCL_EN = CLK4M_EN;
wire [7:0] CPUDI;
wire CPURD;
//wire CPURD;
wire cpu_m1;
wire cpu_mreq, cpu_iorq;
@@ -74,7 +74,7 @@ Z80IP maincpu(
);
assign CPUWR = _cpu_wr & cpu_mreq;
assign CPURD = _cpu_rd & cpu_mreq;
//assign CPURD = _cpu_rd & cpu_mreq;
// Input Port