mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-20 01:34:38 +00:00
Merge pull request #124 from gyurco/master
Segasys1: fix clocking, video timings, etc...
This commit is contained in:
Marcel
GitHub
commit
cfbe30b890
@ -53,8 +53,8 @@ set_time_format -unit ns -decimal_places 3
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create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
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set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
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set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
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set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
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set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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@ -15,7 +15,7 @@
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<dip bits="14" name="Time" ids="2 Minutes,3 Minutes"/>
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</switches>
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<rom index="1">
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<part>04</part>
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<part>00</part>
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</rom>
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<rom index="0" zip="pitfall2.zip" md5="07b1a752e7bf1bf17ae773d1b6977bf1" type="merged|nonmerged|split">
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<part name="epr-6456a.116"/>
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@ -23,41 +23,41 @@ module HVGEN
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reg [8:0] hcnt = 0;
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reg [8:0] vcnt = 0;
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assign HPOS = hcnt-9'd16;
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assign HPOS = hcnt;
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assign VPOS = vcnt;
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wire [8:0] HS_B = 9'd288+(HOFFS*2'd2);
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wire [8:0] HS_B = 9'd462+(HOFFS*2'd2);
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wire [8:0] HS_E = 9'd32+(HS_B);
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wire [8:0] HS_N = 9'd447+(HS_E-9'd320);
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wire [8:0] VS_B = 9'd226+(VOFFS*3'd4);
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wire [8:0] VS_E = 9'd4+(VS_B);
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wire [8:0] VS_N = 9'd481+(VS_E-9'd230);
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always @(posedge CLK) begin
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if (PCLK_EN) begin
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hcnt <= hcnt + 1'd1;
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case (hcnt)
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25: HBLK <= H240;
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37: HBLK <= 0;
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277: HBLK <= H240;
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281: HBLK <= 1;
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511: begin
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hcnt <= 0;
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13: HBLK <= H240;
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21: HBLK <= 0;
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261: HBLK <= H240;
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269: begin
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hcnt <= 9'd462; // original: 0-255, 448-511 = 320, now: 0-269, 462-511 = 320
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HBLK <= 1;
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vcnt <= vcnt + 1'd1;
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case (vcnt)
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223: begin VBLK <= 1; vcnt <= vcnt+9'd1; end
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511: begin VBLK <= 0; vcnt <= 0; end
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default: vcnt <= vcnt+9'd1;
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223: VBLK <= 1;
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255: vcnt <= 9'd505;
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511: VBLK <= 0;
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default: ;
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endcase
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end
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default: hcnt <= hcnt+9'd1;
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default: ;
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endcase
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if (hcnt==HS_B) begin HSYN <= 0; end
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if (hcnt==HS_E) begin HSYN <= 1; hcnt <= HS_N; end
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if (hcnt==HS_E) begin HSYN <= 1; end
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if (vcnt==VS_B) begin VSYN <= 0; end
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if (vcnt==VS_E) begin VSYN <= 1; vcnt <= VS_N; end
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if (vcnt==VS_E) begin VSYN <= 1; end
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oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
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end
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@ -5,7 +5,7 @@
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*********************************************************************/
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module SEGASYSTEM1
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(
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input clk48M,
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input clk40M,
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input reset,
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input [7:0] INP0,
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@ -47,7 +47,7 @@ SEGASYS1_MAIN Main (
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.RESET(reset),
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.INP0(INP0),.INP1(INP1),.INP2(INP2),
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.DSW0(DSW0),.DSW1(DSW1),
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.CLK48M(clk48M),
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.CLK40M(clk40M),
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.CPUAD(CPUAD),.CPUDO(CPUDO),.CPUWR(CPUWR),
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.VBLK(VBLK),.VIDCS(VIDCS),.VIDDO(VIDDO),
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.SNDRQ(SNDRQ),.SNDNO(SNDNO),
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@ -62,7 +62,7 @@ SEGASYS1_MAIN Main (
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// Video
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wire [7:0] OPIX;
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SEGASYS1_VIDEO Video (
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.RESET(reset),.VCLKx8(clk48M),
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.RESET(reset),.VCLKx8(clk40M),
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.PH(PH),.PV(PV),.VFLP(VIDMD[7]),
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.VBLK(VBLK),.PCLK_EN(PCLK_EN),.RGB8(OPIX),.PALDSW(1'b0),
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@ -78,7 +78,7 @@ assign POUT = VIDMD[4] ? 8'd0 : OPIX;
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// Sound
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SEGASYS1_SOUND Sound(
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clk48M, reset, SNDNO, SNDRQ, SOUT,
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clk40M, reset, SNDNO, SNDRQ, SOUT,
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snd_rom_addr, snd_rom_do
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);
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@ -5,7 +5,7 @@
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module SEGASYS1_MAIN
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(
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input CLK48M,
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input CLK40M,
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input RESET,
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@ -38,12 +38,17 @@ module SEGASYS1_MAIN
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input ROMEN
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);
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reg [3:0] clkdiv;
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always @(posedge CLK48M) clkdiv <= clkdiv+1'd1;
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wire CLK3M_EN = clkdiv[2:0] == 0;
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wire AXSCL = CLK48M;
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wire CPUCL_EN = CLK3M_EN;
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reg [4:0] clkdiv;
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reg CLK4M_EN;
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always @(posedge CLK40M) begin
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clkdiv <= clkdiv+1'd1;
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CLK4M_EN <= 0;
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if (clkdiv == 9) begin
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clkdiv <= 0;
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CLK4M_EN <= 1;
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end
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end
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wire CPUCL_EN = CLK4M_EN;
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wire [7:0] CPUDI;
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wire CPURD;
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@ -54,7 +59,7 @@ wire _cpu_rd, _cpu_wr;
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Z80IP maincpu(
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.reset(RESET),
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.clk(CLK48M),
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.clk(CLK40M),
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.clk_en(CPUCL_EN),
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.adr(CPUAD),
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.data_in(CPUDI),
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@ -88,7 +93,7 @@ wire [7:0] cpu_rd_mrom1;
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wire [14:0] rad;
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wire [7:0] rdt;
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SEGASYS1_PRGDEC decr(AXSCL,cpu_m1,CPUAD,cpu_rd_mrom0, rad,rdt, ROMCL,ROMAD,ROMDT,ROMEN);
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SEGASYS1_PRGDEC decr(CLK40M,cpu_m1,CPUAD,cpu_rd_mrom0, rad,rdt, ROMCL,ROMAD,ROMDT,ROMEN);
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assign cpu_rom_addr = CPUAD[15] ? CPUAD[15:0] : {1'b0, rad};
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assign rdt = cpu_rom_do;
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@ -101,7 +106,7 @@ assign cpu_rd_mrom1 = cpu_rom_do;
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// Work RAM
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wire [7:0] cpu_rd_mram;
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wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100) & cpu_mreq;
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SRAM_4096 mainram(CLK48M, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO );
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SRAM_4096 mainram(CLK40M, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO );
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// Video mode latch & Sound Request
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@ -111,7 +116,7 @@ wire cpu_cs_vidm = ((CPUAD[7:0] == 8'h15)|(CPUAD[7:0] == 8'h19)) & cpu_iorq;
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wire cpu_wr_sreq = cpu_cs_sreq & _cpu_wr;
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wire cpu_wr_vidm = cpu_cs_vidm & _cpu_wr;
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always @(posedge CLK48M or posedge RESET) begin
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always @(posedge CLK40M or posedge RESET) begin
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if (RESET) begin
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VIDMD <= 0;
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SNDRQ <= 0;
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@ -125,16 +130,12 @@ end
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// CPU data selector
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dataselector6 mcpudisel(
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CPUDI,
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VIDCS & cpu_mreq, VIDDO,
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cpu_cs_vidm, VIDMD,
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cpu_cs_port, cpu_rd_port,
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cpu_cs_mram, cpu_rd_mram,
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cpu_cs_mrom0, cpu_rd_mrom0,
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cpu_cs_mrom1, cpu_rd_mrom1,
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8'hFF
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);
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assign CPUDI = (VIDCS & cpu_mreq) ? VIDDO :
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cpu_cs_vidm ? VIDMD :
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cpu_cs_port ? cpu_rd_port :
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cpu_cs_mram ? cpu_rd_mram :
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cpu_cs_mrom0 ? cpu_rd_mrom0 :
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cpu_cs_mrom1 ? cpu_rd_mrom1 : 8'hFF;
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endmodule
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@ -162,15 +163,12 @@ wire cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & CPUIO;
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wire cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:2] == 3'b1_00)) & CPUIO;
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wire [7:0] inp;
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dataselector5 dsel(
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inp,
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cs_port1,INP0,
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cs_port2,INP1,
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cs_portS,INP2,
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cs_portA,DSW0,
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cs_portB,DSW1,
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8'hFF
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);
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assign inp = cs_port1 ? INP0 :
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cs_port2 ? INP1 :
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cs_portS ? INP2 :
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cs_portA ? DSW0 :
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cs_portB ? DSW1 : 8'hFF;
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assign DV = cs_port1|cs_port2|cs_portS|cs_portA|cs_portB;
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assign OD = inp;
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@ -4,7 +4,7 @@
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module SEGASYS1_SOUND
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(
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input clk48M,
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input clk40M,
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input reset,
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input [7:0] sndno,
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@ -21,7 +21,7 @@ module SEGASYS1_SOUND
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// ClockGen
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//----------------------------------
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wire clk8M_en,clk4M_en,clk2M_en;
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SndClkGen clkgen(clk48M,clk8M_en,clk4M_en,clk2M_en);
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SndClkGen clkgen(clk40M,clk8M_en,clk4M_en,clk2M_en);
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//----------------------------------
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// Z80 (1.5625MHz)
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@ -39,7 +39,7 @@ SndADec adec(
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);
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Z80IP cpu(
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.clk(clk48M),
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.clk(clk40M),
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.clk_en(clk4M_en & cpuwait_n),
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.reset(reset),
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.adr(cpu_ad),
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@ -63,19 +63,14 @@ assign snd_rom_addr = cpu_ad[12:0];
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assign rom_dt = snd_rom_do;
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//DLROM #(13,8) subir( cpuclkx2, cpu_ad[12:0], rom_dt, ROMCL,ROMAD,ROMDT,ROMEN & `EN_SCPU );
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SRAM_2048 wram( clk48M, cpu_ad[10:0], ram_do, cpu_wr_ram, cpu_do );
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dataselector3 scpudisel(
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cpu_di,
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cpu_cs_rom, rom_dt,
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cpu_cs_ram, ram_do,
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cpu_cs_com, comlatch,
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8'hFF
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);
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SRAM_2048 wram( clk40M, cpu_ad[10:0], ram_do, cpu_wr_ram, cpu_do );
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assign cpu_di = cpu_cs_rom ? rom_dt :
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cpu_cs_ram ? ram_do :
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cpu_cs_com ? comlatch : 8'hFF;
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SndPlayReq sndreq (
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clk48M, clk8M_en, reset,
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clk40M, clk8M_en, reset,
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sndno, sndstart,
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cpu_irq, cpu_irqa,
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cpu_nmi, cpu_nmia,
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@ -91,7 +86,7 @@ wire psg0wait, psg1wait;
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wire cpuwait_n = psg0wait & psg1wait;
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sn76489_top psg0(
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.clock_i(clk48M),
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.clock_i(clk40M),
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.clock_en_i(clk2M_en),
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.res_n_i(~reset),
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.ce_n_i(~(cpu_cs_psg0 & cpu_mreq)),
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@ -102,7 +97,7 @@ sn76489_top psg0(
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);
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sn76489_top psg1(
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.clock_i(clk48M),
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.clock_i(clk40M),
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.clock_en_i(clk4M_en),
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.res_n_i(~reset),
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.ce_n_i(~(cpu_cs_psg1 & cpu_mreq)),
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@ -120,21 +115,21 @@ endmodule
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module SndClkGen
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(
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input clk48M,
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input clk40M,
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output clk8M_en,
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output clk4M_en,
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output clk2M_en
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);
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reg [4:0] count;
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always @( posedge clk48M ) begin
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always @( posedge clk40M ) begin
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count <= count + 1'd1;
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if (count == 23) count <= 0;
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if (count == 19) count <= 0;
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end
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assign clk2M_en = count == 0;
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assign clk4M_en = count == 0 || count == 12;
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assign clk8M_en = count == 0 || count == 6 || count == 12 || count == 18;
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assign clk4M_en = count == 0 || count == 10;
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assign clk8M_en = count == 0 || count == 5 || count == 10 || count == 15;
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endmodule
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@ -302,16 +302,12 @@ VRAM vram1(
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// CPU Read Data Selector
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dataselector6 videodsel(
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cpu_dr,
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cpu_cs_palram, cpu_rd_palram,
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cpu_cs_vram0, cpu_rd_vram0,
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cpu_cs_vram1, cpu_rd_vram1,
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cpu_cs_spram, cpu_rd_spram,
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cpu_cs_sprcoll, cpu_rd_sprcoll,
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cpu_cs_mixcoll, cpu_rd_mixcoll,
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8'hFF
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);
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assign cpu_dr = cpu_cs_palram ? cpu_rd_palram :
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cpu_cs_vram0 ? cpu_rd_vram0 :
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cpu_cs_vram1 ? cpu_rd_vram1 :
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cpu_cs_spram ? cpu_rd_spram :
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cpu_cs_sprcoll ? cpu_rd_sprcoll :
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cpu_cs_mixcoll ? cpu_rd_mixcoll : 8'hFF;
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endmodule
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@ -454,11 +450,7 @@ always @( posedge CLK ) begin
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end
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end
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dataselector1_32 pixsft(
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BGPIX,
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( HP[2:0] != 0 ),{ BGPN, BGCD[22:0], 1'b0 },
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{ BG_COL/*VRAMDT[12:5]*/, TILEDT }
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);
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assign BGPIX = ( HP[2:0] != 0 ) ? { BGPN, BGCD[22:0], 1'b0 } : { BG_COL/*VRAMDT[12:5]*/, TILEDT };
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assign OPIX = { BGPN, BGCD[7], BGCD[15], BGCD[23] };
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@ -503,12 +495,10 @@ assign mixcoll = ~(cltval[2]);
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assign mixcoll_ad = { cltval[3], SPRPX[8:4] };
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wire [10:0] palno_i;
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dataselector2_11 colsel(
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palno_i,
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cltval[1], ( 11'h400 | BG0PX[8:0] ),
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cltval[0], ( 11'h200 | BG1PX[8:0] ),
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( 11'h000 | SPRPX[8:0] )
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);
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assign palno_i = cltval[1] ? ( 11'h400 | BG0PX[8:0] ) :
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cltval[0] ? ( 11'h200 | BG1PX[8:0] ) :
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( 11'h000 | SPRPX[8:0] );
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wire [10:0] palno_d = {HPOS[7],VPOS[7:2],HPOS[6:3]};
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@ -74,8 +74,8 @@ wire clk_sys, sdram_clk;
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wire pll_locked;
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pll_mist pll(
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.inclk0(CLOCK_27),
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.c0(clk_sys),//48
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.c1(sdram_clk),//96
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.c0(sdram_clk),//80
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.c1(clk_sys),//40
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.locked(pll_locked)
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);
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@ -145,7 +145,7 @@ data_io data_io(
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reg port1_req, port2_req;
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wire [24:0] tl_ioctl_addr = ioctl_addr - 18'h20000;
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sdram #(96) sdram(
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sdram #(80) sdram(
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.*,
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.init_n ( pll_locked ),
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.clk ( sdram_clk ),
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@ -201,7 +201,7 @@ always @(posedge sdram_clk) begin
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end
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SEGASYSTEM1 System1_Top(
|
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.clk48M(clk_sys),
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.clk40M(clk_sys),
|
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.reset(reset),
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.INP0(INP0),
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@ -237,8 +237,8 @@ SEGASYSTEM1 System1_Top(
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wire PCLK_EN;
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wire [8:0] HPOS,VPOS;
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wire [7:0] POUT;
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wire [7:0] HOFFS = 8'd16;
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wire [7:0] VOFFS = 0;
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wire [7:0] HOFFS = 8'd2;
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wire [7:0] VOFFS = 8'd2;
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wire hs, vs;
|
||||
wire [2:0] g, r;
|
||||
wire [1:0] b;
|
||||
|
||||
@ -233,117 +233,3 @@ DPRAM1024_11B core (
|
||||
endmodule
|
||||
|
||||
|
||||
//----------------------------------
|
||||
// Data Selector (32bits)
|
||||
//----------------------------------
|
||||
module dataselector1_32(
|
||||
|
||||
output [31:0] oDATA,
|
||||
|
||||
input iSEL0,
|
||||
input [31:0] iDATA0,
|
||||
|
||||
input [31:0] dData
|
||||
);
|
||||
|
||||
assign oDATA = iSEL0 ? iDATA0 :
|
||||
dData;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//----------------------------------
|
||||
// Data Selector 3 to 1
|
||||
//----------------------------------
|
||||
module dataselector3(
|
||||
|
||||
output [7:0] oDATA,
|
||||
|
||||
input iSEL0, input [7:0] iDATA0,
|
||||
input iSEL1, input [7:0] iDATA1,
|
||||
input iSEL2, input [7:0] iDATA2,
|
||||
|
||||
input [7:0] dData
|
||||
);
|
||||
|
||||
assign oDATA = iSEL0 ? iDATA0 :
|
||||
iSEL1 ? iDATA1 :
|
||||
iSEL2 ? iDATA2 :
|
||||
dData;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//----------------------------------
|
||||
// Data Selector 2 to 1 (11bits)
|
||||
//----------------------------------
|
||||
module dataselector2_11(
|
||||
|
||||
output [10:0] oDATA,
|
||||
|
||||
input iSEL0, input [10:0] iDATA0,
|
||||
input iSEL1, input [10:0] iDATA1,
|
||||
|
||||
input [10:0] dData
|
||||
);
|
||||
|
||||
assign oDATA = iSEL0 ? iDATA0 :
|
||||
iSEL1 ? iDATA1 :
|
||||
dData;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//----------------------------------
|
||||
// Data Selector 5 to 1
|
||||
//----------------------------------
|
||||
module dataselector5(
|
||||
|
||||
output [7:0] oDATA,
|
||||
|
||||
input iSEL0, input [7:0] iDATA0,
|
||||
input iSEL1, input [7:0] iDATA1,
|
||||
input iSEL2, input [7:0] iDATA2,
|
||||
input iSEL3, input [7:0] iDATA3,
|
||||
input iSEL4, input [7:0] iDATA4,
|
||||
|
||||
input [7:0] dData
|
||||
);
|
||||
|
||||
assign oDATA = iSEL0 ? iDATA0 :
|
||||
iSEL1 ? iDATA1 :
|
||||
iSEL2 ? iDATA2 :
|
||||
iSEL3 ? iDATA3 :
|
||||
iSEL4 ? iDATA4 :
|
||||
dData;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//----------------------------------
|
||||
// Data Selector 6 to 1
|
||||
//----------------------------------
|
||||
module dataselector6(
|
||||
|
||||
output [7:0] oDATA,
|
||||
|
||||
input iSEL0, input [7:0] iDATA0,
|
||||
input iSEL1, input [7:0] iDATA1,
|
||||
input iSEL2, input [7:0] iDATA2,
|
||||
input iSEL3, input [7:0] iDATA3,
|
||||
input iSEL4, input [7:0] iDATA4,
|
||||
input iSEL5, input [7:0] iDATA5,
|
||||
|
||||
input [7:0] dData
|
||||
);
|
||||
|
||||
assign oDATA = iSEL0 ? iDATA0 :
|
||||
iSEL1 ? iDATA1 :
|
||||
iSEL2 ? iDATA2 :
|
||||
iSEL3 ? iDATA3 :
|
||||
iSEL4 ? iDATA4 :
|
||||
iSEL5 ? iDATA5 :
|
||||
dData;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
@ -98,13 +98,13 @@ module pll_mist (
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 9,
|
||||
altpll_component.clk0_divide_by = 27,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 16,
|
||||
altpll_component.clk0_multiply_by = 80,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 9,
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 32,
|
||||
altpll_component.clk1_multiply_by = 40,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
@ -183,8 +183,8 @@ endmodule
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@ -212,10 +212,10 @@ endmodule
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
@ -259,13 +259,13 @@ endmodule
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user