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add Popey Hardware Protection

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Gehstock
2020-01-01 17:53:40 +01:00
parent c8f4f79ceb
commit f12c74a37b
71 changed files with 7850 additions and 2696 deletions
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19
Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt Normal file
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Traverse USA by Dar (darfpga@aol.fr) (16/03/2019)
Port to MiST
TRAVRUSA.ROM or SHTRIDER.ROM is required at the root of the SD-Card.
Creating in Windows:
copy /B zr1-0.m3 + zr1-5.l3 + zr1-6a.k3 + zr1-7.j3 + mr10.1a + mr10.1a + zippyrac.001 + mr8.3c + mr9.3a + zr1-8.n3 + zr1-9.l3 + zr1-10.k3 + mmi6349.ij + tbp24s10.3 + tbp18s.2 > TRAVRUSA.ROM
copy /B sr01a.bin + sr02a.bin + sr03a.bin + sr04a.bin + sr11a.bin + sr05a.bin + sr06a.bin + sr07a.bin + sr08a.bin + sr09a.bin + sr10b.bin + 1.bpr + 2.bpr + 3.bpr + 4.bpr > SHTRIDER.ROM
Creating in Linux:
cat zr1-0.m3 zr1-5.l3 zr1-6a.k3 zr1-7.j3 mr10.1a mr10.1a zippyrac.001 mr8.3c mr9.3a zr1-8.n3 zr1-9.l3 zr1-10.k3 mmi6349.ij tbp24s10.3 tbp18s.2 > TRAVRUSA.ROM
cat sr01a.bin sr02a.bin sr03a.bin sr04a.bin sr11a.bin sr05a.bin sr06a.bin sr07a.bin sr08a.bin sr09a.bin sr10b.bin 1.bpr 2.bpr 3.bpr 4.bpr > SHTRIDER.ROM
Some ROM files contain different names, like:
zippyrac.000
zippyrac.005
zippyrac.006
zippyrac.007

BIN
Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM Normal file
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Binary file not shown.

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Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
# Date created = 04:04:47 October 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "TropicalAngel_MiST"

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Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:22:13 June 04, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TraverseUSA_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13 JUNE 04, 2019"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY TraverseUSA_MiST
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TraverseUSA_MiST.sv
set_global_assignment -name VHDL_FILE rtl/traverse_usa.vhd
set_global_assignment -name VHDL_FILE rtl/moon_patrol_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.sdc Normal file
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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -to [get_ports {SDRAM_CLK}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2
set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

15
Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

320
Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TraverseUSA_MiST.sv Normal file
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//============================================================================
// Arcade: TraverseUSA, ShotRider
//
// DarFPGA's core ported to MiST by (C) 2019 Szombathelyi György
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module TraverseUSA_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl/build_id.v"
reg shtrider = 1;
wire [7:0] dip1 = 8'hff;
reg [7:0] dip2 = 8'hff;
localparam CONF_STR = {
"TROPANG;rom;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"OA,Blending,Off,On;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = clk_sys;
assign SDRAM_CKE = 1;
wire clk_sys, clk_aud;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys),
.c1(clk_aud),
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
wire [10:0] audio;
wire hs, vs;
wire blankn;
wire [2:0] g,b;
wire [1:0] r;
wire [14:0] cart_addr;
wire [15:0] sdram_do;
wire cart_rd;
wire [12:0] snd_addr;
wire [15:0] snd_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
/* ROM structure
00000-07FFF CPU ROM 32k zr1-0.m3 zr1-5.l3 zr1-6a.k3 zr1-7.j3
08000-09FFF SND ROM 8k mr10.1a mr10.1a
0A000-0FFFF GFX1 24k zippyrac.001 mr8.3c mr9.3a
10000-15FFF GFX2 24k zr1-8.n3 zr1-9.l3 zr1-10.k3
16000-161FF CHR PAL 512b mmi6349.ij
16200-162FF SPR PAL 256b tbp24s10.3
16300-1631F SPR LUT 32b tbp18s.2
*/
data_io data_io (
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_sys ),
// port1 used for main CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 15'h7fff : {1'b0, cart_addr[14:1]} ),
.cpu1_q ( sdram_do ),
// port2 for sound board
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( ioctl_addr[23:1] - 16'h4000 ),
.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.snd_addr ( ioctl_downl ? 15'h7fff : {3'b000, snd_addr[12:1]} ),
.snd_q ( snd_do )
);
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sys) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
// Traverse_usa
traverse_usa traverse_usa (
.clock_36 ( clk_sys ),
.clock_0p895 ( clk_aud ),
.reset ( reset ),
.shtrider ( shtrider ),
.video_r ( r ),
.video_g ( g ),
.video_b ( b ),
.video_hs ( hs ),
.video_vs ( vs ),
.video_blankn ( blankn ),
.audio_out ( audio ),
.dip_switch_1 ( dip1 ),
.dip_switch_2 ( dip2 ),
.start2 ( btn_two_players ),
.start1 ( btn_one_player ),
.coin1 ( btn_coin ),
.right1 ( m_right ),
.left1 ( m_left ),
.brake1 ( m_down ),
.accel1 ( m_up ),
.right2 ( m_right ),
.left2 ( m_left ),
.brake2 ( m_down ),
.accel2 ( m_up ),
.cpu_rom_addr ( cart_addr ),
.cpu_rom_do ( cart_addr[0] ? sdram_do[15:8] : sdram_do[7:0] ),
.cpu_rom_rd ( cart_rd ),
.snd_rom_addr ( snd_addr ),
.snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
.dl_addr ( ioctl_addr[16:0]),
.dl_data ( ioctl_dout ),
.dl_wr ( ioctl_wr )
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? {r, r[1] } : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( {1'b1,status[2]} ),
.scandoubler_disable( scandoublerD ),
.scanlines ( status[4:3] ),
.ypbpr ( ypbpr ),
.ce_divider ( 1'b0 ),
.blend ( status[10] )
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(11))
dac(
.clk_i(clk_aud),
.res_n_i(~reset),
.dac_i(audio),
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
always @(posedge clk_sys) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

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//
// Copyright (c) MikeJ - Jan 2005
// Copyright (c) 2016-2018 Sorgelig
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// BDIR BC MODE
// 0 0 inactive
// 0 1 read value
// 1 0 write value
// 1 1 set address
//
module YM2149
(
input CLK, // Global clock
input CE, // PSG Clock enable
input RESET, // Chip RESET (set all Registers to '0', active hi)
input BDIR, // Bus Direction (0 - read , 1 - write)
input BC, // Bus control
input A8,
input A9_L,
input [7:0] DI, // Data In
output [7:0] DO, // Data Out
output [7:0] CHANNEL_A, // PSG Output channel A
output [7:0] CHANNEL_B, // PSG Output channel B
output [7:0] CHANNEL_C, // PSG Output channel C
input SEL,
input MODE,
output [5:0] ACTIVE,
input [7:0] IOA_in,
output [7:0] IOA_out,
input [7:0] IOB_in,
output [7:0] IOB_out
);
assign ACTIVE = ~ymreg[7][5:0];
assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff;
assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff;
reg [7:0] addr;
reg [7:0] ymreg[16];
wire cs = !A9_L & A8;
// Write to PSG
reg env_reset;
always @(posedge CLK) begin
if(RESET) begin
ymreg <= '{default:0};
ymreg[7] <= '1;
addr <= '0;
env_reset <= 0;
end else begin
env_reset <= 0;
if(cs & BDIR) begin
if(BC) addr <= DI;
else if(!addr[7:4]) begin
ymreg[addr[3:0]] <= DI;
env_reset <= (addr == 13);
end
end
end
end
// Read from PSG
assign DO = dout;
reg [7:0] dout;
always_comb begin
dout = 8'hFF;
if(cs & ~BDIR & BC & !addr[7:4]) begin
case(addr[3:0])
0: dout = ymreg[0];
1: dout = ymreg[1][3:0];
2: dout = ymreg[2];
3: dout = ymreg[3][3:0];
4: dout = ymreg[4];
5: dout = ymreg[5][3:0];
6: dout = ymreg[6][4:0];
7: dout = ymreg[7];
8: dout = ymreg[8][4:0];
9: dout = ymreg[9][4:0];
10: dout = ymreg[10][4:0];
11: dout = ymreg[11];
12: dout = ymreg[12];
13: dout = ymreg[13][3:0];
14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
endcase
end
end
reg ena_div;
reg ena_div_noise;
// p_divider
always @(posedge CLK) begin
reg [3:0] cnt_div;
reg noise_div;
if(CE) begin
ena_div <= 0;
ena_div_noise <= 0;
if(!cnt_div) begin
cnt_div <= {SEL, 3'b111};
ena_div <= 1;
noise_div <= (~noise_div);
if (noise_div) ena_div_noise <= 1;
end else begin
cnt_div <= cnt_div - 1'b1;
end
end
end
reg [2:0] noise_gen_op;
// p_noise_gen
always @(posedge CLK) begin
reg [16:0] poly17;
reg [4:0] noise_gen_cnt;
if(CE) begin
if (ena_div_noise) begin
if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
noise_gen_cnt <= 0;
poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
end else begin
noise_gen_cnt <= noise_gen_cnt + 1'd1;
end
noise_gen_op <= {3{poly17[0]}};
end
end
end
wire [11:0] tone_gen_freq[1:3];
assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
reg [3:1] tone_gen_op;
//p_tone_gens
always @(posedge CLK) begin
integer i;
reg [11:0] tone_gen_cnt[1:3];
if(CE) begin
// looks like real chips count up - we need to get the Exact behaviour ..
for (i = 1; i <= 3; i = i + 1) begin
if(ena_div) begin
if (tone_gen_freq[i]) begin
if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
tone_gen_cnt[i] <= 0;
tone_gen_op[i] <= ~tone_gen_op[i];
end else begin
tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
end
end else begin
tone_gen_op[i] <= ymreg[7][i];
tone_gen_cnt[i] <= 0;
end
end
end
end
end
reg env_ena;
wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
//p_envelope_freq
always @(posedge CLK) begin
reg [15:0] env_gen_cnt;
if(CE) begin
env_ena <= 0;
if(ena_div) begin
if (env_gen_cnt >= env_gen_comp) begin
env_gen_cnt <= 0;
env_ena <= 1;
end else begin
env_gen_cnt <= (env_gen_cnt + 1'd1);
end
end
end
end
reg [4:0] env_vol;
wire is_bot = (env_vol == 5'b00000);
wire is_bot_p1 = (env_vol == 5'b00001);
wire is_top_m1 = (env_vol == 5'b11110);
wire is_top = (env_vol == 5'b11111);
always @(posedge CLK) begin
reg env_hold;
reg env_inc;
// envelope shapes
// C AtAlH
// 0 0 x x \___
//
// 0 1 x x /___
//
// 1 0 0 0 \\\\
//
// 1 0 0 1 \___
//
// 1 0 1 0 \/\/
// ___
// 1 0 1 1 \
//
// 1 1 0 0 ////
// ___
// 1 1 0 1 /
//
// 1 1 1 0 /\/\
//
// 1 1 1 1 /___
if(env_reset | RESET) begin
// load initial state
if(!ymreg[13][2]) begin // attack
env_vol <= 5'b11111;
env_inc <= 0; // -1
end else begin
env_vol <= 5'b00000;
env_inc <= 1; // +1
end
env_hold <= 0;
end
else if(CE) begin
if (env_ena) begin
if (!env_hold) begin
if (env_inc) env_vol <= (env_vol + 5'b00001);
else env_vol <= (env_vol + 5'b11111);
end
// envelope shape control.
if(!ymreg[13][3]) begin
if(!env_inc) begin // down
if(is_bot_p1) env_hold <= 1;
end else if (is_top) env_hold <= 1;
end else if(ymreg[13][0]) begin // hold = 1
if(!env_inc) begin // down
if(ymreg[13][1]) begin // alt
if(is_bot) env_hold <= 1;
end else if(is_bot_p1) env_hold <= 1;
end else if(ymreg[13][1]) begin // alt
if(is_top) env_hold <= 1;
end else if(is_top_m1) env_hold <= 1;
end else if(ymreg[13][1]) begin // alternate
if(env_inc == 1'b0) begin // down
if(is_bot_p1) env_hold <= 1;
if(is_bot) begin
env_hold <= 0;
env_inc <= 1;
end
end else begin
if(is_top_m1) env_hold <= 1;
if(is_top) begin
env_hold <= 0;
env_inc <= 0;
end
end
end
end
end
end
reg [5:0] A,B,C;
always @(posedge CLK) begin
A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}};
B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}};
C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
end
wire [7:0] volTable[64] = '{
//YM2149
8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04,
8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13,
8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47,
8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
//AY8910
8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06,
8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22,
8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72,
8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff
};
assign CHANNEL_A = volTable[A];
assign CHANNEL_B = volTable[B];
assign CHANNEL_C = volTable[C];
endmodule

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Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/build_id.tcl Normal file
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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/cpu68.vhd Normal file
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Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd Normal file
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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- dpram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity dpram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk_a : in std_logic;
we_a : in std_logic := '0';
addr_a : in std_logic_vector((aWidth-1) downto 0);
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_a : out std_logic_vector((dWidth-1) downto 0);
clk_b : in std_logic;
we_b : in std_logic := '0';
addr_b : in std_logic_vector((aWidth-1) downto 0);
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_b : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of dpram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
ram(to_integer(unsigned(addr_a))) <= d_a;
end if;
q_a <= ram(to_integer(unsigned(addr_a)));
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
ram(to_integer(unsigned(addr_b))) <= d_b;
end if;
q_b <= ram(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture;

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Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/gen_ram.vhd Normal file
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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_ram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_ram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
-- q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
-- rAddrReg <= addr;
---- qReg <= ram(to_integer(unsigned(addr)));
q <= ram(to_integer(unsigned(addr)));
end if;
end process;
--q <= ram(to_integer(unsigned(addr)));
end architecture;

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---------------------------------------------------------------------------------
-- Moon patrol sound board by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- gen_ram.vhd
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
---------------------------------------------------------------------------------
-- cpu68 - Version 9th Jan 2004 0.8
-- 6800/01 compatible CPU core
-- GNU public license - December 2002 : John E. Kent
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- Version 0.0 -- 24/11/2017 --
-- initial version
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity moon_patrol_sound_board is
port(
clock_E : in std_logic; -- 3.58 Mhz/4
areset : in std_logic;
select_sound : in std_logic_vector(7 downto 0);
audio_out : out std_logic_vector(11 downto 0);
rom_addr : out std_logic_vector(12 downto 0);
rom_do : in std_logic_vector( 7 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end moon_patrol_sound_board;
architecture struct of moon_patrol_sound_board is
component YM2149
port (
CLK : in std_logic;
CE : in std_logic;
RESET : in std_logic;
A8 : in std_logic := '1';
A9_L : in std_logic := '0';
BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write)
BC : in std_logic; -- Bus control
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CHANNEL_A : out std_logic_vector(7 downto 0);
CHANNEL_B : out std_logic_vector(7 downto 0);
CHANNEL_C : out std_logic_vector(7 downto 0);
SEL : in std_logic;
MODE : in std_logic;
ACTIVE : out std_logic_vector(5 downto 0);
IOA_in : in std_logic_vector(7 downto 0);
IOA_out : out std_logic_vector(7 downto 0);
IOB_in : in std_logic_vector(7 downto 0);
IOB_out : out std_logic_vector(7 downto 0)
);
end component;
signal reset : std_logic := '1';
signal reset_cnt : integer range 0 to 1000000 := 1000000;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal irqraz_cs : std_logic;
signal irqraz_we : std_logic;
signal wram_cs : std_logic;
signal wram_we : std_logic;
signal wram_do : std_logic_vector( 7 downto 0);
signal rom_cs : std_logic;
-- signal rom_do : std_logic_vector( 7 downto 0);
signal ay1_chan_a : std_logic_vector(7 downto 0);
signal ay1_chan_b : std_logic_vector(7 downto 0);
signal ay1_chan_c : std_logic_vector(7 downto 0);
signal ay1_do : std_logic_vector(7 downto 0);
signal ay1_audio : std_logic_vector(9 downto 0);
signal ay1_port_b_do : std_logic_vector(7 downto 0);
signal ay2_chan_a : std_logic_vector(7 downto 0);
signal ay2_chan_b : std_logic_vector(7 downto 0);
signal ay2_chan_c : std_logic_vector(7 downto 0);
signal ay2_do : std_logic_vector(7 downto 0);
signal ay2_audio : std_logic_vector(9 downto 0);
signal ports_cs : std_logic;
signal ports_we : std_logic;
signal port1_bus : std_logic_vector(7 downto 0);
signal port1_data : std_logic_vector(7 downto 0);
signal port1_ddr : std_logic_vector(7 downto 0);
signal port1_in : std_logic_vector(7 downto 0);
signal port2_bus : std_logic_vector(7 downto 0);
signal port2_data : std_logic_vector(7 downto 0);
signal port2_ddr : std_logic_vector(7 downto 0);
signal port2_in : std_logic_vector(7 downto 0);
signal adpcm_cs : std_logic;
signal adpcm_we : std_logic;
signal adpcm_0_di : std_logic_vector(3 downto 0);
signal select_sound_r : std_logic_vector(7 downto 0);
signal audio : std_logic_vector(12 downto 0);
type t_step_size is array(0 to 48) of integer range 0 to 1552;
constant step_size : t_step_size := (
16, 17, 19, 21, 23, 25, 28, 31,
34, 37, 41, 45, 50, 55, 60, 66,
73, 80, 88, 97, 107, 118, 130, 143,
157, 173, 190, 209, 230, 253, 279, 307,
337, 371, 408, 449, 494, 544, 598, 658,
724, 796, 876, 963, 1060, 1166, 1282, 1411, 1552);
type t_delta_step is array(0 to 7) of integer range -1 to 8;
constant delta_step : t_delta_step := (-1,-1,-1,-1,2,4,6,8);
signal adpcm_vclk : std_logic := '0';
signal adpcm_signal : integer range -16384 to 16383 := 0;
-- adpcm algorithm (4bits) [no pcm here]
--
-- val : input value 3bits (0 - 7 : b2b1b0)
-- sign : input value sign (4th bit : 0=>sign=1 ,1=>sign=-1)
--
-- step : internal data, init = 0
-- signal : output value, init = 0;
--
-- for each new val (and sign) :
-- |
-- | step_size = 16*1.1^(step)
-- | delta = sign * (step_size/8 + step_size/4*b0 + step_size/2*b1 + step_size*b2)
-- | signal = signal + delta
-- | step = step + delta_step(val)
-- |
-- | signal is then limited between -2048..2047
-- | step is then limited between 0..48
begin
dbg_cpu_addr <= cpu_addr;
-- cs
wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF
ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F
adpcm_cs <= '1' when cpu_addr(14 downto 11) = "0001" else '0'; -- 0800-0FFF / 8800-8FFF
irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF / 9000-9FFF
rom_cs <= '1' when cpu_addr(14 downto 13) = "11" else '0'; -- 6000-7FFF / E000-FFFF
-- write enables
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
ports_we <= '1' when cpu_rw = '0' and ports_cs = '1' else '0';
adpcm_we <= '1' when cpu_rw = '0' and adpcm_cs = '1' else '0';
irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
-- mux cpu in data between roms/io/wram
cpu_di <=
wram_do when wram_cs = '1' else
port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
rom_do when rom_cs = '1' else X"55";
process (clock_E)
begin
if rising_edge(clock_E) then
reset <= '0';
if reset_cnt /= 0 then
reset_cnt <= reset_cnt - 1;
reset <= '1';
end if;
if areset = '1' then
reset_cnt <= 1000000;
end if;
end if;
end process;
-- irq to cpu
process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then
cpu_irq <= '1';
end if;
if irqraz_we = '1' then
cpu_irq <= '0';
end if;
end if;
end process;
-- cpu nmi
cpu_nmi <= adpcm_vclk;
-- 6803 ports 1 and 2 (only)
process (reset, clock_E)
begin
if reset='1' then
port1_ddr <= (others=>'0'); -- port1 set as input
port1_data <= (others=>'0'); -- port1 data set to 0
port2_ddr <= ("11100000"); -- port2 bit 7 to 5 should always remain output to simulate mode data
port2_data <= ("01000000"); -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up)
elsif rising_edge(clock_E) then
if ports_cs = '1' and ports_we = '1' then
if cpu_addr(3 downto 0) = X"0" then port1_ddr <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"1" then port2_ddr <= cpu_do and "11100000"; end if;
if cpu_addr(3 downto 0) = X"2" then port1_data <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"3" then port2_data <= cpu_do; end if;
end if;
end if;
end process;
port1_in <= (port1_bus and not(port1_ddr)) or (port1_data and port1_ddr);
port2_in <= (port2_bus and not(port2_ddr)) or (port2_data and port2_ddr);
-- port1 bus mux
port1_bus <= ay1_do when port2_data(4) = '0' else
ay2_do when port2_data(3) = '0' else X"FF";
-- port2 bus
port2_bus <= X"FF";
-- latch adpcm (msm5205) data in
process (reset, clock_E)
begin
if reset='1' then
adpcm_0_di <= (others=>'0');
elsif rising_edge(clock_E) then
if adpcm_cs = '1' and adpcm_we = '1' then
if cpu_addr(1) = '0' then adpcm_0_di <= cpu_do(3 downto 0); end if;
end if;
end if;
end process;
-- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz
adpcm_clocks : process(clock_E, ay1_port_b_do)
variable clock_div_a : integer range 0 to 148 := 0;
variable clock_div_b : integer range 0 to 5 := 0;
variable step : integer range 0 to 48;
variable step_n : integer range -1 to 48+8;
variable sz : integer range 0 to 1552;
variable dn : integer range -32768 to 32767;
variable adpcm_signal_n : integer range -32768 to 32767;
begin
if rising_edge(clock_E) then
if clock_div_a = 37 then -- 24kHz
clock_div_a := 0;
case ay1_port_b_do(3 downto 2) is
when "00" => if clock_div_b = 5 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 4kHz
when "01" => if clock_div_b = 2 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 8kHz
when "10" => if clock_div_b = 3 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 6kHz
when others => null;
end case;
if clock_div_b = 0 then adpcm_vclk <= '1'; else adpcm_vclk <= '0'; end if;
else
clock_div_a := clock_div_a + 1;
end if;
if ay1_port_b_do(0) = '1' then
step := 0;
adpcm_signal <= 0;
else
if clock_div_b = 0 then
case clock_div_a is
when 0 => -- it's time to get new nibble (adpcm_0_di)
sz := step_size(step);
dn := sz/8;
if adpcm_0_di(0) = '1' then dn := dn + sz/4; end if;
if adpcm_0_di(1) = '1' then dn := dn + sz/2; end if;
if adpcm_0_di(2) = '1' then dn := dn + sz ; end if;
if adpcm_0_di(3) = '1' then
dn := -dn;
end if;
step_n := step + delta_step(to_integer(unsigned(adpcm_0_di(2 downto 0))));
when 4 =>
adpcm_signal_n := adpcm_signal + dn;
if step_n > 48 then step := 48; else step := step_n; end if;
if step_n < 0 then step := 0; else step := step_n; end if;
when 8 =>
if adpcm_signal_n > 2040 then adpcm_signal <= 2040; else adpcm_signal <= adpcm_signal_n; end if;
if adpcm_signal_n < -2040 then adpcm_signal <= -2040; else adpcm_signal <= adpcm_signal_n; end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
-- audio mux
audio <= ("000"&ay1_audio) + ("000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12)));
audio_out <= audio(12 downto 1);
-- microprocessor 6800/01/03
main_cpu : entity work.cpu68
port map(
clk => clock_E, -- E clock input (falling edge)
rst => reset, -- reset input (active high)
rw => cpu_rw, -- read not write output
vma => open, -- valid memory address (active high)
address => cpu_addr, -- address bus output
data_in => cpu_di, -- data bus input
data_out => cpu_do, -- data bus output
hold => '0', -- hold input (active high) extend bus cycle
halt => '0', -- halt input (active high) grants DMA
irq => cpu_irq, -- interrupt request input (active high)
nmi => cpu_nmi, -- non maskable interrupt request input (active high)
test_alu => open,
test_cc => open
);
-- cpu program rom
--cpu_prog_rom : entity work.travusa_sound
--port map(
-- clk => clock_E,
-- addr => cpu_addr(11 downto 0),
-- data => rom_do
--);
rom_addr <= cpu_addr(12 downto 0);
-- cpu wram
cpu_ram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 7)
port map(
clk => clock_E,
we => wram_we,
addr => cpu_addr(6 downto 0),
d => cpu_do,
q => wram_do
);
ay83910_inst1: YM2149
port map (
CLK => clock_E,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(4),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay1_do,
CHANNEL_A => ay1_chan_a,
CHANNEL_B => ay1_chan_b,
CHANNEL_C => ay1_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => select_sound_r,
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => ay1_port_b_do
);
ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
ay83910_inst2: YM2149
port map (
CLK => clock_E,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(3),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay2_do,
CHANNEL_A => ay2_chan_a,
CHANNEL_B => ay2_chan_b,
CHANNEL_C => ay2_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => (others => '0'),
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => open
);
ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
end struct;

397
Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd Normal file
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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_mist.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_mist IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_mist;
ARCHITECTURE SYN OF pll_mist IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 30,
clk0_duty_cycle => 50,
clk0_multiply_by => 41,
clk0_phase_shift => "0",
clk1_divide_by => 1200,
clk1_duty_cycle => 50,
clk1_multiply_by => 41,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "30"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1200"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.900002"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.922500"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "41"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.86400000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.89500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "30"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1200"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "41"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

327
Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv Normal file
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@@ -0,0 +1,327 @@
//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output [15:0] port1_q,
input [15:1] cpu1_addr,
output reg [15:0] cpu1_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output [15:0] port2_q,
input [15:1] snd_addr,
output reg [15:0] snd_q
);
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1
1 ras0
2 CAS0 data1 returned
3 RAS1 cas0
4 ras1
5 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_LAST = 3'd5;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [15:1] addr_last[2];
reg [15:1] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_REQ = 2'd2;
localparam PORT_SND = 2'd1;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg port1_state;
reg port2_state;
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 9'd0, cpu1_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT2: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (snd_addr != addr_last2[PORT_SND]) begin
next_port[1] = PORT_SND;
addr_latch_next[1] = { 1'b1, 8'd0, snd_addr };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
port1_state <= port1_req;
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][15:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
port2_state <= port2_req;
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
PORT_SND: begin snd_q <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

1006
Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/traverse_usa.vhd Normal file
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23
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/README.txt
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@@ -1,3 +1,26 @@
---------------------------------------------------------------------------------
--
-- Arcade: Spy Hunter port to MiST by Gehstock
-- 16 November 2019
--
SHUNTER.ROM is required at the root of the SD-Card.
Controls
Joy Keyboard
up up : Accelerate
down down : Decelerate
left left : Left
right right : Right
ESC : Coin
start TAB : VAN
Y Z : Shift
X shift left : Oil
C ctrl left : Smoke
B alt left : Missle
A Space : Gun
---------------------------------------------------------------------------------
-- DE10_lite Top level for Spy hunter (Midway MCR) by Dar (darfpga@aol.fr) (06/12/2019)
-- http://darfpga.blogspot.fr

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Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SHUNTER.ROM Normal file
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Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/SpyHunter.rbf Normal file
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Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/Release/TURBOTAG.ROM
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21
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/TurboTag.qsf
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@@ -214,7 +214,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/reset.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/csd.stp
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
@@ -222,22 +222,25 @@ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpyHunter_MiST.sv
set_global_assignment -name VHDL_FILE rtl/spy_hunter.vhd
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TurboTag_MiST.sv
set_global_assignment -name VHDL_FILE rtl/turbo_tag.vhd
set_global_assignment -name VHDL_FILE rtl/turbo_tag_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/cheap_squeak_deluxe.vhd
set_global_assignment -name VHDL_FILE rtl/turbo_tag_control.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd
set_global_assignment -name VHDL_FILE rtl/spy_hunter_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/spy_hunter_control.vhd
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
set_global_assignment -name VHDL_FILE rtl/rom/ttag_ch_bits.vhd
set_global_assignment -name VHDL_FILE rtl/rom/ttag_bg_bits_2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/ttag_bg_bits_1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/midssio_82s123.vhd
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

116
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/SpyHunter_MiST.sv → Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/TurboTag_MiST.sv
View File

@@ -50,12 +50,10 @@ module SpyHunter_MiST(
localparam CONF_STR = {
"TURBOTAG;ROM;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O6,Service,Off,On;",
"O7,Swap Joystick,Off,On;",
"T0,Reset;",
"V,v1.1.",`BUILD_DATE
"V,v1.0.",`BUILD_DATE
};
assign LED = ~ioctl_downl;
@@ -75,18 +73,19 @@ pll_mist pll(
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joy_0;
wire [7:0] joy_1;
wire [15:0] joystick_0;
wire [15:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [15:0] audio_l, audio_r;
wire [9:0] csd_audio;
wire hs, vs, cs;
wire blankn;
wire [2:0] g, r, b;
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [14:0] snd_addr;
wire [15:0] snd_do;
wire [14:1] csd_addr;
wire [15:0] csd_do;
wire [14:0] sp_addr;
wire [31:0] sp_do;
wire ioctl_downl;
@@ -109,7 +108,40 @@ data_io data_io(
.ioctl_dout ( ioctl_dout )
);
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h16000;//e000
// ROM structure:
// 0000 - DFFF - Main ROM (8 bit)
// E000 - FFFF - Super Sound board ROM (8 bit)
// 10000 - 17FFF - CSD ROM (16 bit)
// 18000 - Sprite ROMs (32 bit)
// spy-hunter_cpu_pg0_2-9-84.6d
// spy-hunter_cpu_pg1_2-9-84.7d
// spy-hunter_cpu_pg2_2-9-84.8d
// spy-hunter_cpu_pg3_2-9-84.9d
// spy-hunter_cpu_pg4_2-9-84.10d
// spy-hunter_cpu_pg5_2-9-84.11d
// spy-hunter_snd_0_sd_11-18-83.a7
// spy-hunter_snd_1_sd_11-18-83.a8
// spy-hunter_cs_deluxe_u17_b_11-18-83.u17
// spy-hunter_cs_deluxe_u18_d_11-18-83.u18
// spy-hunter_cs_deluxe_u7_a_11-18-83.u7
// spy-hunter_cs_deluxe_u8_c_11-18-83.u8
// spy-hunter_video_1fg_11-18-83.a7
// spy-hunter_video_0fg_11-18-83.a8
// spy-hunter_video_3fg_11-18-83.a5
// spy-hunter_video_2fg_11-18-83.a6
// spy-hunter_video_5fg_11-18-83.a3
// spy-hunter_video_4fg_11-18-83.a4
// spy-hunter_video_7fg_11-18-83.a1
// spy-hunter_video_6fg_11-18-83.a2
wire [24:0] rom_ioctl_addr = ~ioctl_addr[16] ? ioctl_addr : // 8 bit ROMs
{ioctl_addr[24:16], ioctl_addr[15], ioctl_addr[13:0], ioctl_addr[14]}; // 16 bit ROM
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h16000;
reg port1_req, port2_req;
sdram sdram(
@@ -117,19 +149,22 @@ sdram sdram(
.init_n ( pll_locked ),
.clk ( clk_mem ),
// port1 used for main + sound CPU
// port1 used for main + sound CPUs
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_a ( rom_ioctl_addr[23:1] ),
.port1_ds ( {rom_ioctl_addr[0], ~rom_ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {rom_addr[15:1]} ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]} ),
.cpu1_q ( rom_do ),
.cpu2_addr ( 16'hffff),//ioctl_downl ? 16'hffff : (16'h7000 + snd_addr[14:1]) ),// CSD
.cpu2_q ( ),//snd_do ),
// need higher priority for CSD
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h7000 + csd_addr[14:1]) ),
.cpu2_q ( csd_do ),
.cpu3_addr ( 16'hffff ),
.cpu3_q ( ),
// port2 for sprite graphics
.port2_req ( port2_req ),
@@ -174,7 +209,7 @@ always @(posedge clk_sys) begin
end
spy_hunter_control spy_hunter_control(
turbo_tag_control turbo_tagcontrol(
.clock_40(clk_sys),
.reset(reset),
.vsync(vs),
@@ -186,7 +221,7 @@ spy_hunter_control spy_hunter_control(
.gas(gas)
);
spy_hunter spy_hunter(
turbo_tag turbo_tag(
.clock_40(clk_sys),
.reset(reset),
.video_r(r),
@@ -200,24 +235,22 @@ spy_hunter spy_hunter(
.separate_audio(1'b0),
.audio_out_l(audio_l),
.audio_out_r(audio_r),
.csd_audio_out(csd_audio),
.coin1(btn_coin),
.coin2(1'b0),
.shift(),
.oil(m_fire4),
.missile(),
.van(m_fire2),
.smoke(m_fire3),
.gun(m_fire1),
.steering(steering),
.gas(gas),
.steering(steering),
.start1(btn_one_player),
.start2(btn_two_players),
.shift(m_fire1),
.left(m_left),
.center(btn_fire2),
.right(m_right),
.service(status[6]),
.cpu_rom_addr ( rom_addr ),
.cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr ( snd_addr ),
.snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
.csd_rom_addr ( csd_addr ),
.csd_rom_do ( csd_do ),
.sp_addr ( sp_addr ),
.sp_graphx32_do ( sp_do )
);
@@ -247,7 +280,6 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.blend ( status[5] ),
.scandoubler_disable(1),//scandoublerD ),
.no_csync ( 1'b1 ),
.scanlines ( status[4:3] ),
.ypbpr ( ypbpr )
);
@@ -267,33 +299,29 @@ user_io(
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joy_0 ),
.joystick_1 (joy_1 ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(16))
.C_bits(10))
dac_l(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio_l),
.dac_i(csd_audio),
.dac_o(AUDIO_L)
);
dac #(
.C_bits(16))
.C_bits(10))
dac_r(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio_r),
.dac_i(csd_audio),
.dac_o(AUDIO_R)
);
wire [7:0] joystick_0 = status[7] ? joy_1 : joy_0;
wire [7:0] joystick_1 = status[7] ? joy_0 : joy_1;
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
@@ -312,6 +340,8 @@ reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_fire4 = 0;
reg btn_coin = 0;
reg btn_one_player = 0;
reg btn_two_players = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
@@ -324,8 +354,8 @@ always @(posedge clk_sys) begin
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
// 'h05: btn_one_player <= key_pressed; // F1
// 'h06: btn_two_players <= key_pressed; // F2
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h12: btn_fire4 <= key_pressed; // shift left
'h14: btn_fire3 <= key_pressed; // ctrl left
'h11: btn_fire2 <= key_pressed; // alt left
@@ -334,4 +364,4 @@ always @(posedge clk_sys) begin
end
end
endmodule
endmodule

219
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/cheap_squeak_deluxe.vhd Normal file
View File

@@ -0,0 +1,219 @@
-- Midway Cheap Squeak Deluxe sound board
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.fx68k.all;
entity cheap_squeak_deluxe is
port(
clock_40 : in std_logic;
reset : in std_logic;
input : in std_logic_vector(7 downto 0);
rom_addr : out std_logic_vector(14 downto 1);
rom_do : in std_logic_vector(15 downto 0);
audio_out : out std_logic_vector(9 downto 0)
);
end cheap_squeak_deluxe;
architecture rtl of cheap_squeak_deluxe is
signal cpu_ce1 : std_logic;
signal cpu_ce2 : std_logic;
signal cpu_ce_count : std_logic_vector( 4 downto 0);
signal cpu_addr : std_logic_vector(23 downto 1);
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal cpu_data_in : std_logic_vector(15 downto 0);
signal cpu_data_out : std_logic_vector(15 downto 0);
signal cpu_as_n : std_logic;
signal cpu_lds_n : std_logic;
signal cpu_uds_n : std_logic;
signal cpu_dtack_n : std_logic;
signal cpu_vpa_n : std_logic;
signal cpu_fc : std_logic_vector( 2 downto 0);
signal cpu_ipl2_N : std_logic;
signal cpu_sel : std_logic;
signal pia_data_out : std_logic_vector( 7 downto 0);
signal pia_pa_in : std_logic_vector( 7 downto 0);
signal pia_pa_out : std_logic_vector( 7 downto 0);
signal pia_pa_oe : std_logic_vector( 7 downto 0);
signal pia_pb_in : std_logic_vector( 7 downto 0);
signal pia_pb_out : std_logic_vector( 7 downto 0);
signal pia_pb_oe : std_logic_vector( 7 downto 0);
signal pia_ca1_in : std_logic;
signal pia_ca2_out : std_logic;
signal pia_cb1_in : std_logic;
signal pia_cb2_out : std_logic;
signal pia_irqa : std_logic;
signal pia_irqb : std_logic;
signal cs_rom : std_logic;
signal cs_ram : std_logic;
signal cs_pia : std_logic;
signal ram_we : std_logic;
signal ram_data_out : std_logic_vector(15 downto 0);
signal romd1 : std_logic;
signal romd : std_logic;
signal rom_addr_out : std_logic_vector(14 downto 1);
signal rom_addr_old : std_logic_vector(14 downto 1);
begin
fx68k_inst: fx68k
port map (
clk => clock_40,
extReset => reset,
pwrUp => reset,
enPhi1 => cpu_ce1,
enPhi2 => cpu_ce2,
eRWn => cpu_rw,
ASn => cpu_as_n,
LDSn => cpu_lds_n,
UDSn => cpu_uds_n,
E => open,
VMAn => open,
FC0 => cpu_fc(0),
FC1 => cpu_fc(1),
FC2 => cpu_fc(2),
BGn => open,
oRESETn => open,
oHALTEDn => open,
DTACKn => cpu_dtack_n,
VPAn => cpu_vpa_n,
BERRn => '1',
BRn => '1',
BGACKn => '1',
IPL0n => '1',
IPL1n => '1',
IPL2n => cpu_ipl2_n,
iEdb => cpu_data_in,
oEdb => cpu_data_out,
eab => cpu_addr
);
-- U6
u_wram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 11)
port map(
clk => clock_40,
we => ram_we and not cpu_uds_n,
addr => cpu_addr(11 downto 1),
d => cpu_data_out(15 downto 8),
q => ram_data_out(15 downto 8)
);
-- U16
l_wram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 11)
port map(
clk => clock_40,
we => ram_we and not cpu_lds_n,
addr => cpu_addr(11 downto 1),
d => cpu_data_out(7 downto 0),
q => ram_data_out(7 downto 0)
);
-- U9
pia6821 : entity work.pia6821
port map (
clk => clock_40,
rst => reset,
cs => cs_pia,
rw => cpu_rw,
addr => cpu_addr(1)&cpu_addr(2), -- wired in reverse order
data_in => cpu_data_out(15 downto 8),
data_out => pia_data_out,
irqa => pia_irqa,
irqb => pia_irqb,
pa_i => pia_pa_in,
pa_o => pia_pa_out,
pa_oe => open,
ca1 => pia_ca1_in,
ca2_i => '0',
ca2_o => open,
ca2_oe => open,
pb_i => pia_pb_in,
pb_o => pia_pb_out,
pb_oe => open,
cb1 => pia_cb1_in,
cb2_i => '0',
cb2_o => open,
cb2_oe => open
);
-- clock enable generation: 40/5 = 8 MHz effective clock (original: 7.5 MHz)
process (clock_40, reset)
begin
if reset = '1' then
cpu_ce1 <= '0';
cpu_ce2 <= '0';
cpu_ce_count <= (others => '0');
elsif rising_edge(clock_40) then
cpu_ce1 <= '0';
cpu_ce2 <= '0';
cpu_ce_count <= cpu_ce_count + 1;
if cpu_ce_count = 2 then
cpu_ce1 <= '1';
end if;
if cpu_ce_count = 4 then
cpu_ce2 <= '1';
cpu_ce_count <= (others => '0');
end if;
end if;
end process;
process (clock_40, reset)
begin
if reset = '1' then
rom_addr_old <= (others => '1');
elsif rising_edge(clock_40) then
rom_addr_old <= rom_addr_out;
-- ROMD signal - DTACK_N delay for ROM access
if cpu_as_n = '1' then
romd1 <= '0';
romd <= '0';
elsif cpu_ce1 = '1' then
romd1 <= '1';
romd <= romd1;
end if;
end if;
end process;
cpu_sel <= '1' when cpu_as_n = '0' and (cpu_uds_n = '0' or cpu_lds_n = '0') else '0';
cpu_dtack_n <= not ((cs_rom and romd) or cs_ram or cs_pia);
-- auto-vectored interrupt handling
cpu_vpa_n <= '0' when cpu_fc = "111" else '1';
cpu_ipl2_n <= not (pia_irqa or pia_irqb);
cs_rom <= '1' when cpu_sel = '1' and cpu_addr(16 downto 15) = "00" else '0';
cs_ram <= '1' when cpu_sel = '1' and cpu_addr(16 downto 14) = "111" else '0';
-- PIA uses 6800 bus cycle originally with VMA, VPA and E clock
cs_pia <= '1' when cpu_sel = '1' and cpu_addr(16 downto 14) = "110" else '0';
ram_we <= '1' when cs_ram = '1' and cpu_rw = '0' else '0';
cpu_data_in <= rom_do when cs_rom = '1' else
ram_data_out when cs_ram = '1' else
pia_data_out&x"FF" when cs_pia = '1' else
(others => '1');
rom_addr_out <= cpu_addr(14 downto 1) when cs_rom = '1' else rom_addr_old;
rom_addr <= rom_addr_out;
audio_out <= pia_pa_out(7 downto 0)&pia_pb_out(7 downto 6);
pia_pb_in(5 downto 0) <= "00"&input(3 downto 0); -- stat1-stat0, sr3-sr0
pia_ca1_in <= not input(4); -- sirq
pia_pa_in <= (others => '0');
pia_cb1_in <= '0'; -- spare
end rtl;

BIN
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/0304-00803-0052.u15
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1
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/82s123.12d
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@@ -1 +0,0 @@
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>m<07><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

24
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_spy_hunter_proms.bat
View File

@@ -1,24 +0,0 @@
copy /B ttprog0.bin + ttprog1.bin + ttprog2.bin + ttprog3.bin + ttprog4.bin + ttprog5.bin + ttprog5.bin ttag_cpu.bin
copy /B ttu7.bin + ttu17.bin + ttu8.bin + ttu18.bin ttag_sound_cpu.bin
make_vhdl_prom ttan.bin ttag_ch_bits.vhd
copy /B ttbg0.bin + ttbg1.bin ttag_bg_bits_1.bin
copy /B ttbg2.bin + ttbg3.bin ttag_bg_bits_2.bin
make_vhdl_prom ttag_bg_bits_1.bin ttag_bg_bits_1.vhd
make_vhdl_prom ttag_bg_bits_2.bin ttag_bg_bits_2.vhd
make_vhdl_prom 82s123.12d midssio_82s123.vhd
copy /B ttfg1.bin + ttfg0.bin ttag_sp_bits_1.bin
copy /B ttfg3.bin + ttfg2.bin ttag_sp_bits_2.bin
copy /B ttfg5.bin + ttfg4.bin ttag_sp_bits_3.bin
copy /B ttfg7.bin + ttfg6.bin ttag_sp_bits_4.bin
copy /b ttag_cpu.bin + ttag_sound_cpu.bin + ttag_sp_bits_1.bin + ttag_sp_bits_2.bin + ttag_sp_bits_3.bin + ttag_sp_bits_4.bin TURBOTAG.ROM
pause

BIN
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/make_vhdl_prom.exe
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BIN
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.bin
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1046
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_1.vhd
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File diff suppressed because it is too large Load Diff

BIN
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.bin
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1046
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_bg_bits_2.vhd
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278
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/unzip/ttag_ch_bits.vhd
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@@ -1,278 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity ttag_ch_bits is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of ttag_ch_bits is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"AB",X"AA",X"AA",X"EA",X"AB",X"AA",X"AF",X"FE",X"AA",X"AA",X"AE",X"EE",X"AE",X"EE",X"AF",X"FE",
X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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25
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/sdram.sv
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@@ -50,6 +50,8 @@ module sdram (
output reg [15:0] cpu1_q,
input [16:1] cpu2_addr,
output reg [15:0] cpu2_q,
input [16:1] cpu3_addr,
output reg [15:0] cpu3_q,
input port2_req,
output reg port2_ack,
@@ -150,9 +152,9 @@ assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch[3];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[2];
reg [16:1] addr_last[4];
reg [16:2] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
@@ -162,14 +164,15 @@ reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_CPU2 = 2'd2;
localparam PORT_SP = 2'd1;
localparam PORT_REQ = 2'd3;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1 = 3'd1;
localparam PORT_CPU2 = 3'd2;
localparam PORT_CPU3 = 3'd3;
localparam PORT_SP = 3'd1;
localparam PORT_REQ = 3'd4;
reg [1:0] next_port[2];
reg [1:0] port[2];
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
@@ -189,6 +192,9 @@ always @(*) begin
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 8'd0, cpu2_addr };
end else if (cpu3_addr != addr_last[PORT_CPU3]) begin
next_port[0] = PORT_CPU3;
addr_latch_next[0] = { 8'd0, cpu3_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
@@ -321,6 +327,7 @@ always @(posedge clk) begin
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_CPU2: begin cpu2_q <= sd_din; end
PORT_CPU3: begin cpu3_q <= sd_din; end
default: ;
endcase;
end

169
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter.vhd → Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag.vhd
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@@ -1,5 +1,5 @@
---------------------------------------------------------------------------------
-- Spy hunter by Dar (darfpga@aol.fr) (06/12/2019)
-- Turbo Tag by Dar (darfpga@aol.fr) (06/12/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
--
@@ -134,68 +134,46 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity spy_hunter is
entity turbo_tag is
port(
clock_40 : in std_logic;
reset : in std_logic;
tv15Khz_mode : in std_logic;
video_r : out std_logic_vector(2 downto 0);
video_g : out std_logic_vector(2 downto 0);
video_b : out std_logic_vector(2 downto 0);
video_clk : out std_logic;
video_csync : out std_logic;
video_blankn : out std_logic;
video_hs : out std_logic;
video_vs : out std_logic;
separate_audio : in std_logic;
audio_out_l : out std_logic_vector(15 downto 0);
audio_out_r : out std_logic_vector(15 downto 0);
coin1 : in std_logic;
coin2 : in std_logic;
shift : in std_logic;
oil : in std_logic;
missile : in std_logic;
van : in std_logic;
smoke : in std_logic;
gun : in std_logic;
-- lamp_oil : out std_logic;
-- lamp_missile : out std_logic;
-- lamp_van : out std_logic;
-- lamp_smoke : out std_logic;
-- lamp_gun : out std_logic;
steering : in std_logic_vector(7 downto 0);
gas : in std_logic_vector(7 downto 0);
service : in std_logic;
-- sp_rom_addr : out std_logic_vector(17 downto 0); -- shall contains 1-2-3-4 rom order and 4-3-2-1 rom order
-- sp_rom_rd : out std_logic;
-- sp_graphx0 : in std_logic_vector(31 downto 0);
-- sp_graphx1 : in std_logic_vector(31 downto 0);
-- sp_graphx2 : in std_logic_vector(31 downto 0);
-- sp_graphx3 : in std_logic_vector(31 downto 0);
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
snd_rom_addr : out std_logic_vector(12 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0);
sp_addr : out std_logic_vector(14 downto 0);
-- sp_graphx_do : in std_logic_vector(7 downto 0);
sp_graphx32_do : in std_logic_vector(31 downto 0);
clock_40 : in std_logic;
reset : in std_logic;
tv15Khz_mode : in std_logic;
video_r : out std_logic_vector(2 downto 0);
video_g : out std_logic_vector(2 downto 0);
video_b : out std_logic_vector(2 downto 0);
video_clk : out std_logic;
video_csync : out std_logic;
video_blankn : out std_logic;
video_hs : out std_logic;
video_vs : out std_logic;
separate_audio : in std_logic;
audio_out_l : out std_logic_vector(15 downto 0);
audio_out_r : out std_logic_vector(15 downto 0);
csd_audio_out : out std_logic_vector( 9 downto 0);
start1 : in std_logic;
start2 : in std_logic;
coin1 : in std_logic;
coin2 : in std_logic;
shift : in std_logic;
left : in std_logic;
center : in std_logic;
right : in std_logic;
gas : in std_logic_vector(7 downto 0);
steering : in std_logic_vector(7 downto 0);
service : in std_logic;
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
csd_rom_addr : out std_logic_vector(14 downto 1);
csd_rom_do : in std_logic_vector(15 downto 0);
sp_addr : out std_logic_vector(14 downto 0);
sp_graphx32_do : in std_logic_vector(31 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end spy_hunter;
end turbo_tag;
architecture struct of spy_hunter is
architecture struct of turbo_tag is
signal reset_n : std_logic;
signal clock_vid : std_logic;
@@ -363,17 +341,6 @@ clock_vid <= clock_40;
clock_vidn <= not clock_40;
reset_n <= not reset;
-- debug
process (reset, clock_vid)
begin
if rising_edge(clock_vid) then -- and cpu_ena ='1' and cpu_mreq_n ='0' then
--dbg_cpu_addr<= cpu_addr;
--dbg_cpu_addr<= "000000000000000" & service; --cpu_addr;
--dbg_cpu_addr<= max_sprite_rr & "0000000" & service; --cpu_addr;
dbg_cpu_addr <= steering & gas;
end if;
end process;
-- make enables clock from clock_vid
process (clock_vid, reset)
begin
@@ -512,11 +479,12 @@ end process;
--------------------
-- "11" for test & tilt & unused
input_0 <= not service & "11" & not shift & "11" & not coin2 & not coin1;
input_1 <= "111" & not gun & not smoke & not van & not missile & not oil;
input_1 <= not service & "11" & not right & not start2 & not center & not left & not start1;
input_2 <= steering when output_4(7) = '1' else gas;
input_3 <= x"FF";
input_4 <= x"FF";
-- ssio ouput_4 :
-- OP4 bit 0/3 J5-10/13 md0/3 (to cheap squeak deluxe and lamps)
-- OP4 bit 4 J5-14 st0 (to cheap squeak deluxe)
@@ -524,8 +492,6 @@ input_4 <= x"FF";
-- OP4 bit 6 J5-16 ard (to absolute position)
-- OP4 bit 7 J5-17 sel (to absolute position)
------------------------------------------
-- cpu data input with address decoding --
------------------------------------------
@@ -543,7 +509,7 @@ cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E
ctc_counter_0_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else
X"FF";
cpu_rom_addr <= cpu_addr;-- when cpu_addr < x"A000" else cpu_addr xor x"6000"; -- last rom has upper/lower part swapped - not needed here
cpu_rom_addr <= cpu_addr when cpu_addr < x"A000" else cpu_addr xor x"6000"; -- last rom has upper/lower part swapped
------------------------------------------
-- write enable / ram access from CPU --
@@ -727,7 +693,7 @@ begin
if pix_ena = '1' then
if hcnt(0) = '1' then
if hcnt(3 downto 1) = "111" then -- normal text
if hcnt(3 downto 1) = "111" then
ch_code <= ch_ram_do;
end if;
@@ -810,9 +776,7 @@ begin
if rising_edge(clock_vid) then
video_g <= palette_do(2 downto 0);
video_b <= palette_do(5 downto 3);
video_r <= palette_do(8 downto 6);
video_r <= palette_do(8 downto 6);
case ch_color is
when "01" =>
video_g <= "111";
@@ -948,6 +912,14 @@ port map(
);
-- cpu program ROM 0x0000-0xDFFF
--rom_cpu : entity work.spy_hunter_cpu
--port map(
-- clk => clock_vidn,
-- addr => cpu_rom_addr,
-- data => cpu_rom_do
--);
-- working RAM F000-F7FF 2Ko
wram : entity work.cmos_ram
generic map( dWidth => 8, aWidth => 11)
@@ -1060,7 +1032,7 @@ bg_graphics_1 : entity work.ttag_bg_bits_1
port map(
clk => clock_vidn,
addr => bg_code_line,
data => bg_graphx2_do
data => bg_graphx1_do
);
-- background graphics ROM 5A/6A
@@ -1068,11 +1040,22 @@ bg_graphics_2 : entity work.ttag_bg_bits_2
port map(
clk => clock_vidn,
addr => bg_code_line,
data => bg_graphx1_do
data => bg_graphx2_do
);
-- background & sprite palette
palette : entity work.gen_ram
generic map( dWidth => 9, aWidth => 6)
port map(
clk => clock_vidn,
we => palette_we,
addr => palette_addr,
d => cpu_addr(0) & cpu_do,
q => palette_do
);
-- Spy hunter sound board
sound_board : entity work.spy_hunter_sound_board
sound_board : entity work.turbo_tag_sound_board
port map(
clock_40 => clock_40,
reset => reset,
@@ -1090,25 +1073,21 @@ port map(
input_4 => input_4,
output_4 => output_4,
cpu_rom_addr => snd_rom_addr,
cpu_rom_do => snd_rom_do,
separate_audio => separate_audio,
audio_out_l => audio_out_l,
audio_out_r => audio_out_r,
dbg_cpu_addr => open --dbg_cpu_addr
audio_out_r => audio_out_r
);
-- background & sprite palette
palette : entity work.gen_ram
generic map( dWidth => 9, aWidth => 6)
port map(
clk => clock_vidn,
we => palette_we,
addr => palette_addr,
d => cpu_addr(0) & cpu_do,
q => palette_do
-- Cheap Squeak Deluxe
csd: entity work.cheap_squeak_deluxe
port map (
clock_40 => clock_40,
reset => reset,
input => output_4,
rom_addr => csd_rom_addr,
rom_do => csd_rom_do,
audio_out => csd_audio_out
);
end struct;

14
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_control.vhd → Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_control.vhd
View File

@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity spy_hunter_control is
entity turbo_tag_control is
port(
clock_40 : in std_logic;
reset : in std_logic;
@@ -16,10 +16,10 @@ port(
steering : out std_logic_vector(7 downto 0);
gas : out std_logic_vector(7 downto 0)
);
end spy_hunter_control;
end turbo_tag_control;
architecture struct of spy_hunter_control is
architecture struct of turbo_tag_control is
signal steering_r : std_logic_vector(7 downto 0);
--signal steering_plus : std_logic;
signal steering_plus_r : std_logic;
@@ -35,6 +35,14 @@ architecture struct of spy_hunter_control is
signal gas_timer : std_logic_vector(5 downto 0);
signal vsync_r : std_logic;
begin-- absolute position decoder simulation
--spy PORT_BIT( 0xff, 0x30, IPT_PEDAL ) PORT_MINMAX(0x30,0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
--tag PORT_BIT( 0xff, 0x3c, IPT_PEDAL ) PORT_MINMAX(60,180) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) 0x3c,0xb4
--spy PORT_BIT( 0xff, 0x74, IPT_PADDLE ) PORT_MINMAX(0x34,0xb4) PORT_SENSITIVITY(40) PORT_KEYDELTA(10)
--tag PORT_BIT( 0xff, 0x60, IPT_PADDLE ) PORT_SENSITIVITY(40) PORT_KEYDELTA(10)
--
-- steering :
-- thresholds median

16
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spy_hunter_sound_board.vhd → Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_sound_board.vhd
View File

@@ -1,5 +1,5 @@
---------------------------------------------------------------------------------
-- Timber sound board by Dar (darfpga@aol.fr) (19/10/2019)
-- turbo_tag sound board by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- gen_ram.vhd & io_ps2_keyboard
@@ -52,7 +52,7 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity spy_hunter_sound_board is
entity turbo_tag_sound_board is
port(
clock_40 : in std_logic;
reset : in std_logic;
@@ -70,18 +70,16 @@ port(
input_4 : in std_logic_vector(7 downto 0);
output_4 : out std_logic_vector(7 downto 0);
cpu_rom_addr : out std_logic_vector(12 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
separate_audio : in std_logic;
audio_out_l : out std_logic_vector(15 downto 0);
audio_out_r : out std_logic_vector(15 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end spy_hunter_sound_board;
end turbo_tag_sound_board;
architecture struct of spy_hunter_sound_board is
architecture struct of turbo_tag_sound_board is
signal reset_n : std_logic;
signal clock_snd : std_logic;
@@ -216,7 +214,7 @@ ena_4Mhz <= '1' when clock_cnt1 = "00000" or
------------------------------------------
-- cpu data input with address decoding --
------------------------------------------
cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF
cpu_di <= --cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF
wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"8" else -- 0x8000-0x83FF
iram_0_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9000" else
iram_1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9001" else
@@ -444,8 +442,8 @@ port map(
-- addr => cpu_addr(12 downto 0),
-- data => cpu_rom_do
--);
--cpu_rom_addr <= cpu_addr(12 downto 0);
--cpu_rom_addr <= cpu_addr(12 downto 0);
-- working RAM 0x8000-0x83FF
wram : entity work.gen_ram

BIN
Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/Release/Popeye.rbf
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27
Arcade_MiST/Nintendo Popeye Hardware/Popeye_MiST/rtl/popeye.vhd
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@@ -120,6 +120,7 @@ architecture struct of popeye is
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_wr_n : std_logic;
signal cpu_wr_n_r : std_logic;
signal cpu_rd_n : std_logic;
signal cpu_mreq_n : std_logic;
signal cpu_ioreq_n : std_logic;
@@ -234,6 +235,12 @@ architecture struct of popeye is
signal ay_iob_do : std_logic_vector(7 downto 0);
signal ay_ioa_di : std_logic_vector(7 downto 0);
signal protection_data0 : std_logic_vector(7 downto 0);
signal protection_data1 : std_logic_vector(7 downto 0);
signal protection_do : std_logic_vector(7 downto 0);
signal protection_shift : std_logic_vector(2 downto 0);
begin
@@ -415,8 +422,19 @@ cpu_rom_do_swp <=
cpu_rom_do(3) & cpu_rom_do(4) & cpu_rom_do(2) & cpu_rom_do(5) &
cpu_rom_do(1) & cpu_rom_do(6) & cpu_rom_do(0) & cpu_rom_do(7);
protection_do <=
(protection_data1(7 downto 0) ) or ( "00000000" ) when protection_shift = "000" else
(protection_data1(6 downto 0) & '0' ) or ( "0000000" & protection_data0(7 downto 7)) when protection_shift = "001" else
(protection_data1(5 downto 0) & "00" ) or ( "000000" & protection_data0(7 downto 6)) when protection_shift = "010" else
(protection_data1(4 downto 0) & "000" ) or ( "00000" & protection_data0(7 downto 5)) when protection_shift = "011" else
(protection_data1(3 downto 0) & "0000" ) or ( "0000" & protection_data0(7 downto 4)) when protection_shift = "100" else
(protection_data1(2 downto 0) & "00000" ) or ( "000" & protection_data0(7 downto 3)) when protection_shift = "101" else
(protection_data1(1 downto 0) & "000000" ) or ( "00" & protection_data0(7 downto 2)) when protection_shift = "110" else
(protection_data1(0 downto 0) & "0000000" ) or ( '0' & protection_data0(7 downto 1)); -- protection_shift = "111"
cpu_di <= cpu_rom_do_swp when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"8" else -- program rom 0000-7FFF 32Ko
wram_do_r when cpu_mreq_n = '0' and (cpu_addr and X"E000") = x"8000" else -- work ram 8000-87FF 2Ko + mirroring 1800
protection_do when cpu_mreq_n = '0' and (cpu_addr and X"FFFF") = x"E000" else -- protection E000
input_0 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "00") else
input_1 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "01") else
input_2 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "10") else
@@ -487,7 +505,7 @@ end process;
process (clock_vid)
begin
if rising_edge(clock_vid) then
cpu_wr_n_r <= cpu_wr_n;
if cpu_mreq_n = '0' and cpu_wr_n = '0' then
if (cpu_addr = x"8C00") then hoffset <= cpu_do; end if;
if (cpu_addr = x"8C01") then voffset <= cpu_do; end if;
@@ -497,10 +515,15 @@ begin
bg_palette_addr(4) <= cpu_do(3);
end if;
end if;
if (cpu_addr = x"E000") then protection_shift <= cpu_do(2 downto 0); end if;
if (cpu_addr = x"E001") and cpu_wr_n_r = '1' then
protection_data0 <= protection_data1;
protection_data1 <= cpu_do;
end if;
end if;
end process;
cpu_nmi_n <= video_vs;
audio_out <= ay_audio & X"00";

1
Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/SkySkipper.qsf
View File

@@ -239,5 +239,4 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name VERILOG_FILE rtl/jtpopeye_security.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

56
Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/SkySkipper.vhd
View File

@@ -121,6 +121,7 @@ architecture struct of SkySkipper is
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_wr_n : std_logic;
signal cpu_wr_n_r : std_logic;
signal cpu_rd_n : std_logic;
signal cpu_mreq_n : std_logic;
signal cpu_ioreq_n : std_logic;
@@ -235,23 +236,11 @@ architecture struct of SkySkipper is
signal ay_iob_do : std_logic_vector(7 downto 0);
signal ay_ioa_di : std_logic_vector(7 downto 0);
signal sec_cs : std_logic;
signal sec_we : std_logic;
signal sec_data : std_logic_vector(7 downto 0);
COMPONENT jtpopeye_security
PORT
(
clk : IN STD_LOGIC;
cen : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cs : IN STD_LOGIC;
A0 : IN STD_LOGIC;
rd_n : IN STD_LOGIC;
wr_n : IN STD_LOGIC
);
END COMPONENT;
signal protection_data0 : std_logic_vector(7 downto 0);
signal protection_data1 : std_logic_vector(7 downto 0);
signal protection_do : std_logic_vector(7 downto 0);
signal protection_shift : std_logic_vector(2 downto 0);
begin
@@ -430,10 +419,19 @@ cpu_rom_addr <= (cpu_addr(14 downto 10) & cpu_addr(8 downto 7) & cpu_addr(0) & c
cpu_rom_do(3) & cpu_rom_do(4) & cpu_rom_do(2) & cpu_rom_do(5) &
cpu_rom_do(1) & cpu_rom_do(6) & cpu_rom_do(0) & cpu_rom_do(7);
protection_do <=
(protection_data1(7 downto 0) ) or ( "00000000" ) when protection_shift = "000" else
(protection_data1(6 downto 0) & '0' ) or ( "0000000" & protection_data0(7 downto 7)) when protection_shift = "001" else
(protection_data1(5 downto 0) & "00" ) or ( "000000" & protection_data0(7 downto 6)) when protection_shift = "010" else
(protection_data1(4 downto 0) & "000" ) or ( "00000" & protection_data0(7 downto 5)) when protection_shift = "011" else
(protection_data1(3 downto 0) & "0000" ) or ( "0000" & protection_data0(7 downto 4)) when protection_shift = "100" else
(protection_data1(2 downto 0) & "00000" ) or ( "000" & protection_data0(7 downto 3)) when protection_shift = "101" else
(protection_data1(1 downto 0) & "000000" ) or ( "00" & protection_data0(7 downto 2)) when protection_shift = "110" else
(protection_data1(0 downto 0) & "0000000" ) or ( '0' & protection_data0(7 downto 1)); -- protection_shift = "111"
cpu_di <= cpu_rom_do_swp when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"8" else -- program rom 0000-7FFF 32Ko
wram_do_r when cpu_mreq_n = '0' and (cpu_addr and X"E000") = x"8000" else -- work ram 8000-87FF 2Ko + mirroring 1800
-- sec_data when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"E" else
sec_data when cpu_mreq_n = '0' and cpu_addr(15 downto 0) = "1110000000000001" else
protection_do when cpu_mreq_n = '0' and (cpu_addr and X"FFFF") = x"E000" else -- protection E000
input_0 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "00") else
input_1 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "01") else
input_2 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "10") else
@@ -450,8 +448,6 @@ ch_ram_txt_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr an
ch_ram_color_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"EC00") = x"A400" and hcnt(0) = '0' else '0';
bg_ram_lnib_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F000") = x"C000" and hcnt(0) = '0' else '0';
bg_ram_hnib_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F000") = x"D000" and hcnt(0) = '0' else '0';--not needed
--sec_cs <= '1' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"E" else '0';
sec_cs <= '1' when cpu_addr(15 downto 0) = "1110000000000001" else '0';
-----------------------------------------------------
-- Transfer sprite data from wram to sprite ram
-- once per frame. Read sprite ram on every scanline.
@@ -505,7 +501,7 @@ end process;
process (clock_vid)
begin
if rising_edge(clock_vid) then
cpu_wr_n_r <= cpu_wr_n;
if cpu_mreq_n = '0' and cpu_wr_n = '0' then
if (cpu_addr = x"8C00") then hoffset <= cpu_do; end if;
if (cpu_addr = x"8C01") then voffset <= cpu_do; end if;
@@ -515,7 +511,11 @@ begin
bg_palette_addr(4) <= cpu_do(3);
end if;
end if;
if (cpu_addr = x"E000") then protection_shift <= cpu_do(2 downto 0); end if;
if (cpu_addr = x"E001") and cpu_wr_n_r = '1' then
protection_data0 <= protection_data1;
protection_data1 <= cpu_do;
end if;
end if;
end process;
@@ -977,16 +977,4 @@ port map (
CLK => clock_vid --: in std_logic -- note 6 Mhz!
);
sec : jtpopeye_security
port map (
clk => clock_vid,
cen => cpu_ena,
din => cpu_do,
dout => sec_data,
rd_n => cpu_rd_n,
wr_n => cpu_wr_n,
cs => sec_cs,
A0 => cpu_addr(0)
);
end;

96
Arcade_MiST/Nintendo Popeye Hardware/SkySkipper_MiST/rtl/jtpopeye_security.v
View File

@@ -1,96 +0,0 @@
/* This file is part of JTPOPEYE.
JTPOPEYE program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JTPOPEYE program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR AD PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JTPOPEYE. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 12-3-2019 */
`timescale 1ns/1ps
// 7J: '139 decoder
// /MemWR and /MemRD serve as enable signals. If H all outputs will be H
//
// /OE is the same as addr1
// Mode is the same addr0. Mode pin is not used in this model.
//
// CPU || /MemWR || /MemRD
// /sec_cs addr0 || A[1:0] || /OE || Mode
// ===========================================
// 0 0 || 10 || 1 || 0
// 0 1 || 01 || 0 || 1
// 1 x || 11 || 1 || 1
// based on code provided by www.JAMMARCADE.net
module jtpopeye_security(
input clk,
input cen,
input [7:0] din,
output reg [7:0] dout,
input cs,
input A0,
input rd_n,
input wr_n
);
reg [7:0] fifo [1:0];
reg [2:0] shift;
reg last_addr0, last_addr1;
reg addr0, addr1, oen;
wire csn = ~cs;
reg [7:0] result;
always @(*) begin
addr0 = 1'b1;
addr1 = 1'b1;
oen = 1'b1;
// mode = 1'b1;
if( csn ) begin
if(!wr_n) begin
addr0 = A0;
addr1 = ~A0;
end
if(!rd_n) begin
oen = A0;
//mode = ~A0;
end
end
// dout = result;
// dout = A0 ? 8'd0 : result;
end
always @(posedge clk) if(cen) begin
// if( !addr0 )
// shift <= din[2:0];
// if( !addr1 ) begin
// fifo[0] <= fifo[1];
// fifo[1] <= din;
// end
if( cs && !wr_n ) begin
if( A0 ) begin
fifo[0] <= fifo[1];
fifo[1] <= din;
end else begin
shift <= din[2:0];
end
end
result <= (fifo[1] << shift) | (fifo[0] >> (4'd8-{1'b0,shift}));
// dout <= { result[7:3], A0 ? 3'd0 : result[2:0] };
if( cs && !rd_n) dout <= A0 ? 8'd0 : result;
end
endmodule