mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-13 07:09:49 +00:00
Sync
This commit is contained in:
parent
52e96079b7
commit
f4ef413666
38
Arcade_MiST/Namco Super Pacman Hardware/meta/Grobda.mra
Normal file
38
Arcade_MiST/Namco Super Pacman Hardware/meta/Grobda.mra
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
<misterromdescription>
|
||||||
|
<name>Grobda</name>
|
||||||
|
<mameversion>0220</mameversion>
|
||||||
|
<setname>grobda</setname>
|
||||||
|
<mratimestamp>20210307</mratimestamp>
|
||||||
|
<rbf>druaga</rbf>
|
||||||
|
<rom index="1">
|
||||||
|
<part>05</part>
|
||||||
|
</rom>
|
||||||
|
<rom index="0" zip="grobda.zip" md5="None">
|
||||||
|
<!-- main CPU -->
|
||||||
|
<part repeat="0x2000"> FF </part>
|
||||||
|
<part name="gr2-3.1d"/>
|
||||||
|
<part name="gr2-2.1c"/>
|
||||||
|
<part name="gr2-1.1b"/>
|
||||||
|
|
||||||
|
<!-- GFX2 -->
|
||||||
|
<part name="gr1-5.3f"/>
|
||||||
|
<part name="gr1-6.3e"/>
|
||||||
|
<part name="gr1-5.3f"/>
|
||||||
|
<part name="gr1-6.3e"/>
|
||||||
|
|
||||||
|
<!-- sound CPU -->
|
||||||
|
<part name="gr1-4.1k"/>
|
||||||
|
|
||||||
|
<!-- GFX1 -->
|
||||||
|
<part name="gr1-7.3c"/>
|
||||||
|
|
||||||
|
<part name="gr1-4.3l"/>
|
||||||
|
<part name="gr1-4.3l"/>
|
||||||
|
<part name="gr1-4.3l"/>
|
||||||
|
<part name="gr1-4.3l"/>
|
||||||
|
|
||||||
|
<part name="gr1-5.4e"/>
|
||||||
|
<part name="gr1-3.3m"/>
|
||||||
|
<part name="gr1-6.4c"/>
|
||||||
|
</rom>
|
||||||
|
</misterromdescription>
|
||||||
39
Arcade_MiST/Namco Super Pacman Hardware/meta/Pac n Pal.mra
Normal file
39
Arcade_MiST/Namco Super Pacman Hardware/meta/Pac n Pal.mra
Normal file
@ -0,0 +1,39 @@
|
|||||||
|
<misterromdescription>
|
||||||
|
<name>Pac & Pal</name>
|
||||||
|
<mameversion>0220</mameversion>
|
||||||
|
<setname>pacnpal</setname>
|
||||||
|
<mratimestamp>20210307</mratimestamp>
|
||||||
|
<rbf>druaga</rbf>
|
||||||
|
<rom index="1">
|
||||||
|
<part>05</part>
|
||||||
|
</rom>
|
||||||
|
<rom index="0" zip="pacnpal.zip" md5="None">
|
||||||
|
<!-- main CPU -->
|
||||||
|
<part repeat="0x2000"> FF </part>
|
||||||
|
<part name="pap1-3b.1d"/>
|
||||||
|
<part name="pap1-2b.1c"/>
|
||||||
|
<part name="pap3-1.1b"/>
|
||||||
|
|
||||||
|
<!-- GFX2 -->
|
||||||
|
<part name="pap1-5.3f"/>
|
||||||
|
<part name="pap1-5.3f"/>
|
||||||
|
<part name="pap1-5.3f"/>
|
||||||
|
<part name="pap1-5.3f"/>
|
||||||
|
|
||||||
|
<!-- sound CPU -->
|
||||||
|
<part repeat="0x1000"> FF </part>
|
||||||
|
<part name="pap1-4.1k"/>
|
||||||
|
|
||||||
|
<!-- GFX1 -->
|
||||||
|
<part name="pap1-6.3c"/>
|
||||||
|
|
||||||
|
<part name="pap1-4.3l"/>
|
||||||
|
<part name="pap1-4.3l"/>
|
||||||
|
<part name="pap1-4.3l"/>
|
||||||
|
<part name="pap1-4.3l"/>
|
||||||
|
|
||||||
|
<part name="pap1-5.4e"/>
|
||||||
|
<part name="pap1-3.3m"/>
|
||||||
|
<part name="pap1-6.4c"/>
|
||||||
|
</rom>
|
||||||
|
</misterromdescription>
|
||||||
@ -18,7 +18,7 @@
|
|||||||
#
|
#
|
||||||
# Quartus II 64-Bit
|
# Quartus II 64-Bit
|
||||||
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
|
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||||
# Date created = 20:10:17 February 28, 2021
|
# Date created = 00:42:55 March 05, 2021
|
||||||
#
|
#
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
#
|
#
|
||||||
@ -46,7 +46,7 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|||||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||||
set_global_assignment -name SMART_RECOMPILE ON
|
set_global_assignment -name SMART_RECOMPILE ON
|
||||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/CannelF_MiST.sv
|
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ChannelF_MiST.sv
|
||||||
set_global_assignment -name VHDL_FILE rtl/channel_f.vhd
|
set_global_assignment -name VHDL_FILE rtl/channel_f.vhd
|
||||||
set_global_assignment -name VHDL_FILE rtl/f8_cpu.vhd
|
set_global_assignment -name VHDL_FILE rtl/f8_cpu.vhd
|
||||||
set_global_assignment -name VHDL_FILE rtl/f8_psu.vhd
|
set_global_assignment -name VHDL_FILE rtl/f8_psu.vhd
|
||||||
@ -99,10 +99,10 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
|||||||
# Analysis & Synthesis Assignments
|
# Analysis & Synthesis Assignments
|
||||||
# ================================
|
# ================================
|
||||||
set_global_assignment -name FAMILY "Cyclone III"
|
set_global_assignment -name FAMILY "Cyclone III"
|
||||||
set_global_assignment -name TOP_LEVEL_ENTITY CannelF_MiST
|
|
||||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||||
|
set_global_assignment -name TOP_LEVEL_ENTITY ChannelF_MiST
|
||||||
|
|
||||||
# Fitter Assignments
|
# Fitter Assignments
|
||||||
# ==================
|
# ==================
|
||||||
@ -142,8 +142,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
|||||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||||
|
|
||||||
# --------------------------
|
# ---------------------------
|
||||||
# start ENTITY(CannelF_MiST)
|
# start ENTITY(ChannelF_MiST)
|
||||||
|
|
||||||
# start DESIGN_PARTITION(Top)
|
# start DESIGN_PARTITION(Top)
|
||||||
# ---------------------------
|
# ---------------------------
|
||||||
@ -157,6 +157,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
|
|||||||
# end DESIGN_PARTITION(Top)
|
# end DESIGN_PARTITION(Top)
|
||||||
# -------------------------
|
# -------------------------
|
||||||
|
|
||||||
# end ENTITY(CannelF_MiST)
|
# end ENTITY(ChannelF_MiST)
|
||||||
# ------------------------
|
# -------------------------
|
||||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||||
Binary file not shown.
@ -1,173 +0,0 @@
|
|||||||
module CannelF_MiST(
|
|
||||||
output LED,
|
|
||||||
output [5:0] VGA_R,
|
|
||||||
output [5:0] VGA_G,
|
|
||||||
output [5:0] VGA_B,
|
|
||||||
output VGA_HS,
|
|
||||||
output VGA_VS,
|
|
||||||
output AUDIO_L,
|
|
||||||
output AUDIO_R,
|
|
||||||
input SPI_SCK,
|
|
||||||
output SPI_DO,
|
|
||||||
input SPI_DI,
|
|
||||||
input SPI_SS2,
|
|
||||||
input SPI_SS3,
|
|
||||||
input CONF_DATA0,
|
|
||||||
input CLOCK_27
|
|
||||||
);
|
|
||||||
|
|
||||||
`include "rtl\build_id.v"
|
|
||||||
|
|
||||||
localparam CONF_STR = {
|
|
||||||
"ChannelF;BINCHF;",
|
|
||||||
"O1,Swap Joystick,Off,On;",
|
|
||||||
"O34,Scanlines,Off,25%,50%,75%;",
|
|
||||||
"O6,Blending,Off,On;",
|
|
||||||
"T0,Reset;",
|
|
||||||
"V,v1.00.",`BUILD_DATE
|
|
||||||
};
|
|
||||||
|
|
||||||
assign LED = ~ioctl_downl;
|
|
||||||
assign AUDIO_R = AUDIO_L;
|
|
||||||
|
|
||||||
wire pll_locked,clock_48, clk3p579;
|
|
||||||
pll pll(
|
|
||||||
.locked(pll_locked),
|
|
||||||
.inclk0(CLOCK_27),
|
|
||||||
.c0(clock_48),
|
|
||||||
.c1(clk3p579)//3.579545
|
|
||||||
);
|
|
||||||
// NTSC : 3.579545MHz * 12 = 42.95454MHz
|
|
||||||
// PAL : 4MHz * 12 = 48MHz
|
|
||||||
|
|
||||||
channel_f channel_f(
|
|
||||||
.clk(clk3p579),
|
|
||||||
.reset(status[0] | buttons[1]),
|
|
||||||
.pll_locked(pll_locked),
|
|
||||||
.vga_r(r),
|
|
||||||
.vga_g(g),
|
|
||||||
.vga_b(b),
|
|
||||||
.vga_hs(hs),
|
|
||||||
.vga_vs(vs),
|
|
||||||
.vga_de(blankn),
|
|
||||||
.Keys({m_four_players, m_three_players, m_two_players, m_one_player}),
|
|
||||||
.joystick_0({m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right}),
|
|
||||||
.joystick_1({m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2}),
|
|
||||||
.ioctl_download(ioctl_downl),
|
|
||||||
.ioctl_index(ioctl_index),
|
|
||||||
.ioctl_wr(~ioctl_wr),//todo
|
|
||||||
.ioctl_addr(ioctl_addr),
|
|
||||||
.ioctl_dout(ioctl_dout),
|
|
||||||
// .ioctl_wait(ioctl_wait),
|
|
||||||
.audio(audio)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
wire ioctl_downl;
|
|
||||||
wire [7:0] ioctl_index;
|
|
||||||
wire ioctl_wr;
|
|
||||||
wire [24:0] ioctl_addr;
|
|
||||||
wire [7:0] ioctl_dout;
|
|
||||||
|
|
||||||
data_io data_io(
|
|
||||||
.clk_sys ( clock_48 ),
|
|
||||||
.SPI_SCK ( SPI_SCK ),
|
|
||||||
.SPI_SS2 ( SPI_SS2 ),
|
|
||||||
.SPI_DI ( SPI_DI ),
|
|
||||||
.ioctl_download( ioctl_downl ),
|
|
||||||
.ioctl_index ( ioctl_index ),
|
|
||||||
.ioctl_wr ( ioctl_wr ),
|
|
||||||
.ioctl_addr ( ioctl_addr ),
|
|
||||||
.ioctl_dout ( ioctl_dout )
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(10)) mist_video(
|
|
||||||
.clk_sys(clock_48),
|
|
||||||
.SPI_SCK(SPI_SCK),
|
|
||||||
.SPI_SS3(SPI_SS3),
|
|
||||||
.SPI_DI(SPI_DI),
|
|
||||||
.R(blankn ? r[7:2] : 0),
|
|
||||||
.G(blankn ? g[7:2] : 0),
|
|
||||||
.B(blankn ? b[7:2] : 0),
|
|
||||||
.HSync(hs),
|
|
||||||
.VSync(vs),
|
|
||||||
.VGA_R(VGA_R),
|
|
||||||
.VGA_G(VGA_G),
|
|
||||||
.VGA_B(VGA_B),
|
|
||||||
.VGA_VS(VGA_VS),
|
|
||||||
.VGA_HS(VGA_HS),
|
|
||||||
.ce_divider(1'b0),
|
|
||||||
.blend(status[6]),
|
|
||||||
.scandoubler_disable(scandoublerD),
|
|
||||||
.scanlines(status[4:3]),
|
|
||||||
.ypbpr(ypbpr),
|
|
||||||
.no_csync(no_csync)
|
|
||||||
);
|
|
||||||
|
|
||||||
wire [31:0] status;
|
|
||||||
wire [1:0] buttons;
|
|
||||||
wire [1:0] switches;
|
|
||||||
wire [31:0] joystick_0;
|
|
||||||
wire [31:0] joystick_1;
|
|
||||||
wire scandoublerD;
|
|
||||||
wire [7:0] r, g, b;
|
|
||||||
wire hs, vs, blankn;
|
|
||||||
wire [15:0] audio;
|
|
||||||
wire ypbpr;
|
|
||||||
wire no_csync;
|
|
||||||
wire key_strobe;
|
|
||||||
wire key_pressed;
|
|
||||||
wire [7:0] key_code;
|
|
||||||
|
|
||||||
user_io #(
|
|
||||||
.STRLEN(($size(CONF_STR)>>3)))
|
|
||||||
user_io(
|
|
||||||
.clk_sys (clock_48 ),
|
|
||||||
.conf_str (CONF_STR ),
|
|
||||||
.SPI_CLK (SPI_SCK ),
|
|
||||||
.SPI_SS_IO (CONF_DATA0 ),
|
|
||||||
.SPI_MISO (SPI_DO ),
|
|
||||||
.SPI_MOSI (SPI_DI ),
|
|
||||||
.buttons (buttons ),
|
|
||||||
.switches (switches ),
|
|
||||||
.scandoubler_disable (scandoublerD),
|
|
||||||
.ypbpr (ypbpr ),
|
|
||||||
.no_csync (no_csync ),
|
|
||||||
.key_strobe (key_strobe ),
|
|
||||||
.key_pressed (key_pressed ),
|
|
||||||
.key_code (key_code ),
|
|
||||||
.joystick_0 (joystick_0 ),
|
|
||||||
.joystick_1 (joystick_1 ),
|
|
||||||
.status (status )
|
|
||||||
);
|
|
||||||
|
|
||||||
dac #(
|
|
||||||
.C_bits(16))
|
|
||||||
dac(
|
|
||||||
.clk_i(clock_48),
|
|
||||||
.res_n_i(1'b1),
|
|
||||||
.dac_i(audio),
|
|
||||||
.dac_o(AUDIO_L)
|
|
||||||
);
|
|
||||||
|
|
||||||
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
|
|
||||||
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
|
|
||||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
|
||||||
|
|
||||||
arcade_inputs inputs (
|
|
||||||
.clk ( clock_48 ),
|
|
||||||
.key_strobe ( key_strobe ),
|
|
||||||
.key_pressed ( key_pressed ),
|
|
||||||
.key_code ( key_code ),
|
|
||||||
.joystick_0 ( joystick_0 ),
|
|
||||||
.joystick_1 ( joystick_1 ),
|
|
||||||
.rotate ( 0 ),
|
|
||||||
.orientation ( 2'b00 ),
|
|
||||||
.joyswap ( status[1] ),
|
|
||||||
.oneplayer ( 1'b0 ),
|
|
||||||
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
|
|
||||||
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
|
|
||||||
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
|
|
||||||
);
|
|
||||||
endmodule
|
|
||||||
178
Console_MiST/ChannelF_MiST/rtl/ChannelF_MiST.sv
Normal file
178
Console_MiST/ChannelF_MiST/rtl/ChannelF_MiST.sv
Normal file
@ -0,0 +1,178 @@
|
|||||||
|
module ChannelF_MiST(
|
||||||
|
output LED,
|
||||||
|
output [5:0] VGA_R,
|
||||||
|
output [5:0] VGA_G,
|
||||||
|
output [5:0] VGA_B,
|
||||||
|
output VGA_HS,
|
||||||
|
output VGA_VS,
|
||||||
|
output AUDIO_L,
|
||||||
|
output AUDIO_R,
|
||||||
|
input SPI_SCK,
|
||||||
|
output SPI_DO,
|
||||||
|
input SPI_DI,
|
||||||
|
input SPI_SS2,
|
||||||
|
input SPI_SS3,
|
||||||
|
input CONF_DATA0,
|
||||||
|
input CLOCK_27
|
||||||
|
);
|
||||||
|
|
||||||
|
`include "rtl\build_id.v"
|
||||||
|
|
||||||
|
localparam CONF_STR = {
|
||||||
|
"ChannelF;BINCHF;",
|
||||||
|
"O1,Swap Joystick,Off,On;",
|
||||||
|
"O34,Scanlines,Off,25%,50%,75%;",
|
||||||
|
// "O6,Blending,Off,On;",
|
||||||
|
"T0,Reset;",
|
||||||
|
"V,v1.00.",`BUILD_DATE
|
||||||
|
};
|
||||||
|
|
||||||
|
assign LED = ~ioctl_downl;
|
||||||
|
//assign AUDIO_R = AUDIO_L;
|
||||||
|
|
||||||
|
wire pll_locked,clock_28p636, clk3p579;
|
||||||
|
pll pll(
|
||||||
|
.locked ( pll_locked ),
|
||||||
|
.inclk0 ( CLOCK_27 ),
|
||||||
|
.c0 ( clock_28p636 ),//28.63636000
|
||||||
|
.c1 ( clk3p579 )//3.579545
|
||||||
|
);
|
||||||
|
|
||||||
|
channel_f channel_f(
|
||||||
|
.clk ( clk3p579 ),
|
||||||
|
.reset ( status[0] | buttons[1]),
|
||||||
|
.pll_locked ( pll_locked ),
|
||||||
|
.vga_r ( r ),
|
||||||
|
.vga_g ( g ),
|
||||||
|
.vga_b ( b ),
|
||||||
|
.vga_hs ( hs ),
|
||||||
|
.vga_vs ( vs ),
|
||||||
|
.vga_de ( blankn ),
|
||||||
|
.Keys ( {m_four_players, m_three_players, m_two_players, m_one_player}),
|
||||||
|
.joystick_0 ( {m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right}),
|
||||||
|
.joystick_1 ( {m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2}),
|
||||||
|
.ioctl_download ( ioctl_downl ),
|
||||||
|
.ioctl_index ( ioctl_index ),
|
||||||
|
.ioctl_wr ( ~ioctl_wr ),//todo
|
||||||
|
.ioctl_addr ( ioctl_addr ),
|
||||||
|
.ioctl_dout ( ioctl_dout ),
|
||||||
|
.ioctl_wait ( ),//todo
|
||||||
|
.audio ( audio )
|
||||||
|
);
|
||||||
|
|
||||||
|
wire ioctl_downl;
|
||||||
|
wire [7:0] ioctl_index;
|
||||||
|
wire ioctl_wr;
|
||||||
|
wire [24:0] ioctl_addr;
|
||||||
|
wire [7:0] ioctl_dout;
|
||||||
|
|
||||||
|
data_io data_io(
|
||||||
|
.clk_sys ( clock_28p636 ),
|
||||||
|
.SPI_SCK ( SPI_SCK ),
|
||||||
|
.SPI_SS2 ( SPI_SS2 ),
|
||||||
|
.SPI_DI ( SPI_DI ),
|
||||||
|
.ioctl_download ( ioctl_downl ),
|
||||||
|
.ioctl_index ( ioctl_index ),
|
||||||
|
.ioctl_wr ( ioctl_wr ),
|
||||||
|
.ioctl_addr ( ioctl_addr ),
|
||||||
|
.ioctl_dout ( ioctl_dout )
|
||||||
|
);
|
||||||
|
|
||||||
|
mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(10)) mist_video(
|
||||||
|
.clk_sys ( clock_28p636 ),
|
||||||
|
.SPI_SCK ( SPI_SCK ),
|
||||||
|
.SPI_SS3 ( SPI_SS3 ),
|
||||||
|
.SPI_DI ( SPI_DI ),
|
||||||
|
.R ( blankn ? r[7:2] : 0),
|
||||||
|
.G ( blankn ? g[7:2] : 0),
|
||||||
|
.B ( blankn ? b[7:2] : 0),
|
||||||
|
.HSync ( hs ),
|
||||||
|
.VSync ( vs ),
|
||||||
|
.VGA_R ( VGA_R ),
|
||||||
|
.VGA_G ( VGA_G ),
|
||||||
|
.VGA_B ( VGA_B ),
|
||||||
|
.VGA_VS ( VGA_VS ),
|
||||||
|
.VGA_HS ( VGA_HS ),
|
||||||
|
.ce_divider ( 0 ),
|
||||||
|
.blend ( status[6] ),
|
||||||
|
.scandoubler_disable(scandoublerD ),
|
||||||
|
.scanlines ( status[4:3] ),
|
||||||
|
.ypbpr ( ypbpr ),
|
||||||
|
.no_csync ( no_csync )
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [31:0] status;
|
||||||
|
wire [1:0] buttons;
|
||||||
|
wire [1:0] switches;
|
||||||
|
wire [31:0] joystick_0;
|
||||||
|
wire [31:0] joystick_1;
|
||||||
|
wire scandoublerD;
|
||||||
|
wire [7:0] r, g, b;
|
||||||
|
wire hs, vs, blankn;
|
||||||
|
wire [15:0] audio;
|
||||||
|
wire ypbpr;
|
||||||
|
wire no_csync;
|
||||||
|
wire key_strobe;
|
||||||
|
wire key_pressed;
|
||||||
|
wire [7:0] key_code;
|
||||||
|
|
||||||
|
user_io #(
|
||||||
|
.STRLEN(($size(CONF_STR)>>3)))
|
||||||
|
user_io(
|
||||||
|
.clk_sys ( clock_28p636 ),
|
||||||
|
.conf_str ( CONF_STR ),
|
||||||
|
.SPI_CLK ( SPI_SCK ),
|
||||||
|
.SPI_SS_IO ( CONF_DATA0 ),
|
||||||
|
.SPI_MISO ( SPI_DO ),
|
||||||
|
.SPI_MOSI ( SPI_DI ),
|
||||||
|
.buttons ( buttons ),
|
||||||
|
.switches ( switches ),
|
||||||
|
.scandoubler_disable (scandoublerD ),
|
||||||
|
.ypbpr ( ypbpr ),
|
||||||
|
.no_csync ( no_csync ),
|
||||||
|
.key_strobe ( key_strobe ),
|
||||||
|
.key_pressed ( key_pressed ),
|
||||||
|
.key_code ( key_code ),
|
||||||
|
.joystick_0 ( joystick_0 ),
|
||||||
|
.joystick_1 ( joystick_1 ),
|
||||||
|
.status ( status )
|
||||||
|
);
|
||||||
|
|
||||||
|
//dac #(
|
||||||
|
// .C_bits(16))
|
||||||
|
//dac(
|
||||||
|
// .clk_i ( clock_28p636 ),
|
||||||
|
// .res_n_i ( 1'b1 ),
|
||||||
|
// .dac_i ( audio ),
|
||||||
|
// .dac_o ( AUDIO_L )
|
||||||
|
// );
|
||||||
|
|
||||||
|
mist_audio #(16,0,0) mist_audio(
|
||||||
|
.clk ( clock_28p636 ),
|
||||||
|
.reset_n ( 1'b1 ),
|
||||||
|
.audio_inL ( audio ),
|
||||||
|
// .audio_inR ( audio ),
|
||||||
|
.AUDIO_L ( AUDIO_L ),
|
||||||
|
.AUDIO_R ( AUDIO_R )
|
||||||
|
);
|
||||||
|
|
||||||
|
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
|
||||||
|
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
|
||||||
|
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||||
|
|
||||||
|
arcade_inputs inputs (
|
||||||
|
.clk ( clock_28p636 ),
|
||||||
|
.key_strobe ( key_strobe ),
|
||||||
|
.key_pressed ( key_pressed ),
|
||||||
|
.key_code ( key_code ),
|
||||||
|
.joystick_0 ( joystick_0 ),
|
||||||
|
.joystick_1 ( joystick_1 ),
|
||||||
|
.rotate ( 0 ),
|
||||||
|
.orientation ( 2'b00 ),
|
||||||
|
.joyswap ( status[1] ),
|
||||||
|
.oneplayer ( 1'b0 ),
|
||||||
|
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
|
||||||
|
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
|
||||||
|
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
@ -1,180 +0,0 @@
|
|||||||
--------------------------------------------------------------------------------
|
|
||||||
-- Overlay
|
|
||||||
--------------------------------------------------------------------------------
|
|
||||||
-- DO 10/2017
|
|
||||||
--------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
LIBRARY ieee;
|
|
||||||
USE ieee.std_logic_1164.ALL;
|
|
||||||
USE ieee.numeric_std.ALL;
|
|
||||||
|
|
||||||
LIBRARY work;
|
|
||||||
USE work.base_pack.ALL;
|
|
||||||
|
|
||||||
ENTITY ovo IS
|
|
||||||
GENERIC (
|
|
||||||
COLS : natural :=32;
|
|
||||||
LINES : natural :=2;
|
|
||||||
RGB : unsigned(23 DOWNTO 0) :=x"FFFFFF");
|
|
||||||
PORT (
|
|
||||||
-- VGA IN
|
|
||||||
i_r : IN uv8;
|
|
||||||
i_g : IN uv8;
|
|
||||||
i_b : IN uv8;
|
|
||||||
i_hs : IN std_logic;
|
|
||||||
i_vs : IN std_logic;
|
|
||||||
i_de : IN std_logic;
|
|
||||||
i_en : IN std_logic;
|
|
||||||
i_clk : IN std_logic;
|
|
||||||
|
|
||||||
-- VGA_OUT
|
|
||||||
o_r : OUT uv8;
|
|
||||||
o_g : OUT uv8;
|
|
||||||
o_b : OUT uv8;
|
|
||||||
o_hs : OUT std_logic;
|
|
||||||
o_vs : OUT std_logic;
|
|
||||||
o_de : OUT std_logic;
|
|
||||||
|
|
||||||
-- Control
|
|
||||||
ena : IN std_logic; -- Overlay ON/OFF
|
|
||||||
|
|
||||||
-- Probes
|
|
||||||
in0 : IN unsigned(0 TO COLS*5-1);
|
|
||||||
in1 : IN unsigned(0 TO COLS*5-1)
|
|
||||||
);
|
|
||||||
END ENTITY ovo;
|
|
||||||
|
|
||||||
--##############################################################################
|
|
||||||
|
|
||||||
ARCHITECTURE rtl OF ovo IS
|
|
||||||
TYPE arr_slv8 IS ARRAY (natural RANGE <>) OF uv8;
|
|
||||||
CONSTANT chars : arr_slv8 :=(
|
|
||||||
x"3E", x"63", x"73", x"7B", x"6F", x"67", x"3E", x"00", -- 0
|
|
||||||
x"0C", x"0E", x"0C", x"0C", x"0C", x"0C", x"3F", x"00", -- 1
|
|
||||||
x"1E", x"33", x"30", x"1C", x"06", x"33", x"3F", x"00", -- 2
|
|
||||||
x"1E", x"33", x"30", x"1C", x"30", x"33", x"1E", x"00", -- 3
|
|
||||||
x"38", x"3C", x"36", x"33", x"7F", x"30", x"78", x"00", -- 4
|
|
||||||
x"3F", x"03", x"1F", x"30", x"30", x"33", x"1E", x"00", -- 5
|
|
||||||
x"1C", x"06", x"03", x"1F", x"33", x"33", x"1E", x"00", -- 6
|
|
||||||
x"3F", x"33", x"30", x"18", x"0C", x"0C", x"0C", x"00", -- 7
|
|
||||||
x"1E", x"33", x"33", x"1E", x"33", x"33", x"1E", x"00", -- 8
|
|
||||||
x"1E", x"33", x"33", x"3E", x"30", x"18", x"0E", x"00", -- 9
|
|
||||||
x"0C", x"1E", x"33", x"33", x"3F", x"33", x"33", x"00", -- A
|
|
||||||
x"3F", x"66", x"66", x"3E", x"66", x"66", x"3F", x"00", -- B
|
|
||||||
x"3C", x"66", x"03", x"03", x"03", x"66", x"3C", x"00", -- C
|
|
||||||
x"1F", x"36", x"66", x"66", x"66", x"36", x"1F", x"00", -- D
|
|
||||||
x"7F", x"46", x"16", x"1E", x"16", x"46", x"7F", x"00", -- E
|
|
||||||
x"7F", x"46", x"16", x"1E", x"16", x"06", x"0F", x"00", -- F
|
|
||||||
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", --' ' 10
|
|
||||||
x"00", x"00", x"3F", x"00", x"00", x"3F", x"00", x"00", -- = 11
|
|
||||||
x"00", x"0C", x"0C", x"3F", x"0C", x"0C", x"00", x"00", -- + 12
|
|
||||||
x"00", x"00", x"00", x"3F", x"00", x"00", x"00", x"00", -- - 13
|
|
||||||
x"18", x"0C", x"06", x"03", x"06", x"0C", x"18", x"00", -- < 14
|
|
||||||
x"06", x"0C", x"18", x"30", x"18", x"0C", x"06", x"00", -- > 15
|
|
||||||
x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- ^ 16
|
|
||||||
x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- v 17
|
|
||||||
x"18", x"0C", x"06", x"06", x"06", x"0C", x"18", x"00", -- ( 18
|
|
||||||
x"06", x"0C", x"18", x"18", x"18", x"0C", x"06", x"00", -- ) 19
|
|
||||||
x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"00", -- : 1A
|
|
||||||
x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"00", -- . 1B
|
|
||||||
x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"06", -- , 1C
|
|
||||||
x"1E", x"33", x"30", x"18", x"0C", x"00", x"0C", x"00", -- ? 1D
|
|
||||||
x"18", x"18", x"18", x"00", x"18", x"18", x"18", x"00", -- | 1E
|
|
||||||
x"36", x"36", x"7F", x"36", x"7F", x"36", x"36", x"00"); -- # 1F
|
|
||||||
|
|
||||||
SIGNAL vcpt,hcpt,hcpt2 : natural RANGE 0 TO 4095;
|
|
||||||
SIGNAL vin0,vin1 : unsigned(0 TO COLS*5-1);
|
|
||||||
|
|
||||||
SIGNAL t_r,t_g,t_b : uv8;
|
|
||||||
SIGNAL t_hs,t_vs,t_de : std_logic;
|
|
||||||
|
|
||||||
SIGNAL col : uv8;
|
|
||||||
SIGNAL de : std_logic;
|
|
||||||
|
|
||||||
SIGNAL in0s,in1s : unsigned(in0'range);
|
|
||||||
BEGIN
|
|
||||||
|
|
||||||
in0s<=in0 WHEN rising_edge(i_clk);
|
|
||||||
in1s<=in1 WHEN rising_edge(i_clk);
|
|
||||||
|
|
||||||
----------------------------------------------------------
|
|
||||||
Megamix:PROCESS(i_clk) IS
|
|
||||||
VARIABLE vin_v : unsigned(0 TO 32*5-1);
|
|
||||||
VARIABLE char_v : unsigned(4 DOWNTO 0);
|
|
||||||
BEGIN
|
|
||||||
IF rising_edge(i_clk) THEN
|
|
||||||
IF i_en='1' THEN
|
|
||||||
----------------------------------
|
|
||||||
-- Propagate VGA signals. 2 cycles delay
|
|
||||||
t_r<=i_r;
|
|
||||||
t_g<=i_g;
|
|
||||||
t_b<=i_b;
|
|
||||||
t_hs<=i_hs;
|
|
||||||
t_vs<=i_vs;
|
|
||||||
t_de<=i_de;
|
|
||||||
|
|
||||||
o_r<=t_r;
|
|
||||||
o_g<=t_g;
|
|
||||||
o_b<=t_b;
|
|
||||||
o_hs<=t_hs;
|
|
||||||
o_vs<=t_vs;
|
|
||||||
o_de<=t_de;
|
|
||||||
|
|
||||||
----------------------------------
|
|
||||||
-- Latch sampled values during vertical sync
|
|
||||||
IF i_vs='1' THEN
|
|
||||||
vin0<=in0s;
|
|
||||||
vin1<=in1s;
|
|
||||||
END IF;
|
|
||||||
|
|
||||||
----------------------------------
|
|
||||||
IF i_vs='1' THEN
|
|
||||||
vcpt<=0;
|
|
||||||
de<='0';
|
|
||||||
ELSIF i_hs='1' AND t_hs='0' AND de='1' THEN
|
|
||||||
vcpt<=(vcpt+1) MOD 4096;
|
|
||||||
END IF;
|
|
||||||
|
|
||||||
----------------------------------
|
|
||||||
IF (vcpt/8) MOD 2=0 THEN
|
|
||||||
vin_v:=vin0;
|
|
||||||
ELSE
|
|
||||||
vin_v:=vin1;
|
|
||||||
END IF;
|
|
||||||
|
|
||||||
IF i_hs='1' THEN
|
|
||||||
hcpt<=0;
|
|
||||||
ELSIF i_de='1' THEN
|
|
||||||
hcpt<=(hcpt+1) MOD 4096;
|
|
||||||
de<='1';
|
|
||||||
END IF;
|
|
||||||
hcpt2<=hcpt;
|
|
||||||
|
|
||||||
----------------------------------
|
|
||||||
-- Pick characters
|
|
||||||
IF hcpt<COLS * 8 AND vcpt<LINES * 8 THEN
|
|
||||||
char_v:=vin_v((hcpt/8)*5 TO (hcpt/8)*5+4);
|
|
||||||
ELSE
|
|
||||||
char_v:="10000"; -- " " : Blank character
|
|
||||||
END IF;
|
|
||||||
|
|
||||||
col<=chars(to_integer(char_v)*8+(vcpt MOD 8));
|
|
||||||
|
|
||||||
----------------------------------
|
|
||||||
-- Insert Overlay
|
|
||||||
IF ena='1' THEN
|
|
||||||
IF col(hcpt2 MOD 8)='1' THEN
|
|
||||||
o_r<=rgb(23 DOWNTO 16);
|
|
||||||
o_g<=rgb(15 DOWNTO 8);
|
|
||||||
o_b<=rgb( 7 DOWNTO 0);
|
|
||||||
END IF;
|
|
||||||
END IF;
|
|
||||||
END IF;
|
|
||||||
END IF;
|
|
||||||
END PROCESS Megamix;
|
|
||||||
|
|
||||||
|
|
||||||
END ARCHITECTURE rtl;
|
|
||||||
|
|
||||||
@ -1,4 +0,0 @@
|
|||||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
|
||||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
|
||||||
@ -40,30 +40,26 @@ module pll (
|
|||||||
inclk0,
|
inclk0,
|
||||||
c0,
|
c0,
|
||||||
c1,
|
c1,
|
||||||
c2,
|
|
||||||
locked);
|
locked);
|
||||||
|
|
||||||
input inclk0;
|
input inclk0;
|
||||||
output c0;
|
output c0;
|
||||||
output c1;
|
output c1;
|
||||||
output c2;
|
|
||||||
output locked;
|
output locked;
|
||||||
|
|
||||||
wire [4:0] sub_wire0;
|
wire [4:0] sub_wire0;
|
||||||
wire sub_wire2;
|
wire sub_wire2;
|
||||||
wire [0:0] sub_wire7 = 1'h0;
|
wire [0:0] sub_wire6 = 1'h0;
|
||||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
|
||||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||||
wire c1 = sub_wire1;
|
wire c1 = sub_wire1;
|
||||||
wire locked = sub_wire2;
|
wire locked = sub_wire2;
|
||||||
wire c0 = sub_wire3;
|
wire c0 = sub_wire3;
|
||||||
wire c2 = sub_wire4;
|
wire sub_wire4 = inclk0;
|
||||||
wire sub_wire5 = inclk0;
|
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
|
||||||
|
|
||||||
altpll altpll_component (
|
altpll altpll_component (
|
||||||
.inclk (sub_wire6),
|
.inclk (sub_wire5),
|
||||||
.clk (sub_wire0),
|
.clk (sub_wire0),
|
||||||
.locked (sub_wire2),
|
.locked (sub_wire2),
|
||||||
.activeclock (),
|
.activeclock (),
|
||||||
@ -102,18 +98,14 @@ module pll (
|
|||||||
.vcounderrange ());
|
.vcounderrange ());
|
||||||
defparam
|
defparam
|
||||||
altpll_component.bandwidth_type = "AUTO",
|
altpll_component.bandwidth_type = "AUTO",
|
||||||
altpll_component.clk0_divide_by = 33,
|
altpll_component.clk0_divide_by = 50,
|
||||||
altpll_component.clk0_duty_cycle = 50,
|
altpll_component.clk0_duty_cycle = 50,
|
||||||
altpll_component.clk0_multiply_by = 35,
|
altpll_component.clk0_multiply_by = 53,
|
||||||
altpll_component.clk0_phase_shift = "0",
|
altpll_component.clk0_phase_shift = "0",
|
||||||
altpll_component.clk1_divide_by = 400,
|
altpll_component.clk1_divide_by = 400,
|
||||||
altpll_component.clk1_duty_cycle = 50,
|
altpll_component.clk1_duty_cycle = 50,
|
||||||
altpll_component.clk1_multiply_by = 53,
|
altpll_component.clk1_multiply_by = 53,
|
||||||
altpll_component.clk1_phase_shift = "0",
|
altpll_component.clk1_phase_shift = "0",
|
||||||
altpll_component.clk2_divide_by = 715,
|
|
||||||
altpll_component.clk2_duty_cycle = 50,
|
|
||||||
altpll_component.clk2_multiply_by = 106,
|
|
||||||
altpll_component.clk2_phase_shift = "0",
|
|
||||||
altpll_component.compensate_clock = "CLK0",
|
altpll_component.compensate_clock = "CLK0",
|
||||||
altpll_component.inclk0_input_frequency = 37037,
|
altpll_component.inclk0_input_frequency = 37037,
|
||||||
altpll_component.intended_device_family = "Cyclone III",
|
altpll_component.intended_device_family = "Cyclone III",
|
||||||
@ -148,7 +140,7 @@ module pll (
|
|||||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||||
altpll_component.port_clk0 = "PORT_USED",
|
altpll_component.port_clk0 = "PORT_USED",
|
||||||
altpll_component.port_clk1 = "PORT_USED",
|
altpll_component.port_clk1 = "PORT_USED",
|
||||||
altpll_component.port_clk2 = "PORT_USED",
|
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||||
@ -187,15 +179,12 @@ endmodule
|
|||||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
|
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50"
|
||||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "400"
|
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "400"
|
||||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "715"
|
|
||||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.620001"
|
||||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636364"
|
|
||||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "3.577500"
|
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "3.577500"
|
||||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "4.002797"
|
|
||||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||||
@ -217,33 +206,25 @@ endmodule
|
|||||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
|
||||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "53"
|
||||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "35"
|
|
||||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "53"
|
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "53"
|
||||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "106"
|
|
||||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63636000"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63636000"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "3.57954500"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "3.57954500"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "4.00000000"
|
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
|
||||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
|
||||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
|
||||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||||
@ -267,32 +248,25 @@ endmodule
|
|||||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
|
||||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
|
||||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
|
||||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
|
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
|
||||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "35"
|
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "53"
|
||||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "400"
|
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "400"
|
||||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "53"
|
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "53"
|
||||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "715"
|
|
||||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
|
||||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "106"
|
|
||||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
|
||||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||||
@ -326,7 +300,7 @@ endmodule
|
|||||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||||
@ -345,14 +319,12 @@ endmodule
|
|||||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
|
||||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
|
||||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||||
|
|||||||
BIN
common/mra.exe
Normal file
BIN
common/mra.exe
Normal file
Binary file not shown.
Loading…
x
Reference in New Issue
Block a user