mirror of
https://github.com/Gehstock/Mist_FPGA.git
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add Changes from Mr. X, sound now Works for all Games, needs new MRA Files
This commit is contained in:
Marcel
parent
b4ad2b3e4f
commit
fb494ba98f
@ -18,7 +18,7 @@
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#
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# Quartus II 64-Bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
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# Date created = 23:55:41 May 24, 2020
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# Date created = 02:55:28 May 26, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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@ -43,6 +43,23 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv
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set_global_assignment -name VERILOG_FILE rtl/System1_Top.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Main.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Decoder.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Video.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v
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set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v
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set_global_assignment -name VERILOG_FILE rtl/SN76496.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
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set_global_assignment -name VERILOG_FILE rtl/z80ip.v
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set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
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set_global_assignment -name VHDL_FILE rtl/dpram.vhd
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set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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# Pin & Location Assignments
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# ==========================
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@ -222,20 +239,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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# end ENTITY(System1_MiST)
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# ------------------------
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv
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set_global_assignment -name VERILOG_FILE rtl/System1_Top.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Main.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Video.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Sound.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Sprite.v
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set_global_assignment -name VERILOG_FILE rtl/System1_Parts.v
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set_global_assignment -name VERILOG_FILE rtl/System1_hvgen.v
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set_global_assignment -name VERILOG_FILE rtl/SN76496.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
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set_global_assignment -name VERILOG_FILE rtl/z80ip.v
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set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
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set_global_assignment -name VHDL_FILE rtl/dpram.vhd
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set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -0,0 +1,206 @@
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// Copyright (c) 2017,19 MiSTer-X
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`define DECTBLADRS (25'h2E100)
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`define EN_DEC1TBL (dl_addr[17:7]==11'b10111000010;//2E100
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`define EN_DEC2XOR (dl_addr[17:7]==11'b10111000010;//2E100
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`define EN_DEC2SWP (dl_addr[17:7]==11'b10111000011;//2E180
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module System1_Decoder
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(
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input clk,
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input mrom_m1, // connect to CPU
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input [14:0] mrom_ad,
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output [7:0] mrom_dt,
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output [14:0] rad, // connect to ROM
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input [7:0] rdt,
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input [17:0] dl_addr,
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input [7:0] dl_data,
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input dl_wr,
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input dl_clk
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);
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wire [7:0] od0,od1;
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wire [14:0] dum;
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SEGASYS1_DECT1 t1(clk,mrom_m1,mrom_ad, od0, rad,rdt, dl_addr,dl_data,dl_wr,dl_clk);
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SEGASYS1_DECT2 t2(clk,mrom_m1,mrom_ad, od1, dum,rdt, dl_addr,dl_data,dl_wr,dl_clk);
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// Type Detect and switch
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reg [15:0] cnt0,cnt2;
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always @(posedge dl_clk) begin
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if (~dl_wr) begin
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if (dl_addr>=`DECTBLADRS) begin
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cnt2 <= (dl_data>=8'd24) ? 0 : (cnt2+1);
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cnt0 <= (dl_data!=8'd0 ) ? 0 : (cnt0+1);
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end
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else begin
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cnt2 <= 0;
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cnt0 <= 0;
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end
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end
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end
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assign mrom_dt = (cnt0>=128) ? rdt : (cnt2>=128) ? od1 : od0;
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endmodule
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//----------------------------------------
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// Program ROM Decryptor (Type 1)
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//----------------------------------------
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module SEGASYS1_DECT1
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(
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input clk,
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input mrom_m1, // connect to CPU
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input [14:0] mrom_ad,
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output reg [7:0] mrom_dt,
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output [14:0] rad, // connect to ROM
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input [7:0] rdt,
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input [17:0] dl_addr,
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input [7:0] dl_data,
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input dl_wr,
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input dl_clk
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);
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reg [15:0] madr;
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wire [7:0] mdat = rdt;
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wire f = mdat[7];
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wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 };
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wire [7:0] andv = ~(8'hA8);
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wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f };
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wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 };
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wire [7:0] dectbl;
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wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv );
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//DLROM #(7,8) dect( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC1TBL );
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wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100
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dpram#(8,7)decrom(
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.clk_a(clk),
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.addr_a(decidx),
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.q_a(dectbl),
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.clk_b(dl_clk),
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.addr_b(dl_addr[6:0]),
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.we_b(dec_we & dl_wr),
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.d_b(dl_data)
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);
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assign rad = madr[14:0];
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assign mdat = rdt;
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reg phase = 1'b0;
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always @( negedge clk ) begin
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if ( phase ) mrom_dt <= mdec;
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else madr <= { mrom_m1, mrom_ad };
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phase <= ~phase;
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end
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endmodule
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//----------------------------------------
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// Program ROM Decryptor (Type 2)
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//----------------------------------------
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module SEGASYS1_DECT2
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(
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input clk,
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input mrom_m1, // connect to CPU
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input [14:0] mrom_ad,
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output reg [7:0] mrom_dt,
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output [14:0] rad, // connect to ROM
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input [7:0] rdt,
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input [17:0] dl_addr,
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input [7:0] dl_data,
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input dl_wr,
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input dl_clk
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);
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`define bsw(A,B,C,D) {v[7],v[A],v[5],v[B],v[3],v[C],v[1],v[D]}
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function [7:0] bswp;
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input [4:0] m;
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input [7:0] v;
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case (m)
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0: bswp = `bsw(6,4,2,0);
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1: bswp = `bsw(4,6,2,0);
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2: bswp = `bsw(2,4,6,0);
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3: bswp = `bsw(0,4,2,6);
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4: bswp = `bsw(6,2,4,0);
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5: bswp = `bsw(6,0,2,4);
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6: bswp = `bsw(6,4,0,2);
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7: bswp = `bsw(2,6,4,0);
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8: bswp = `bsw(4,2,6,0);
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9: bswp = `bsw(4,6,0,2);
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10: bswp = `bsw(6,0,4,2);
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11: bswp = `bsw(0,6,4,2);
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12: bswp = `bsw(4,0,6,2);
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13: bswp = `bsw(0,4,6,2);
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14: bswp = `bsw(6,2,0,4);
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15: bswp = `bsw(2,6,0,4);
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16: bswp = `bsw(0,6,2,4);
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17: bswp = `bsw(2,0,6,4);
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18: bswp = `bsw(0,2,6,4);
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19: bswp = `bsw(4,2,0,6);
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20: bswp = `bsw(2,4,0,6);
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21: bswp = `bsw(4,0,2,6);
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22: bswp = `bsw(2,0,4,6);
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23: bswp = `bsw(0,2,4,6);
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default: bswp = 0;
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endcase
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endfunction
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reg [15:0] madr;
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wire [7:0] sd,xd;
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wire [6:0] ix = {madr[14],madr[12],madr[9],madr[6],madr[3],madr[0],~madr[15]};
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//DLROM #(7,8) xort(clk,ix,xd, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC2XOR);
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wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100
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dpram#(8,7)decrom(
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.clk_a(clk),
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.addr_a(ix),
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.q_a(xd),
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.clk_b(dl_clk),
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.addr_b(dl_addr[6:0]),
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.we_b(dec_we & dl_wr),
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.d_b(dl_data)
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);
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assign rad = madr[14:0];
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//assign mdat = rdt;
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//DLROM #(7,8) swpt(clk,ix,sd, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC2SWP);
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wire dec2_we = dl_addr[17:7] == 11'b10111000011;//2E180 10 1110 0001 1000 0000
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dpram#(8,7)decrom2(
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.clk_a(clk),
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.addr_a(ix),
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.q_a(sd),
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.clk_b(dl_clk),
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.addr_b(dl_addr[6:0]),
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.we_b(dec2_we & dl_wr),
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.d_b(dl_data)
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);
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reg phase = 1'b0;
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always @( negedge clk ) begin
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if ( phase ) mrom_dt <= (bswp(sd,rdt) ^ xd);
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else madr <= { mrom_m1, mrom_ad };
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phase <= ~phase;
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end
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endmodule
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@ -1,9 +1,11 @@
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// Copyright (c) 2017,19 MiSTer-X
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`define EN_MCPU0 (dl_addr[17:15]==3'b00_0 ) //todo
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`define EN_MCPU8 (dl_addr[17:14]==4'b00_10) //todo
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module System1_Main
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(
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input CLK48M,
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input CLK3M,
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input RESET,
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input crypt,
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@ -17,13 +19,14 @@ module System1_Main
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input VBLK,
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input VIDCS,
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input [7:0] VIDDO,
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output reg [7:0] VIDMD,
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output CPUCLn,
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output [15:0] CPUAD,
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output [7:0] CPUDO,
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output CPUWR,
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output SNDRQ,
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output reg SNDRQ,
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output reg [7:0] SNDNO,
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output [15:0] cpu_rom_addr,
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input [7:0] cpu_rom_do,
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input [17:0] dl_addr,
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@ -32,6 +35,10 @@ module System1_Main
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input dl_clk
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);
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reg [3:0] clkdiv;
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always @(posedge CLK48M) clkdiv <= clkdiv+1;
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wire CLK3M = clkdiv[3];
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wire AXSCL = CLK48M;
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wire CPUCL = CLK3M;
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assign CPUCLn = ~CPUCL;
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@ -64,104 +71,105 @@ Z80IP maincpu(
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assign CPUWR = _cpu_wr & cpu_mreq;
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assign CPURD = _cpu_rd & cpu_mreq;
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assign SNDRQ = (CPUAD[4:0] == 5'b1_1000) & cpu_iorq & _cpu_wr;
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// Input Port
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wire cpu_cs_port;
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wire [7:0] cpu_rd_port;
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SEGASYS1_IPORT port(CPUAD,cpu_iorq, INP0,INP1,INP2, DSW0,DSW1, cpu_cs_port,cpu_rd_port);
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wire cpu_cs_port1 = (CPUAD[4:2] == 3'b0_00) & cpu_iorq;
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wire cpu_cs_port2 = (CPUAD[4:2] == 3'b0_01) & cpu_iorq;
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wire cpu_cs_portS = (CPUAD[4:2] == 3'b0_10) & cpu_iorq;
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wire cpu_cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & cpu_iorq;
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wire cpu_cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:0] == 5'b1_0000)) & cpu_iorq;
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wire cpu_cs_portI = (CPUAD[4:2] == 3'b1_10) & cpu_iorq;
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wire [7:0] cpu_rd_port1 = INP0;
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wire [7:0] cpu_rd_port2 = INP1;
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wire [7:0] cpu_rd_portS = INP2;
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wire [7:0] cpu_rd_portA = DSW0;
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wire [7:0] cpu_rd_portB = DSW1;
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wire [7:0] cpu_rd_mrom;
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wire cpu_cs_mrom = (CPUAD[15:12] < 4'b1100);
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PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr[14:0],cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk );
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wire cpu_cs_mrom0 = (CPUAD[15] == 1'b0 ) & cpu_mreq;
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wire cpu_cs_mrom1 = (CPUAD[15:14] == 2'b10) & cpu_mreq;
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wire [7:0] cpu_rd_mrom0;
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wire [7:0] cpu_rd_mrom1;
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wire [14:0] rad;
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wire [7:0] rdt;
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System1_Decoder decr(AXSCL,cpu_m1,CPUAD,cpu_rd_mrom0, cpu_rom_addr,cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk );
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//PRGROM prom(AXSCL, cpu_m1, CPUAD[14:0], cpu_rd_mrom, cpu_rom_addr[14:0],cpu_rom_do,dl_addr,dl_data,dl_wr,dl_clk );
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//DLROM #(15,8) rom0(AXSCL, rad, rdt, ROMCL,ROMAD,ROMDT,ROMEN & `EN_MCPU0); // ($0000-$7FFF encrypted)
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//DLROM #(14,8) rom1(CPUCLn,CPUAD,cpu_rd_mrom1, ROMCL,ROMAD,ROMDT,ROMEN & `EN_MCPU8); // ($8000-$BFFF non-encrypted)
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wire rom2_we = (dl_addr >= 16'h8000) & (dl_addr < 16'hC000);
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dpram#(8,14)rom2(
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.clk_a(CPUCLn),
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.addr_a(CPUAD),
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.q_a(cpu_rd_mrom1),
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.clk_b(dl_clk),
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.addr_b(dl_addr[7:0]),
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.we_b(rom2_we & dl_wr),
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.d_b(dl_data)
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);
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// Work RAM
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wire [7:0] cpu_rd_mram;
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wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100);
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wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100) & cpu_mreq;
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SRAM_4096 mainram(CPUCLn, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO );
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reg [7:0] vidmode;
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always @(posedge CPUCLn) begin
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if ((CPUAD[4:0] == 5'b1_1001) & cpu_iorq & _cpu_wr) begin
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vidmode <= CPUDO;
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// Video mode latch & Sound Request
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wire cpu_cs_sreq = ((CPUAD[7:0] == 8'h14)|(CPUAD[7:0] == 8'h18)) & cpu_iorq;
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wire cpu_cs_vidm = ((CPUAD[7:0] == 8'h15)|(CPUAD[7:0] == 8'h19)) & cpu_iorq;
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wire cpu_wr_sreq = cpu_cs_sreq & _cpu_wr;
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wire cpu_wr_vidm = cpu_cs_vidm & _cpu_wr;
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always @(posedge CPUCLn or posedge RESET) begin
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if (RESET) begin
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VIDMD <= 0;
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SNDRQ <= 0;
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SNDNO <= 0;
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end
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else begin
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if (cpu_wr_vidm) VIDMD <= CPUDO;
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if (cpu_wr_sreq) begin SNDNO <= CPUDO; SNDRQ <= 1'b1; end else SNDRQ <= 1'b0;
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end
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end
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|
||||
wire [7:0] mrom_data = (crypt == 1'b1 & CPUAD[15] == 1'b0) ? cpu_rd_mrom : cpu_rom_do;
|
||||
|
||||
dataselector8 mcpudisel(
|
||||
// CPU data selector
|
||||
dataselector6 mcpudisel(
|
||||
CPUDI,
|
||||
VIDCS, VIDDO,
|
||||
cpu_cs_port1, cpu_rd_port1,
|
||||
cpu_cs_port2, cpu_rd_port2,
|
||||
cpu_cs_portS, cpu_rd_portS,
|
||||
cpu_cs_portA, cpu_rd_portA,
|
||||
cpu_cs_portB, cpu_rd_portB,
|
||||
VIDCS, VIDDO,
|
||||
cpu_cs_vidm, VIDMD,
|
||||
cpu_cs_port, cpu_rd_port,
|
||||
cpu_cs_mram, cpu_rd_mram,
|
||||
cpu_cs_mrom, mrom_data,
|
||||
cpu_cs_mrom0, (crypt == 1'b1) ? cpu_rd_mrom0 : cpu_rom_do,
|
||||
cpu_cs_mrom1, cpu_rd_mrom1,
|
||||
8'hFF
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//----------------------------------
|
||||
// Program ROM with Decryptor
|
||||
//----------------------------------
|
||||
module PRGROM
|
||||
module SEGASYS1_IPORT
|
||||
(
|
||||
input clk,
|
||||
input [15:0] CPUAD,
|
||||
input CPUIO,
|
||||
|
||||
input mrom_m1,
|
||||
input [14:0] mrom_ad,
|
||||
output reg [7:0] mrom_dt,
|
||||
output [14:0] cpu_rom_addr,
|
||||
input [7:0] cpu_rom_do,
|
||||
input [17:0] dl_addr,
|
||||
input [7:0] dl_data,
|
||||
input dl_wr,
|
||||
input dl_clk
|
||||
input [7:0] INP0,
|
||||
input [7:0] INP1,
|
||||
input [7:0] INP2,
|
||||
|
||||
input [7:0] DSW0,
|
||||
input [7:0] DSW1,
|
||||
|
||||
output DV,
|
||||
output [7:0] OD
|
||||
);
|
||||
|
||||
reg [15:0] madr;
|
||||
wire [7:0] mdat;
|
||||
wire cs_port1 = (CPUAD[4:2] == 3'b0_00) & CPUIO;
|
||||
wire cs_port2 = (CPUAD[4:2] == 3'b0_01) & CPUIO;
|
||||
wire cs_portS = (CPUAD[4:2] == 3'b0_10) & CPUIO;
|
||||
wire cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & CPUIO;
|
||||
wire cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:2] == 3'b1_00)) & CPUIO;
|
||||
|
||||
wire f = mdat[7];
|
||||
wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 };
|
||||
wire [7:0] andv = ~(8'hA8);
|
||||
wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f };
|
||||
wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 };
|
||||
wire [7:0] dectbl;
|
||||
wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv );
|
||||
wire [7:0] inp;
|
||||
dataselector5 dsel(
|
||||
inp,
|
||||
cs_port1,INP0,
|
||||
cs_port2,INP1,
|
||||
cs_portS,INP2,
|
||||
cs_portA,DSW0,
|
||||
cs_portB,DSW1,
|
||||
8'hFF
|
||||
);
|
||||
|
||||
//DLROM #( 7,8) decrom( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16: 7]==10'b1_1110_0001_0) ); // $1E100-$1E17F
|
||||
wire dec_we = dl_addr[17:7] == 11'b10111000010;//2E100
|
||||
dpram#(8,7)decrom(
|
||||
.clk_a(clk),
|
||||
.addr_a(decidx),
|
||||
.q_a(dectbl),
|
||||
.clk_b(dl_clk),
|
||||
.addr_b(dl_addr[6:0]),
|
||||
.we_b(dec_we & dl_wr),
|
||||
.d_b(dl_data)
|
||||
);
|
||||
assign DV = cs_port1|cs_port2|cs_portS|cs_portA|cs_portB;
|
||||
assign OD = inp;
|
||||
|
||||
assign cpu_rom_addr = madr[14:0];
|
||||
assign mdat = cpu_rom_do;
|
||||
|
||||
reg phase = 1'b0;
|
||||
always @( negedge clk ) begin
|
||||
if ( phase ) mrom_dt <= mdec;
|
||||
else madr <= { mrom_m1, mrom_ad };
|
||||
phase <= ~phase;
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
@ -71,8 +71,10 @@ always @(*) begin
|
||||
DSW1 = 8'hFF;
|
||||
// crypt = 1'b0;
|
||||
case (core_mod)
|
||||
7'h0: // FLICKY - PIO
|
||||
7'h0: // FLICKY
|
||||
begin
|
||||
//Sound OK(on latest Version)
|
||||
//not working anymore try with new MRA(Decoder Rom2)
|
||||
INP0 = ~{m_left, m_right,3'b000,m_fireA,2'b00};
|
||||
INP1 = ~{m_left2,m_right2,3'b000,m_fire2A,2'b00};
|
||||
INP2 = ~{2'b00,m_two_players, m_one_player,3'b000, m_coin1};
|
||||
@ -81,8 +83,9 @@ always @(*) begin
|
||||
|
||||
// crypt = 1'b1;
|
||||
end
|
||||
7'h1: // PITFALL2 - PIO
|
||||
7'h1: // PITFALL2
|
||||
begin
|
||||
//Sound OK
|
||||
INP0 = ~{m_left, m_right,3'd0,m_fireA,m_fireB,1'b0};
|
||||
INP1 = ~{m_left2,m_right2,3'd0,m_fire2A,m_fire2B,1'b0};
|
||||
INP2 = ~{2'b00,m_two_players, m_one_player,3'd0, m_coin1};
|
||||
@ -91,8 +94,9 @@ always @(*) begin
|
||||
|
||||
// crypt = 1'b0;
|
||||
end
|
||||
7'h2: // STARJACKER no Sound todo
|
||||
7'h2: // STARJACKER
|
||||
begin
|
||||
//Sound OK
|
||||
INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,m_fireB,1'b0};
|
||||
INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,m_fire2B,1'b0};
|
||||
INP2 = ~{2'b00,m_two_players, m_one_player,dsService,2'b00, m_coin1};
|
||||
@ -101,8 +105,9 @@ always @(*) begin
|
||||
|
||||
// crypt = 1'b0;
|
||||
end
|
||||
7'h3: // REGULUS - PPI no Sound todo
|
||||
7'h3: // REGULUS
|
||||
begin
|
||||
//Sound OK
|
||||
INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,m_fireB,1'b0};
|
||||
INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,m_fire2B,1'b0};
|
||||
INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1};
|
||||
@ -111,8 +116,9 @@ always @(*) begin
|
||||
|
||||
// crypt = 1'b0;
|
||||
end
|
||||
7'h4: // UPN´DOWN - PPI no Sound todo
|
||||
7'h4: // UPN´DOWN
|
||||
begin
|
||||
//Sound OK
|
||||
INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0};
|
||||
INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0};
|
||||
INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1};
|
||||
@ -121,8 +127,9 @@ always @(*) begin
|
||||
|
||||
// crypt = 1'b0;
|
||||
end
|
||||
7'h5: // My Hero - PIO
|
||||
7'h5: // My Hero
|
||||
begin
|
||||
//Sound OK
|
||||
INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0};
|
||||
INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0};
|
||||
INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1};
|
||||
@ -133,6 +140,7 @@ always @(*) begin
|
||||
end
|
||||
7'h6: // Sega Ninja - PIO
|
||||
begin
|
||||
//Sound OK
|
||||
INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0};
|
||||
INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0};
|
||||
INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1};
|
||||
@ -144,6 +152,8 @@ always @(*) begin
|
||||
end
|
||||
7'h7: // Mr Viking
|
||||
begin
|
||||
//Sound OK(on latest Version)
|
||||
//not working anymore try with new MRA(Decoder Rom2)
|
||||
INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireA,2'b0};
|
||||
INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2A,2'b0};
|
||||
INP2 = ~{2'd0,m_two_players, m_one_player,dsService,2'b0, m_coin1};
|
||||
@ -223,7 +233,7 @@ wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
wire dl_wr = ioctl_wr && ioctl_addr < 18'h2E180;
|
||||
wire dl_wr = ioctl_wr && ioctl_addr < 18'h2E200;
|
||||
|
||||
data_io data_io(
|
||||
.clk_sys ( clk_sys ),
|
||||
@ -237,7 +247,6 @@ data_io data_io(
|
||||
.ioctl_dout ( ioctl_dout )
|
||||
);
|
||||
|
||||
|
||||
reg port1_req, port2_req;
|
||||
wire [24:0] tl_ioctl_addr = ioctl_addr - 18'h22000;
|
||||
sdram sdram(
|
||||
|
||||
@ -300,6 +300,30 @@ assign oDATA = iSEL0 ? iDATA0 :
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------
|
||||
// Data Selector 5 to 1
|
||||
//----------------------------------
|
||||
module dataselector5(
|
||||
|
||||
output [7:0] oDATA,
|
||||
|
||||
input iSEL0, input [7:0] iDATA0,
|
||||
input iSEL1, input [7:0] iDATA1,
|
||||
input iSEL2, input [7:0] iDATA2,
|
||||
input iSEL3, input [7:0] iDATA3,
|
||||
input iSEL4, input [7:0] iDATA4,
|
||||
|
||||
input [7:0] dData
|
||||
);
|
||||
|
||||
assign oDATA = iSEL0 ? iDATA0 :
|
||||
iSEL1 ? iDATA1 :
|
||||
iSEL2 ? iDATA2 :
|
||||
iSEL3 ? iDATA3 :
|
||||
iSEL4 ? iDATA4 :
|
||||
dData;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------
|
||||
// Data Selector 8 to 1
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
module System1_Sound
|
||||
(
|
||||
input clk8M,
|
||||
input clk48M,
|
||||
input reset,
|
||||
|
||||
input [7:0] sndno,
|
||||
@ -16,8 +16,8 @@ module System1_Sound
|
||||
//----------------------------------
|
||||
// ClockGen
|
||||
//----------------------------------
|
||||
wire clk4M,clk2M;
|
||||
SndClkGen clkgen(clk8M,clk4M,clk2M);
|
||||
wire clk8M,clk4M,clk2M;
|
||||
SndClkGen clkgen(clk48M,clk8M,clk4M,clk2M);
|
||||
|
||||
wire cpuclkx2 = clk8M;
|
||||
wire cpu_clk = clk4M;
|
||||
@ -78,7 +78,7 @@ dataselector3 scpudisel(
|
||||
);
|
||||
|
||||
SndPlayReq sndreq (
|
||||
clk4M, reset,
|
||||
clk8M, reset,
|
||||
sndno, sndstart,
|
||||
cpu_irq, cpu_irqa,
|
||||
cpu_nmi, cpu_nmia,
|
||||
@ -121,10 +121,21 @@ endmodule
|
||||
|
||||
module SndClkGen
|
||||
(
|
||||
input clk8M,
|
||||
output clk4M,
|
||||
output clk2M
|
||||
input clk48M,
|
||||
output reg clk8M,
|
||||
output clk4M,
|
||||
output clk2M
|
||||
);
|
||||
|
||||
reg [1:0] count;
|
||||
always @( posedge clk48M ) begin
|
||||
if (count > 2'd2) begin
|
||||
count <= count - 2'd2;
|
||||
clk8M <= ~clk8M;
|
||||
end
|
||||
else count <= count + 2'd1;
|
||||
end
|
||||
|
||||
reg [1:0] clkdiv;
|
||||
always @ ( posedge clk8M ) clkdiv <= clkdiv+1;
|
||||
|
||||
@ -168,7 +179,7 @@ endmodule
|
||||
//----------------------------------
|
||||
module SndPlayReq
|
||||
(
|
||||
input clk4M,
|
||||
input clk8M,
|
||||
input reset,
|
||||
|
||||
input [7:0] sndno,
|
||||
@ -183,10 +194,10 @@ module SndPlayReq
|
||||
output reg [7:0] comlatch
|
||||
);
|
||||
|
||||
reg [15:0] timercnt;
|
||||
reg [16:0] timercnt;
|
||||
reg psndstart;
|
||||
|
||||
always @( posedge clk4M or posedge reset ) begin
|
||||
always @( posedge clk8M or posedge reset ) begin
|
||||
if ( reset ) begin
|
||||
cpu_nmi <= 0;
|
||||
cpu_irq <= 0;
|
||||
@ -204,11 +215,11 @@ always @( posedge clk4M or posedge reset ) begin
|
||||
end
|
||||
psndstart <= sndstart;
|
||||
|
||||
if ( timercnt == 16666 ) cpu_irq <= 1'b1;
|
||||
if ( timercnt == 33333 ) cpu_irq <= 1'b1;
|
||||
if ( timercnt == 66666 ) cpu_irq <= 1'b1;
|
||||
|
||||
timercnt <= ( timercnt == 33333 ) ? 0 : (timercnt+1); // 1/60sec
|
||||
timercnt <= ( timercnt == 66666 ) ? 0 : (timercnt+1); // 1/60sec
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
@ -44,7 +44,7 @@ CLKGEN clks( clk48M, clk24M, clk12M, clk6M, clk3M, clk8M );
|
||||
// CPU
|
||||
wire CPUCLn;
|
||||
wire [15:0] CPUAD;
|
||||
wire [7:0] CPUDO,VIDDO;
|
||||
wire [7:0] CPUDO,VIDDO,SNDNO,VIDMD;
|
||||
wire CPUWR,VIDCS,VBLK;
|
||||
wire SNDRQ;
|
||||
|
||||
@ -57,7 +57,6 @@ System1_Main System1_Main(
|
||||
.DSW0(DSW0),
|
||||
.DSW1(DSW1),
|
||||
.CLK48M(clk48M),
|
||||
.CLK3M(clk3M),
|
||||
.CPUCLn(CPUCLn),
|
||||
.CPUAD(CPUAD),
|
||||
.CPUDO(CPUDO),
|
||||
@ -65,7 +64,9 @@ System1_Main System1_Main(
|
||||
.VBLK(VBLK),
|
||||
.VIDCS(VIDCS),
|
||||
.VIDDO(VIDDO),
|
||||
.VIDMD(VIDMD),
|
||||
.SNDRQ(SNDRQ),
|
||||
.SNDNO(SNDNO),
|
||||
.cpu_rom_addr(cpu_rom_addr),
|
||||
.cpu_rom_do(cpu_rom_do),
|
||||
.dl_addr(dl_addr),
|
||||
@ -75,12 +76,11 @@ System1_Main System1_Main(
|
||||
);
|
||||
|
||||
System1_Video System1_Video(
|
||||
.VCLKx8(clk48M),
|
||||
.VCLKx4(clk24M),
|
||||
.VCLKx2(clk12M),
|
||||
.VCLK(clk6M),
|
||||
.RESET(reset),
|
||||
.VCLKx8(clk8M),
|
||||
.PH(HPOS),
|
||||
.PV(VPOS),
|
||||
.VFLP(VIDMD[7]),
|
||||
.VBLK(VBLK),
|
||||
.RGB8(POUT),
|
||||
.PALDSW(1'b0),
|
||||
@ -102,9 +102,9 @@ System1_Video System1_Video(
|
||||
assign PCLK = clk6M;
|
||||
|
||||
System1_Sound System1_Sound(
|
||||
.clk8M(clk8M),
|
||||
.clk48M(clk48M),
|
||||
.reset(reset),
|
||||
.sndno(CPUDO),
|
||||
.sndno(SNDNO),
|
||||
.sndstart(SNDRQ),
|
||||
.sndout(SOUT),
|
||||
.snd_rom_addr(snd_rom_addr),
|
||||
|
||||
@ -2,13 +2,13 @@
|
||||
|
||||
module System1_Video
|
||||
(
|
||||
input RESET,
|
||||
input VCLKx8,
|
||||
input VCLKx4,
|
||||
input VCLKx2,
|
||||
input VCLK,
|
||||
|
||||
|
||||
input [8:0] PH,
|
||||
input [8:0] PV,
|
||||
input VFLP,
|
||||
|
||||
output VBLK,
|
||||
output [7:0] RGB8,
|
||||
@ -31,6 +31,12 @@ module System1_Video
|
||||
input dl_clk
|
||||
);
|
||||
|
||||
reg [2:0] clkdiv;
|
||||
always @(posedge VCLKx8) clkdiv <= clkdiv+1;
|
||||
wire VCLKx4 = clkdiv[0];
|
||||
wire VCLKx2 = clkdiv[1];
|
||||
wire VCLK = clkdiv[2];
|
||||
|
||||
// CPU Interface
|
||||
wire [10:0] palno;
|
||||
wire [7:0] palout;
|
||||
@ -52,6 +58,7 @@ wire [15:0] scrx;
|
||||
wire [7:0] scry;
|
||||
|
||||
VIDCPUINTF intf(
|
||||
RESET,
|
||||
cpu_cl,
|
||||
cpu_ad, cpu_wr, cpu_dw,
|
||||
cpu_rd, cpu_dr,
|
||||
@ -150,6 +157,7 @@ endmodule
|
||||
//----------------------------------
|
||||
module VIDCPUINTF
|
||||
(
|
||||
input RESET,
|
||||
input cpu_cl,
|
||||
input [15:0] cpu_ad,
|
||||
input cpu_wr,
|
||||
@ -225,14 +233,20 @@ VIDADEC adecs(
|
||||
);
|
||||
|
||||
// Scroll Register
|
||||
always @ ( posedge cpu_cl ) begin
|
||||
if (cpu_wr_scrreg) begin
|
||||
case({cpu_ad[6],cpu_ad[0]})
|
||||
2'b11: scrx[15:8] <= cpu_dw;
|
||||
2'b10: scrx[ 7:0] <= cpu_dw;
|
||||
2'b01: scry <= cpu_dw;
|
||||
2'b00: ;
|
||||
endcase
|
||||
always @ ( posedge cpu_cl or posedge RESET) begin
|
||||
if (RESET) begin
|
||||
scrx <= 0;
|
||||
scry <= 0;
|
||||
end
|
||||
else begin
|
||||
if (cpu_wr_scrreg) begin
|
||||
case(cpu_ad[7:0])
|
||||
8'hBD: scry <= cpu_dw;
|
||||
8'hFC: scrx[ 7:0] <= cpu_dw;
|
||||
8'hFD: scrx[15:8] <= cpu_dw;
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
@ -254,16 +268,15 @@ DPRAM2048_8_16 sprram(
|
||||
|
||||
|
||||
// Collision RAM (Mixer & Sprite)
|
||||
wire noclip = 1'b1;
|
||||
wire [7:0] cpu_rd_mixcoll;
|
||||
wire [7:0] cpu_rd_sprcoll;
|
||||
COLLRAM_M mixc(
|
||||
cpu_cl,cpu_ad[5:0],cpu_wr_mixcoll,cpu_wr_mixcollclr,cpu_rd_mixcoll,
|
||||
VCLKx4,mixcoll_ad,mixcoll & noclip
|
||||
VCLKx4,mixcoll_ad,mixcoll
|
||||
);
|
||||
COLLRAM_S sprc(
|
||||
cpu_cl,cpu_ad[9:0],cpu_wr_sprcoll,cpu_wr_sprcollclr,cpu_rd_sprcoll,
|
||||
VCLKx4,sprcoll_ad,sprcoll & noclip
|
||||
VCLKx4,sprcoll_ad,sprcoll
|
||||
);
|
||||
|
||||
|
||||
@ -377,16 +390,16 @@ module VIDHVGEN
|
||||
output VBLK
|
||||
);
|
||||
|
||||
assign VBLK = (PV == 8'd224) & (PH <= 8'd64);
|
||||
assign VBLK = (PV == 9'd224) & (PH <= 9'd64);
|
||||
|
||||
assign HPOS = PH+1;
|
||||
assign VPOS = PV;
|
||||
|
||||
wire [8:0] BGHSCR = (511-scrx[9:1])-10;
|
||||
wire [8:0] BGVSCR = { 1'b0, scry };
|
||||
wire [7:0] BGHSCR = scrx[9:1]+14;
|
||||
wire [7:0] BGVSCR = scry;
|
||||
|
||||
assign BG0HP = BGHSCR+HPOS;
|
||||
assign BG0VP = BGVSCR+VPOS;
|
||||
assign BG0HP = (HPOS-BGHSCR)+3;
|
||||
assign BG0VP = (VPOS+BGVSCR);
|
||||
|
||||
assign BG1HP = HPOS+3;
|
||||
assign BG1VP = VPOS;
|
||||
@ -422,15 +435,15 @@ module VIDADEC
|
||||
output cpu_rd
|
||||
);
|
||||
|
||||
assign cpu_cs_palram = ( cpu_ad[15:11] == 5'b1101_1 );
|
||||
assign cpu_cs_spram = ( cpu_ad[15:11] == 5'b11010 );
|
||||
assign cpu_cs_mixcoll = ( cpu_ad[15:10] == 6'b1111_00 );
|
||||
wire cpu_cs_mixcollclr = ( cpu_ad[15:10] == 6'b1111_01 );
|
||||
assign cpu_cs_sprcoll = ( cpu_ad[15:10] == 6'b1111_10 );
|
||||
wire cpu_cs_sprcollclr = ( cpu_ad[15:10] == 6'b1111_11 );
|
||||
assign cpu_cs_vram0 = ( cpu_ad[15:11] == 5'b11100 );
|
||||
assign cpu_cs_vram1 = ( cpu_ad[15:11] == 5'b11101 );
|
||||
wire cpu_cs_scrreg = ((cpu_ad[15: 0] & 16'b1111_1111_1011_1110) == 16'b1110_1111_1011_1100);
|
||||
assign cpu_cs_palram = (cpu_ad[15:11] == 5'b1101_1 );
|
||||
assign cpu_cs_spram = (cpu_ad[15:11] == 5'b1101_0 );
|
||||
assign cpu_cs_mixcoll = (cpu_ad[15:10] == 6'b1111_00 );
|
||||
wire cpu_cs_mixcollclr = (cpu_ad[15:10] == 6'b1111_01 );
|
||||
assign cpu_cs_sprcoll = (cpu_ad[15:10] == 6'b1111_10 );
|
||||
wire cpu_cs_sprcollclr = (cpu_ad[15:10] == 6'b1111_11 );
|
||||
assign cpu_cs_vram0 = (cpu_ad[15:11] == 5'b1110_0 );
|
||||
assign cpu_cs_vram1 = (cpu_ad[15:11] == 5'b1110_1 );
|
||||
wire cpu_cs_scrreg = (cpu_ad[15: 8] == 8'b1110_1111);
|
||||
|
||||
|
||||
assign cpu_wr_palram = cpu_cs_palram & cpu_wr;
|
||||
@ -566,17 +579,12 @@ module COLLRAM_M
|
||||
reg [63:0] core;
|
||||
reg coll_rd, coll_sm;
|
||||
|
||||
always @(posedge cpu_cl) coll_rd <= core[cpu_ad];
|
||||
|
||||
always @(posedge VCLKx4) begin
|
||||
if (cpu_cl) begin
|
||||
if (cpu_wr_coll) core[cpu_ad] <= 1'b0;
|
||||
if (cpu_wr_collclr) coll_sm <= 1'b0;
|
||||
end
|
||||
else coll_sm <= coll;
|
||||
if (coll) core[coll_ad] <= 1'b1;
|
||||
if (cpu_cl & cpu_wr_coll) core[cpu_ad] <= 1'b0; else if (coll) core[coll_ad] <= 1'b1;
|
||||
if (cpu_cl & cpu_wr_collclr) coll_sm <= 1'b0; else if (coll) coll_sm <= 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge cpu_cl) coll_rd <= core[cpu_ad];
|
||||
assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd };
|
||||
|
||||
endmodule
|
||||
@ -597,18 +605,12 @@ module COLLRAM_S
|
||||
reg [1023:0] core;
|
||||
reg coll_rd, coll_sm;
|
||||
|
||||
always @(posedge cpu_cl) coll_rd <= core[cpu_ad];
|
||||
|
||||
always @(posedge VCLKx4) begin
|
||||
if (cpu_cl) begin
|
||||
if (cpu_wr_coll) core[cpu_ad] <= 1'b0;
|
||||
if (cpu_wr_collclr) coll_sm <= 1'b0;
|
||||
end
|
||||
else coll_sm <= coll;
|
||||
if (coll) core[coll_ad] <= 1'b1;
|
||||
if (cpu_cl & cpu_wr_coll ) core[cpu_ad] <= 1'b0; else if (coll) core[coll_ad] <= 1'b1;
|
||||
if (cpu_cl & cpu_wr_collclr) coll_sm <= 1'b0; else if (coll) coll_sm <= 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge cpu_cl) coll_rd <= core[cpu_ad];
|
||||
assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd };
|
||||
|
||||
endmodule
|
||||
|
||||
endmodule
|
||||
@ -1,4 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
|
||||
Loading…
x
Reference in New Issue
Block a user