1
0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-20 01:34:38 +00:00
Gyorgy Szombathelyi e74e5f77f8 MiST-common: add a signal to select the scandoubler pixel clock
clk_sys/4 (default) or clk_sys/2
2019-06-13 19:25:08 +02:00
..