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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-18 17:06:57 +00:00
Gyorgy Szombathelyi e74e5f77f8 MiST-common: add a signal to select the scandoubler pixel clock
clk_sys/4 (default) or clk_sys/2
2019-06-13 19:25:08 +02:00
..
2019-06-11 20:31:33 +02:00
2019-06-11 20:31:33 +02:00
2019-06-03 19:47:05 +02:00
2019-06-03 19:47:05 +02:00
2019-06-03 19:47:05 +02:00