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Code Issues Releases Wiki Activity

Make CPE_LATCH separate

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This commit is contained in:
Miodrag Milanovic
2025-06-30 09:44:16 +02:00
parent 474ba2d1e7
commit 2dc2732225
4 changed files with 8 additions and 6 deletions
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3
himbaechel/uarch/gatemate/bitstream.cc
View File

@@ -250,6 +250,7 @@ struct BitstreamBackend
case id_CPE_ADDCIN.index:
case id_CPE_CI.index:
case id_CPE_FF.index:
case id_CPE_LATCH.index:
case id_CPE_RAMI.index:
case id_CPE_RAMO.index:
case id_CPE_RAMIO.index: {
@@ -292,7 +293,7 @@ struct BitstreamBackend
}
}
if (cell.second->type.in(id_CPE_FF)) {
if (cell.second->type.in(id_CPE_FF, id_CPE_LATCH)) {
update_cpe_inv(cell.second.get(), id_CLK, id_C_CPE_CLK, params);
update_cpe_inv(cell.second.get(), id_EN, id_C_CPE_EN, params);
bool set = int_or_default(params, id_C_EN_SR, 0) == 1;

1
himbaechel/uarch/gatemate/constids.inc
View File

@@ -2237,3 +2237,4 @@ X(CPE_CONCAT)
X(CPE_ADDCIN)
X(CPE_CI)
X(CPE_DUMMY)
X(CPE_LATCH)

6
himbaechel/uarch/gatemate/gatemate.cc
View File

@@ -340,7 +340,7 @@ IdString GateMateImpl::getBelBucketForCellType(IdString cell_type) const
return id_GPIO;
else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_L2T5_U, id_CPE_CI))
return id_CPE_LT;
else if (cell_type.in(id_CPE_FF_U, id_CPE_FF_L, id_CPE_FF))
else if (cell_type.in(id_CPE_FF_U, id_CPE_FF_L, id_CPE_FF, id_CPE_LATCH))
return id_CPE_FF;
else if (cell_type.in(id_CPE_RAMIO, id_CPE_RAMI, id_CPE_RAMO))
return id_CPE_RAMIO;
@@ -371,9 +371,9 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
else if (bel_type == id_CPE_LT_L)
return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_CI, id_CPE_DUMMY);
else if (bel_type == id_CPE_FF_U)
return cell_type.in(id_CPE_FF_U, id_CPE_FF);
return cell_type.in(id_CPE_FF_U, id_CPE_FF, id_CPE_LATCH);
else if (bel_type == id_CPE_FF_L)
return cell_type.in(id_CPE_FF_L, id_CPE_FF);
return cell_type.in(id_CPE_FF_L, id_CPE_FF, id_CPE_LATCH);
else if (bel_type.in(id_CPE_RAMIO_U, id_CPE_RAMIO_L))
return cell_type.in(id_CPE_RAMIO, id_CPE_RAMI, id_CPE_RAMO);
else

4
himbaechel/uarch/gatemate/pack_cpe.cc
View File

@@ -192,7 +192,7 @@ void GateMatePacker::pack_cpe()
dff->renamePort(id_D, id_DIN);
dff->renamePort(id_Q, id_DOUT);
dff_to_cpe(dff);
dff->type = id_CPE_FF;
dff->type = (dff->type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
}
}
}
@@ -292,7 +292,7 @@ void GateMatePacker::pack_cpe()
lt->params[id_INIT_L10] = Property(0b1010, 4);
ci.movePortTo(id_D, lt, id_IN1);
dff_to_cpe(&ci);
ci.type = id_CPE_FF;
ci.type = (ci.type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
NetInfo *conn = ctx->createNet(ctx->idf("%s$di", ci.name.c_str(ctx)));
lt->connectPort(id_OUT, conn);
ci.ports[id_DIN].name = id_DIN;