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Fix signal routing

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This commit is contained in:
Miodrag Milanovic
2025-06-30 08:38:26 +02:00
parent 4a92942acb
commit b150f24e85
1 changed files with 3 additions and 0 deletions
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3
himbaechel/uarch/gatemate/pack_clocking.cc
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@@ -205,6 +205,9 @@ void GateMatePacker::pack_bufg()
// SER_CLK
clkin[die]->params[ctx->idf("REF%d", i)] = Property(0b100, 3);
clkin[die]->params[ctx->idf("REF%d_INV", i)] = Property(Property::State::S0);
NetInfo *conn = ctx->createNet(ci.name);
clkin[die]->connectPort(ctx->idf("CLK_REF%d", i), conn);
glbout[die]->connectPort(ctx->idf("CLK_REF_OUT%d", i), conn);
}
ci.movePortTo(id_O, glbout[die], ctx->idf("GLB%d", i));