Define open_(o|i)fstream_and_log_error in log.h to:
- quote 'filename'
- add error cause to easier troubleshoot
- use existing consistent string style
- easily allows OS specific message
Introduce it when file are opened and add it where error message
was missing.
* gatemate: removing recursion in GateMateImpl::reassign_bridges
* gatemate: improving comments in GateMateImpl:reassign_bridges
* gatemate: making naming more consistent, adding comments about the need for recursion removal
Add CLKDIV — a frequency divider with ratios of 1, 2, 3, 3.5, 4,
5, 6, 7, and 8.
A direct, non-switchable connection to CLKDIV2 makes placement more
difficult — we have to account for CLKDIV2’s occupancy for IOLOGIC and,
if necessary, duplicate the cell, as well as create clusters of CLKDIV
and CLKDIV2.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Implement GW5A HCLK and CLKDIV2.
HCLK pins have been added for the GW5A series, and the placement of
CLKDIV2 primitives has been updated to account for the specific
characteristics of this chip series.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix style.
* Gowin. Fix style.
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* GOWIN. BUGFIX. BSRAM port renaming.
The renumbering of the BSRAM pins has been corrected.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* GOWIN. Comment BSRAM port renaming
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add DL-series latch cell support
Teach the himbaechel Gowin backend to recognize and place all 12
DL-series latch primitives onto DFF BEL sites. Latches use the CLK
pin for the gate signal and share placement resources with DFFs.
* gowin: convert latches to DFFs with LATCH attribute during packing
Instead of teaching all DFF infrastructure about 12 DL latch types,
pack_latches() converts them to corresponding DFF types early and sets
a LATCH attribute. This attribute is picked up by gowin_pack to set
REGMODE=LATCH instead of FF.
* gowin: exclude latch gate signals from clock buffer promotion
Latch cells are mapped to DFFs with a LATCH attribute, so their gate
signal drives the CLK port. This caused pack_buffered_nets to promote
the gate signal onto a global clock buffer (BUFG), which has different
timing/initialization behavior and caused the first gate transition
to be lost. Skip CLK pins on cells with the LATCH attribute when
checking for clock users.
* gowin: update latch message to be user friendly.
* fix: handle string DRIVE property in pack_io without crashing
The XDC parser stores all set_property values as string Properties,
but pack_io.cc called as_int64() on DRIVE which asserts !is_string.
Rather than converting numeric values to integer Properties in the
XDC parser (which risks breaking properties like LOC that downstream
code reads via to_string()/as_string()), fix the consumption site
in pack_io.cc to convert string values to integers when needed.
* refactor: use int_or_default for DRIVE property parsing
Replace manual is_string/as_int64 branching with int_or_default(),
which already handles both Property types with proper error reporting.
Dual Port has a defective output register. This only manifests itself at
small data widths and only on -C chips.
That is, Tangprimer20k (GW2A-18) works perfectly, while Tangnano20k
(GW2A-18C) stutters. The same story with GW1N-9 and GW1N-9C.
Fortunately, the fix has long been included in nextpnr for SDP memory,
so all that remains is to call the same function for Dual Port.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
We are fixing a hardware error - in BYPASS mode, dual port bsram
requires synchronization of CE and OCE signals for some data widths.
We are also getting rid of port renaming in the loop, but not all of
them yet.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The new multiplier is made from two 27x18 units by switching inputs and
creating a cluster connected via CASO->CASI.
A second pass was required to process the multipliers created on the
fly—the processing of DSP cells was separated into a separate function,
which resulted in a large diff, but in reality there were very few
changes.
An important point is that in the 5A series, there is a gap between
adjacent DSPs in one row. There are still SIA/CASI wires, so the DSPs on
either side of the gap are connected, but the distance between them is
greater than usual. We take this fact into account based on the gap
coordinates from the chip database.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This primitive occupies one DSP block entirely and can be connected into
complex chains both by arguments (shifting operands from SOA to SIA) and
by results (CASO->CASI cascades).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: add CCF floorplanning parser
* apply constraints
* cleanup
* print detected region and error if not found
* Add wildcard matching
* Validate placebox and use official coordinate system
* Fix some messages
* gatemate: improve mode arg error message
* gatemate: fix initial capitals and periods in log_*() messages
* gatemate: replace operation -> performance for mode in help and log_*()
This is the term used both in the datasheet and the primitive library PDF.
* gatemate: add alternate clock routes
* use additional pins
* Fix clock router and timings
* Fix DDR nets
* Test passtrough concept
* remove not used variable
* wip
* handle pip masks
* Cleanup
* create CPE_CPLINES cells and set properties on them
* Fix pip masking
* rough code to break cplines into subnets
* add ports to cell
* mux bridges need cell bel pins too
* fix multiplier output register packing
* remove empty if
* Fix ODDR
* Add options to disable some pips
* Use resources info
* mask field to resource field
* produce valid netlist with propagation netlist at least
* adapt reassign_cplines for internal resource pips
* Handle block and resources
* fix formatting
* It is required to set all mandatory properties now
* arch API for resources
* current progress
* Add option to skip bridges
* perform per-wire resource congestion costing
* Added no-cpe-cp option
* resource bugfix
* comment out spammy debug message
* Fix routing conflicts issues
* allow only some pass trough for clock router
* handle inversion bits for pass signals
* verify inversion before/after assigning bridges
* we care only if there is net
* Revert "we care only if there is net"
This reverts commit 3da2769e31.
* Revert "verify inversion before/after assigning bridges"
This reverts commit 8613ee17c8.
* chipdb version bump
* clangformat
* cleanup
* cleanup
* Initial conversion to GroupId
* Keep group info in pip extra
* Cleanup headers
* Initialize resource efficiently
* Addressing review comments
* improve resource docs
* Make CP lines not use as clocks as default
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
* Gowin. DSP. Implement MULT12x12.
The 5A series DSP differs from previous ones. Many things have been
greatly simplified: there are only two control signals of one type per
cell (2 CLK, 2 CE and 2 RESET), and these signals are now explicitly
specified in the DSP attributes, which makes the automatic assignment
mechanism unnecessary for them.
The DSP occupies 3 cells instead of nine due to the exclusion of 4
low-bit multipliers - now there are only two 12x12. There will naturally
be clusters, but they will be simpler and consist of other primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Implement MULTADDALU12X12.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
