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nextpnr-0.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

nextpnr-0.9

Mono Color

• 3de0be7c06 interchange: xdc: add get_cells command Alessandro Comodi 2021-07-12 16:44:33 +02:00
• d9668df818 interchange: add constraints constraints application routine Alessandro Comodi 2021-07-12 16:02:51 +02:00
• 24b7084feb Merge pull request #760 from YosysHQ/gatecat/xcup-ibufds gatecat 2021-07-12 13:00:44 +01:00
• f03abe14d1 interchange: Skip IO ports in dedicated routing check gatecat 2021-07-12 11:43:18 +01:00
• 8604b03008 interchange: Debug IO port validity check failures gatecat 2021-07-12 11:40:23 +01:00
• 96a5885051 interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDS gatecat 2021-07-12 11:30:21 +01:00
• a63e7b3db8 Merge pull request #759 from pepijndevos/gw1ndb gatecat 2021-07-11 14:00:52 +01:00
• c89c14b6bf GW1NR is not a seperate family, but GW1NS is Pepijn de Vos 2021-07-11 14:12:34 +02:00
• eecc6147df Merge pull request #758 from YosysHQ/gatecat/hist-oob gatecat 2021-07-11 08:10:57 +01:00
• 76070a7647 timing: Fix out-of-bounds histogram bins in all cases gatecat 2021-07-10 23:44:21 +01:00
• 8531658019 Merge branch 'master' of github.com:YosysHQ/nextpnr gatecat 2021-07-10 23:24:38 +01:00
• d290766101 ice40: Fix order of values in error gatecat 2021-07-10 23:23:19 +01:00
• 478456e6e9 Merge pull request #755 from yrabbit/io_port gatecat 2021-07-08 17:22:10 +01:00
• 7b62c7fa50 Merge pull request #756 from acomodi/fix-clustering-runtime gatecat 2021-07-08 16:58:44 +01:00
• b64642fc99 interchange: bump python-interchange version Alessandro Comodi 2021-07-08 16:41:17 +02:00
• fbd291deaf interchange: update chipdb version Alessandro Comodi 2021-07-08 16:43:30 +02:00
• dc0819b01a interchange: reduce run-time to check dedicated interconnect Alessandro Comodi 2021-07-07 19:16:48 +02:00
• 6829e4c197 clangformat gatecat 2021-07-08 15:42:36 +01:00
• 881fd97c5a Fix the boolean. YRabbit 2021-07-08 07:09:30 +10:00
• d613626ab9 Fix formating YRabbit 2021-07-07 22:53:49 +10:00
• 5d8b27710d Fix boolean value. YRabbit 2021-07-07 22:02:43 +10:00
• 5f018df4e4 Merge branch 'master' into io_port YRabbit 2021-07-07 08:36:45 +10:00
• fd7734f000 Wip parser YRabbit 2021-07-07 08:36:05 +10:00
• c696e88573 Merge pull request #751 from trabucayre/gw1ns-2 gatecat 2021-07-06 15:17:41 +01:00
• bf542f07b0 Merge pull request #754 from YosysHQ/gatecat/ecp5-dcs gatecat 2021-07-06 14:06:31 +01:00
• 027d54e771 .cirrus/Dockerfile.ubuntu20.04: update apycula to 0.0.1a9 Gwenhael Goavec-Merou 2021-07-06 14:34:33 +02:00
• 5b2db015a9 Merge pull request #752 from YosysHQ/gatecat/du-mem-error gatecat 2021-07-06 12:43:48 +01:00
• 81c549549d ecp5: Add DCSC support gatecat 2021-07-06 11:45:27 +01:00
• c0bb2fb76a Merge pull request #750 from YosysHQ/gatecat/io-improve gatecat 2021-07-06 11:43:24 +01:00
• 3d0facf119 design_utils: Fix memory error gatecat 2021-07-06 11:34:14 +01:00
• 96263058c3 add support for GW1NS-2 family Gwenhael Goavec-Merou 2021-06-18 09:20:24 +02:00
• 31abefc8e4 interchange: Allow pseudo pip wires to overlap with bound site wires on the same net gatecat 2021-07-06 10:38:08 +01:00
• 6fe071ad1d router2: Dump pre-bound routes when routing fails in debug mode gatecat 2021-07-06 10:21:31 +01:00
• f64d06fa02 interchange: Improve search for PAD-attached bels gatecat 2021-07-06 10:13:50 +01:00
• 6edc11de4d interchange: tests: add obuftds test Alessandro Comodi 2021-07-05 13:34:34 +02:00
• baa68fa4c1 Parser YRabbit 2021-07-05 08:31:01 +10:00
• 1aae331ddc Merge branch 'master' into io_port YRabbit 2021-07-03 10:09:38 +10:00
• 5c5982c50a Fix parser. Comments and IO_PORT YRabbit 2021-07-03 08:23:25 +10:00
• 8a9fb81036 Merge pull request #748 from acomodi/fix-phys-net-writing gatecat 2021-07-02 18:34:46 +01:00
• 888a2462af interchange: phys: skip only nets writing on disconnected out ports Alessandro Comodi 2021-07-02 16:11:58 +02:00
• 9443267717 Syntax YRabbit 2021-07-02 14:58:17 +10:00
• a65f0e57b9 Add IO_PORT parsing YRabbit 2021-07-02 14:00:20 +10:00
• fe38e70dc1 Merge pull request #747 from cr1901/machxo2 gatecat 2021-07-01 20:17:02 +01:00
• 55c663f7ac Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const gatecat 2021-07-01 15:28:24 +01:00
• 344cfe6216 Merge pull request #745 from YosysHQ/gatecat/ic-node-source gatecat 2021-07-01 15:28:16 +01:00
• 41d09f7187 machxo2: Fix packing for directly-connected DFFs. William D. Jones 2021-06-30 15:23:09 -04:00
• e625876949 machxo2: Add VHDL primitives, demo, and script. William D. Jones 2021-04-13 17:37:30 -04:00
• 45c33e9dcf machxo2: Add a special case for pips whose config bits are in multiple tiles. William D. Jones 2021-02-23 06:51:40 -05:00
• ec239c8c35 machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output. William D. Jones 2021-02-22 22:33:47 -05:00
• b1f25d4b33 machxo2: Set Pip and Wire delays to reasonable fake values mirroring estimateDelay. William D. Jones 2021-02-22 21:52:39 -05:00
• 74ffe2c543 interchange: Handle canInvert PIPs when processing preferred constants gatecat 2021-07-01 13:47:02 +01:00
• f17643bc08 interchange: Handle case where routing source is a node gatecat 2021-07-01 13:19:10 +01:00
• 86bc708299 clangformat gatecat 2021-07-01 13:18:34 +01:00
• ddff2e2e5e Merge pull request #744 from YosysHQ/gatecat/const-in-macro gatecat 2021-07-01 13:12:38 +01:00
• 79ab283890 Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports gatecat 2021-07-01 13:12:29 +01:00
• 8b4e880827 Merge pull request #742 from acomodi/interchange-do-not-output-zero-user-nets gatecat 2021-07-01 13:12:19 +01:00
• 006a40a353 interchange: Fix handling of constants in macros gatecat 2021-07-01 11:45:23 +01:00
• dd7cfccbae interchange: phys: do not output nets which have no users Alessandro Comodi 2021-07-01 11:56:55 +02:00
• 523ffbaa37 interchange: Reserve site ports only reachable from dedicated routing gatecat 2021-07-01 11:08:36 +01:00
• 2124da44d8 Merge pull request #741 from acomodi/fix-ded-interc gatecat 2021-06-30 20:09:52 +01:00
• cfbd1dfa4d interchange: fix dedicated interconnect exploration Alessandro Comodi 2021-06-30 18:43:15 +02:00
• 152c41c3ac Merge pull request #739 from YosysHQ/gatecat/usp-io-macro gatecat 2021-06-30 13:00:12 +01:00
• b3882f8324 interchange: Fix dedicated interconnect check when site is the same gatecat 2021-06-30 11:48:51 +01:00
• ef18590043 interchange: Place IO macro content based on routing gatecat 2021-06-30 11:37:30 +01:00
• 91b998bb11 Merge pull request #738 from YosysHQ/json_load_reinit gatecat 2021-06-30 09:59:38 +01:00
• 5c6b8a5f04 Preserve ArchArgs and reinit Context when applicable in GUI Miodrag Milanovic 2021-06-30 10:10:18 +02:00
• 6c23fe202c loading json should be disabled in this place Miodrag Milanovic 2021-06-30 09:46:25 +02:00
• 2476f116bb interchange: Track the macros that cells have been expanded from gatecat 2021-06-29 14:48:47 +01:00
• 78c965141f Merge pull request #736 from YosysHQ/gatecat/pp-multi-output gatecat 2021-06-28 16:27:04 +01:00
• 7115dd3393 Merge pull request #735 from YosysHQ/gatecat/ic-disconn-belpin gatecat 2021-06-28 16:26:53 +01:00
• 65a4bce9ad interchange: Allow site wires driven by more than one bel gatecat 2021-06-28 14:55:56 +01:00
• 980a7013d2 interchange: Handle disconnected bel pins in dedicated interconnect gatecat 2021-06-28 14:45:27 +01:00
• 454617f0cb Merge pull request #734 from acomodi/remove-rw-patch gatecat 2021-06-24 08:27:47 +01:00
• 721e760f1a ci: remove RapidWright patching Alessandro Comodi 2021-06-24 08:23:35 +02:00
• c73d4cf6dd Merge pull request #733 from acomodi/interchange-move-macro-before-io gatecat 2021-06-18 19:09:18 +01:00
• 0344fdcf8d interchange: arch: move macro expansion step before ios packing Alessandro Comodi 2021-06-18 16:41:19 +02:00
• 0f9a88b2cd Merge pull request #731 from YosysHQ/gatecat/timing-mem-error gatecat 2021-06-17 18:32:43 +01:00
• 889c295baf sta: Fix a memory error introduced by the dict move gatecat 2021-06-17 12:06:26 +01:00
• 167867ff7c Merge pull request #730 from YosysHQ/gatecat/dcc-routehtru gatecat 2021-06-17 08:53:54 +01:00
• 3d528adfdc nexus: Disable center DCC-thrus on 17k device gatecat 2021-06-16 13:47:21 +01:00
• 84fc2877c6 nexus: Fix FASM gen for DCC-thru gatecat 2021-06-16 13:23:42 +01:00
• ded32f3390 Merge pull request #728 from YosysHQ/gatecat/nexus-ram gatecat 2021-06-15 17:39:23 +01:00
• 9df05c4f98 interchange: Bump versions gatecat 2021-06-15 16:32:02 +01:00
• b77119e1a3 Merge pull request #729 from acomodi/interchange-fix-phys-net-writer gatecat 2021-06-15 15:45:09 +01:00
• f9054190fd interchange: fix phys net writer Alessandro Comodi 2021-06-15 14:07:20 +02:00
• 3e8f08895b nexus: Add modified version of RAM test gatecat 2021-06-15 09:11:14 +01:00
• f42ad6b90c nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules gatecat 2021-06-15 09:21:53 +01:00
• f4bfc2af5b Merge pull request #727 from YosysHQ/gatecat/ic-undriven gatecat 2021-06-14 11:57:56 +01:00
• 377f56c151 interchange: Cope with undriven nets in more places gatecat 2021-06-14 10:58:42 +01:00
• ee65e6f32d Merge pull request #724 from YosysHQ/gatecat/update-names gatecat 2021-06-12 14:07:47 +01:00
• c1d35c1bce Merge pull request #726 from YosysHQ/gatecat/mem-errors gatecat 2021-06-12 14:02:07 +01:00
• c401ca3d1e Bump tests submodule gatecat 2021-06-09 13:20:39 +01:00
• 1941d1aa81 Update URLs gatecat 2021-06-09 13:13:50 +01:00
• 2ffb081442 Fixing old emails and names in copyrights gatecat 2021-06-09 13:09:08 +01:00
• f9d3b99e63 HeAP: Fix memory error introduced by switch to dict gatecat 2021-06-12 13:07:11 +01:00
• 1c7efdc02c Merge pull request #720 from acomodi/interchange-clusters gatecat 2021-06-11 11:36:42 +01:00
• aa1784c5d9 interchange: ci: add RW patch for missing cell bel maps Alessandro Comodi 2021-06-11 11:49:27 +02:00
• b65dbd5c9e interchange: clusters: always get cell bel map and add asserts Alessandro Comodi 2021-06-11 11:17:43 +02:00
• af520f0f92 interchange: ci: update python-interchange tag Alessandro Comodi 2021-06-10 18:21:21 +02:00
• 64b45848d7 interchange: run clang formatter Alessandro Comodi 2021-06-10 13:46:53 +02:00