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nextpnr-0.1

nextpnr-0.2

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nextpnr-0.4

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nextpnr-0.6

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nextpnr-0.8

nextpnr-0.9

Mono Color

• 2912860c97 Merge pull request #677 from YosysHQ/gatecat/ppip-no-input gatecat 2021-04-13 11:49:48 +01:00
• 06e54f08e6 interchange: Allow pseudo-cells with no input pins gatecat 2021-04-13 09:49:04 +01:00
• 423da76ff2 Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash gatecat 2021-04-13 10:34:14 +01:00
• ece10c3e04 timing: Fix domain init when loops are present gatecat 2021-04-13 09:23:08 +01:00
• 5cd2a7f9c2 Merge pull request #674 from adamgreig/heap-spreader-fix gatecat 2021-04-12 14:16:22 +01:00
• dc6453b720 Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-ref gatecat 2021-04-12 13:54:11 +01:00
• 2fdf41ac01 HeAP: Skip high-strength cells in both cell loops. Adam Greig 2021-04-12 13:42:20 +01:00
• fc15105643 clangformat gatecat 2021-04-12 10:26:39 +01:00
• 5b35329abb fast_bels: Don't return pointer that might become invalid gatecat 2021-04-12 10:23:41 +01:00
• b5731cee02 Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc gatecat 2021-04-09 14:33:12 +01:00
• 9cc09207fc Merge pull request #669 from YosysHQ/gatecat/prjoxide-pin gatecat 2021-04-09 11:37:54 +01:00
• 7acef00443 interchange: Pin prjoxide commit gatecat 2021-04-09 11:09:42 +01:00
• 93e34b8754 interchange: Disambiguate cell and bel pins when creating Vcc ties gatecat 2021-04-09 10:23:56 +01:00
• 581682a08e Merge pull request #667 from YosysHQ/fix_qt Miodrag Milanović 2021-04-08 13:40:44 +02:00
• 157cc1b60c Add same fix as in issue #373 Miodrag Milanovic 2021-04-08 12:33:34 +02:00
• 883ece6034 Merge pull request #665 from cr1901/optional-lto gatecat 2021-04-07 12:21:23 +01:00
• 2cb2985539 Add CMake option to enable IPO (enabled by default). William D. Jones 2021-04-07 06:24:29 -04:00
• 31eda82b3f Merge pull request #659 from litghost/pseudo_pip_fixes gatecat 2021-04-06 20:08:37 +01:00
• 8501098c16 Merge pull request #663 from litghost/fix_router2_without_bb gatecat 2021-04-06 19:35:55 +01:00
• ae2f7551c1 [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined. Keith Rothman 2021-04-02 16:23:29 -07:00
• c43ad2fab6 Don't fail-fast for GH actions to allow for easier CI debugging. Keith Rothman 2021-04-05 10:10:11 -07:00
• 3200026e1f [interchange] Remove requirement to have wire_lut. Keith Rothman 2021-04-02 16:21:41 -07:00
• c2a6f6ce62 [interchange] Fix invalid use of local variables due to refactoring. Keith Rothman 2021-04-02 16:20:12 -07:00
• 8773c645ca [interchange] Prevent site router from generating incorrect LUTs. Keith Rothman 2021-04-01 15:19:21 -07:00
• c11ad31393 [interchange] Scale edge cost of pseudo pips. Keith Rothman 2021-04-01 15:18:17 -07:00
• 9b82ded77b [interchange] Fix missing inline methods in site_arch.impl.h Keith Rothman 2021-04-01 15:17:08 -07:00
• 90aa1d3b7e [interchange] Disallow site edges during general routing. Keith Rothman 2021-04-01 15:12:53 -07:00
• 0d41fff3a7 [interchange] Add crude pseudo pip model. Keith Rothman 2021-04-01 13:18:07 -07:00
• a519341112 Fix bug in router2 where router may give up too early. Keith Rothman 2021-04-05 16:11:05 -07:00
• ff449ca997 Merge pull request #661 from litghost/document_site_router gatecat 2021-04-06 09:20:03 +01:00
• cf6833b9cd Merge pull request #662 from litghost/fix_cirrus_ci gatecat 2021-04-06 09:18:30 +01:00
• 8e0d8df791 Merge pull request #657 from acomodi/interchange-counter-multi-board gatecat 2021-04-06 08:12:02 +01:00
• d399d3ae1b Increase vCPU to 5 because of cirrus resource limit change. Keith Rothman 2021-04-05 16:12:47 -07:00
• 4301e4705b [interchange] Add some documentation for the site router. Keith Rothman 2021-04-05 15:15:48 -07:00
• bb6079133c Merge pull request #658 from litghost/increment_chipdb gatecat 2021-04-02 09:46:21 +01:00
• 3a85088d66 [interchange] Update interchange CI for new chipdb change. Keith Rothman 2021-04-01 15:24:38 -07:00
• 009d3b64b6 [interchange] Update to v6 of FPGA interchange chipdb. Keith Rothman 2021-04-01 15:16:23 -07:00
• 366f8782cb interchange: counter: testing on multiple boards Alessandro Comodi 2021-03-31 12:10:28 +02:00
• ec98fee1ee Merge pull request #646 from YosysHQ/gatecat/nexus-cmake gatecat 2021-03-31 15:14:51 +01:00
• 3678eff5dc interchange: Fix nexus cmake review comments gatecat 2021-03-31 10:11:09 +01:00
• edecc06fcf Merge pull request #656 from litghost/fix_dedicated_interconnect_bug gatecat 2021-03-30 22:36:51 +01:00
• 8675945b26 Fix bug where DedicateInterconnect incorrectly allows some placement. Keith Rothman 2021-03-30 13:23:15 -07:00
• 4dc45ffdc8 Merge pull request #653 from litghost/fix_site_pip_check gatecat 2021-03-30 18:50:16 +01:00
• 7e47af1085 [interchange] Fix site pip check for drivers. Keith Rothman 2021-03-29 16:19:47 -07:00
• 9259763599 ci: Build prjoxide only for LIFCL gatecat 2021-03-30 16:33:50 +01:00
• a003aae7c2 interchange: Split xc7 and nexus chipdb cmake gatecat 2021-03-30 11:05:43 +01:00
• ecfaae7f9e interchange: Add Nexus LUT test gatecat 2021-03-25 12:51:19 +00:00
• b6b8959397 interchange: Add Nexus to CI gatecat 2021-03-24 13:17:12 +00:00
• 3cb5e81d50 interchange: Add CMake support for Nexus/prjoxide gatecat 2021-03-24 11:09:06 +00:00
• 7a9082e698 Merge pull request #655 from YosysHQ/gatecat/alt-placer-fix gatecat 2021-03-30 16:20:41 +01:00
• 8863b962fd interchange: Fix illegal placements gatecat 2021-03-30 14:44:18 +01:00
• 99298d0aba nexus: Fix some IO FASM gen gatecat 2021-03-30 12:04:01 +01:00
• 7ae3f636ef nexus: Fix LIFCL-17 LRAM FASM gatecat 2021-03-30 11:56:07 +01:00
• a6a92f6b6b nexus: Fix default IO config gatecat 2021-03-29 21:35:44 +01:00
• 0b1e089547 Merge pull request #651 from YosysHQ/gatecat/nexus-vcco gatecat 2021-03-29 21:32:35 +01:00
• df339f4f3c nexus: Default HF_OSC_EN to ENABLED gatecat 2021-03-29 21:25:14 +01:00
• d2579282a6 nexus: Fix bank Vcco FASM gatecat 2021-03-29 20:38:50 +01:00
• 692d7dc26d Merge pull request #645 from litghost/add_counter_and_ram gatecat 2021-03-29 18:23:16 +01:00
• 4419c36db5 Merge pull request #649 from acomodi/add-archcheck-to-all-tests gatecat 2021-03-26 18:39:18 +00:00
• d0bc033ab8 gh-actions: better yosys caching based on version Alessandro Comodi 2021-03-26 12:01:16 +01:00
• b5ba3ee9ee interchange: add archcheck tests to all-device-test target Alessandro Comodi 2021-03-26 10:24:59 +01:00
• 0e9a1abc7e Merge pull request #650 from YosysHQ/gatecat/nexus-17k-fixes gatecat 2021-03-26 14:04:40 +00:00
• 0f425aff5a nexus: Fix FASM gen for LIFCL-17 gatecat 2021-03-26 13:06:03 +00:00
• f33d02dca9 Update README with latest develpment progress. Keith Rothman 2021-03-25 17:54:44 -07:00
• 55c9d43c70 interchange: Fix bug in site router where a bad solution isn't remove. Keith Rothman 2021-03-25 17:12:13 -07:00
• c8dccd3e7b Implement debugging tools for site router. Keith Rothman 2021-03-25 17:11:06 -07:00
• cc4f2b4516 Add some FIXME's around VCC assumption in LUT logic. Keith Rothman 2021-03-25 13:36:11 -07:00
• bbe1881293 Add targets to generate YAML outputs for DeviceResource files. Keith Rothman 2021-03-25 13:34:06 -07:00
• 91ca5f110b Re-work LUT mapping logic to only put VCC pins when required. Keith Rothman 2021-03-24 16:25:15 -07:00
• 5dda3a14ff Fixup some of the re-mapping logic. Keith Rothman 2021-03-24 11:07:45 -07:00
• 77bc2f9130 Add initial handling of local site inverters and constant signals. Keith Rothman 2021-03-23 16:53:42 -07:00
• 5e96740451 [FPGA interchange] Small fix to get_net_type. Keith Rothman 2021-03-23 10:57:37 -07:00
• 22fb2c1548 Enable counter tests and add RAM tests. Keith Rothman 2021-03-22 17:59:20 -07:00
• 7b1df27c1a Merge pull request #648 from YosysHQ/gatecat/nexus-get_pins gatecat 2021-03-25 17:36:21 +00:00
• c388cebf7f nexus: Add support for get_pins PDC command gatecat 2021-03-25 16:39:24 +00:00
• f233bee970 Merge pull request #628 from acomodi/add-interchange-devices gatecat 2021-03-25 16:03:22 +00:00
• c4cb86efe9 gh-actions: use ccache and build tools before running tests Alessandro Comodi 2021-03-25 11:52:39 +01:00
• 9f28fa4e75 gh-actions: interchange: multiple jobs, one for each device Alessandro Comodi 2021-03-24 11:11:29 +01:00
• 1a774a0526 interchange: examples: remove unused makefiles Alessandro Comodi 2021-03-24 12:00:10 +01:00
• b6d2a59fc2 interchange: devices: bel_bucket_seeds -> device_config Alessandro Comodi 2021-03-23 21:05:31 +01:00
• 15e945aa1c interchange: added boards and group testing across multiple boards Alessandro Comodi 2021-03-23 20:35:53 +01:00
• 2956a0ca03 gh-actions: remove multi-process arch generation Alessandro Comodi 2021-03-23 16:56:33 +01:00
• 4812092cdb fpga_interchange: add test data for new architectures Alessandro Comodi 2021-03-19 17:38:45 +01:00
• 658dadaa70 fpga_interchange: use higher java heap space Alessandro Comodi 2021-03-18 20:37:51 +01:00
• 336d31cbcf fpga_interchange: add more devices Alessandro Comodi 2021-03-17 18:43:29 +01:00
• 3cc50a5744 Merge pull request #644 from litghost/add_global_buffers gatecat 2021-03-23 17:33:55 +00:00
• 323da87dec Merge pull request #643 from litghost/id_constants gatecat 2021-03-23 17:33:40 +00:00
• 2300d81c3c Merge pull request #640 from litghost/inversion_logic gatecat 2021-03-23 16:59:35 +00:00
• 8c85e648df Merge pull request #639 from litghost/parameter_iteration gatecat 2021-03-23 16:51:28 +00:00
• 720f64ea60 [FPGA interchange] Add support for global buffers from chipdb. Keith Rothman 2021-03-23 09:41:45 -07:00
• 0dd93035e4 [FPGA interchange] Convert some string constants to IdString. Keith Rothman 2021-03-23 09:37:22 -07:00
• b7bf2c706f Merge pull request #642 from YosysHQ/gatecat/missing-cell-pin gatecat 2021-03-23 16:34:10 +00:00
• 831b94cdac Initial version of inverter logic. Keith Rothman 2021-03-22 17:38:15 -07:00
• ae71206e1f Update FPGA interchange chipdb to v4 with inverter data. Keith Rothman 2021-03-22 17:38:15 -07:00
• 8a50b02b9b Use new parameter definition data in FPGA interchange processing. Keith Rothman 2021-03-22 15:55:34 -07:00
• af1fba9f52 Update latest version of FPGA interchange schema. Keith Rothman 2021-03-22 12:42:11 -07:00
• 4d8dcab1d3 Merge pull request #641 from litghost/initial_lookahead gatecat 2021-03-23 16:00:17 +00:00
• 79400756f5 interchange: Add nice error for missing cell pins gatecat 2021-03-23 15:40:34 +00:00
• 8d1eb0a195 Initial lookahead for FPGA interchange. Keith Rothman 2021-03-22 17:46:00 -07:00
• 9ef412c2cc Merge pull request #638 from litghost/fixup_physical_netlist_writer gatecat 2021-03-22 18:32:26 +00:00