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nextpnr-0.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

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Mono Color

• 9ef412c2cc Merge pull request #638 from litghost/fixup_physical_netlist_writer gatecat 2021-03-22 18:32:26 +00:00
• a3ed97c0db Merge pull request #637 from litghost/refine_site_router gatecat 2021-03-22 18:32:04 +00:00
• e8d36bf5bd Merge pull request #634 from litghost/add_get_bel_pin_type gatecat 2021-03-22 18:31:48 +00:00
• f6ae068cb2 Merge pull request #632 from litghost/add_check_pip_for_net gatecat 2021-03-22 18:31:32 +00:00
• 32f2ec86c4 Rework FPGA interchange site router. Keith Rothman 2021-03-19 18:26:00 -07:00
• 0f4014615c Add missing dependencies to CMake targets. Keith Rothman 2021-03-19 18:28:48 -07:00
• 06bcde6243 Correct some bugs in writing of physical netlist w.r.t. site sources. Keith Rothman 2021-03-19 18:52:27 -07:00
• 4cd74bba2c Add getBelPinType to Python interface. Keith Rothman 2021-03-19 17:18:01 -07:00
• e7d81913a4 Add "checkPipAvailForNet" to Arch API. Keith Rothman 2021-03-18 16:31:40 -07:00
• 53ed6979a9 Merge pull request #636 from litghost/add_pseudo_pip_data gatecat 2021-03-22 15:24:36 +00:00
• 694f9ec3a5 Increment required python-fpga-interchange version. Keith Rothman 2021-03-19 18:15:24 -07:00
• db12a83ced Add pseudo pip data to chipdb (with schema bump). Keith Rothman 2021-03-19 18:10:30 -07:00
• 68ca923bfe Merge pull request #635 from litghost/refactor_headers gatecat 2021-03-22 09:30:38 +00:00
• 22c6754bcd Update tests to include Tcl header order fix. Keith Rothman 2021-03-19 18:11:30 -07:00
• 2cd5bacca0 Refactor header structures in FPGA interchange Arch. Keith Rothman 2021-03-19 17:35:29 -07:00
• f52b522964 Merge pull request #633 from YosysHQ/gatecat/optional-ipo gatecat 2021-03-19 10:38:12 +00:00
• bac2a8ba02 cmake: Use IPO only if supported gatecat 2021-03-19 09:39:34 +00:00
• aa8b12db6f Merge pull request #631 from litghost/fixup_gui_dependencies gatecat 2021-03-18 22:02:37 +00:00
• bc3fe7d014 Merge pull request #630 from litghost/run_clangformat gatecat 2021-03-18 21:38:02 +00:00
• 76c6e1248c Add option to link against "libprofiler". Keith Rothman 2021-03-18 14:02:07 -07:00
• d5021e7ed5 Add IPO support for nextpnr, and have it enabled by default. Keith Rothman 2021-03-18 14:01:40 -07:00
• f4dc67879e Fixup GUI link dependencies on headers from libraries. Keith Rothman 2021-03-18 13:47:06 -07:00
• a3dd5b33bc Run "make clangformat". to fix up master. Keith Rothman 2021-03-18 13:30:37 -07:00
• b8678e778e Merge pull request #629 from litghost/move_hash_selection_to_header gatecat 2021-03-18 08:14:16 +00:00
• 965ba00e0f Moving hash map/set type selection to header. Keith Rothman 2021-03-17 16:53:05 -07:00
• 5feea4497f Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchange gatecat 2021-03-17 14:05:49 +00:00
• 01a95faf21 fpga_interchange: temporarily disable failing test Alessandro Comodi 2021-03-17 10:32:35 +01:00
• f6583f7ecc fpga_interchange: minor fixes and comments addition Alessandro Comodi 2021-03-16 22:40:15 +01:00
• c1e668f823 fpga_interchange: address review comments Alessandro Comodi 2021-03-16 21:49:06 +01:00
• f9e9fadbc8 github-actions: use capnp v0.8.0 Alessandro Comodi 2021-03-16 16:56:13 +01:00
• 83544cdf6a github-actions: pin python-fpga-interchange to tag Alessandro Comodi 2021-03-16 16:34:27 +01:00
• c68dfb09c4 github-actions: add basic CI to test FPGA interchange Alessandro Comodi 2021-03-16 15:37:42 +01:00
• f63a9a48a4 fpga_interchange: re-add README with updated instructions Alessandro Comodi 2021-03-15 18:03:14 +01:00
• f52b5b39ed fpga_interchange: tests: add techmap optional source file Alessandro Comodi 2021-03-15 11:02:56 +01:00
• 3f3cabea2d fpga_interchange: add bbasm step and archcheck Alessandro Comodi 2021-03-15 10:51:37 +01:00
• 0b62e540a3 fpga_interchange: address review comments Alessandro Comodi 2021-03-12 20:04:51 +01:00
• bd2da27e4e fpga_interchange: tests: added comment and fixed XDC Alessandro Comodi 2021-03-12 19:03:02 +01:00
• e5cc03965e fpga_interchange: chipdb: use generic patching function Alessandro Comodi 2021-03-12 19:02:00 +01:00
• 490fdb0a1c fpga_interchange: cmake: generate only one device family Alessandro Comodi 2021-03-12 16:37:00 +01:00
• 77ffdd7fd4 fpga_interchange: tests: add cmake functions Alessandro Comodi 2021-03-12 13:53:09 +01:00
• 6a08b0d733 bump fpga_interchange_schema Alessandro Comodi 2021-03-12 12:26:18 +01:00
• d77d0ff34a fpga_intrchange: add cmake infrastructure to generate chipdbs Alessandro Comodi 2021-03-12 12:25:41 +01:00
• 701587241f Merge pull request #626 from YosysHQ/missing-includes gatecat 2021-03-16 09:43:35 +00:00
• e1cd98ba15 Add missing includes to fix WASI build. whitequark 2021-03-16 05:52:41 +00:00
• bf5f0fc58f Merge pull request #625 from litghost/use_namespace_macro gatecat 2021-03-15 21:08:28 +00:00
• 351ca3b5ea Use NEXTPNR_NAMESPACE macro's now that headers are seperated. Keith Rothman 2021-03-15 10:25:46 -07:00
• a8e35062c6 Merge pull request #621 from litghost/fix_header_nightmare gatecat 2021-03-15 17:00:52 +00:00
• 3cf4a33666 Merge pull request #624 from YosysHQ/gatecat/fix-623 gatecat 2021-03-15 17:00:03 +00:00
• 3c71911c26 opt-timing: Skip undriven nets gatecat 2021-03-15 16:08:47 +00:00
• fe4608386e Split nextpnr.h to allow for linear inclusion. Keith Rothman 2021-03-12 13:09:44 -08:00
• 035b797ec2 Merge pull request #620 from litghost/handle_partial_routed gatecat 2021-03-12 22:25:24 +00:00
• a342ae56e0 Add support for partially routed nets from the placer in router2. Keith Rothman 2021-03-12 09:51:55 -08:00
• bffaad477a Merge pull request #618 from YosysHQ/no-absl-on-wasi gatecat 2021-03-12 11:23:10 +00:00
• bdf13ddcfb CMake: Don't include Abseil if it is not used. whitequark 2021-03-12 03:00:58 +00:00
• cc367d7e67 Merge pull request #615 from litghost/add_lookahead_diag_to_router2 gatecat 2021-03-10 18:24:11 +00:00
• 7168cf8657 Add diagnostic prints to debug lookahead performance. Keith Rothman 2021-03-09 13:26:05 -08:00
• 7f0c23dff3 Merge pull request #617 from YosysHQ/no-absl-on-wasi gatecat 2021-03-10 10:03:24 +00:00
• 979e7b8709 Only depend on Abseil in threaded builds. whitequark 2021-03-10 06:18:42 +00:00
• d1f44fe91a Merge pull request #607 from litghost/add_absl_flat_hash_map gatecat 2021-03-09 08:48:25 +00:00
• 326b34887c Merge pull request #609 from YosysHQ/gatecat/sta-v2 gatecat 2021-03-09 08:48:12 +00:00
• 0f17e80eef Merge pull request #613 from YosysHQ/gatecat/nexus-dphy gatecat 2021-03-08 21:11:13 +00:00
• 08c7f97b1e nexus: Support for hard DPHY gatecat 2021-03-08 15:05:58 +00:00
• 91064c7ec8 nexus: Add pin definitions for DPHY gatecat 2021-03-04 19:37:44 +00:00
• e1534e1dec Merge pull request #612 from YosysHQ/gatecat/router2-bb-fix gatecat 2021-03-08 15:58:56 +00:00
• da88d3d825 router2: Fix vast perf drop when leaving bounding box gatecat 2021-03-08 15:05:15 +00:00
• 55fa8b7745 nexus: Fix copypasta gatecat 2021-03-08 14:40:13 +00:00
• f0e30abf62 nexus: Fail gracefully when seeing special pins gatecat 2021-03-05 12:15:58 +00:00
• 8a4bf3a780 timing: Integration tweaks gatecat 2021-03-05 10:04:35 +00:00
• 98d1c5a411 timing: Skip route delays for unplaced/nullptr cells gatecat 2021-03-04 11:34:20 +00:00
• 1ff2023f32 timing: Replace all users of criticality with new engine gatecat 2021-03-04 11:29:11 +00:00
• 5f6aaa2475 timing: Use new engine in SA except for budget-based mode gatecat 2021-03-04 10:24:59 +00:00
• ebc2527368 timing: Use new engine for HeAP gatecat 2021-03-04 10:14:20 +00:00
• bbf5a7d461 timing: Add support for critical path printing gatecat 2021-03-03 13:01:54 +00:00
• e681e0f14c timing: Slack and criticality computation gatecat 2021-03-03 10:39:03 +00:00
• 296e6d10c2 timing: Produce plausible Fmax figure gatecat 2021-03-02 11:00:34 +00:00
• 541376f8cc timing: Add Fmax printing for debugging gatecat 2021-03-02 10:54:33 +00:00
• 16e7bba87b timing: Add backwards path walking gatecat 2021-03-02 10:39:26 +00:00
• 0528ceead1 timing: Add forward path walking gatecat 2021-03-01 15:18:58 +00:00
• 9c8d1bd6e3 timing: Compute domain pairs gatecat 2021-03-01 14:50:00 +00:00
• 534e69fbff timing: Add port-domain tracking gatecat 2021-03-01 11:25:28 +00:00
• 7a546b1554 timing: Add topological sort from Yosys gatecat 2021-03-01 10:36:23 +00:00
• d0772ce1e3 timing: Import cell delays to our own structures gatecat 2021-02-26 11:25:07 +00:00
• fac6a6c068 timing: Data structures for STA rewrite gatecat 2021-02-26 10:38:39 +00:00
• 1aab019f1e Merge pull request #608 from YosysHQ/gatecat/lifcl-17 gatecat 2021-03-03 15:19:17 +00:00
• 685cc23b94 nexus: Fix global handling for LIFCL-17 gatecat 2021-03-03 13:46:05 +00:00
• fba71bd182 clangformat gatecat 2021-03-03 10:39:47 +00:00
• 6e38e236f8 Merge pull request #604 from litghost/add_counter_test gatecat 2021-03-03 07:06:07 +00:00
• 27fbee5233 Merge pull request #605 from litghost/add_placement_sanity_check gatecat 2021-03-02 08:27:12 +00:00
• 392156c250 Correct spelling of RAII and add missing check in unlock_early. Keith Rothman 2021-03-01 10:03:42 -08:00
• 0afa0da19f Add absl::flat_hash_map. Keith Rothman 2021-03-01 09:48:29 -08:00
• 99a2262d61 Use scope in router1/2 and placer1. Keith Rothman 2021-03-01 09:41:29 -08:00
• 6ff02248a3 Merge pull request #606 from pepijndevos/gowin_fixes gatecat 2021-02-28 18:20:11 +00:00
• 354d497a57 only one type of dff per slice Pepijn de Vos 2021-02-28 17:48:05 +01:00
• 6689bfe923 Merge pull request #603 from litghost/fix_trival_bad_swap gatecat 2021-02-26 20:06:02 +00:00
• 77a5a60a66 Fix latent bug with context locking in placer HeAP. Keith Rothman 2021-02-26 11:37:27 -08:00
• 7878561970 Add placement sanity check in placer_heap. Keith Rothman 2021-02-26 11:26:52 -08:00
• 71b92cb813 Update FPGA interchange README. Keith Rothman 2021-02-26 10:22:52 -08:00
• 78748a67be For now just return false in the site router. Keith Rothman 2021-02-26 09:44:52 -08:00
• cfa449c3f3 Initial LUT rotation logic. Keith Rothman 2021-02-24 14:02:21 -08:00
• 9cbfd0b967 Add counter test. Keith Rothman 2021-02-25 09:11:32 -08:00