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nextpnr-0.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

nextpnr-0.9

Mono Color

• 396af7470b Merge pull request #602 from YosysHQ/gatecat/remove-unused-constr gatecat 2021-02-26 11:03:21 +00:00
• b64f45a8ba Remove unused advanced timing constraint API gatecat 2021-02-26 10:07:00 +00:00
• 89928a0e6b Merge pull request #599 from litghost/allow_router2_to_use_preroutes gatecat 2021-02-26 09:44:03 +00:00
• 49fae99063 Merge pull request #601 from YosysHQ/no-default-Werror gatecat 2021-02-26 08:06:07 +00:00
• a0af4d8768 cmake: Don't enable any -Werror flags without opt-in. whitequark 2021-02-26 00:33:05 +00:00
• c64a910151 Allow router2 to use routed but not fixed arcs. Keith Rothman 2021-02-25 15:55:29 -08:00
• de107da5b3 Merge pull request #598 from YosysHQ/gatecat/compiler-flags gatecat 2021-02-25 16:16:37 +00:00
• 23413a4d12 Fix compiler warnings introduced by -Wextra gatecat 2021-02-25 11:21:39 +00:00
• 17183fff05 cmake: Enable -Wextra, and -Werror in some cases gatecat 2021-02-25 10:57:54 +00:00
• ab8dfcfba4 Merge pull request #591 from litghost/add_constant_network gatecat 2021-02-25 10:22:45 +00:00
• e2cdaa653c Merge pull request #597 from litghost/add_dynamic_bitarray gatecat 2021-02-24 18:22:16 +00:00
• e0a4af09ed Bump tests submodule. Keith Rothman 2021-02-24 09:04:43 -08:00
• 6d193ffd8b Fix some bugs found in review. Keith Rothman 2021-02-24 08:52:26 -08:00
• 4026082470 docs/archapi: Typo fixes gatecat 2021-02-24 15:28:33 +00:00
• 3650294e51 Add dynamic bitarray to common library. Keith Rothman 2021-02-23 15:36:51 -08:00
• 19ae97afd1 Merge pull request #595 from litghost/const_cell_info gatecat 2021-02-23 22:55:09 +00:00
• 5de1978632 Merge pull request #596 from litghost/make_clang_format gatecat 2021-02-23 22:49:35 +00:00
• a30043c8da Fix assorted bugs in FPGA interchange. Keith Rothman 2021-02-23 13:35:45 -08:00
• 184665652e Finish dedicated interconnect implementation. Keith Rothman 2021-02-22 09:13:44 -08:00
• 5574455d2a Working FF example now that constant merging is done. Keith Rothman 2021-02-19 17:28:25 -08:00
• 2fc353d559 Add initial logic for handling dedicated interconnect situations. Keith Rothman 2021-02-19 16:18:59 -08:00
• cd8297f54d Move RapidWright git URI back to upstream. Keith Rothman 2021-02-19 09:46:27 -08:00
• 5c6e231412 Remove some signedness warnings. Keith Rothman 2021-02-19 09:44:14 -08:00
• 46b38f8a40 Fix reference copy. Keith Rothman 2021-02-18 19:03:05 -08:00
• 3ccb164f2a Run "make clangformat". Keith Rothman 2021-02-18 16:57:09 -08:00
• 15459cae91 Initial working constant network support! Keith Rothman 2021-02-18 16:51:36 -08:00
• cf554f9338 Add constant network test case. Keith Rothman 2021-02-18 16:51:05 -08:00
• 3e5a23ed5b Add tests to confirm constant routing import. Keith Rothman 2021-02-17 18:34:32 -08:00
• 761d9d9229 Correct some bugs in the create_bba Makefile. Keith Rothman 2021-02-17 18:08:52 -08:00
• 40df4f4f65 Add initial constant network support to FPGA interchange arch. Keith Rothman 2021-02-17 18:08:26 -08:00
• 0758f68020 Update archapi.md with latest signature. Keith Rothman 2021-02-23 14:07:11 -08:00
• 423a10bc31 Change CellInfo in getBelPinsForCellPin to be const. Keith Rothman 2021-02-23 13:49:01 -08:00
• bf458cbc5a Run "make clangformat" to fix new Bits library. Keith Rothman 2021-02-23 13:55:05 -08:00
• 85af066d4f Merge pull request #594 from YosysHQ/gatecat/heap-tidying gatecat 2021-02-23 21:53:00 +00:00
• 162793aa87 Refactor some common code to CellInfo methods gatecat 2021-02-23 11:42:33 +00:00
• 72b7a2e107 HeAP: Document legalise_placement_strict better gatecat 2021-02-23 10:53:35 +00:00
• 20f0ba9526 nexus: Fix getPipDelay returning negative after refactor gatecat 2021-02-23 12:21:55 +00:00
• 3b45174375 pyconsole: Avoid lockup when reading from stdin gatecat 2021-02-22 10:48:21 +00:00
• c0a7cff304 Demote the 'no clocks' warning to info and make clearer gatecat 2021-02-20 20:15:52 +00:00
• 6672f17d0a Merge pull request #592 from YosysHQ/gatecat/rework-delay gatecat 2021-02-20 10:51:57 +00:00
• e571c707b5 Update generic.md gatecat 2021-02-20 10:51:30 +00:00
• 130c5cc768 clangformat gatecat 2021-02-19 13:52:06 +00:00
• 8ab36b4a05 python: Bindings for DelayPair and DelayQuad gatecat 2021-02-19 13:41:40 +00:00
• 7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad gatecat 2021-02-19 10:39:57 +00:00
• 8376db94a7 Add DelayPair and DelayQuad structures gatecat 2021-02-17 11:38:39 +00:00
• 5dcb59b13d Merge pull request #576 from litghost/add_cell_bel_pin_mapping gatecat 2021-02-19 08:41:58 +00:00
• c21e23b3eb Fix sign mismatch. Keith Rothman 2021-02-18 14:07:17 -08:00
• e138a6c56d Do some spell checking on site_router.cc Keith Rothman 2021-02-18 13:34:06 -08:00
• 4766e889c0 Add some utility methods for site instance access. Keith Rothman 2021-02-18 13:26:52 -08:00
• 532954847a Update README's with latest instructions and features. Keith Rothman 2021-02-18 13:01:42 -08:00
• b4a97efe4d Merge pull request #588 from YosysHQ/gatecat/gowin-fixes gatecat 2021-02-18 11:05:04 +00:00
• cbff1e1371 Merge pull request #590 from cbalint13/master gatecat 2021-02-18 10:47:39 +00:00
• 456688a49d Expose ice40 arch placer-heap internal parameters. Balint Cristian 2021-02-18 00:06:23 +02:00
• 7ecfd98b2d Update tests library to include Bits unit test. Keith Rothman 2021-02-17 12:03:35 -08:00
• 8ef5411f70 Add utility targets for getting plain text outputs. Keith Rothman 2021-02-17 11:58:57 -08:00
• b3dcc9d507 Add IOSTANDARD to ports. Keith Rothman 2021-02-17 11:58:28 -08:00
• 5833c90210 Emit fixed attributes to output physical netlist. Keith Rothman 2021-02-17 11:57:49 -08:00
• 8f668f06ca Use Bits library for bit instrisics. Keith Rothman 2021-02-17 10:49:19 -08:00
• 558a753d3d Refactor "get only from iterator" to a utility. Keith Rothman 2021-02-17 10:18:24 -08:00
• 9e0ca72827 Keep all build artifacts under create_bba/build. Keith Rothman 2021-02-17 09:31:55 -08:00
• f9bd692f75 Change how package pin IO sites are selected. Keith Rothman 2021-02-16 17:25:16 -08:00
• cc687b3b72 Change makefiles to build a FPGA interchange BBA. Keith Rothman 2021-02-16 17:22:24 -08:00
• 5a7f83c705 Add examples invoking FPGA interchange nextpnr. Keith Rothman 2021-02-16 12:24:15 -08:00
• 7c1544f4d8 Continue fixes. Keith Rothman 2021-02-16 14:51:25 -08:00
• 6f1c835221 Disable traversal limit when reading logical netlist. Keith Rothman 2021-02-16 12:24:42 -08:00
• c385321248 Add initial site router. Keith Rothman 2021-02-16 09:45:43 -08:00
• a7421399f7 Working on standing up initial constraints system. Keith Rothman 2021-02-05 14:18:38 -08:00
• f6dc2dd198 Bump tests submodule to include bits tests gatecat 2021-02-17 20:02:33 +00:00
• 782747cc0c Merge pull request #589 from litghost/add_bits_library gatecat 2021-02-17 20:01:24 +00:00
• e189666a2d Add a Bits utility library. Keith Rothman 2021-02-17 10:53:03 -08:00
• a8c55728e2 gowin: Fix archcheck errors and add to CI gatecat 2021-02-17 16:03:03 +00:00
• 18113ff43d gowin: Use base bel bucket/cell type methods gatecat 2021-02-17 15:58:00 +00:00
• 09535a95ca gowin: Fix IdStrings being overwritten by wireToGlobal gatecat 2021-02-17 15:57:31 +00:00
• cb957795a3 Update docs/archapi.md gatecat 2021-02-17 11:25:53 +00:00
• d83259828e Merge pull request #587 from YosysHQ/gatecat/generic-vcc gatecat 2021-02-17 11:17:25 +00:00
• 399c24c805 clangformat gatecat 2021-02-17 10:45:23 +00:00
• 6b4bd0993f generic: Don't generate Vcc if not needed gatecat 2021-02-17 10:24:06 +00:00
• da1ecf0813 Merge pull request #586 from litghost/add_cell_bel_mapping_only gatecat 2021-02-17 10:16:45 +00:00
• a77ceec5cf Merge pull request #585 from YosysHQ/gatecat/remove-ivbfc gatecat 2021-02-17 08:50:31 +00:00
• 26a187e5eb Require --package when arch BBA contains multiple packages. Keith Rothman 2021-02-16 14:00:01 -08:00
• bb4fa7af5b [FPGA Interchange] Add Cell -> BEL Pin maps. Keith Rothman 2021-02-15 09:45:52 -08:00
• a74d1a8b32 Bump test submodule gatecat 2021-02-16 13:35:01 +00:00
• c7c13cd95f Remove isValidBelForCell gatecat 2021-02-16 11:52:16 +00:00
• 815b57b9e1 Merge pull request #583 from litghost/add_fpga_interchange_front_and_backend gatecat 2021-02-16 09:48:40 +00:00
• 1be70320b9 Pull in fix for out of source builds. Keith Rothman 2021-02-15 09:53:52 -08:00
• 2c7ee44046 Move CMake logic into fpga-interchange-schema. Keith Rothman 2021-02-15 09:07:23 -08:00
• 6b04fd1524 Small fixes from review. Keith Rothman 2021-02-15 08:27:19 -08:00
• e60dda57f3 Add libcapnp-dev for FPGA interchange compilation support. Keith Rothman 2021-02-12 16:16:54 -08:00
• 664407089b Add FPGA interchange frontend and backend. Keith Rothman 2021-02-12 16:12:16 -08:00
• 5e11e29ba2 Add interchange schema 3rdparty. Keith Rothman 2021-02-12 15:52:23 -08:00
• 9fc02041fe Merge pull request #584 from YosysHQ/gatecat/generic-belpin gatecat 2021-02-15 16:19:25 +00:00
• f0b2a91bda generic: Update docs gatecat 2021-02-15 10:37:06 +00:00
• a8a5153873 generic: Add bel pin mapping test gatecat 2021-02-15 10:22:29 +00:00
• a002ccfbc1 generic: Add APIs for controlling cell->bel pin mapping gatecat 2021-02-15 09:58:56 +00:00
• 065f46daeb Merge pull request #578 from YosysHQ/machxo2-rebase gatecat 2021-02-15 09:39:56 +00:00
• 1b6cdce925 Merge pull request #575 from YosysHQ/gatecat/belpin-2 gatecat 2021-02-15 09:38:22 +00:00
• f1ccc0e205 Merge pull request #582 from litghost/add_xdc_parser gatecat 2021-02-12 22:40:41 +00:00
• 033cc6731b Add FPGA interchange tests to CI. Keith Rothman 2021-02-12 12:51:32 -08:00
• 5312945757 Update tests to include XDC unit test. Keith Rothman 2021-02-12 08:14:58 -08:00
• 82ab3c1aad Run "make clangformat". Keith Rothman 2021-02-12 08:14:27 -08:00