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Commit Graph

  • af6e9aa6a3 gatemate: Proper KEEPER handling Miodrag Milanovic 2025-07-28 12:11:32 +02:00
  • 2c20ca917c clangformat Miodrag Milanovic 2025-07-28 12:11:07 +02:00
  • 356278d068 Gowin. Preparing to support the 5A series. (#1520) YRabbit 2025-07-23 16:45:24 +10:00
  • 2d7d1e2408 gatemate: optimizations and cleanups (#1517) Miodrag Milanović 2025-07-17 09:50:24 +03:00
  • 4831e50843 Gowin. Allow clock network routing from GP pins. (#1518) YRabbit 2025-07-13 17:24:40 +10:00
  • 840354a28a Fixes for I3C pins and RPLL (#1516) via 2025-07-10 08:47:49 -04:00
  • 24785a3219 ecp5: Fix placement of ECLKSYNCB driving PLL CLKFB (#1512) myrtle 2025-07-08 08:50:12 +02:00
  • 0ebd7afab9 clangformat Miodrag Milanovic 2025-07-07 10:15:50 +02:00
  • 84d8e1abe7 Use improved CPE model (#1503) Miodrag Milanović 2025-07-07 10:14:48 +02:00
  • 1d4b0eeac4 himbaechel: xilinx: misc CMakeLists.txt improvements (#1509) José Miguel Sánchez García 2025-07-02 14:58:09 +02:00
  • cb9f3117ba himbaechel: gatemate: replace VLA with C++ features (#1513) José Miguel Sánchez García 2025-07-01 19:39:25 +02:00
  • 27635785c8 heap: Allow customising legalisation ordering (#1507) myrtle 2025-07-01 15:32:28 +02:00
  • 77311a8cdd Clean up MsbRoutingCell lofty/gatemate-mult Lofty 2025-07-01 11:48:48 +01:00
  • 012f78c9e3 Clean up CarryGenCell config Lofty 2025-07-01 11:06:28 +01:00
  • 9fa4bb8ba2 Remove A passthrough inversion option Lofty 2025-07-01 09:57:43 +01:00
  • b2d8123b17 fixed some undefined behaviour Lofty 2025-06-28 20:02:31 +01:00
  • 2d81d34991 current progress (013 seems to work?) Lofty 2025-06-28 18:47:30 +01:00
  • bdf235721e current progress Lofty 2025-06-27 09:03:51 +01:00
  • 7122a98c13 refactor multiplier structure into uarch Lofty 2025-06-26 22:12:41 +01:00
  • 4fd43f8928 current progress (passes 2x2\!) Lofty 2025-06-26 01:02:36 +01:00
  • f4179e0330 current progress Lofty 2025-06-25 17:40:36 +01:00
  • 091bc57eab current progress Lofty 2025-06-24 01:29:40 +01:00
  • 35c6fab0d0 current progress Lofty 2025-06-23 11:28:00 +01:00
  • fcecdb9397 current progress Lofty 2025-06-21 15:26:41 +01:00
  • 1ac1b67f7f current progress Lofty 2025-06-20 16:36:00 +01:00
  • 6a1051302f current progress Lofty 2025-06-20 00:05:20 +01:00
  • e66e6f4c11 wip multiplier support Lofty 2025-06-18 04:52:26 +01:00
  • 39f020b033 Gowin. Unbreak the segment routing. (#1508) YRabbit 2025-06-30 18:14:21 +10:00
  • e642e21f9b himbaechel: output normalised wire in getWireByName (#1506) Lofty 2025-06-25 17:46:19 +01:00
  • 9ade2d1877 himbaechel: Add Python binding for get_tile_wire_range gatecat 2025-06-25 18:37:17 +02:00
  • 1cd1e4a8d9 xilinx: Fix packing of weird mux trees gatecat 2025-06-25 12:38:11 +02:00
  • 23cf1d3b92 docs: Fix outdated content in generic.md gatecat 2025-06-25 12:02:27 +02:00
  • ff695f26d5 sdc: Fix EOF handling during string parse gatecat 2025-06-25 11:58:11 +02:00
  • f74aee7047 gowin: Remove logspam during build gatecat 2025-06-25 11:49:42 +02:00
  • a77eb9e941 ice40: Fix accidental division by DIVR in 2_PAD mode gatecat 2025-06-25 11:43:22 +02:00
  • 0c86a218fd Add sources to detailed timing report (#1502) Frans Skarman 2025-06-25 11:39:25 +02:00
  • 66f051d853 Gowin. BUGFIX. Stupid == vs = (#1504) YRabbit 2025-06-24 21:24:10 +10:00
  • 311a1a711d gatemate: do not use special serdes pins for auto placement Miodrag Milanovic 2025-06-18 09:56:54 +02:00
  • f58dd2d719 clangformat Miodrag Milanovic 2025-06-18 09:12:14 +02:00
  • 7318d6a8ba gatemate: Multi die support and primitives model improvement (#1501) Miodrag Milanović 2025-06-18 08:32:57 +02:00
  • 5275c14ac0 gatemate: include DDR route-throughs in clock router (#1499) Lofty 2025-06-10 17:00:15 +01:00
  • 000faab213 Gowin. BUGFIX. Fix routing of the FF inputs. (#1498) YRabbit 2025-06-10 15:54:20 +10:00
  • fd3b4d36e7 gatemate: fix CLK inversion Miodrag Milanovic 2025-06-04 18:53:58 +02:00
  • bac5a9145f gatemate: memory clock signal handling Miodrag Milanovic 2025-05-29 13:26:35 +02:00
  • 9994fdb393 gatemate: make sure to use latest chipdb Miodrag Milanovic 2025-05-27 15:37:25 +02:00
  • 12f597dcd1 gatemate: propagate clock constraints on input ports (#1497) Miodrag Milanović 2025-05-26 11:16:45 +02:00
  • e7f52d1b6b gatemate: enable only used banks, including CFG one Miodrag Milanovic 2025-05-24 14:56:07 +02:00
  • 9cfc7ee263 gatemate: improve estimateDelay (#1494) Lofty 2025-05-22 08:15:12 +01:00
  • 06d3408ba4 Use clock router even for non-global clocks (#1493) Lofty 2025-05-21 15:17:20 +01:00
  • 226a2dfdb4 clangformat gatecat 2025-05-20 13:19:52 +02:00
  • 77a6df131c gatemate: use BUFG input in case it is routed to PLL Miodrag Milanovic 2025-05-20 09:30:27 +02:00
  • 520616248e Reserve all CPE control signals in clock router (#1492) Lofty 2025-05-19 13:55:12 +01:00
  • 2b33800d77 Reserve EN and SR wires in GateMate clock router (#1491) Lofty 2025-05-19 11:36:16 +01:00
  • b0c29aa634 gatemate: PLL priority for BUFG (#1488) Miodrag Milanović 2025-05-19 09:55:39 +02:00
  • 6c3956c3b9 gatemate: BRAM cascade mode support (#1487) Miodrag Milanović 2025-05-19 09:55:11 +02:00
  • 23a99989d1 gatemate: invert output enable for io buffer Miodrag Milanovic 2025-05-19 09:47:17 +02:00
  • 27594f904f Reserve sinks in GateMate clock router (#1486) Lofty 2025-05-15 15:53:06 +01:00
  • 0bbe031a4b set CXX standard for bba and remove boost lib (#1485) Miodrag Milanović 2025-05-14 13:42:47 +02:00
  • b127fa9c11 bba: fix #embed on Windows. William D. Jones 2025-05-14 04:08:11 +00:00
  • 7a821623f0 bba: use std::filesystem instead of boost::filesystem. Catherine 2025-05-14 02:18:39 +00:00
  • 46fbe7c6d7 GateMate clock router (#1483) Lofty 2025-05-13 15:07:47 +01:00
  • b1c147083d Gowin. Fill in delay values in HCLK. YRabbit 2025-05-13 20:00:30 +10:00
  • 764b5402e8 gatemate: Initial SERDES support (#1476) Miodrag Milanović 2025-05-06 15:56:26 +02:00
  • 182b77a2e8 ecp5: fix frequency constraint on bypassed PLL outputs (#1475) Dave Anderson 2025-05-06 06:55:38 -07:00
  • 18c7b4070a Only add subdirectory tests, if BUILD_TESTS=ON Benjamins Stürz 2025-05-02 18:34:44 +02:00
  • 900249033f gatemate: fix ccf default values and handling Miodrag Milanovic 2025-04-24 11:08:04 +02:00
  • bc25b042e9 gatemate: implemented remaining PLL features (#1474) Miodrag Milanović 2025-04-24 09:51:00 +02:00
  • c84f20934f gatemate: make build work as for other uarch Miodrag Milanovic 2025-04-22 19:28:58 +02:00
  • d6483adb4d Gatemate FPGA initial support (#1473) Miodrag Milanović 2025-04-22 16:41:01 +02:00
  • 7a3a43e150 placer1: add sanity check for try_swap_chain (#1472) Miodrag Milanović 2025-04-13 19:11:11 +02:00
  • a5cff55520 Gowin. BUGFIX Use a separate net for segment gates (#1470) YRabbit 2025-03-31 19:36:48 +10:00
  • 0c01cb9e41 Gowin. Fix non-DCS networks. (#1467) nextpnr-0.8 YRabbit 2025-03-20 18:07:37 +10:00
  • 06992bda0a rust: add getBels() binding (#1460) Lofty 2025-03-19 09:02:34 +00:00
  • c84879e4d5 Gowin. Implement the DLLDLY primitive. (#1464) YRabbit 2025-03-19 17:41:35 +10:00
  • 864c1e471d Gowin. Add a router for segments. (#1456) YRabbit 2025-03-18 21:02:49 +10:00
  • d8988e1682 Gowin. Add HCLK wires to PLL. (#1462) YRabbit 2025-03-12 18:32:38 +10:00
  • 0492c55efd ci: test that BUILD_RUST=ON builds (#1459) Lofty 2025-03-03 13:44:33 +00:00
  • f4640b9aee rust: add getBels() binding lofty/pipe-dream Lofty 2025-03-01 12:15:40 +00:00
  • 661f76d51a Add arch API function for pip inversion (#1457) Lofty 2025-02-27 11:21:15 +00:00
  • e2307a37b2 Add arch API function for pip inversion Lofty 2025-02-03 12:38:34 +00:00
  • 0c458f14f2 generic: Enable viaduct example test in CI gatecat 2025-02-25 16:01:30 +01:00
  • e751eaca47 generic: Fix archcheck crash gatecat 2025-02-25 15:58:03 +01:00
  • f3a5024de2 Gowin: Remove nextpnr-gowin (#1318) YRabbit 2025-02-14 10:08:12 +10:00
  • 1ed03ae9be gowin: Add deprecation message for nextpnr-gowin (#1455) Miodrag Milanović 2025-02-13 20:31:53 +01:00
  • 6caa6e4e85 CMake: add_custom_target does not require EXCLUDE_FROM_ALL Miodrag Milanovic 2025-02-11 10:44:00 +01:00
  • e4115e85f7 Prevent chipdb array type narrowing conversion issues Gabriel Somlo 2025-01-31 13:25:26 -05:00
  • 77187613e3 kernel: look up ports when applying clock constraints. (#1448) Catherine 2025-01-31 08:30:39 +00:00
  • b64bf018ea frontend: don't connect a const net to ports connected to x. (#1447) Catherine 2025-01-31 08:29:58 +00:00
  • 81ccada239 Gowin. Add I3C io buffer. (#1445) YRabbit 2025-01-29 23:02:21 +10:00
  • a76c5b5a0f Gowin. Typo fix. YRabbit 2025-01-29 08:18:39 +10:00
  • b95a3ca567 Gowin. Implement MIPI IO. YRabbit 2025-01-23 19:17:31 +10:00
  • cf9c74575b CMake: exclude *-bba and *-chipdb targets from make all. Catherine 2025-01-29 04:27:10 +00:00
  • 922c3a1b7f Update README to mention checking out submodules. Catherine 2025-01-28 03:07:57 +00:00
  • 8c968092a7 Update README to represent most recent changes in build system Miodrag Milanovic 2025-01-26 11:10:46 +01:00
  • ede78f3730 ecp5: Fix constant and inverted CEMUX gatecat 2025-01-27 09:00:07 +01:00
  • 0c060512c1 Fix undefined type error in 3rdparty/json11/json11.cpp Gabriel Somlo 2025-01-23 07:53:52 -05:00
  • d673d04ff3 CMake: fix windows BBA resource embedding Miodrag Milanovic 2025-01-23 12:00:13 +01:00
  • e12093201a CMake: Add include guards when IMPORT_BBA_FILES is used (#1438) Miodrag Milanović 2025-01-23 10:54:37 +01:00
  • 1623243d50 CMake: disallow in-tree builds. Catherine 2025-01-22 21:47:38 +00:00
  • 90d746f79e CMake: add support for exporting and importing .bba files. Catherine 2025-01-22 22:43:34 +00:00