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Revert "wip simlib"

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This reverts commit c7ea80661d.
This commit is contained in:
Emil J. Tywoniak
2026-01-19 12:22:49 +01:00
parent 8cf422a823
commit 57fa330572
1 changed files with 5 additions and 11 deletions
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16
techlibs/common/simlib.v
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@@ -3259,16 +3259,10 @@ endmodule
//- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
//-
module \$priority (A, Y);
parameter WIDTH = 0;
parameter P_WIDTH = 0;
parameter POLARITY = 0;
input [P_WIDTH*WIDTH-1:0] A;
output [P_WIDTH*WIDTH-1:0] Y;
parameter WIDTH = 8;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A & (~A + 1);
genvar offset;
generate
for (offset = 0; offset < P_WIDTH*WIDTH; offset = offset + P_WIDTH) begin
assign Y[offset : offset+P_WIDTH-1] = POLARITY[offset : offset+P_WIDTH-1] ^ ((A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) & (~(A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) + 1));
end
endgenerate
endmodule