github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-12 00:42:47 +00:00
Code Issues Releases Wiki Activity

aiger2: fix case where submodule cell input port has empty SigSpec

Browse Source
This commit is contained in:
Emil J. Tywoniak 2025-12-01 19:40:58 +01:00
parent cebb80250c
commit b2270ae1c8
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/aiger2/aiger.cc
View File

@ -849,7 +849,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
for (auto wire : mod->wires()) {
if (wire->port_input && !wire->port_output) {
SigSpec port = driver->getPort(wire->name);
for (int i = 0; i < wire->width; i++) {
for (int i = 0; i < std::min(wire->width, port.size()); i++) {
int ilevel = visit(cursor, port[i]);
max = std::max(max, ilevel + 1);
}