tests/verific: ensure mixed -f requires VHDL unit

tests/verific/mixed_flist.sv

@@ -1,3 +1,4 @@
 module sv_top(input logic a, output logic y);
-	assign y = a;
+	// Instantiates VHDL entity to ensure mixed -f list is required
+	vhdl_mod u_vhdl(.a(a), .y(y));
 endmodule

tests/verific/mixed_flist.ys

@@ -1,4 +1,3 @@
 verific -f -sv mixed_flist.flist
-verific -import -all
+verific -import sv_top
 select -assert-mod-count 1 sv_top
-select -assert-mod-count 2 =*