Claire Xenia Wolf
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72787f52fc
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Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
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2021-06-08 00:39:36 +02:00 |
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Marcelina Kościelnicka
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aee439360b
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Add force_downto and force_upto wire attributes.
Fixes #2058.
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2020-05-19 01:42:40 +02:00 |
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Clifford Wolf
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151db528e4
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Fix missing newline at end of file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-22 18:09:37 +02:00 |
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Miodrag Milanovic
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5f561bdcb1
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Proper arith for Anlogic and use standard pass
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2019-08-12 20:21:36 +02:00 |
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Miodrag Milanovic
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837cb0a1b9
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anlogic : Fix alu mapping
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2019-08-03 14:47:33 +02:00 |
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Miodrag Milanovic
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83bce9f59c
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Initial support for Anlogic FPGA
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2018-12-01 18:28:54 +01:00 |
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