Emil J. Tywoniak
|
b4bb200dec
|
Revert "techmap: call hierarchy on map files to determine port directions"
This reverts commit eabbf6d225.
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
0d62ac186c
|
hierarchy: tolerance for apparent recursive instances in techmap files
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
38255da162
|
techmap: call hierarchy on map files to determine port directions
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
e78a1a7b3d
|
tests: use memory -bram-register in tests/bram
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
33e5d9340f
|
memory: add -bram-register
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
23523603dc
|
memory_bram: add -register
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
e3c428b6a9
|
ffmerge: initvals signorm compatibility fixup
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
8e0a0db296
|
timinginfo: special-case $specify2 in signorm invariant
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
d1c463d685
|
opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
e4d532b886
|
connect: remove input ports on conflict
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
708bc57e79
|
opt_dff: sigma harder, FfDataSigMapped
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
274823041b
|
ff: add FfDataSigMapped
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
b58952cf2a
|
opt_dff: temporarily disable signorm due to muxtree traversal
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
451d8471b7
|
tests: fix rtlil roundtrip test
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
a65d8fbcb9
|
design: fix signorm commit connectivity to design
|
2026-05-05 21:35:14 +02:00 |
|
Emil J. Tywoniak
|
992d20071b
|
cxxrtl: ignore $input_port
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
80baffb60e
|
flatten: redo signormalization to work around fanout issue
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
b8f2dfbd5c
|
abstract: fix test signorm
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
e75523bf61
|
signorm: disable passes that use rewrite_sigspecs
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
66af891caa
|
aiger: ignore $input_port
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
99f88aa7e8
|
check: stitch info about $connect ports together for driver analysis
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
e8144f16ac
|
signorm: remove $input cells when leaving
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
d001b407c4
|
abstract: skip $input_port cells
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
e7bffe1d75
|
flatten: skip $input_port cells in template module
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
6f0ba0060e
|
signorm: skip const when fixing fanout
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
e8dd4868c1
|
signorm: disable in passes that use swap_names
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
0c9d373458
|
opt_expr: fix invert_map
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
aa52efb96e
|
satgen: support $connect
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
f481b5e4df
|
rtlil: add dump_sigmap for hacky signorm debugging
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
1da5f4dfef
|
techmap: disable signorm more
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
9d98604020
|
techmap: disable signorm
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
d37e0acc1f
|
opt_hier: disable signorm
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
3c1a0d44df
|
timinginfo: disable output wire check due to signorm
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
bcf42fcec1
|
rtlil: forbid rewrite_sigspecs in signorm
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
6defcfab50
|
opt_merge_inc: re add initvals deletion
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
4a5ff094ba
|
synth_ice40: always read abc9 model to understand port direction
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
547a715659
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
66f2d67f5e
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
0673455daa
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
42a75ffda9
|
wreduce: fixup initvals after setPort
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
b0c3f3ea00
|
ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
92f97bd5e7
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
c5839deb3d
|
rtlil: fix zero width SigSpec crash in signorm setPort unsetPort
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
57ee22883a
|
bug2920: disable
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
63355cdd03
|
rtlil_bufnorm: fix cell deletion deferral bug
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
3faa9b46de
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
d8520e20bc
|
check: don't fail on $input_port
|
2026-05-05 21:35:13 +02:00 |
|
Emil J. Tywoniak
|
3d5ee37d9a
|
mem: fix signorm cell type morph
|
2026-05-05 21:35:13 +02:00 |
|
Jannis Harder
|
7a6c111375
|
WIP half broken snapshot
|
2026-05-05 21:35:13 +02:00 |
|
Jannis Harder
|
ec796ad0b8
|
WIP remove dead code
|
2026-05-05 21:35:13 +02:00 |
|