Miodrag Milanovic
cf4d4ff23d
CI: add support for merge queue
2026-03-04 11:35:16 +01:00
Miodrag Milanović
05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix
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abc9: preserve topological-loop asserts with targeted SCC fallback
2026-03-04 11:09:38 +01:00
Miodrag Milanović
d3e297fcd4
Merge pull request #5722 from YosysHQ/release/v0.63
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Yosys Release v0.63
2026-03-04 09:31:22 +01:00
Miodrag Milanovic
228052bfb3
Next dev cycle
2026-03-04 08:45:13 +01:00
Miodrag Milanovic
70a11c6bf0
Release version 0.63
2026-03-04 07:46:57 +01:00
Miodrag Milanovic
b7d013e6bf
Fix help message for equiv passes
2026-03-04 07:46:40 +01:00
Emil J
04113eb95d
Merge pull request #5714 from likeamahoney/auto-proc-vars
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support automatic lifetime qualifier on procedural variables
2026-03-03 17:31:37 +01:00
KrystalDelusion
1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc
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Update help text for rename -witness and write_aiger -ywmap
2026-03-02 09:29:25 +13:00
likeamahoney
e9442194f2
support automatic lifetime qualifier on procedural variables
2026-02-27 20:42:52 +03:00
Miodrag Milanović
687a36af38
Merge pull request #5711 from YosysHQ/gowin_warning
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gowin: remove spurious warning
2026-02-27 14:04:27 +01:00
Miodrag Milanovic
7f1f247c56
gowin: remove spurious warning
2026-02-27 13:12:32 +01:00
Miodrag Milanović
2dd71c3ba2
Merge pull request #5709 from YosysHQ/update_abc
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Update ABC as per 2026-02-27
2026-02-27 08:32:34 +01:00
Miodrag Milanovic
b3caec1a93
Update ABC as per 2026-02-27
2026-02-27 07:55:34 +01:00
Andrew Pullin
5970be33fb
abc9: preserve topological-loop asserts with targeted SCC fallback
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A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.
Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).
To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.
Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
2026-02-26 22:30:32 -08:00
nella
2c52546e2a
Fix docs.
2026-02-25 16:42:05 +01:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
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equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Miodrag Milanović
fd1ac58767
Merge pull request #5706 from YosysHQ/remove-flake-lock
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Remove already disabled CI job
2026-02-25 11:15:33 +01:00
Miodrag Milanovic
31f7d0d92d
Remove already disabled CI job
2026-02-25 10:36:46 +01:00
Miodrag Milanović
53d8eb43ff
Merge pull request #5702 from YosysHQ/verific_build_all
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Check verific configurations
2026-02-23 09:41:59 +01:00
Miodrag Milanovic
b51110a50b
Build various Verific configurations
2026-02-23 09:01:55 +01:00
Krystine Sherwin
fd311c5501
tests/arch/gowin: Add wr_en test
2026-02-22 09:00:37 +01:00
Krystine Sherwin
2386923b8f
gowin: Fix bram ADA byte enables
2026-02-22 09:00:37 +01:00
Miodrag Milanović
fb653c4181
Merge pull request #5700 from YosysHQ/wasi_speedup
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CI: WASI - Applying YoWASP changes to script
2026-02-20 18:00:24 +01:00
Miodrag Milanovic
68e47ebcfe
CI: WASI - Applying YoWASP changes to script
2026-02-20 15:23:45 +01:00
Miodrag Milanović
0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify
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abc9: verify post-mapping equivalence by default
2026-02-20 13:41:11 +01:00
Krystine Sherwin
094481739f
memory_libmap: Add -force-params
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Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-02-20 10:57:00 +00:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks
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aigerparse: add some bounds checks
2026-02-20 11:53:49 +01:00
Emil J
74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684
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Fix segfault from shift with 0-width signed arg.
2026-02-20 11:53:05 +01:00
Emil J
53509a9b2a
Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion
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modtools: fix database sanity
2026-02-20 10:49:28 +01:00
Miodrag Milanović
679156d323
Merge pull request #5686 from YosysHQ/version_bump
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Automatic version bump
2026-02-19 09:52:22 +01:00
Emil J. Tywoniak
abc7563a35
modtools: add ModIndex unit test
2026-02-18 22:15:44 +01:00
Emil J. Tywoniak
c75d80905a
modtools: fix database sanity on wire name swap
2026-02-18 21:23:21 +01:00
Gus Smith
29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges
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kernel/celledges: cover more cell types
2026-02-18 07:50:41 -08:00
Miodrag Milanovic
5bb31485b7
Display repo and branch when applicable
2026-02-18 13:34:36 +01:00
Emil J. Tywoniak
62f19cb3a9
modtools: fix port_del db erase
2026-02-18 12:20:36 +01:00
Emil J
33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check
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blifparse: add bounds check
2026-02-18 12:18:05 +01:00
nella
01e89a8f9e
Remove cell mentions.
2026-02-18 09:29:35 +01:00
nella
2b4f481850
Cleanup docs.
2026-02-18 09:24:41 +01:00
Emil J. Tywoniak
77f64de997
satgen: move report_missing_model here from equiv.h
2026-02-16 17:01:09 +01:00
Emil J. Tywoniak
81ea922512
sat: use the same cell import warnings as equiv
2026-02-16 16:54:26 +01:00
Miodrag Milanovic
63068f9b8f
count relative to version tag, and ignore non existing
2026-02-16 16:44:33 +01:00
nella
e6e57b33e3
document abc --keep-going pdr [sc-220].
2026-02-15 09:00:04 +01:00
Miodrag Milanović
ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default
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Run unit tests on make test
2026-02-13 15:02:50 +01:00
Miodrag Milanovic
0090aa96b6
Remove version bump action
2026-02-13 14:22:33 +01:00
Miodrag Milanovic
adf8b6b0d8
Add +post to version if from tarbal
2026-02-13 14:22:10 +01:00
Miodrag Milanovic
c7d88ded94
Make version bump automatic
2026-02-13 14:21:41 +01:00
Chris Hathhorn
1e852cef16
Fix segfault from shift with 0-width signed arg.
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Fixes #5684 .
2026-02-12 22:03:42 -06:00
github-actions[bot]
e2f0c4d9a0
Bump version
2026-02-13 00:35:27 +00:00
Miodrag Milanovic
bb7aa7d208
Cleanup of yml files
2026-02-12 14:56:45 +01:00
Miodrag Milanović
e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult
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Gowin: Add DSP inference for GW1N and GW2A
2026-02-12 14:30:27 +01:00
