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Commit Graph

  • 187e91ad65 opt_clean: refactor Emil J. Tywoniak 2026-02-24 00:00:57 +01:00
  • 17688f053b opt_clean: refactor Emil J. Tywoniak 2026-02-23 20:08:58 +01:00
  • 090a0fd575 opt_clean: refactor Emil J. Tywoniak 2026-02-23 19:43:46 +01:00
  • 7d7978a929 opt_clean: more comments Emil J. Tywoniak 2026-02-23 19:15:59 +01:00
  • 9710be2f84 opt_clean: more comments Emil J. Tywoniak 2026-02-17 11:22:27 +01:00
  • a5f554f00a opt_clean: add extra comments Emil J. Tywoniak 2026-02-16 10:57:45 +01:00
  • 341cd563bd Add symfpu -classify Krystine Sherwin 2026-02-24 15:19:50 +13:00
  • 88b348f9ff docs: Add information on CI docs-preview-ci Krystine Sherwin 2026-02-24 12:56:56 +13:00
  • 366f98ae25 ADd clarification gus/sim-with-vcd-tuneup Gus Smith 2026-02-23 11:51:54 -08:00
  • c0f1654028 Expand test into three tests for three cases Gus Smith 2026-02-23 10:27:36 -08:00
  • 90638650d3 Fix typo. nella/fast-celltypes nella 2026-02-23 14:44:29 +01:00
  • f7243ce122 Fix stdcells mem. nella 2026-02-23 14:29:16 +01:00
  • 3611fca18b Fix pop order. nella 2026-02-23 13:46:34 +01:00
  • 4b657938dc Cell evaluable fix. nella 2026-02-23 13:15:14 +01:00
  • 80cfa5141b Add support for out of dir builds. nella 2026-02-23 10:39:52 +01:00
  • 4df3267610 Adjusted compilation order. nella 2026-02-23 10:13:05 +01:00
  • 53d8eb43ff Merge pull request #5702 from YosysHQ/verific_build_all Miodrag Milanović 2026-02-23 09:41:59 +01:00
  • b51110a50b Build various Verific configurations Miodrag Milanovic 2026-02-23 09:01:55 +01:00
  • 826d1d91cd tests/symfpu: Extra muladd tests Krystine Sherwin 2026-02-23 16:58:34 +13:00
  • fd311c5501 tests/arch/gowin: Add wr_en test Krystine Sherwin 2026-02-20 12:42:55 +13:00
  • 2386923b8f gowin: Fix bram ADA byte enables Krystine Sherwin 2026-02-20 12:34:41 +13:00
  • 97e1a3b7c7 Add celltype unit tests. nella 2026-02-21 12:23:15 +01:00
  • 0b5d64f068 tests/symfpu: Testing sqrt Krystine Sherwin 2026-02-21 17:11:11 +13:00
  • c2731b43a4 symfpu: Add altsqrt Krystine Sherwin 2026-02-21 17:08:35 +13:00
  • b454582f54 Detect undriven and error/warn Gus Smith 2026-02-20 11:00:59 -08:00
  • cdc728b6f0 Suggest use of YW when possible Gus Smith 2026-02-20 09:33:51 -08:00
  • fb653c4181 Merge pull request #5700 from YosysHQ/wasi_speedup Miodrag Milanović 2026-02-20 18:00:24 +01:00
  • 68e47ebcfe CI: WASI - Applying YoWASP changes to script Miodrag Milanovic 2026-02-20 15:23:45 +01:00
  • cbe847e8f5 Increase max gen. nella 2026-02-20 13:51:25 +01:00
  • 0ed7c5ad53 Merge pull request #5620 from YosysHQ/lofty/abc9-verify Miodrag Milanović 2026-02-20 13:41:11 +01:00
  • bc275e623a Add missing categories. nella 2026-02-20 13:17:22 +01:00
  • a4d998d6cd Implemented celltype lookups. nella 2026-02-20 12:44:30 +01:00
  • fd2d87719c analogdevices: update T40LP timings Lofty 2026-01-05 14:45:54 +00:00
  • d30a7978ca analogdevices: update T16FFC timings Lofty 2026-01-05 10:27:46 +00:00
  • b71f5bb908 synth_analogdevices: update timing model and tests Lofty 2025-11-10 13:19:12 +00:00
  • f07f4d53d1 analogdevices: double LUT RAM cost Lofty 2025-10-21 18:04:01 +01:00
  • 9d2070cb7b analogdevices: ignore $assert cells Lofty 2025-10-20 18:23:25 +01:00
  • bdef403d92 analogdevices: Extra tests Krystine Sherwin 2025-10-18 17:38:01 +13:00
  • 935eaa72b9 analogdevices: Fixing up bram Krystine Sherwin 2025-10-18 17:31:54 +13:00
  • e753f6c6ce analogdevices: Add BRAM options Krystine Sherwin 2025-10-18 12:59:55 +13:00
  • ccbb80dc36 analogdevices: LUT RAM only on positive edge Lofty 2025-10-18 12:11:18 +01:00
  • 9fdfaf3c79 analogdevices: DSP tweaks Lofty 2025-10-18 12:10:50 +01:00
  • fa1c859d07 analogdevices: DSP inference Lofty 2025-10-16 23:33:59 +01:00
  • 9d5ddcb356 analogdevices: remove cells_xtra Lofty 2025-10-15 04:55:12 +01:00
  • eee01fcf7d analogdevices: timings for t40lp Lofty 2025-10-12 12:55:09 +01:00
  • 13b4b8c6b9 analogdevices: use single tech param Lofty 2025-10-12 11:31:23 +01:00
  • f234e553dd analogdevices: expreso does not care about clock buffers Lofty 2025-10-12 11:22:46 +01:00
  • 1f5e6d5c61 analogdevices: prepare for t40lp timings Lofty 2025-10-12 11:17:50 +01:00
  • 4ba732d1dd analogdevices: Adding RBRAM2 and -tech Krystine Sherwin 2025-10-11 12:06:35 +13:00
  • 4ff97770f5 analogdevices: (some) Native BRAM Krystine Sherwin 2025-10-08 17:32:46 +13:00
  • e7eae91abf analogdevices: Update lutram.ys test Krystine Sherwin 2025-10-08 14:13:57 +13:00
  • 49e463bfcc analogdevices: Native LUTRAM primitives Krystine Sherwin 2025-10-08 14:08:41 +13:00
  • 5cdda40f14 analogdevices: LUTRAM config Lofty 2025-10-09 04:38:49 +01:00
  • 3780857f59 analogdevices: update timing model Lofty 2025-10-01 20:13:29 +01:00
  • e6849b081f I thought I removed this... Lofty 2025-10-01 12:47:21 +01:00
  • d45282042e analogdevices: user retargeting Lofty 2025-09-30 10:02:44 +01:00
  • 0ee490041e analogdevices: more housekeeping Lofty 2025-09-30 10:02:19 +01:00
  • 1690678911 analogdevices: remove some extra cells! Lofty 2025-09-25 15:09:16 +01:00
  • bdf767e65e test suite Lofty 2025-09-24 20:56:27 +01:00
  • 9055d99215 synth_analogdevices: remove scopeinfo cells Lofty 2025-09-24 16:29:38 +01:00
  • 80f7d0ee6f Create synth_analogdevices Lofty 2025-09-23 11:08:17 +01:00
  • 094481739f memory_libmap: Add -force-params Krystine Sherwin 2025-10-18 12:58:25 +13:00
  • 13795203a1 Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks Emil J 2026-02-20 11:53:49 +01:00
  • 74f7b0cf92 Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 Emil J 2026-02-20 11:53:05 +01:00
  • 48a475e015 Merge pull request #5456 from YosysHQ/emil/proc_mux-better-src emil/src-locations-story Emil J 2026-02-20 11:24:05 +01:00
  • 53509a9b2a Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion Emil J 2026-02-20 10:49:28 +01:00
  • 48cb1d10b1 symfpu: Add alt2div Krystine Sherwin 2026-02-20 15:49:38 +13:00
  • f39427f40a symfpu: Add altdiv Krystine Sherwin 2026-02-20 14:01:49 +13:00
  • 1629c2bd3d tests/symfpu: Add cover checks Krystine Sherwin 2026-02-20 10:09:12 +13:00
  • 679156d323 Merge pull request #5686 from YosysHQ/version_bump Miodrag Milanović 2026-02-19 09:52:22 +01:00
  • abc7563a35 modtools: add ModIndex unit test Emil J. Tywoniak 2026-02-18 22:15:44 +01:00
  • b1a997aa9a modtools, wreduce: check_db sanity check emil/wreduce-db-mystery Emil J. Tywoniak 2026-02-17 19:52:30 +01:00
  • c75d80905a modtools: fix database sanity on wire name swap Emil J. Tywoniak 2026-02-18 21:20:13 +01:00
  • 29a270c4b6 Merge pull request #5675 from rowanG077/add-missing-celledges Gus Smith 2026-02-18 07:50:41 -08:00
  • 5bb31485b7 Display repo and branch when applicable Miodrag Milanovic 2026-02-18 13:34:36 +01:00
  • 62f19cb3a9 modtools: fix port_del db erase Emil J. Tywoniak 2026-02-18 12:20:36 +01:00
  • 33a2de9635 Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check Emil J 2026-02-18 12:18:05 +01:00
  • 01e89a8f9e Remove cell mentions. nella 2026-02-18 09:29:35 +01:00
  • 2b4f481850 Cleanup docs. nella 2026-02-18 09:24:41 +01:00
  • 7f1b4dcf99 Add 'init' attributes to RTLIL fuzzing Robert O'Callahan 2026-02-05 18:20:31 +00:00
  • 6b9f152a1a Add unit tests for ConcurrentWorkQueue Robert O'Callahan 2026-02-03 00:02:00 +00:00
  • e2f939a93f Add some tests for ShardedHashSet Robert O'Callahan 2026-02-02 23:36:41 +00:00
  • 71c5b6269f Add unit tests for ConcurrentQueue and ThreadPool Robert O'Callahan 2026-02-02 23:16:20 +00:00
  • 722a4fc335 Add unit-tests for ParallelDispatchThread and friends Robert O'Callahan 2026-02-02 23:04:34 +00:00
  • f2340639e8 Pass the module Subpool to rmunused_module_signals and parallelize that function Robert O'Callahan 2026-01-28 22:59:44 +00:00
  • e2345d197b Add test that connects a wire with init to a constant Robert O'Callahan 2026-02-05 19:23:10 +00:00
  • cbb5d8fa12 Pass the module Subpool to rmunused_module_cells and parallelize that function Robert O'Callahan 2026-01-28 22:59:04 +00:00
  • e213437095 Pass the module Subpool to rmunused_module_init and parallelize that function Robert O'Callahan 2026-01-28 22:46:10 +00:00
  • 2659f32616 Pass the toplevel thread pool to rmunused_module, create a Subpool, and parallelize remove_temporary_cells Robert O'Callahan 2026-01-28 22:06:19 +00:00
  • 0a64402dde Create a toplevel ParallelDispatchThreadPool and parallelize keep_cache_t::scan_module() with it Robert O'Callahan 2026-01-28 21:58:37 +00:00
  • 20189460bd Introduce RmStats struct to encapsulate removal statistics Robert O'Callahan 2026-01-28 19:27:09 +00:00
  • b153fc2d16 Make keep_cache_t process all modules up-front instead of on-demand Robert O'Callahan 2026-01-28 19:14:09 +00:00
  • 6bf9fd3e1f Parallelize Design::check() Robert O'Callahan 2026-01-29 22:45:10 +00:00
  • 704d110560 Parallelize collect_garbage() Robert O'Callahan 2026-01-29 22:16:46 +00:00
  • 937c7ceb4d Add FfInitVals::set_parallel() method Robert O'Callahan 2026-01-28 18:20:13 +00:00
  • 8ced93b176 Add MonotonicFlag Robert O'Callahan 2026-01-28 19:01:43 +00:00
  • 1a461f95c5 Add ConcurrentWorkQueue Robert O'Callahan 2026-01-28 19:00:47 +00:00
  • 6182db64d2 Add ShardedHashSet Robert O'Callahan 2026-01-28 18:59:35 +00:00
  • 8a30051fc2 Add ShardedVector Robert O'Callahan 2026-01-28 18:58:09 +00:00
  • d711cf6185 Add ParallelDispatchThreadPool Robert O'Callahan 2026-01-28 18:52:17 +00:00