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Mono Color

• 629bf3dffd Merge pull request #5630 from apullin/array-assignment gh-readonly-queue/main/pr-5630-4caffa7ebdfc31fe291683967745022d7f3bee0d Emil J 2026-03-05 11:10:12 +00:00
• 23eb38fe3f celltypes: include newcelltypes to allow legacy code access to migrated yosys_celltypes emil/double-expose-yosys_celltypes Emil J. Tywoniak 2026-03-05 11:59:20 +01:00
• da83c93673 analogdevices: fix SHIFTX name lofty/analogdevices Lofty 2026-03-04 12:25:11 +00:00
• f3efa51b3e analogdevices: fix SHREG name Lofty 2026-03-04 12:24:53 +00:00
• e2e8245be9 analogdevices: fix MUXF78 name Lofty 2026-03-04 12:24:13 +00:00
• c747466a7a analogdevices: update missed T40LP timings Lofty 2026-03-04 12:16:35 +00:00
• 91740645a9 analogdevices: update T40LP timings Lofty 2026-01-05 14:45:54 +00:00
• 709746b184 analogdevices: update T16FFC timings Lofty 2026-01-05 10:27:46 +00:00
• cd60dd4912 synth_analogdevices: update timing model and tests Lofty 2025-11-10 13:19:12 +00:00
• 241db706e1 analogdevices: double LUT RAM cost Lofty 2025-10-21 18:04:01 +01:00
• 3592d42d3b analogdevices: ignore $assert cells Lofty 2025-10-20 18:23:25 +01:00
• 5d3ed5a418 analogdevices: Extra tests Krystine Sherwin 2025-10-18 17:38:01 +13:00
• f06018306d analogdevices: Fixing up bram Krystine Sherwin 2025-10-18 17:31:54 +13:00
• 95ef0cd788 analogdevices: Add BRAM options Krystine Sherwin 2025-10-18 12:59:55 +13:00
• 8a09cc5463 analogdevices: LUT RAM only on positive edge Lofty 2025-10-18 12:11:18 +01:00
• dea8c275ff analogdevices: DSP tweaks Lofty 2025-10-18 12:10:50 +01:00
• 39cb61615f analogdevices: DSP inference Lofty 2025-10-16 23:33:59 +01:00
• 891b89f60d analogdevices: remove cells_xtra Lofty 2025-10-15 04:55:12 +01:00
• 4954fc980f analogdevices: timings for t40lp Lofty 2025-10-12 12:55:09 +01:00
• 2c3876671b analogdevices: use single tech param Lofty 2025-10-12 11:31:23 +01:00
• 0a2b6a4f21 analogdevices: expreso does not care about clock buffers Lofty 2025-10-12 11:22:46 +01:00
• 6ee0bfa913 analogdevices: prepare for t40lp timings Lofty 2025-10-12 11:17:50 +01:00
• 9dcffc3dbf analogdevices: Adding RBRAM2 and -tech Krystine Sherwin 2025-10-11 12:06:35 +13:00
• 99e26d80b0 analogdevices: (some) Native BRAM Krystine Sherwin 2025-10-08 17:32:46 +13:00
• 9be3cfb3f9 analogdevices: Update lutram.ys test Krystine Sherwin 2025-10-08 14:13:57 +13:00
• 376f746bc9 analogdevices: Native LUTRAM primitives Krystine Sherwin 2025-10-08 14:08:41 +13:00
• 30a03886a5 analogdevices: LUTRAM config Lofty 2025-10-09 04:38:49 +01:00
• ae5325fe53 analogdevices: update timing model Lofty 2025-10-01 20:13:29 +01:00
• c4bec4e8b8 I thought I removed this... Lofty 2025-10-01 12:47:21 +01:00
• 85eb07d14d analogdevices: user retargeting Lofty 2025-09-30 10:02:44 +01:00
• c9f6d7b2d4 analogdevices: more housekeeping Lofty 2025-09-30 10:02:19 +01:00
• f659cbd159 analogdevices: remove some extra cells! Lofty 2025-09-25 15:09:16 +01:00
• 6f205b41f5 test suite Lofty 2025-09-24 20:56:27 +01:00
• 4f2f064262 synth_analogdevices: remove scopeinfo cells Lofty 2025-09-24 16:29:38 +01:00
• d5ea7f7016 Create synth_analogdevices Lofty 2025-09-23 11:08:17 +01:00
• 4caffa7ebd Merge pull request #5725 from yrabbit/disable-wm-2 main Lofty 2026-03-05 05:36:28 +00:00
• 6ac8c8cb05 ast: Add support for array-to-array assignment Andrew Pullin 2026-01-23 06:46:21 -08:00
• 26dc01102e GOWIN. Disable read-before-write mode. YRabbit 2026-03-05 09:17:37 +10:00
• 39343f5f33 docs: document S&R undefined for $dffsr and $dffsre emil/dffsr-sr-priority-undef Emil J. Tywoniak 2026-03-04 19:39:41 +01:00
• 0d7a875675 Merge pull request #5512 from YosysHQ/emil/turbo-celltypes Emil J 2026-03-04 14:47:57 +00:00
• 6485a13809 newcelltypes: mark header unstable Emil J. Tywoniak 2026-03-04 15:17:26 +01:00
• 3bc26ff4d0 Merge pull request #5723 from YosysHQ/micko/merge_queue Miodrag Milanović 2026-03-04 13:18:09 +01:00
• 16b1a914f1 Aiger use defines for known ops. nella 2026-03-02 12:24:41 +01:00
• 04822c6660 Readd builtin_ff_cell_types for plugin parity. nella 2026-03-02 12:11:25 +01:00
• b8ee0803ab Remove todo. nella 2026-02-28 18:39:16 +01:00
• 66bd4716cf rtlil use newcelltypes. nella 2026-02-28 18:30:37 +01:00
• cae54a4c7b Aiger use newcelltypes. nella 2026-02-28 18:09:34 +01:00
• 6d4736269b newcelltypes: extend testing Emil J. Tywoniak 2025-11-27 03:32:41 +01:00
• 0284595e9c celltypes: fix absurd eval declarations Emil J. Tywoniak 2025-11-27 03:32:31 +01:00
• 793a3513c6 newcelltypes: use unordered_map Emil J. Tywoniak 2025-11-27 02:53:29 +01:00
• ae10e9e955 pyosys: disable test Emil J. Tywoniak 2025-11-27 01:58:06 +01:00
• 661fcb24cb newcelltypes: fix MSVC build Emil J. Tywoniak 2025-11-26 13:17:24 +01:00
• f594014bef newcelltypes: proper bounds for unit test Emil J. Tywoniak 2025-11-26 13:15:02 +01:00
• 12412d1fa5 register: use newcelltypes Emil J. Tywoniak 2025-11-26 00:53:01 +01:00
• ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users Emil J. Tywoniak 2025-11-26 00:50:41 +01:00
• 5216d32d1b yosys: use newcelltypes for yosys_celltypes Emil J. Tywoniak 2025-11-26 00:47:30 +01:00
• 7a5c303ccd backends: use newcelltypes Emil J. Tywoniak 2025-11-26 00:32:11 +01:00
• c3ed884bc4 drivertools: use newcelltypes Emil J. Tywoniak 2025-11-26 00:16:07 +01:00
• 665b6eeb4a aiger2: add TODO Emil J. Tywoniak 2025-11-26 00:14:12 +01:00
• 4ab22cbb97 abc: use newcelltypes Emil J. Tywoniak 2025-11-26 00:03:53 +01:00
• d91e1c8607 newcelltypes: test against builtin_ff_cell_types Emil J. Tywoniak 2025-11-26 00:03:43 +01:00
• 31b86ebc2e newcelltypes: comment Emil J. Tywoniak 2025-11-25 23:52:30 +01:00
• 8e17fb0266 consteval: use newcelltypes Emil J. Tywoniak 2025-11-25 23:47:56 +01:00
• a0f87dc2d1 modtools: use newcelltypes Emil J. Tywoniak 2025-11-25 23:36:40 +01:00
• a9463d1aee newcelltypes: fix non-cells Emil J. Tywoniak 2025-11-25 22:41:12 +01:00
• e3f9911e33 newcelltypes: refactor Emil J. Tywoniak 2025-11-25 20:21:33 +01:00
• 07ec8708e4 share: use newcelltypes Emil J. Tywoniak 2025-11-25 20:17:27 +01:00
• 3212dfaf1f newcelltypes: fix unit test Emil J. Tywoniak 2025-11-25 20:08:41 +01:00
• 2d7d6ca10b newcelltypes: unit test Emil J. Tywoniak 2025-11-25 20:08:26 +01:00
• 7e9e88c2ec newcelltypes: bounds check Emil J. Tywoniak 2025-11-25 19:06:46 +01:00
• 9e59f05c25 newcelltypes: wrap design celltypes support Emil J. Tywoniak 2025-11-25 18:41:26 +01:00
• 35ccaa60d7 newcelltypes: TurboCellTypes -> StaticCellTypes Emil J. Tywoniak 2025-11-25 16:11:05 +01:00
• 6adc08b0e5 opt_expr: use newcelltypes Emil J. Tywoniak 2025-11-25 15:15:16 +01:00
• 3671d577a0 opt_clean: use newcelltypes Emil J. Tywoniak 2025-11-25 15:07:17 +01:00
• a61455645d newcelltypes: init Emil J. Tywoniak 2025-11-25 15:06:36 +01:00
• cf4d4ff23d CI: add support for merge queue Miodrag Milanovic 2026-03-04 11:35:16 +01:00
• 05d1d56b9d Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix Miodrag Milanović 2026-03-04 11:09:38 +01:00
• d3e297fcd4 Merge pull request #5722 from YosysHQ/release/v0.63 Miodrag Milanović 2026-03-04 09:31:22 +01:00
• 228052bfb3 Next dev cycle Miodrag Milanovic 2026-03-04 08:45:13 +01:00
• 70a11c6bf0 Release version 0.63 v0.63 Miodrag Milanovic 2026-03-04 07:46:57 +01:00
• b7d013e6bf Fix help message for equiv passes Miodrag Milanovic 2026-03-04 07:46:40 +01:00
• 126492742b read_liberty: fix for msvc Emil J. Tywoniak 2026-03-03 17:34:58 +01:00
• 04113eb95d Merge pull request #5714 from likeamahoney/auto-proc-vars Emil J 2026-03-03 17:31:37 +01:00
• 9a8d8886e1 fixup! dfflibmap: refactor emil/dffsr-sr-correct-dfflibmap Emil J. Tywoniak 2026-03-03 17:24:34 +01:00
• dc70d58b76 dfflibmap: refactor Emil J. Tywoniak 2026-03-03 14:26:08 +01:00
• d4239cfc60 read_liberty: fix for msvc Emil J. Tywoniak 2026-03-03 10:34:02 +01:00
• 5858ad2648 dfflibmap: fix formal $dffsr tests with sat, prove "no s&r" assumption only needed when appropriate Emil J. Tywoniak 2026-03-03 01:19:22 +01:00
• 5b4603c54f dfflibmap: fix formal $dffsr tests with sat, prove "no s&r" assumption only needed when appropriate Emil J. Tywoniak 2026-03-03 01:19:22 +01:00
• 22916aaab1 read_liberty: model clear_preset_variable correctly Emil J. Tywoniak 2026-03-02 22:39:21 +01:00
• 024408004a dfflibmap: allow formal dffsr mapping tests with clk2fflogic Emil J. Tywoniak 2026-02-27 20:05:53 +01:00
• 6f74c54c02 async2sync: $dffsr has undef output on S&R Emil J. Tywoniak 2026-01-29 11:53:24 +01:00
• 857bc02710 liberty: warn if dffsr has clear&preset well defined Emil J. Tywoniak 2026-01-28 18:40:20 +01:00
• 2dddc53ccf dfflibmap: test dffsr and dffsre from proc with equiv Emil J. Tywoniak 2026-01-28 18:26:26 +01:00
• c13a623dbc dfflibmap: test dffsr with either priority liberty file Emil J. Tywoniak 2026-01-28 18:11:55 +01:00
• ffb76a3486 dfflibmap: test dffsr mapping without assume Emil J. Tywoniak 2026-01-28 18:09:16 +01:00
• a53104379d clk2fflogic: $dffsr has undef output on S&R Emil J. Tywoniak 2026-01-20 13:00:12 +01:00
• 1d3f9b7905 Merge pull request #5687 from YosysHQ/nella/pdr-doc KrystalDelusion 2026-03-02 09:29:25 +13:00
• 6e45ec6795 symfpu: Convert with flags krys/symfpu Krystine Sherwin 2026-02-28 17:24:31 +13:00
• 1ca73b0cea symfpu: Add symfpu_convert Krystine Sherwin 2026-02-28 10:39:49 +13:00
• e9442194f2 support automatic lifetime qualifier on procedural variables likeamahoney 2026-02-27 20:42:40 +03:00