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Commit Graph

  • 1a52a714b4 Merge pull request #5280 from YosysHQ/krys/ci_changes Miodrag Milanović 2025-08-18 10:17:12 +02:00
  • d73cd78001 Bump version github-actions[bot] 2025-08-18 00:27:23 +00:00
  • 3f2c4f6f83 Remove redundant construction of assign_map. Robert O'Callahan 2025-08-17 23:34:11 +00:00
  • 6d55ca204b Merge pull request #5281 from suisseWalter/add_parameterised_cells_stat KrystalDelusion 2025-08-18 09:21:45 +12:00
  • 9278bed853 removed copyright notice on lib file. Should be covered by the yosys license not anything else. clemens 2025-08-14 16:33:59 +02:00
  • 4e45b5e1bb permit trailing comma clemens 2025-08-14 11:13:40 +02:00
  • 73d1177665 testcases one testcase for single parameter cells. one testcase for double parameter cells. clemens 2025-08-14 09:57:44 +02:00
  • 8b1f77ebd2 cleanup. printf to errors or warnings clemens 2025-08-13 15:16:15 +02:00
  • 50fe9dd7f2 clean parsing code clemens 2025-08-12 09:37:55 +02:00
  • 5fc0e77c3d add functionality to be able to use parameterised cells. clemens 2025-08-12 08:56:05 +02:00
  • d8fb4da437 updated testcase clemens 2025-08-16 09:32:08 +02:00
  • a6e0ab5ea5 Update (sequential) area to be only local without -hierarchy clemens 2025-08-16 09:09:57 +02:00
  • f5b219f59e Update passes/cmds/stat.cc suisseWalter 2025-08-16 08:36:06 +02:00
  • d10fdc0ec5 Bump version github-actions[bot] 2025-08-16 00:24:02 +00:00
  • 7799c6e6ac Merge pull request #5291 from YosysHQ/krys/rename_escape KrystalDelusion 2025-08-16 12:19:49 +12:00
  • e906ea3f1b Add tests for dynamic precision and with with an int parameter Robert O'Callahan 2025-08-15 23:58:58 +00:00
  • 4a324e1da8 Merge pull request #5292 from rocallahan/wasm-varargs KrystalDelusion 2025-08-16 10:29:36 +12:00
  • 70600bb596 Merge pull request #5239 from rocallahan/abc-incremental Emil J 2025-08-15 20:17:32 +02:00
  • 39027dd374 fixup! check: add bufnorm invariant check emil/bufnorm-jix-refactor Emil J. Tywoniak 2025-08-15 11:16:57 +02:00
  • 8384460b4b check: add bufnorm invariant check Emil J. Tywoniak 2025-08-15 11:14:02 +02:00
  • be956f3416 fixup! refactor Emil J. Tywoniak 2025-08-15 11:13:45 +02:00
  • 436d698525 refactor Emil J. Tywoniak 2025-08-14 23:34:03 +02:00
  • 6d62a1fff7 Fix vararg alignment Robert O'Callahan 2025-08-15 05:43:53 +00:00
  • bf625951d7 Bump version github-actions[bot] 2025-08-15 00:26:03 +00:00
  • dd88423334 Make OptMuxtree int-indexed vectors into hashtables Robert O'Callahan 2025-08-13 21:22:45 +00:00
  • ec18d1aede rename.cc: Fixup ports after -unescape Krystine Sherwin 2025-08-15 10:48:32 +12:00
  • 62c441107d Build FfInitVals for the entire module once and use it for every ABC run. Robert O'Callahan 2025-08-05 22:21:30 +00:00
  • 2654bd5355 Compute is_port in AbcPass without iterating through all cells and wires in the module every time we run ABC. Robert O'Callahan 2025-07-27 23:44:41 +00:00
  • ac8259b02e Preserve assign_map across ABC invocations. Robert O'Callahan 2025-07-17 06:16:54 +00:00
  • 4de3ee093e Mark kept FF output wires as ports directly instead of via the 'keep' attribute Robert O'Callahan 2025-07-26 09:34:37 +00:00
  • 741e088e3a bufnorm: fix priority when connecting new driver to existing inout wire Jannis Harder 2025-08-14 21:26:05 +02:00
  • 1770a7a11b bufnorm: don't require normalizing $connect's A port Jannis Harder 2025-08-14 17:38:24 +02:00
  • 4b57de01ea fixup! HACK to unconditionally debug bufnorm drivers in show output Jannis Harder 2025-08-14 17:18:51 +02:00
  • 195d3ef940 Merge pull request #5100 from jix/rename_move_to_cell Emil J 2025-08-14 16:45:33 +02:00
  • efb08dcdc2 HACK to unconditionally debug bufnorm drivers in show output Jannis Harder 2025-08-14 16:19:42 +02:00
  • 4de384d776 WIP prototype bidir aware kernel bufnorm code Jannis Harder 2025-08-14 16:16:19 +02:00
  • 727dabba95 fixup! WIP add placeholder $connect cell Jannis Harder 2025-08-14 16:15:28 +02:00
  • b394629e3f kernel: Add RTLIL::PortDir for a combined input and output flag Jannis Harder 2025-08-14 16:13:43 +02:00
  • 9f62dd6e0e WIP add placeholder $connect cell Jannis Harder 2025-08-14 16:12:53 +02:00
  • 1dbf2df983 Add libfl-dev for CodeQL CI job Miodrag Milanovic 2025-08-14 09:15:43 +02:00
  • a265b23ac0 Bump version github-actions[bot] 2025-08-14 00:25:16 +00:00
  • e486994f60 opt_dff: add test Anhijkt 2025-08-14 00:13:23 +03:00
  • 71307b4a51 add Testcases Fix existing testcases Fix edgecase where modules where counted as cells. clemens 2025-08-13 14:46:01 +02:00
  • dbb977aa8b Merge pull request #5288 from YosysHQ/emil/demote-verilog-parser-errors-again Emil J 2025-08-13 12:52:50 +02:00
  • 856fc43a87 rename: format vector slices consistently with HDL upto/downto direction Emil J. Tywoniak 2025-06-04 11:18:38 +02:00
  • 77089a8d03 rename: add -move-to-cell option in -wire mode Jannis Harder 2025-05-07 12:22:37 +02:00
  • 1603828b30 verilog_parser: fix locations of warnings for restrict keyword Emil J. Tywoniak 2025-08-13 10:56:48 +02:00
  • 910ff3ff36 verilog: demote some parser errors to warnings again Emil J. Tywoniak 2025-08-13 10:54:47 +02:00
  • 383d11c2ac fix design overview in json. clemens 2025-08-13 10:09:02 +02:00
  • 1eb8844e38 fix labeling in report fix design hierarchy containing wrong values. remove left over debug print. clemens 2025-08-13 08:36:26 +02:00
  • ccb23ffc1a Fix indentation Robert O'Callahan 2025-07-15 04:19:09 +00:00
  • 885bb744e3 Make module a parameter of the function so we can change its constness in context Robert O'Callahan 2025-07-15 04:17:48 +00:00
  • 53c72c0d39 Move code in abc_module() that modifies the design into a new function extract() Robert O'Callahan 2025-07-15 03:54:41 +00:00
  • ceedcecfae Move the input parameters to abc_module that are identical across modules to an AbcConfig struct. Robert O'Callahan 2025-07-15 03:38:54 +00:00
  • 4ba42c4752 Move ABC pass state to a struct instead of storing it in global variables. Robert O'Callahan 2025-07-15 01:26:24 +00:00
  • 8634d83320 Bump version github-actions[bot] 2025-08-13 00:25:15 +00:00
  • b3ca5ee0f1 opt_dff: fix timeout issue Anhijkt 2025-08-13 01:48:59 +03:00
  • 1f876f3a22 abstract: Add -initstates option Jannis Harder 2025-08-12 15:26:36 +02:00
  • 256aa3e389 check: Limit detailed cell edge checking for $pmux and $bmux Jannis Harder 2025-08-12 14:38:20 +02:00
  • 9d047f9a30 Merge pull request #5283 from YosysHQ/emil/fix-simplify-initstate Emil J 2025-08-12 14:28:31 +02:00
  • 6042ae0e8a simplify: add smoke test for system function calls Emil J. Tywoniak 2025-08-12 12:59:31 +02:00
  • 8582136a45 simplify: fix $initstate segfault Emil J. Tywoniak 2025-08-12 12:39:36 +02:00
  • fb024c4d55 Merge pull request #5135 from YosysHQ/emil/ast-ownership Emil J 2025-08-12 10:58:12 +02:00
  • 2a97987cf2 formatting and remove debug statements clemens 2025-08-12 09:16:05 +02:00
  • a0dde68487 Improve STAT clemens 2025-04-15 09:39:49 +02:00
  • 407d425114 Merge pull request #5024 from YosysHQ/krys/update_evals KrystalDelusion 2025-08-12 14:27:03 +12:00
  • 1e6e25c81f ci: Use correct build artifact Krystine Sherwin 2025-08-12 12:43:14 +12:00
  • 0f8c040371 ci: Move SAN into a separate workflow Krystine Sherwin 2025-08-12 12:21:50 +12:00
  • 73403ad830 ci: Adjust workflow triggers for tests Krystine Sherwin 2025-08-12 12:05:23 +12:00
  • c630f995d5 ci: Reduce test_cell count and use a seed Krystine Sherwin 2025-08-12 11:17:00 +12:00
  • ba01f7c64f ci: Run test_cell Krystine Sherwin 2025-08-12 10:57:59 +12:00
  • 1afe8d9f4d celltypes: Comment pointing to ConstEval Krystine Sherwin 2025-08-12 10:57:59 +12:00
  • 20c2d2a6f3 test_cell: Add comment on $pmux Krystine Sherwin 2025-08-12 10:57:59 +12:00
  • c589714433 test_cell: Update to $macc_v2 Martin Povišer 2025-08-12 10:57:59 +12:00
  • db4ffaffd2 consteval: Fix $bwmux handling Krystine Sherwin 2025-08-12 10:57:58 +12:00
  • 014eadd8b9 test_cell: Fix $bweqx Krystine Sherwin 2025-08-12 10:57:58 +12:00
  • 22aa9fba3b test_cell: Support more cell types Krystine Sherwin 2025-08-12 10:57:58 +12:00
  • 481ecb51a7 test_cell: Disable $macc testing Krystine Sherwin 2025-08-12 10:57:58 +12:00
  • 2d90e80b52 Merge pull request #5270 from zhanghongce/main Jannis Harder 2025-08-11 15:35:25 +02:00
  • 642e041f77 const2ast: fix for consistency with previous diagnostics behavior Emil J. Tywoniak 2025-08-08 16:32:51 +02:00
  • 99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location Emil J. Tywoniak 2025-08-08 16:22:54 +02:00
  • 5195f81257 ast: fix import node Emil J. Tywoniak 2025-08-08 16:15:20 +02:00
  • df8422d244 verilog_lexer: refactor Emil J. Tywoniak 2025-08-08 13:00:51 +02:00
  • 740ed3fc1c ast: refactor Emil J. Tywoniak 2025-08-08 13:00:39 +02:00
  • 646c45e6b8 ast: remove null_check as dead code Emil J. Tywoniak 2025-08-08 12:32:43 +02:00
  • 25d2a8ce3a simplify: simplify Emil J. Tywoniak 2025-08-08 12:31:40 +02:00
  • 97bc0088d8 simplify: std::gcd Emil J. Tywoniak 2025-08-08 12:31:13 +02:00
  • d3e33a3be5 simplify.cc: Drop unused debug prints Krystine Sherwin 2025-08-08 17:14:31 +12:00
  • 9b882c32c1 frontends/ast: More usage of auto Krystine Sherwin 2025-08-08 17:10:16 +12:00
  • 720f33271d docs: Update ubuntu apt-get Krystine Sherwin 2025-08-08 14:00:53 +12:00
  • 5b62616b63 preproc: formatting Emil J. Tywoniak 2025-07-19 22:57:53 +02:00
  • 9a10f4c02f verilog_lexer, verilog_parser: remove comment Emil J. Tywoniak 2025-07-19 22:56:48 +02:00
  • ae65b4fc84 verilog_lexer: fix fallthrough warning Emil J. Tywoniak 2025-07-19 22:53:02 +02:00
  • 39c5c256c0 verilog_lexer: remove comment Emil J 2025-07-19 22:46:17 +02:00
  • abb8b8d28b preproc: formatting Emil J. Tywoniak 2025-07-19 22:45:19 +02:00
  • deedfbefe2 fixup! readme, verilog_parser: bison 3.8 and ubuntu 22.04 example Emil J. Tywoniak 2025-07-19 22:40:45 +02:00
  • cbccc01d38 Revert "CI: bump flex and bison on Windows" Emil J. Tywoniak 2025-07-19 22:39:55 +02:00
  • aedc237c7a rtlil: remove comment Emil J 2025-07-19 22:21:17 +02:00
  • 1a63dd56bd Add flex lib to vcxsrc include dirs Krystine Sherwin 2025-07-16 13:48:31 +12:00
  • 4f824e4223 Sneak FlexLexer.h into VS build Krystine Sherwin 2025-07-16 11:52:46 +12:00