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Mono Color

• c525b5f919 Bump version github-actions[bot] 2022-05-24 00:18:18 +00:00
• 335b4888ce Merge pull request #3332 from YosysHQ/verific_f Miodrag Milanović 2022-05-23 20:01:44 +02:00
• fdb393b6ce fix text to fit 80 columns Miodrag Milanovic 2022-05-23 19:57:21 +02:00
• 4a5790d404 Update verific command file documentation Miodrag Milanovic 2022-05-23 19:35:14 +02:00
• a6ec5754c6 Use analysis mode if set in file Miodrag Milanovic 2022-05-23 19:13:45 +02:00
• e47cfe277e Merge pull request #3331 from YosysHQ/git_rev_fix Miodrag Milanović 2022-05-23 18:33:11 +02:00
• 87149b3f8e Change way to get commit sha Jannis Harder 2022-05-23 17:04:07 +02:00
• 166a175983 abc9_ops: Don't leave unused derived modules lying around gatecat 2022-05-01 09:24:17 +01:00
• 0b1a1a576b Bump version github-actions[bot] 2022-05-21 00:16:34 +00:00
• 795c445159 Merge pull request #3324 from jix/confusing-select-errors Jannis Harder 2022-05-20 17:40:40 +02:00
• fc65ea47df select: Fix -assert-none and -assert-any error output and docs Jannis Harder 2022-05-19 13:58:46 +02:00
• 015ca4ddac Bump version github-actions[bot] 2022-05-19 00:17:59 +00:00
• 606f1637ae Add memory_bmux2rom pass. Marcelina Kościelnicka 2022-05-18 21:20:42 +02:00
• 982a11c709 Add memory_libmap tests. Marcelina Kościelnicka 2022-05-06 16:30:56 +02:00
• 2a2dc12eb6 gatemate: Use memory_libmap pass. Marcelina Kościelnicka 2022-03-06 06:49:18 +01:00
• 2dcb0797f0 machxo2: Use memory_libmap pass. Marcelina Kościelnicka 2022-03-06 03:43:13 +01:00
• 9d11575856 efinix: Use memory_libmap pass. Marcelina Kościelnicka 2022-03-06 02:21:53 +01:00
• f4d1426229 anlogic: Use memory_libmap pass. Marcelina Kościelnicka 2022-02-27 09:57:10 +01:00
• d7dc2313b9 ice40: Use memory_libmap pass. Marcelina Kościelnicka 2022-02-27 09:29:26 +01:00
• 3b2f95953c xilinx: Use memory_libmap pass. Marcelina Kościelnicka 2022-02-06 10:10:40 +01:00
• e4d811561c gowin: Use memory_libmap pass. Marcelina Kościelnicka 2022-02-09 09:25:45 +01:00
• 0a8eaca322 nexus: Use memory_libmap pass. Marcelina Kościelnicka 2022-02-08 03:52:50 +01:00
• a04b025abf ecp5: Use memory_libmap pass. Marcelina Kościelnicka 2022-02-08 03:52:16 +01:00
• 7c5dba8b77 Add memory_libmap pass. Marcelina Kościelnicka 2022-02-06 10:10:21 +01:00
• 9450f308f0 proc_rom: Add special handling of const-0 address bits. Marcelina Kościelnicka 2022-05-18 08:18:13 +02:00
• 06ef3f264a Bump version github-actions[bot] 2022-05-18 00:16:27 +00:00
• 7c64c70727 Merge pull request #3310 from robinsonb5-PRs/master Miodrag Milanović 2022-05-17 09:33:20 +02:00
• 98c7804b89 opt_ffinv: Use ModIndex instead of ModWalker. Marcelina Kościelnicka 2022-05-17 01:52:55 +02:00
• 6c6017c973 Use log_warning when Tcl_Init fails, report error with Tcl_ErrnoMsg. Alastair M. Robinson 2022-05-16 20:22:28 +01:00
• 2864f2826a Merge pull request #3314 from jix/sva_value_change_logic_wide Jannis Harder 2022-05-16 16:15:04 +02:00
• 3f8fb28cd2 Bump version github-actions[bot] 2022-05-14 00:19:50 +00:00
• 2858bb03cd Add opt_ffinv pass. Marcelina Kościelnicka 2022-05-13 16:59:52 +02:00
• f56a3bd48f Bump version github-actions[bot] 2022-05-13 00:19:56 +00:00
• 990c9b8e11 Add proc_rom pass. Marcelina Kościelnicka 2022-05-12 23:36:28 +02:00
• fada77b8cf verific: Use new value change logic also for $stable of wide signals. Jannis Harder 2022-05-11 12:55:53 +02:00
• c96e19bd43 abc9: break conflict between boxes and outputs lofty/abc9-output-conflict Lofty 2022-05-10 19:12:39 +01:00
• 83dbea1689 Now calls Tcl_Init after creating the interp, fixes clock format. Alastair M. Robinson 2022-05-10 18:48:54 +01:00
• c862b1dbfb Bump version github-actions[bot] 2022-05-10 00:16:26 +00:00
• 587e09d551 Merge pull request #3305 from jix/sva_value_change_logic Jannis Harder 2022-05-09 16:40:34 +02:00
• 5ca2ee0c31 Merge pull request #3297 from jix/sva_nested_clk_else Jannis Harder 2022-05-09 16:07:39 +02:00
• a855d62b42 verific: Improve logic generated for SVA value change expressions Jannis Harder 2022-05-09 15:04:01 +02:00
• d562bfd165 Next dev cycle Miodrag Milanovic 2022-05-09 10:12:32 +02:00
• 6f9602b4cf Release version 0.17 yosys-0.17 Miodrag Milanovic 2022-05-09 10:11:04 +02:00
• 72d2efeb32 Update CHANGELOG Miodrag Milanovic 2022-05-09 10:06:15 +02:00
• 65f70b9d50 Update manual Miodrag Milanovic 2022-05-09 09:53:01 +02:00
• 58b23954e8 Merge pull request #3299 from YosysHQ/mmicko/sim_memory Miodrag Milanović 2022-05-09 09:28:09 +02:00
• 600079e281 Fix running sva tests Miodrag Milanovic 2022-05-09 09:01:57 +02:00
• 9c69e9f8a6 Bump version github-actions[bot] 2022-05-08 00:16:45 +00:00
• 77b1dfd8c3 opt_mem: Remove constant-value bit lanes. Marcelina Kościelnicka 2022-05-06 23:29:16 +02:00
• 048170d376 Bump version github-actions[bot] 2022-05-07 00:15:38 +00:00
• 37b6614718 include latest abc changes Miodrag Milanovic 2022-05-06 15:52:24 +02:00
• 7fcf976f9e include latest abc changes Miodrag Milanovic 2022-05-06 15:42:39 +02:00
• 384d2120ee Merge pull request #3300 from imhcyx/master Miodrag Milanović 2022-05-06 09:17:59 +02:00
• 52d8ddee0c Include abc change to fix FreeBSD build Miodrag Milanovic 2022-05-06 08:08:06 +02:00
• d8adbff72f Handle possible non-memory indexed data Miodrag Milanovic 2022-05-06 08:05:23 +02:00
• 71166eeecf memory_share: fix wrong argidx in extra_args imhcyx 2022-05-05 16:58:39 +08:00
• a8cc0c3930 Bump version github-actions[bot] 2022-05-05 00:15:34 +00:00
• 18a48b1337 abc: Use dict/pool instead of std::map/std::set Marcelina Kościelnicka 2022-05-04 20:43:59 +02:00
• 8b3657454b map memory location to wire value, if memory is converted to FFs Miodrag Milanovic 2022-05-04 13:08:16 +02:00
• 8e02b3ca30 fix crash when no fst input Miodrag Milanovic 2022-05-04 11:21:39 +02:00
• ad48639cdd Start restoring memory state from VCD/FST Miodrag Milanovic 2022-05-04 10:41:04 +02:00
• 3fb32540ea Add propagated clock signals into btor info file Claire Xenia Wolf 2022-05-04 08:10:18 +02:00
• 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures Jannis Harder 2022-05-03 13:22:18 +02:00
• 11e75bc27c Bump version github-actions[bot] 2022-05-03 00:16:24 +00:00
• 3730db4b98 AIM file could have gaps in or between inputs and inits Miodrag Milanovic 2022-05-02 11:18:30 +02:00
• c785cb7fe3 Bump version github-actions[bot] 2022-04-30 00:18:55 +00:00
• 7bdf7365e7 Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ff Miodrag Milanović 2022-04-29 14:35:46 +02:00
• 422db937d4 Ignore merging past ffs that we are not properly merging Miodrag Milanovic 2022-04-29 14:35:02 +02:00
• b30d90a14a Bump version github-actions[bot] 2022-04-26 00:18:47 +00:00
• 414dc25a96 Add missing parameters for ecp5 Rick Luiken 2022-04-08 14:41:48 +02:00
• 6ae0b51c76 Merge pull request #3287 from jix/smt2-conditional-store Jannis Harder 2022-04-25 16:23:21 +02:00
• e0e31bfc5c Merge pull request #3257 from jix/tribuf-formal Jannis Harder 2022-04-25 16:23:06 +02:00
• 3c0f3504c6 Merge pull request #3290 from mpasternacki/bugfix/freebsd-build Miodrag Milanović 2022-04-25 10:16:50 +02:00
• a511c27eb7 Merge pull request #3289 from YosysHQ/micko/sim_improve Miodrag Milanović 2022-04-25 10:16:25 +02:00
• 0302e97ebc Fix build on FreeBSD, which has no alloca.h Maciej Pasternacki 2022-04-24 19:35:50 +02:00
• bbfdea2f8a Match $anyseq input if connected to public wire Miodrag Milanovic 2022-04-22 17:20:17 +02:00
• 4d80bc24c7 Treat $anyseq as input from FST Miodrag Milanovic 2022-04-22 16:23:39 +02:00
• 9c7deabf94 Ignore change on last edge Miodrag Milanovic 2022-04-22 15:24:02 +02:00
• 33f4009bb5 Last sample from input does not represent change Miodrag Milanovic 2022-04-22 13:46:11 +02:00
• 83cad82b29 latches are always set to zero Miodrag Milanovic 2022-04-22 12:04:05 +02:00
• c989adcc2d If not multiclock, output only on clock edges Miodrag Milanovic 2022-04-22 12:03:39 +02:00
• 75032a565d Set init state for all wires from FST and set past Miodrag Milanovic 2022-04-22 11:57:39 +02:00
• 8fa2f3b260 Fix multiclock for btor2 witness Miodrag Milanovic 2022-04-22 11:53:41 +02:00
• c7ef0f2932 smt2: Make write port array stores conditional on nonzero write mask Jannis Harder 2022-04-20 17:49:48 +02:00
• 29c0a59589 Bump version github-actions[bot] 2022-04-19 00:14:02 +00:00
• c3a3f68b4d Merge pull request #3280 from YosysHQ/micko/fix_readaiw Miodrag Milanović 2022-04-18 09:49:21 +02:00
• 2610b04033 Update abc Miodrag Milanovic 2022-04-18 09:27:00 +02:00
• 1cc281ca6f verific: allow memories to be inferred in loops (vhdl) Miodrag Milanovic 2022-04-18 09:10:28 +02:00
• d23260d381 Merge pull request #3282 from nakengelhardt/verific_loop_rams Miodrag Milanović 2022-04-18 09:09:36 +02:00
• 36b5caf821 Bump version github-actions[bot] 2022-04-16 00:14:57 +00:00
• 25ff83f0b5 memory_share: Fix up mismatched address widths. Marcelina Kościelnicka 2022-04-15 15:05:08 +02:00
• 48eea3efcf opt_dff: Fix behavior on $ff with D == Q. Marcelina Kościelnicka 2022-04-14 15:08:20 +02:00
• 57bc29c64a verific: allow memories to be inferred in loops N. Engelhardt 2022-04-15 15:10:48 +02:00
• 9508bb2330 Fix reading aiw from other solvers Miodrag Milanovic 2022-04-15 11:45:16 +02:00
• bc48500548 tribuf: -formal option: convert all to logic and detect conflicts Jannis Harder 2022-03-29 12:11:28 +02:00
• c1646a00ac Bump version github-actions[bot] 2022-04-09 00:15:22 +00:00
• 4772bc70d0 Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix Miodrag Milanović 2022-04-08 17:38:54 +02:00
• 868409361c Use wrap_async_control_gate if ff is fine Miodrag Milanovic 2022-04-08 16:30:29 +02:00
• bd7ee79486 Merge pull request #3273 from modwizcode/fix-build Miodrag Milanović 2022-04-08 10:08:05 +02:00
• 1f1a403cce pass jny: flipped the defaults for the inclusion of various bits of metadata Aki Van Ness 2022-03-17 07:26:14 -04:00