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Mono Color

• 5204694123 FstData already do conversion to VCD Miodrag Milanovic 2022-03-11 15:21:36 +01:00
• b72c779204 Support cell name in btor witness file Miodrag Milanovic 2022-03-11 15:11:14 +01:00
• d340f302f6 Fix handling of some formal cells in btor back-end Claire Xenia Wolf 2022-03-11 14:21:12 +01:00
• ebe2ee431e handle state names of $anyconst and $anyseq Miodrag Milanovic 2022-03-11 14:04:02 +01:00
• 5e7ea57d8e Prune Linux CI builds Zachary Snow 2022-03-01 10:20:59 +01:00
• 357336339a Proper write of memory data Miodrag Milanovic 2022-03-11 11:19:53 +01:00
• 75c0391f06 Disable tests on most of platforms Miodrag Milanovic 2022-03-10 11:05:00 +01:00
• eb8c61f033 Bump version github-actions[bot] 2022-03-10 01:11:52 +00:00
• 9f7a55c99f intel_alm: M10K write-enable is negative-true Lofty 2022-03-09 16:40:32 +00:00
• 295b0d1899 Start work on memory init Miodrag Milanovic 2022-03-09 18:34:02 +01:00
• f37ac5d934 Fixes and error check Miodrag Milanovic 2022-03-09 09:48:29 +01:00
• ede348cdc2 cleanup Miodrag Milanovic 2022-03-07 16:32:32 +01:00
• 1b1ecd4ab0 Error checks for aiger witness Miodrag Milanovic 2022-03-07 15:00:14 +01:00
• b6aca1d743 btor2 witness co-simulation Miodrag Milanovic 2022-03-07 13:59:36 +01:00
• 4ccc2adbda Merge pull request #3210 from rqou/json-signed Miodrag Milanović 2022-03-07 09:41:25 +01:00
• 7ba636cb32 Bump version github-actions[bot] 2022-03-05 01:06:31 +00:00
• a95e5d505b Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id Miodrag Milanović 2022-03-04 16:39:12 +01:00
• 13655ddccf Merge pull request #3206 from YosysHQ/micko/quote_remove Miodrag Milanović 2022-03-04 16:39:01 +01:00
• c3124023e4 Merge pull request #3207 from nakengelhardt/json_escape_quotes Miodrag Milanović 2022-03-04 13:57:32 +01:00
• 7be7f5e02e Next dev cycle Miodrag Milanovic 2022-03-04 11:37:18 +01:00
• 07a43689d8 Release version 0.15 yosys-0.15 Miodrag Milanovic 2022-03-04 11:36:03 +01:00
• 66ba5ed7a5 Update ABC Miodrag Milanovic 2022-03-04 11:32:15 +01:00
• a7090e9711 Update documentation Miodrag Milanovic 2022-03-04 10:56:33 +01:00
• 9581b9adac Merge pull request #3219 from YosysHQ/micko/quick_vcd Miodrag Milanović 2022-03-04 10:42:14 +01:00
• d1fbe738a7 Merge pull request #3220 from YosysHQ/claire/simstuff Miodrag Milanović 2022-03-04 10:41:02 +01:00
• e768f7552c Bump version github-actions[bot] 2022-03-03 01:08:21 +00:00
• 59983eda17 Add option to ignore X only signals in output Miodrag Milanovic 2022-03-02 16:02:13 +01:00
• 48b56a4f7f Write simulation files after simulation is performed Miodrag Milanovic 2022-03-02 15:23:07 +01:00
• 3818e1160d Update CHANGELOG Miodrag Milanovic 2022-03-02 14:26:15 +01:00
• 2ca69e1b88 Merge pull request #3224 from YosysHQ/micko/refactor Claire Xen 2022-03-02 13:52:18 +01:00
• 28bc88a57e Cleanup Miodrag Milanovic 2022-03-02 09:39:22 +01:00
• 4a38d15f0d Bump version github-actions[bot] 2022-03-01 01:12:24 +00:00
• 94505395a9 Refactor sim output writers Miodrag Milanovic 2022-02-28 18:22:39 +01:00
• dfd4c81eac Quick fix Miodrag Milanovic 2022-02-28 11:40:06 +01:00
• 56b968f61c Add writing of aiw files to "sim" command Claire Xenia Wolf 2022-02-28 10:50:08 +01:00
• 1fd3a642c9 Hotfix in AIGER witness reader state machine Claire Xenia Wolf 2022-02-28 10:41:44 +01:00
• 8be09b5b24 VCD reader support by using external tool Miodrag Milanovic 2022-02-28 09:09:07 +01:00
• ec4af6af2f Merge pull request #3216 from YosysHQ/claire/simstuff Miodrag Milanović 2022-02-28 08:19:54 +01:00
• 9571acc0bf Support extended aiw format Miodrag Milanovic 2022-02-27 16:37:40 +01:00
• fca168797e Fix for last clock edge data Miodrag Milanovic 2022-02-25 16:15:32 +01:00
• ca261d3c28 Experimental sim changes Claire Xenia Wolf 2022-02-25 15:50:46 +01:00
• 08c771078f Bump version github-actions[bot] 2022-02-25 01:04:22 +00:00
• 22d9bbb308 gowin: Remove unnecessary attributes YRabbit 2022-02-24 12:33:55 +10:00
• 9b3cd4f0d8 gowin: Add support for true differential output YRabbit 2022-02-23 16:11:47 +10:00
• 89300b2dca abc: Fix {I} and {P} substitution Anton Blanchard 2022-02-23 18:54:28 +11:00
• dc739362c7 print cell name for properties in yosys-smtbmc N. Engelhardt 2022-02-04 18:23:12 +01:00
• a41c1df76f Merge pull request #3211 from YosysHQ/micko/witness Claire Xen 2022-02-22 16:22:06 +01:00
• ac294ed419 Merge pull request #3197 from YosysHQ/claire/smtbmcfix Claire Xen 2022-02-22 15:26:22 +01:00
• 2d3a337795 json: Add help message for signed field R 2022-02-21 21:59:25 -08:00
• 286caa09bd Bump version github-actions[bot] 2022-02-22 00:59:35 +00:00
• d0b72e75d9 Merge pull request #3203 from YosysHQ/micko/sim_ff Miodrag Milanović 2022-02-21 17:57:44 +01:00
• d0f4d0b153 ecp5: Do not use specify in generate in cells_sim.v. Marcelina Kościelnicka 2022-02-21 16:30:42 +01:00
• fd3f08753a Fix handling of ce_over_srst Miodrag Milanovic 2022-02-21 16:36:12 +01:00
• 8fd1b06249 fix handling of escaped chars in json backend and frontend N. Engelhardt 2022-02-18 17:13:09 +01:00
• 1aa9ad25d0 Fix cycle 0 in aiger witness co-simulation Claire Xenia Wolf 2022-02-18 16:27:41 +01:00
• 5f918803de Changed error message Miodrag Milanovic 2022-02-18 15:06:49 +01:00
• 41754b4207 Added AIGER witness file co simulation Miodrag Milanovic 2022-02-18 15:04:02 +01:00
• 13a5c28459 simplify logic of handling flip-flops and latches Miodrag Milanovic 2022-02-18 09:17:36 +01:00
• 61752b255f Review cleanup Miodrag Milanovic 2022-02-17 17:18:36 +01:00
• 29293a57bb Remove quotes if any from attribute Miodrag Milanovic 2022-02-16 19:10:13 +01:00
• 21baf48e04 test dlatchsr and adlatch Miodrag Milanovic 2022-02-16 13:58:51 +01:00
• 271ac28b41 Added test cases Miodrag Milanovic 2022-02-15 09:35:53 +01:00
• fb22d7cdc4 Add support for various ff/latch cells simulation Miodrag Milanovic 2022-02-15 09:30:42 +01:00
• 1586000048 Bump version github-actions[bot] 2022-02-16 01:01:23 +00:00
• c9a32c0d92 Merge pull request #3204 from YosysHQ/claire/update-abc Miodrag Milanović 2022-02-15 20:51:54 +01:00
• 3bae2705fc Bump ABC version Miodrag Milanovic 2022-02-15 18:44:05 +01:00
• 426f89fc6f Bump version github-actions[bot] 2022-02-15 01:05:31 +00:00
• 15a4e900b2 verilog: support for time scale delay values Zachary Snow 2022-02-11 22:57:31 +01:00
• 68c67c40ec Fix access to whole sub-structs (#3086) Kamil Rakoczy 2022-02-14 14:34:20 +01:00
• 59738c09be Bump version github-actions[bot] 2022-02-13 01:02:04 +00:00
• 3a62fa0c97 gowin: Add remaining block RAM blackboxes. Marcelina Kościelnicka 2022-02-12 11:35:10 +01:00
• 1772a1e98e Bump version github-actions[bot] 2022-02-12 01:01:05 +00:00
• 15eb66b99d verilog: fix dynamic dynamic range asgn elab Zachary Snow 2022-01-17 23:18:12 -07:00
• 90bb47d181 verilog: fix const func eval with upto variables Zachary Snow 2022-01-11 23:51:08 -07:00
• ca876e7c12 Merge pull request #2376 from nmoroze/clk2ff-better-names Claire Xen 2022-02-11 17:30:32 +01:00
• 30eb7f8665 Add a bit of flexibilty re trace length when processing aiger witnesses in smtbmc.py Claire Xenia Wolf 2022-02-11 17:24:49 +01:00
• fc7d78f071 Merge pull request #3164 from zachjs/fix-ast-warn Miodrag Milanović 2022-02-11 16:43:35 +01:00
• 49545c73f7 Merge branch 'master' into clk2ff-better-names Claire Xen 2022-02-11 16:03:12 +01:00
• e016518866 Merge pull request #2019 from boqwxp/glift Claire Xen 2022-02-11 15:51:24 +01:00
• 7ac98d1c87 Add -suffix option to rename -wire. bfg86 2022-02-11 00:05:13 +01:00
• 5ac32ea68c abc9: add flow3mfs script Lofty 2022-02-10 18:28:35 +00:00
• c8903e7053 Bump version github-actions[bot] 2022-02-10 00:58:51 +00:00
• a08fff9c0f Merge pull request #3193 from YosysHQ/micko/verific_f Miodrag Milanović 2022-02-09 12:41:26 +01:00
• 2cef48bf2c Add ability to override verilog mode for verific -f command Miodrag Milanovic 2022-02-09 09:19:25 +01:00
• f61f2a4078 gowin: Fix LUT RAM inference, add more models. Marcelina Kościelnicka 2022-02-09 06:13:34 +01:00
• ac2bb70b52 ecp5: Fix DPR16X4 sim model. Marcelina Kościelnicka 2022-02-09 05:35:05 +01:00
• 23d062fea3 Bump version github-actions[bot] 2022-02-08 00:59:03 +00:00
• 818060880d Next dev cycle Miodrag Milanovic 2022-02-07 17:10:50 +01:00
• a4522d6282 Release version 0.14 yosys-0.14 Miodrag Milanovic 2022-02-07 17:08:39 +01:00
• 9647f6326f Update CHANGELOG and manual Miodrag Milanovic 2022-02-07 17:07:48 +01:00
• d7f7227ce8 Merge pull request #3185 from YosysHQ/micko/co_sim Miodrag Milanović 2022-02-07 16:36:43 +01:00
• 9c93668954 Bump version github-actions[bot] 2022-02-07 00:56:31 +00:00
• 958c3a46ad nexus: Fix arith_map CO signal. Marcelina Kościelnicka 2022-02-06 12:48:44 +01:00
• c0a156bcb4 Error detection for co-simulation Miodrag Milanovic 2022-02-04 11:11:36 +01:00
• 6db23de7b1 bug fix and cleanups Miodrag Milanovic 2022-02-04 10:01:06 +01:00
• 675a7bd22c Bump version github-actions[bot] 2022-02-03 00:54:22 +00:00
• 2d98fe870c Merge pull request #3183 from YosysHQ/micko/nto1mux Miodrag Milanović 2022-02-02 16:22:53 +01:00
• 0b633b6c2e Use bmux for NTO1MUX Miodrag Milanovic 2022-02-02 16:16:08 +01:00
• 7ef6da4c7d Add test cases for co-simulation Miodrag Milanovic 2022-02-02 13:22:44 +01:00
• 518521c72e Merge pull request #3182 from yrabbit/wip-doc2 Miodrag Milanović 2022-02-02 12:19:17 +01:00