Lofty 6f205b41f5 test suite

2026-03-05 05:37:12 +00:00

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aiger

Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order

2025-12-12 10:00:09 +01:00

alumacc

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arch

test suite

2026-03-05 05:37:12 +00:00

asicworld

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bind

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blif

blif: add -gatesi test

2026-01-14 21:41:56 +01:00

bram

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bugpoint

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cxxrtl

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errors

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fmt

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fsm

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functional

Add test

2026-01-06 16:19:04 -08:00

hana

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liberty

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lut

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memfile

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memlib

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memories

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opt

Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors

2026-02-25 15:39:31 +01:00

opt_share

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peepopt

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proc

Test empty switches

2026-01-07 13:21:33 +13:00

pyosys

Remove todo.

2026-03-04 12:39:45 +01:00

realmath

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rpc

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rtlil

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sat

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sdc

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select

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share

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sim

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simple

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simple_abc9

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smv

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sva

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svinterfaces

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svtypes

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techmap

abc9: preserve topological-loop asserts with targeted SCC fallback

2026-02-26 22:30:32 -08:00

tools

Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it.

2025-12-22 21:56:26 +00:00

unit

rtlil use newcelltypes.

2026-03-04 12:39:45 +01:00

various

Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors

2026-02-25 15:39:31 +01:00

verific

tests/verific: ensure mixed -f requires VHDL unit

2026-01-28 22:46:10 -08:00

verilog

support automatic lifetime qualifier on procedural variables

2026-02-27 20:42:52 +03:00

vloghtb

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xprop

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.gitignore

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common-env.sh

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gen-tests-makefile.sh

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pass-fuzzing.md

Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it.

2025-12-22 21:56:26 +00:00